Bus number allocation method, device, system, equipment and medium of exchange chip

Abstract

The application discloses a bus number allocation method, device, system, equipment and medium of a switching chip, and relates to the technical field of chip design. The method determines each host to which each downlink bridge device and the endpoint device corresponding to each downlink bridge device belongs, and then allocates bus numbers to the downlink bridge devices belonging to each host and the endpoint devices corresponding to each downlink bridge device within the bus number range of each host according to the bus number range of each host, so that the bus numbers of the downlink bridge devices belonging to the same host and the endpoint devices corresponding to each downlink bridge device are not repeated. In this way, in the scene of switching chip interconnection, bus number conversion is no longer needed, and bus numbers do not need to be reserved, so that the problem that the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers, but the host still cannot correctly allocate bus numbers to each device can be solved.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and in particular to methods, apparatus, systems, devices and media for assigning bus numbers to switching chips. Background Technology

[0002] For domain-isolated switching chips, the CPU (Central Processing Unit) inside the switching chip typically manages the switching chip connected to the host and the endpoint devices connected to the switching chip. This CPU acts as the actual RC (Root Complex), enumerating and assigning bus numbers to the downlink bridge devices inside the switching chip and the endpoint devices connected to the downlink bridge devices.

[0003] In scenarios where switching chips are interconnected, bus numbers may overlap among multiple switching chips, necessitating bus number translation when devices access each other. Since each switching chip needs to reserve bus numbers for potential access from other switching chips, and the range of bus numbers is limited by the communication protocol, this can lead to situations where the number of devices does not exceed the total limit of bus numbers, but the host still cannot correctly assign a bus number to each device. Summary of the Invention

[0004] This application provides a method, apparatus, system, device, and medium for assigning bus numbers to a switching chip, to at least solve the problem that the host cannot correctly assign a bus number to each device even when the number of current devices in the switching chip does not exceed the limit of the total number of bus numbers.

[0005] This application provides a method for allocating bus numbers for a switching chip. The switching chip includes multiple downlink bridge devices, and each downlink bridge device is connected to a corresponding endpoint device. The method includes: obtaining each downlink bridge device and its corresponding endpoint device; determining the host to which each downlink bridge device and its corresponding endpoint device belong; obtaining the bus number range corresponding to each host; and allocating bus numbers to each downlink bridge device and its corresponding endpoint device using the bus number range.

[0006] This application also provides a bus number allocation device for a switching chip. The switching chip includes multiple downlink bridge devices, and each downlink bridge device is connected to a corresponding endpoint device. The device includes: a device acquisition module for acquiring each downlink bridge device and its corresponding endpoint device; a host determination module for determining the host to which each downlink bridge device and its corresponding endpoint device belong; a bus number acquisition module for acquiring the bus number range corresponding to each host; and a bus number allocation module for allocating bus numbers to each downlink bridge device and its corresponding endpoint device using the bus number range.

[0007] This application also provides a communication system, which includes multiple hosts, multiple switching chips, and multiple endpoint devices, wherein one host is connected to one switching chip, and one switching chip is connected to multiple endpoint devices, and the switching chip is used to implement the steps of any of the above-described switching chip bus number allocation methods.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the bus number allocation method of any of the above-described switching chips when executing the computer program.

[0009] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the bus number allocation method of any of the above-described switching chips.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the bus number allocation method for any of the above-described switching chips.

[0011] Through this application, each downlink bridge device and its corresponding endpoint device in the switching chip corresponds to a different host. During the process of the switching chip assigning bus numbers to each downlink bridge device and its corresponding endpoint device, the host to which each downlink bridge device and its corresponding endpoint device belong is first determined. Then, based on the bus number range of each host, bus numbers are assigned to the downlink bridge devices and their corresponding endpoint devices within that range. This ensures that the bus numbers of downlink bridge devices and their corresponding endpoint devices belonging to the same host are not duplicated, and that these devices are not located in the same switching chip. Therefore, in scenarios involving interconnected switching chips, there is no need to convert bus numbers or reserve bus numbers, thus resolving the problem that even when the number of devices within the switching chip does not exceed the total number of bus numbers, the host still cannot correctly assign a bus number to each device. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 It is a domain isolation switching chip;

[0014] Figure 2 A domain isolation switching chip from the host's perspective;

[0015] Figure 3 A domain isolation switching chip from a real-world perspective;

[0016] Figure 4 This is a schematic diagram showing the interconnection between switching chip A and switching chip B.

[0017] Figure 5 A schematic diagram illustrating the interconnection between switching chip A and switching chip B, provided for an embodiment of this application;

[0018] Figure 6 A flowchart illustrating a method for allocating bus numbers for a switching chip, provided in an embodiment of this application;

[0019] Figure 7 A schematic diagram illustrating a routing ambiguity scenario for switch chip A, provided in an embodiment of this application;

[0020] Figure 8 A flowchart illustrating a method for allocating bus numbers for a switching chip, provided in an embodiment of this application;

[0021] Figure 9 This is a schematic diagram illustrating routing via a target routing table, provided as an embodiment of this application.

[0022] Figure 10 This is a schematic diagram illustrating routing via a target communication bus, provided as an embodiment of this application.

[0023] Figure 11 A schematic diagram of a bus number allocation device for a switching chip provided in an embodiment of this application;

[0024] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0026] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] For traditional switching chips, an RC device located in the host manages the switching chip connected to the host and the endpoint devices connected to the switching chip. The management process includes device enumeration and assigning bus numbers to the devices, etc. Figure 1 The domain isolation switch chip shown typically manages the switch chip connected to the host and the endpoint devices connected to it via its internal CPU (Central Processing Unit). This CPU, acting as the actual RC (Root Complex), enumerates and assigns bus numbers to the downlink bridge devices (the bridge devices connected to the downlink ports are called downlink bridge devices) and the corresponding endpoint devices connected to them. The PCIe domain (Peripheral Component Interconnect Express) managed by the CPU as the RC is called the real domain, while the PCIe domain managed by the host's RC device is called the host domain.

[0028] For domain-isolated switching chips, after the CPU enumerates the devices, it responds to the host's enumeration process with a deceptive reply, making the host "believe" that the downlink bridge devices inside the switching chip and the endpoint devices connected to the downlink bridge devices are still managed by itself. For example... Figure 2 As shown, from the host's perspective, there is no internal CPU within the switching chip. All downlink bridge devices and endpoint devices are directly managed by the host, which assigns bus numbers to all downlink bridge devices and endpoint devices. Figure 3As shown, from a real-world perspective, apart from the uplink bridge device connected to the host (the bridge device connected to the uplink port is called the uplink bridge device), all other bridge devices are managed by the CPU. Furthermore, the bus number actually used by the downlink bridge devices and endpoint devices (i.e., the bus number used on the PCIe link) is assigned by the internal CPU, and its numerical value is generally different from the bus number assigned by the host. For example, Figure 2 and Figure 3 The downlink bridge device and its corresponding endpoint device have different bus numbers. Because the bus number assigned by the host is different from the actual bus number, the host needs to perform bus number conversion when accessing the device.

[0029] like Figure 4 As shown, considering the scenario of two interconnected switching chips, since each CPU independently manages its own PCIe domain, each switching chip can allocate bus numbers starting from 0, and the device enumeration process does not require interaction with other CPUs, making the process relatively simple. However, this method also has the following drawbacks:

[0030] 1. Because the device BDF (Best DF, representing the Bus Number, Device Number, and Function Number) of each switching chip may be duplicated, device communication between switching chips requires BDF conversion. When multiple switching chips are networked, a set of conversion rules is needed for every two chips.

[0031] 2. Because each switching chip needs to reserve a Bus Depth Array (BDF) for potential access from other switching chips (devices belonging to the same host can access each other), and the bus number range is limited by the communication protocol (0~255), the existence of reserved bus numbers can lead to a situation where, from the host's perspective, even if the number of current devices does not exceed the bus number limit, it is still impossible to correctly assign a bus number to each device.

[0032] In view of this, this application proposes a method, apparatus, system, device, and medium for bus number allocation of a switching chip. The switching chip includes multiple downlink bridge devices, each connected to a corresponding endpoint device. The method includes: acquiring each downlink bridge device and its corresponding endpoint device; determining the host to which each downlink bridge device and its corresponding endpoint device belong; acquiring the bus number range corresponding to each host; and allocating bus numbers to each downlink bridge device and its corresponding endpoint device using the bus number ranges.

[0033] In the bus number allocation method of the switching chip in this application, each downlink bridge device and its corresponding endpoint device in the switching chip correspond to a different host. During the process of allocating bus numbers for each downlink bridge device and its corresponding endpoint device, the host to which each downlink bridge device and its corresponding endpoint device belongs is first determined. Then, based on the bus number range of each host, bus numbers are allocated to the downlink bridge devices and their corresponding endpoint devices within the bus number range of each host. This ensures that the bus numbers of downlink bridge devices and their corresponding endpoint devices belonging to the same host are not duplicated, and that downlink bridge devices and their corresponding endpoint devices belonging to the same host are not located in the same switching chip. Therefore, in scenarios where switching chips are interconnected, there is no need to convert bus numbers or reserve bus numbers, thus solving the problem that even when the number of devices in the switching chip does not exceed the total number of bus numbers, the host still cannot correctly allocate a bus number to each device.

[0034] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] First, the specific application environment architecture or specific hardware architecture on which the execution of the bus number allocation method of the switching chip depends is described here.

[0036] This application provides a communication system, which includes multiple hosts, multiple switching chips, and multiple endpoint devices, wherein one host is connected to one switching chip, and one switching chip is connected to multiple endpoint devices.

[0037] like Figure 5 As shown, in an interconnected network composed of switching chip A and switching chip B, host 0 is connected to switching chip A, and switching chip A contains four downlink bridge devices, each connected to one of the four endpoint devices. Host 1 is connected to switching chip B, and switching chip B also contains four downlink bridge devices, each connected to one of the four endpoint devices. In switching chip A, downlink bridge device A and its corresponding endpoint device A belong to host 0, while downlink bridge device B and its corresponding endpoint device B belong to host 1. In switching chip B, downlink bridge device A and its corresponding endpoint device A belong to host 0, while downlink bridge device B and its corresponding endpoint device B belong to host 1. That is, within the same switching chip, each downlink bridge device and its corresponding endpoint device belongs to a different host.

[0038] Secondly, the bus number allocation method of the switching chip of this application will be further described in detail with reference to the above application environment, accompanying drawings and specific implementation methods.

[0039] According to an embodiment of this application, a method for allocating bus numbers for a switching chip is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0040] This embodiment provides a bus number allocation method for a switching chip, which can be used in the aforementioned switching chip, specifically in the CPU of the switching chip. The switching chip includes multiple downlink bridge devices, and each downlink bridge device is connected to a corresponding endpoint device. Figure 6 This is a flowchart of a bus number allocation method for a switching chip according to an embodiment of this application, as shown below. Figure 6 As shown, the process includes the following steps:

[0041] Step S602: Obtain each downlink bridge device and its corresponding endpoint device.

[0042] A bridge device is a functional module used to connect different buses or interfaces, enabling data transmission and protocol conversion. For example... Figure 5 As shown, a downlink bridge device is a bridge device that connects downlink ports. An endpoint device refers to a terminal device connected to a network or switching system.

[0043] To obtain information about each downlink bridge device and its corresponding endpoint device, the CPU of the switching chip needs to know in advance which downlink bridge devices and endpoint devices are configured in the switching chip. There are several ways to obtain this information. For example, it can obtain the configuration information stored in non-volatile memory to identify the configured downlink bridge devices and their corresponding endpoint devices. Alternatively, the CPU can obtain this information by communicating with each downlink bridge device and its corresponding endpoint device.

[0044] Step S604: Determine the host to which each downlink bridge device and its corresponding endpoint device belong.

[0045] As mentioned earlier, in a switching chip, each downlink bridge device and its corresponding endpoint device belong to a different host. To facilitate the allocation of bus numbers to the downlink bridge devices and their corresponding endpoint devices within the bus number range corresponding to each host, it is necessary to determine the host to which each downlink bridge and its corresponding endpoint device belong before allocating bus numbers. In practical applications, the host to which each downlink bridge device and its corresponding endpoint device belong can be determined based on the topology of the switching chip stored in non-volatile memory.

[0046] Step S606: Obtain the bus number range corresponding to each host.

[0047] In a switching chip, the bus number is used to identify different devices or groups of devices on the PCIe bus. Under the PCIe communication protocol, the bus number range for each host is 0 to 255. In practical applications, the bus number range for each host can be obtained by reading non-volatile memory cells; alternatively, it can be obtained by communicating with the host.

[0048] Optionally, the bus number range can be the same for each host, i.e., 0~255. However, since other switching chips assign bus numbers to their own downlink bridge devices and endpoint devices, the bus number range obtained by each switching chip for each host can also be different.

[0049] Step S608: Using the various bus number ranges, assign bus numbers to each downlink bridge device and its corresponding endpoint device.

[0050] In a PCIe topology, a single upper-level bus can branch out into multiple lower-level bridge devices, which share the bus number assigned by the upper-level bus. For example... Figure 5 As shown, for downlink bridge device A belonging to host 0, their bus numbers are all 1. Endpoint device A connected to switch chip A and endpoint device B connected to switch chip B both belong to host 0, and their bus numbers are different, namely {2,0,0}, {3,0,0}, {4,0,0}, and {5,0,0} respectively. Endpoint device B connected to switch chip A and endpoint device B connected to switch chip B both belong to host 1, and their bus numbers are also different, namely {2,0,0}, {3,0,0}, {4,0,0}, and {5,0,0} respectively. Since endpoint devices A and B connected to switch chip A belong to different hosts, their bus numbers can be the same. That is, downlink bridge devices and endpoint devices belonging to the same host have different bus numbers, while downlink bridge devices and endpoint devices belonging to different hosts can have the same bus number.

[0051] It should be noted that, for Figure 5 {2,0,0}, {3,0,0}, {4,0,0}, and {5,0,0} are all BDF codes. Here, B is the bus number, D is the device number, and F is the function number.

[0052] The bus number allocation method for the switching chip provided in this embodiment corresponds to different hosts for each downlink bridge device and its corresponding endpoint device. During the process of allocating bus numbers for each downlink bridge device and its corresponding endpoint device, the host to which each downlink bridge device and its corresponding endpoint device belongs is first determined. Then, based on the bus number range of each host, bus numbers are allocated to the downlink bridge devices and their corresponding endpoint devices within that range. This ensures that the bus numbers of downlink bridge devices and their corresponding endpoint devices belonging to the same host are not duplicated, and that these devices are not located in the same switching chip. Therefore, in scenarios where switching chips are interconnected, there is no need to convert bus numbers or reserve bus numbers. This solves the problem that even when the number of devices within the switching chip does not exceed the total number of bus numbers, the host still cannot correctly allocate a bus number to each device.

[0053] like Figure 5 As shown, the bus number in switch chip A is not the same as the bus number in switch chip B. Therefore, in the scenario where switch chip A and switch chip B are interconnected, there is no need to perform BDF conversion or reserve a BDF. This solves the problem that the number of devices in the current switch chip does not exceed the limit of the total number of bus numbers, but the host still cannot correctly assign a bus number to each device.

[0054] In one optional implementation, determining the host to which each downlink bridge device and its corresponding endpoint device belong includes: obtaining host information corresponding to each downlink bridge device; if the host information is used to characterize a first target host corresponding to a downlink bridge device, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the first target host; if the host information is used to characterize a second target host corresponding to a downlink bridge device, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the second target host, wherein the first target host is the host corresponding to the switching chip itself, and the second target host is a host not corresponding to the switching chip.

[0055] Host information is used to identify the host corresponding to the downlink bridge device, and it can be pre-stored in a non-volatile memory unit. For the switching chip, the host information can be directly obtained by reading the non-volatile memory unit. Based on the host information, it is clear and quick to know which host each downlink bridge device and its corresponding endpoint device in the switching chip belongs to.

[0056] For example, such as Figure 5 As shown, taking switching chip A as an example, the non-volatile storage unit in switching chip A can be read to obtain host information. This host information can be represented as, but is not limited to, downlink bridge device A belonging to host 0 and downlink bridge device B belonging to host 1. Thus, it can be determined that downlink bridge device A and its corresponding endpoint device A belong to host 0, and downlink bridge device B and its corresponding endpoint device B belong to host 1.

[0057] The first target host is the host corresponding to the switching chip itself, and the second target host is a host not corresponding to the switching chip itself. Thus, there can be one or more second target hosts. For example... Figure 5 As shown, the switching chip A includes downlink bridge device A and downlink bridge device B. Downlink bridge device A corresponds to host 0, which is the first target host; downlink bridge device B corresponds to host 1, which is the second target host.

[0058] By using the host information corresponding to each downlink bridge device, the host to which each downlink bridge device and its corresponding endpoint device belong can be quickly and efficiently determined.

[0059] To avoid duplicate bus numbers for downlink bridge devices and their corresponding endpoint devices belonging to the same host, in one optional implementation, bus numbers are allocated to each downlink bridge device and its corresponding endpoint device using various bus number ranges. This includes: obtaining a first bus number range corresponding to a first target host; allocating bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the first target host using the first bus number range; obtaining a second bus number range corresponding to a second target host; and allocating bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the second bus number range.

[0060] The first bus number range corresponding to the first target host and the second bus number range corresponding to the second target host can both be pre-stored in the non-volatile memory unit of the switching chip. It should be understood that if there are multiple second target hosts, there will also be multiple second bus number ranges corresponding to each second target host.

[0061] Within the same host's bus number range, bus numbers are assigned to downlink bridge devices belonging to the same host and their corresponding endpoint devices. This avoids the problem of duplicate bus numbers for downlink bridge devices belonging to the same host and their corresponding endpoint devices.

[0062] In one optional implementation, a first bus number range is used to assign bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the first target host, including: using the first bus number range to determine the first bus number of the downlink bridge devices and the second bus number of each endpoint device; assigning the first bus number to all downlink bridge devices; and assigning each second bus number to each endpoint device, wherein the second bus numbers of each endpoint device are different.

[0063] In a PCIe topology, a single upper-level bus can branch out into multiple lower-level bridge devices, all sharing the bus number assigned by the upper-level bus. This means multiple downlink bridge devices can share the same bus number. Therefore, a first bus number can be determined within a first bus number range, and this first bus number can be assigned to multiple downlink bridge devices belonging to the first target host. Similarly, multiple second bus numbers can be determined within the first bus number range, and each second bus number can be assigned to an endpoint device. This avoids duplicate bus numbers for endpoint devices belonging to the same host and prevents situations where duplicate bus numbers prevent accurate location of the endpoint device.

[0064] For example, such as Figure 5 As shown, for switch chip A, two downlink bridge devices A and two endpoint devices A belong to host 0. Then switch chip A can determine a first bus number and two second bus numbers within the first bus number range corresponding to host 0, allocate the first bus number to the two downlink bridge devices A, and allocate the two second bus numbers to the two endpoint devices A.

[0065] like Figure 5 As shown, for switch chip A, since the two downlink bridge devices B and the two endpoint devices B belong to host 1, it also needs to allocate total signals to the two downlink bridge devices B and the two endpoint devices B. How can switch chip A allocate these signals to avoid the problem of duplicate bus numbers for the two downlink bridge devices B and the two endpoint devices B corresponding to switch chip B? To address this problem, in one optional implementation, a second bus number range is used to allocate bus numbers to the downlink bridge devices belonging to the second target host and their corresponding endpoint devices. This includes: obtaining the central processing unit (CPU) corresponding to the second target host, where the CPU is the processor in the switch chip corresponding to the second target host; and communicating with the CPU to allocate bus numbers to the downlink bridge devices belonging to the second target host and their corresponding endpoint devices using the second bus number range.

[0066] The central processing unit (CPU) corresponding to the second target host is the CPU in the switching chip to which the second target host is connected. For example... Figure 5 As shown, the central processing unit corresponding to the second target host can be the CPU in the switching chip B corresponding to host 1.

[0067] The central processing unit (CPU) of the first target host and the CPU of the second target host communicate and negotiate, which can quickly and efficiently assign unique bus numbers to the downlink bridge devices belonging to the second target host and the endpoint devices corresponding to the downlink bridge devices.

[0068] As mentioned above, the second bus number range corresponding to the second target host can be divided into multiple bus number sub-ranges. The bus number sub-ranges are pre-stored in the non-volatile memory units of different switching chips. In this way, after the central processing unit corresponding to the first target host obtains the bus number sub-range from the non-volatile memory unit, it can allocate bus numbers to the downlink bridge devices and the endpoint devices corresponding to the downlink bridge devices belonging to the second target host within the bus number sub-range. This can eliminate the process of mutual negotiation between the central processing units of different switching chips.

[0069] Optionally, by communicating with the central processing unit to allocate bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the second bus number range, the method includes: communicating with the central processing unit to obtain a bus number subrange sent by the central processing unit, the bus number subrange being included in the second bus number range; and allocating bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the bus number subrange.

[0070] The central processing unit (CPU) of the first target host receives a bus number subrange sent by the CPU of the second target host. It then determines the bus number corresponding to the downlink bridge device and its corresponding endpoint device from this subrange, and assigns the bus number to the downlink bridge device and its corresponding endpoint device. This allows the CPU of the second target host to globally control the bus numbers of the downlink bridge devices and their corresponding endpoint devices belonging to the second target host, thus avoiding the problem of duplicate bus numbers for downlink bridge devices and their corresponding endpoint devices belonging to the same host.

[0071] Optionally, by communicating with the central processing unit to allocate bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the second bus number range, the method includes: determining a bus number subrange using the second bus number range, wherein the bus number subrange is included in the second bus number range; allocating bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the bus number subrange; and communicating with the central processing unit to send the bus number subrange to the central processing unit.

[0072] The central processing unit (CPU) of the first target host can determine a sub-range of bus numbers from the second bus number range, and then determine the bus numbers corresponding to the downlink bridge devices and their corresponding endpoint devices from the bus number sub-range, thereby allocating the bus numbers to the downlink bridge devices and their corresponding endpoint devices. To avoid the problem of duplicate bus numbers for downlink bridge devices and their corresponding endpoint devices belonging to the same host, the CPU of the first target host also needs to send the bus number sub-range to the CPU of the second target host. In this way, the CPU of the second target host can know that the bus numbers in the bus number sub-range may have been occupied, and will no longer allow other hosts to use the bus number sub-range to allocate bus numbers.

[0073] After determining the bus number subrange from the second total signal range, the specific process of assigning bus numbers to the downlink bridge devices belonging to the second target host and their corresponding endpoint devices is the same as the process of assigning bus numbers to the downlink bridge devices belonging to the first target host and their corresponding endpoint devices, and will not be described in detail here.

[0074] like Figure 5 As shown, after using the above-described bus number allocation method for the switching chip, when an endpoint device with BDF {4,0,0} located in switching chip B accesses a device with BDF {3,0,0} located in switching chip A, BDF conversion will no longer be required, and there will be no need to reserve a BDF in switching chip A for the endpoint device of switching chip B.

[0075] like Figure 5 and Figure 7 As shown, there are two endpoint devices with BDF {3,0,0} inside switch chip A, belonging to host 0 and host 1 respectively. This will lead to path ambiguity when using BDF to route communication data packets. For example, as... Figure 7 As shown, when host 0 sends a BDF-routed communication data packet to endpoint device A{3,0,0} belonging to host 0, it may be misrouted to endpoint device B{3,0,0} belonging to host 1. Similarly, when host 1 accesses endpoint device B belonging to host 1 with BDF {3,0,0}, it may also be misrouted to endpoint device A belonging to host 0. Furthermore, when endpoint device B{2,0,0} belonging to host 1 accesses endpoint device B{3,0,0} belonging to host 1, it may also be misrouted to endpoint device A{3,0,0} belonging to host 0.

[0076] To address the issue of route ambiguity, this embodiment provides a bus number allocation method for a switching chip, which can be used in the aforementioned switching chip, specifically in the CPU of the switching chip. The switching chip includes multiple downlink bridge devices, and each downlink bridge device is connected to a corresponding endpoint device. Figure 8 This is a flowchart of a bus number allocation method for a switching chip according to an embodiment of this application, as shown below. Figure 8 As shown, the process includes the following steps:

[0077] Step S802: Obtain each downlink bridge device and its corresponding endpoint device. For details, please refer to [link to relevant documentation]. Figure 6 Step S602 of the illustrated embodiment will not be described again here.

[0078] Step S804: Determine the host to which each downlink bridge device and its corresponding endpoint device belong. For details, please refer to [link to relevant documentation]. Figure 6 Step S604 of the illustrated embodiment will not be described again here.

[0079] Step S806: Obtain the bus number range corresponding to each host. For details, please refer to [link to relevant documentation]. Figure 6 Step S606 of the illustrated embodiment will not be described again here.

[0080] Step S808: Using the various bus number ranges, assign bus numbers to each downlink bridge device and its corresponding endpoint device. For details, please refer to [link to relevant documentation]. Figure 6 Step S608 of the illustrated embodiment will not be described again here.

[0081] Step S810: Obtain the identification information of each host.

[0082] The host's identification information is used to represent the host's identity. This identification information can be the host's MAC (Media Access Control Address), UUID (Universally Unique Identifier), or IP (Internet Protocol Address). Alternatively, the host's identification information can be encoded according to a predetermined encoding method.

[0083] Step S812: Update the bus routing table corresponding to each downlink bridge device using the identification information of each host.

[0084] The bus routing table is used to represent the PCIe bus topology and routing information, that is, to represent the correspondence between the BDF (Browser Layout Function) of downlink bridge devices and their physical port numbers. Within the same switching chip, each downlink bridge device has its own bus routing table, and the bus routing tables of each downlink bridge device can be identical.

[0085] By using the identification information of each host, the bus routing table corresponding to each downlink bridge device can be updated, which means adding the identification information of the host corresponding to each downlink bridge device to the bus routing table.

[0086] The bus number allocation method for the switching chip provided in this embodiment uses the obtained identification information of each host to update the bus routing table corresponding to each downlink bridge device, so that two endpoint devices with duplicate bus numbers are stored separately in the bus routing table. In this way, when the downlink bridge device queries the bus routing table, it can use its own corresponding host identifier and the bus number in the communication data packet to form {host identifier, bus number}, and then query the bus routing table according to {host identifier, bus number}, thereby solving the problem of routing ambiguity.

[0087] There are multiple ways to obtain the identification information of each host.

[0088] Optionally, the identification information of each host is obtained, including: obtaining the total number of hosts corresponding to the switching chip; and determining the identification information of each host according to a predetermined encoding method and the total number.

[0089] The predetermined encoding method can be a pre-set encoding method, which can be encoded by numbers or by other means. This application does not limit the actual method of the predetermined encoding method.

[0090] For switching chips, after obtaining the total number of hosts corresponding to the switching chip, the identification information of each host can be determined according to the predetermined encoding method and the total number, which allows for a more flexible determination of the identification information of each host.

[0091] For example, such as Figure 5 As shown, for switch chip A, there are two corresponding hosts: host 0 and host 1. Switch chip A can use a predetermined encoding method and the total number of hosts to determine the identification information of host 0 as 00 and the identification information of host 1 as 01. For switch chip B, it may use the same method to determine the identification information of host 0 as 11 and the identification information of host 1 as 10. From a global perspective, although host 0 and host 1 each correspond to two different host identifiers, because endpoint devices under different hosts in the PCIe protocol do not communicate directly with each other, even if the same host corresponds to different host identifiers, they will not affect each other.

[0092] For example, when a switching chip contains N hosts, the identification information (HostID) of each host can be encoded as 0 to N-1 respectively.

[0093] Optionally, the identification information of each host is obtained, including: obtaining the host information corresponding to each downlink bridge device; determining the host to which each downlink bridge device belongs based on the host information, thereby obtaining the identification information of each host.

[0094] Since host information is used to identify the host corresponding to each downlink bridge device, the host corresponding to each downlink bridge device can be obtained from the host information table. Once the host corresponding to a downlink bridge device is known, its identification information can be obtained by accessing the host. This scheme ensures that the identification information of hosts throughout the entire interconnected network is unique.

[0095] Alternatively, global encoding can be performed in an interconnection network consisting of multiple switching chips. For example, in an interconnection network consisting of two switching chips, one switching chip corresponds to N1 hosts and the other switching chip corresponds to N2 hosts. In this way, each host can be encoded as 0 to N1+N2-1.

[0096] After determining the identification information of each host, the switching chip can also send the identification information of each host to the downlink bridge device belonging to each host. This allows the downlink bridge device to perform routing queries by forming {host identifier, bus number} based on its own host identifier and the bus number in the communication data packet, and then querying the bus routing table based on {host identifier, bus number}.

[0097] The bus routing table is used to record the bus number and physical port number of each downlink bridge device. Figure 9 The correspondence between Port# in the table is as follows: the bus routing table typically has 256 entries, with a range of 0 to 255.

[0098] As mentioned earlier, there is a problem of duplicate bus numbers within the same switching chip. Therefore, when storing the relationship between bus numbers and physical port numbers of downlink bridge devices using the bus routing table, one bus number may correspond to multiple physical port numbers. To address this issue, the bus routing table needs to be updated. In one optional implementation, the bus routing table corresponding to each downlink bridge device is updated using the identification information of each host. This includes: obtaining the total number of hosts corresponding to the switching chip; expanding the entries in the bus routing table using the total number of hosts to obtain the target routing table; updating the target routing table using the identification information of each host; and sending the updated target routing table to each downlink bridge device.

[0099] Since multiple hosts correspond to the same switching chip, the bus routing table before the update cannot accommodate the routing information of all downlink bridge devices. Therefore, the entries in the bus routing table need to be expanded, and the target routing table is updated using the identification information of each host.

[0100] In one optional implementation, updating the target routing table using the identification information of each host includes: for each downlink bridge device, constructing target routing information using the identification information, bus number and corresponding physical port number of the host corresponding to the downlink bridge device to obtain multiple target routing information; and filling the multiple target routing information into the target routing table to update the target routing table.

[0101] The mapping between bus numbers and physical port numbers of downlink bridge devices in the bus routing table is updated to include the host identification information, bus number, and corresponding physical port number of the downlink bridge device. In other words, the host identification information is added to the target routing table, ensuring that downlink bridge devices with the same bus number within the same switching chip are stored separately in the target routing table. Specifically, as follows... Figure 9 As shown, this further solves the routing ambiguity problem caused by duplicate bus numbers in the same switching chip.

[0102] For example, such as Figure 9 As shown, the process of updating the bus routing table includes the following steps: First, the entries in the bus routing table are expanded to 256*N, where N is the maximum number of hosts supported by each switching chip. Second, the Host ID is used as the high-order bits of the lookup address; that is, the target routing information is constructed using {Host ID, Bus, Port#} and populated into the target routing table to update it. Subsequent lookups using the target routing table can then be performed using {Host ID, Bus}. For example, the physical port number with Host ID=1 and Bus=2 is located in entry 258 (hexadecimal 0x102 equals decimal 258).

[0103] Since the internal CPU of the domain isolation switching chip is a real domain RC device, this means that the RC device managing two identical bus numbers on the PCIe tree violates the PCIe protocol and will also cause routing ambiguity issues when the CPU accesses endpoint devices. To solve this problem, in an optional implementation, each downlink bridge device in the switching chip is connected to a target communication bus, and each downlink bridge device corresponds to a communication identifier on the target communication bus; the target communication bus is constructed using a predetermined communication protocol, and communication data packets are routed using the communication identifiers.

[0104] By connecting each downlink bridge device to the target communication bus, the CPU no longer uses standard PCIe interconnect when accessing internal downlink bridge devices. Instead, it uses the predetermined communication protocol followed by the target communication bus for interconnection. This solves the problem of violating the PCIe protocol caused by having two identical bus numbers on the PCIe tree, as well as the problem of routing ambiguity when the CPU accesses endpoint devices.

[0105] The predetermined communication protocol is a communication protocol that does not use BDF for routing, but it can be a communication protocol that uses communication identifiers for routing. These communication identifiers include, but are not limited to, addresses and port numbers.

[0106] In an optional implementation, the method further includes: acquiring communication data packets to be transmitted to the target downlink bridge device; performing protocol conversion on the communication data packets using a predetermined communication protocol corresponding to the target communication bus; and sending the protocol-converted communication data packets to the target downlink bridge device, thereby enabling the target downlink bridge device to recognize communication data packets conforming to the PCIe protocol.

[0107] For example, such as Figure 10 As shown, a target communication bus is used within the switching chip, and each downlink bridge device is connected to this target communication bus. This target communication bus can use the most common address routing method, where each downlink bridge device has a separate physical port on the target communication bus, and this physical port occupies a pre-allocated communication address. When the CPU needs to access a downlink bridge device, the CPU sends a communication data packet to the target communication bus where that downlink bridge device resides. This communication data packet is encapsulated using a predetermined communication protocol. Subsequently, the communication data packet is routed by the target communication bus to the corresponding physical port via the communication address. Before the communication data packet enters the downlink bridge device, it undergoes protocol conversion using the predetermined communication protocol to restore it to a PCIe-compliant communication data packet that the downlink bridge device can recognize. In other words, the core of this method is to avoid using the routing method defined by the standard PCIe protocol to prevent routing ambiguity, and to use protocol conversion to complete the conversion between the predetermined communication protocol followed by the target communication bus and the PCIe protocol.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] Embodiments of this application also provide a bus number allocation device for a switching chip, the switching chip including multiple downlink bridge devices, and each downlink bridge device connected to a corresponding endpoint device. For example... Figure 11As shown, the device includes a device acquisition module, a host determination module, a bus number acquisition module, and a bus number allocation module. Among them,

[0110] The device acquisition module 1110 is used to acquire each downlink bridge device and its corresponding endpoint device;

[0111] The host determination module 1120 is used to determine the host to which each downlink bridge device and its corresponding endpoint device belong;

[0112] Bus number acquisition module 1130 is used to acquire the bus number range corresponding to each host;

[0113] The bus number allocation module 1140 is used to allocate bus numbers to each downlink bridge device and its corresponding endpoint device using various bus number ranges.

[0114] In one optional embodiment, the host determination module is used to obtain host information corresponding to each downlink bridge device; if the host information is used to indicate that the downlink bridge device corresponds to a first target host, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the first target host; if the host information is used to indicate that the downlink bridge device corresponds to a second target host, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the second target host, wherein the first target host is the host corresponding to the switching chip itself, and the second target host is a host that does not correspond to the switching chip itself.

[0115] In one optional embodiment, the bus number allocation module is used to obtain a first bus number range corresponding to a first target host; allocate bus numbers to downlink bridge devices belonging to the first target host and their corresponding endpoint devices using the first bus number range; obtain a second bus number range corresponding to a second target host; and allocate bus numbers to downlink bridge devices belonging to the second target host and their corresponding endpoint devices using the second bus number range.

[0116] In one alternative embodiment, the bus number allocation module is further configured to determine a first bus number of the downlink bridge device and a second bus number of each endpoint device using a first bus number range; allocate the first bus number to all downlink bridge devices; and allocate each second bus number to each endpoint device, wherein the second bus numbers of each endpoint device are different.

[0117] In one optional embodiment, the bus number allocation module is further configured to obtain the central processing unit corresponding to the second target host, wherein the central processing unit is the processor in the switching chip corresponding to the second target host; and to allocate bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host by communicating with the central processing unit, using the second bus number range.

[0118] In one alternative embodiment, the bus number allocation module is further configured to communicate with the central processing unit to obtain a bus number subrange sent by the central processing unit, the bus number subrange being included in the second bus number range; and to allocate bus numbers to the downlink bridge devices belonging to the second target host and their corresponding endpoint devices using the bus number subrange.

[0119] In one alternative embodiment, the bus number allocation module is further configured to: determine a bus number subrange using a second bus number range, the bus number subrange being included in the second bus number range; allocate bus numbers to downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the bus number subrange; and communicate with the central processing unit to send the bus number subrange to the central processing unit.

[0120] In one optional embodiment, the device further includes a host identifier acquisition module and a routing information update module, wherein the host identifier acquisition module is used to acquire the identifier information of each host; and the routing information update module is used to update the bus routing table corresponding to each downlink bridge device using the identifier information of each host.

[0121] In one optional embodiment, the host identifier acquisition module is used to acquire the total number of hosts corresponding to the switching chip; and determine the identifier information of each host according to a predetermined encoding method and the total number.

[0122] In one optional embodiment, the host identifier acquisition module is used to acquire host information corresponding to each downlink bridge device; based on the host information, it determines the host to which each downlink bridge device belongs, thereby acquiring the identifier information of each host.

[0123] In one optional embodiment, the routing information update module is used to obtain the total number of hosts corresponding to the switching chip; expand the entries of the bus routing table using the total number of hosts to obtain the target routing table; update the target routing table using the identification information of each host; and send the updated target routing table to each downlink bridge device.

[0124] In one optional embodiment, the routing information update module is used to construct target routing information for each downlink bridge device using the identification information, bus number and corresponding physical port number of the host corresponding to the downlink bridge device, thereby obtaining multiple target routing information; and to populate the multiple target routing information into the target routing table to update the target routing table.

[0125] In one alternative embodiment, each downlink bridge device in the switching chip is connected to a target communication bus, and each downlink bridge device corresponds to a communication identifier on the target communication bus; the target communication bus is constructed using a predetermined communication protocol, and communication data packets are routed using the communication identifiers.

[0126] In one optional embodiment, the device further includes a data packet acquisition module and a protocol conversion module. The data packet acquisition module is used to acquire communication data packets to be transmitted to the target downlink bridge device. The protocol conversion module is used to convert the communication data packets according to a predetermined communication protocol corresponding to the target communication bus, and send the protocol-converted communication data packets to the target downlink bridge device.

[0127] In the bus number allocation device of the switching chip in this application, each downlink bridge device and its corresponding endpoint device in the switching chip correspond to a different host. During the process of the switching chip allocating bus numbers to each downlink bridge device and its corresponding endpoint device, the host to which each downlink bridge device and its corresponding endpoint device belong is first determined. Then, based on the bus number range of each host, bus numbers are allocated to the downlink bridge devices and their corresponding endpoint devices belonging to each host within that range. This ensures that the bus numbers of downlink bridge devices and their corresponding endpoint devices belonging to the same host are not duplicated, and that downlink bridge devices and their corresponding endpoint devices belonging to the same host are not located in the same switching chip. Therefore, in scenarios where switching chips are interconnected, there is no need to convert bus numbers or reserve bus numbers, thus solving the problem that even when the number of devices in the switching chip does not exceed the total number of bus numbers, the host still cannot correctly allocate a bus number to each device.

[0128] For a description of the features of the bus number allocation device for the switching chip in the corresponding embodiment, please refer to the relevant description of the bus number allocation method for the switching chip in the corresponding embodiment, which will not be repeated here.

[0129] Embodiments of this application also provide a communication system, which includes multiple hosts, multiple switching chips, and multiple endpoint devices, wherein one host is connected to one switching chip, and one switching chip is connected to multiple endpoint devices, and the switching chip is used to implement the steps of any of the above-described switching chip bus number allocation methods.

[0130] The communication system of this application includes multiple hosts, multiple switching chips, and multiple endpoint devices. The multiple switching chips can execute the aforementioned bus number allocation method. In this method, firstly, the hosts to which each downlink bridge device and its corresponding endpoint device belong are determined. Then, based on the bus number range of each host, bus numbers are allocated to the downlink bridge devices and their corresponding endpoint devices within that range. This ensures that the bus numbers of downlink bridge devices and their corresponding endpoint devices belonging to the same host are not duplicated, and that these devices are not located in the same switching chip. Thus, in scenarios where switching chips are interconnected, bus number conversion is no longer required, and no bus numbers need to be reserved. This solves the problem that even when the number of devices within a switching chip does not exceed the total number of bus numbers, the host still cannot correctly allocate a bus number to each device.

[0131] In one optional implementation, the switching chip includes a central processing unit (CPU), an uplink bridge device, at least one cascaded bridge device, and multiple downlink bridge devices. The CPU is used to assign bus numbers to each downlink bridge device in the switching chip and to each endpoint device connected to each downlink bridge device. The uplink bridge devices are used to forward communication data packets sent by a first target host or each of the downlink bridge devices, where the first target host is the host corresponding to the switching chip itself. The at least one cascaded bridge device is used to forward the communication data packets sent by the CPU or each of the downlink bridge devices. The multiple downlink bridge devices are used to connect to multiple endpoint devices.

[0132] Embodiments of this application also provide an electronic device, such as... Figure 12 As shown, it includes a memory 1210 and a processor 1220. The memory 1210 stores a computer program, and the processor 1220 is configured to run the computer program to perform the steps in any of the above-described embodiments of the bus number allocation method for a switching chip.

[0133] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the bus number allocation method for any of the above-described switching chips when running.

[0134] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0135] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the embodiments of the bus number allocation method for any of the above-described switching chips.

[0136] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described embodiments of the bus number allocation method for a switching chip.

[0137] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0138] The present application provides a detailed description of a bus number allocation method, apparatus, system, device, and medium for a switching chip. Specific examples have been used to illustrate the principles and implementation methods of the present application. The descriptions of these embodiments are merely illustrative of the methods and core concepts of the present application. It should be noted that those skilled in the art can make various improvements and modifications to the present application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A method for allocating bus numbers for a switching chip, characterized in that, The switching chip includes multiple downlink bridge devices, and each of the downlink bridge devices is connected to a corresponding endpoint device. The method includes: Obtain each of the downlink bridge devices and their corresponding endpoint devices; Determine the host to which each of the downlink bridge devices and their corresponding endpoint devices belong; Obtain the bus number range corresponding to each of the aforementioned hosts; Using the various bus number ranges, bus numbers are assigned to each downlink bridge device and its corresponding endpoint device, wherein the bus numbers of downlink bridge devices belonging to the same host and the corresponding endpoint devices of each downlink bridge device are not repeated, and the downlink bridge devices belonging to the same host and the corresponding endpoint devices of each downlink bridge device are not located in the same switching chip.

2. The method according to claim 1, characterized in that, Determining the host to which each of the downlink bridge devices and their corresponding endpoint devices belongs includes: Obtain the host information corresponding to each of the downlink bridge devices; If the host information is used to characterize the downlink bridge device as corresponding to the first target host, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the first target host; If the host information is used to characterize the downlink bridge device as corresponding to the second target host, then the host to which the downlink bridge device and its corresponding endpoint device belong is determined to be the second target host, wherein the first target host is the host corresponding to the switching chip itself, and the second target host is the host that does not correspond to the switching chip itself.

3. The method according to claim 2, characterized in that, Using the various bus number ranges, assign bus numbers to each of the downlink bridge devices and their corresponding endpoint devices, including: Obtain the first bus number range corresponding to the first target host; Using the first bus number range, the bus number is assigned to the downlink bridge device belonging to the first target host and its corresponding endpoint device; Obtain the second bus number range corresponding to the second target host; Using the second bus number range, the bus number is assigned to the downlink bridge device belonging to the second target host and its corresponding endpoint device.

4. The method according to claim 3, characterized in that, Using the first bus number range, assigning the bus number to the downlink bridge device belonging to the first target host and its corresponding endpoint device includes: Using the first bus number range, determine the first bus number of the downlink bridge device and the second bus number of each of the endpoint devices; The first bus number is assigned to all of the downlink bridge devices; Each of the second bus numbers is assigned to each of the endpoint devices, and the second bus numbers of each of the endpoint devices are different.

5. The method according to claim 3, characterized in that, Using the second bus number range, assigning bus numbers to the downlink bridge device belonging to the second target host and its corresponding endpoint device includes: Obtain the central processing unit corresponding to the second target host, wherein the central processing unit is the processor in the switching chip corresponding to the second target host; By communicating with the central processing unit, the bus number is allocated to the downlink bridge device and its corresponding endpoint device belonging to the second target host using the second bus number range.

6. The method according to claim 5, characterized in that, By communicating with the central processing unit to allocate bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the second bus number range, the following steps are included: Communicate with the central processing unit to obtain a bus number subrange sent by the central processing unit, the bus number subrange being included in the second bus number range; The bus number is assigned to the downlink bridge device and its corresponding endpoint device belonging to the second target host using the bus number subrange.

7. The method according to claim 5, characterized in that, By communicating with the central processing unit to allocate bus numbers to the downlink bridge devices and their corresponding endpoint devices belonging to the second target host using the second bus number range, the following steps are included: Using the second bus number range, a bus number subrange is determined, wherein the bus number subrange is included in the second bus number range; Using the bus number subrange, the bus number is assigned to the downlink bridge device belonging to the second target host and its corresponding endpoint device; Communicate with the central processing unit to send the bus number subrange to the central processing unit.

8. The method according to claim 1, characterized in that, The method further includes: Obtain the identification information of each of the aforementioned hosts; The bus routing table corresponding to each downlink bridge device is updated using the identification information of each host.

9. The method according to claim 8, characterized in that, Obtain the identification information of each of the hosts, including: Obtain the total number of hosts corresponding to the switching chip; The identification information of each host is determined according to the predetermined encoding method and the total number.

10. The method according to claim 8, characterized in that, Obtain the identification information of each of the hosts, including: Obtain the host information corresponding to each of the downlink bridge devices; Based on the host information, the host to which each downlink bridge device belongs is determined, thereby obtaining the identification information of each host.

11. The method according to claim 8, characterized in that, Using the identification information of each of the hosts, update the bus routing table corresponding to each of the downlink bridge devices, including: Obtain the total number of hosts corresponding to the switching chip; Using the total number of hosts, the entries in the bus routing table are expanded to obtain the target routing table; The target routing table is updated using the identification information of each host; The updated target routing table is sent to each of the downlink bridge devices.

12. The method according to claim 11, characterized in that, Updating the target routing table using the identification information of each of the hosts includes: For each downlink bridge device, target routing information is constructed using the identification information of the host corresponding to the downlink bridge device, the bus number and its corresponding physical port number, to obtain multiple target routing information. Multiple target routing information entries are populated into the target routing table to update the target routing table.

13. The method according to any one of claims 1 to 12, characterized in that, Each of the downlink bridge devices in the switching chip is connected to the target communication bus, and each of the downlink bridge devices corresponds to a communication identifier on the target communication bus; The target communication bus is constructed using a predetermined communication protocol and uses the communication identifier to route communication data packets.

14. The method according to claim 13, characterized in that, The method further includes: Acquire the communication data packet to be transmitted to the target downlink bridge device; The communication data packets are converted using the predetermined communication protocol corresponding to the target communication bus, and the converted communication data packets are sent to the target downlink bridge device.

15. A bus number allocation device for a switching chip, characterized in that, The switching chip includes multiple downlink bridge devices, and each of the downlink bridge devices is connected to a corresponding endpoint device. The device includes: The device acquisition module is used to acquire each of the downlink bridge devices and their corresponding endpoint devices; The host determination module is used to determine the host to which each of the downlink bridge devices and their corresponding endpoint devices belong; The bus number acquisition module is used to acquire the bus number range corresponding to each of the hosts; The bus number allocation module is used to allocate bus numbers to each downlink bridge device and its corresponding endpoint device using the various bus number ranges, wherein the bus numbers of downlink bridge devices belonging to the same host and the corresponding endpoint devices of each downlink bridge device are not repeated, and the downlink bridge devices belonging to the same host and the corresponding endpoint devices of each downlink bridge device are not located in the same switching chip.

16. A communication system, characterized in that, The communication system includes multiple hosts, multiple switching chips, and multiple endpoint devices, wherein one host is connected to one switching chip, and one switching chip is connected to multiple endpoint devices. The switching chip is used to implement the steps of the bus number allocation method of the switching chip as described in any one of claims 1 to 14.

17. The system according to claim 16, characterized in that, The switching chip includes: A central processing unit is used to assign bus numbers to each downlink bridge device in the switching chip and to each endpoint device connected to each downlink bridge device; The uplink bridge device is used to forward communication data packets sent by the first target host or each of the downlink bridge devices, wherein the first target host is the host corresponding to the switching chip itself; At least one cascaded bridge device is used to forward the communication data packets sent by the central processing unit or each of the downlink bridge devices; Multiple downlink bridge devices are used to connect multiple endpoint devices.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the bus number allocation method for the switching chip as described in any one of claims 1 to 14 when executing the computer program.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the bus number allocation method for the switching chip as described in any one of claims 1 to 14.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the bus number allocation method for the switching chip as described in any one of claims 1 to 14.

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