Semiconductor device and electronic system including the same

Abstract

The invention discloses a semiconductor device and an electronic system including the same, the semiconductor device including: a substrate having a first active region, a second active region, and a third active region; a first transistor on the first active region and including a first gate structure including a first gate insulating layer and a first gate electrode; a second transistor on the second active region and including a second gate structure, the second gate structure including a second gate insulating layer, the second gate insulating layer including a high dielectric layer, a work function metal layer, and a second gate electrode; and a third transistor on the third active region and including a third gate structure, the third gate structure including a third gate insulating layer, the third gate insulating layer including a high dielectric layer, a work function metal layer, and a third gate electrode, wherein the first gate electrode includes a first semiconductor layer and a second semiconductor layer sequentially arranged on the first gate insulating layer and each including polysilicon.

Description

Technical Field

[0001] The inventive concept relates to semiconductor devices, methods of manufacturing semiconductor devices, and / or electronic systems including semiconductor devices, and more particularly to semiconductor devices having vertical channels, methods of manufacturing semiconductor devices, and / or electronic systems including semiconductor devices. Background Art

[0002] Electronic systems that need to store data require semiconductor devices capable of storing high-capacity data. Accordingly, methods of increasing the data storage capacity of semiconductor devices are being studied. For example, to increase the data storage capacity of semiconductor devices, semiconductor devices including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] The inventive concept provides semiconductor devices, methods of manufacturing semiconductor devices, and / or electronic systems including semiconductor devices having improved operational reliability.

[0004] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate having a first active region, a second active region, and a third active region defined by device isolation layers; a first transistor disposed on the first active region and including a first gate structure including a first gate insulating layer disposed on the first active region and a first gate electrode disposed on the first gate insulating layer; a second transistor disposed on the second active region and including a second gate structure including a second gate insulating layer disposed on the second active region and including a high-k layer, a work function metal layer disposed on the second gate insulating layer, and a second gate electrode disposed on the work function metal layer and including a metal; and a third transistor disposed on the third active region and including a third gate structure including a third gate insulating layer disposed on the third active region and including a high-k layer, a work function metal layer disposed on the third gate insulating layer, and a third gate electrode disposed on the work function metal layer and including a metal, wherein the first gate electrode includes a first semiconductor layer and a second semiconductor layer each including polysilicon and disposed in sequence on the first gate insulating layer.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a peripheral circuit structure provided on a substrate; and a cell array structure disposed on the peripheral circuit structure and including a plurality of memory cells disposed in a vertical direction perpendicular to an upper surface of the substrate, wherein the peripheral circuit structure includes: a device isolation layer disposed on the substrate and defining a first active region, a second active region, and a third active region; a first gate structure disposed on the first active region and including a first gate insulating layer and a first gate electrode disposed on the first gate insulating layer; a second gate structure disposed on the second active region and including a second gate insulating layer including a high-k dielectric layer, a work function metal layer disposed on the second gate insulating layer, and a second gate electrode disposed on the work function metal layer and including a metal; and a third gate structure disposed on the third active region and including a third gate insulating layer including a high-k dielectric layer, a work function metal layer disposed on the third gate insulating layer, and a third gate electrode disposed on the work function metal layer and including a metal, the first gate electrode including a first semiconductor layer and a second semiconductor layer sequentially disposed on the first gate insulating layer and each including polysilicon.

[0006] According to an exemplary embodiment of the inventive concept, an electronic system includes a main board, a semiconductor device on the main board, and a controller electrically connected to the semiconductor device on the main board, wherein the semiconductor device includes a peripheral circuit structure provided on a substrate and a cell array structure disposed on the peripheral circuit structure and including a plurality of memory cells disposed in a vertical direction perpendicular to an upper surface of the substrate, the peripheral circuit structure including: a device isolation layer disposed on the substrate and defining a first active region, a second active region, and a third active region; a first gate structure disposed on the first active region and including a first gate insulating layer including a silicon oxide film and a first gate electrode disposed on the first gate insulating layer; a second gate structure disposed on the second active region and including a second gate insulating layer, a work function metal layer disposed on the second gate insulating layer, and a second gate electrode disposed on the work function metal layer and including a metal, the second gate insulating layer including a first insulating layer including a silicon oxide film and including a second insulating layer including a high-k dielectric film; and a third gate structure disposed on the third active region and including a third gate insulating layer including a high-k dielectric layer, a work function metal layer disposed on the third gate insulating layer, and a third gate electrode disposed on the work function metal layer and including a metal, the first gate electrode including a first semiconductor layer and a second semiconductor layer sequentially disposed on the first gate insulating layer and each including polysilicon, and an upper surface of the first semiconductor layer being at the same vertical level as an upper surface of the first insulating layer and an upper surface of the third gate insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram showing a semiconductor device according to an exemplary embodiment;

[0009] Figure 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an exemplary embodiment;

[0010] Figure 3 is a perspective view schematically showing a semiconductor device according to an exemplary embodiment;

[0011] Figure 4 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment;

[0012] Figure 5 is showing Figure 4 a layout diagram of a peripheral circuit structure of the semiconductor device;

[0013] Figure 6 is a cross-sectional view taken along line A-A' of Figure 5 ;

[0014] Figure 7 is Figure 4 an enlarged cross-sectional view of part EX of

[0015] Figure 8 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment;

[0016] Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 are cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0017] Figure 27 is a diagram schematically showing an electronic system including a semiconductor device according to an example embodiment;

[0018] Figure 28 is a perspective view schematically showing an electronic system including a semiconductor device according to an example embodiment; and

[0019] Figure 29 is a cross-sectional view schematically showing a semiconductor package according to an example embodiment. Detailed Embodiments

[0020] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and repeated descriptions thereof are omitted.

[0021] Although the terms "same", "equal", or "equivalent" are used in the description of the example embodiments, it should be understood that there may be some inaccuracies. Thus, when an element is referred to as being the same as another element, it should be understood that the one element or value is the same as the other element or value within the desired manufacturing or operating tolerances (e.g., ±10%).

[0022] When the terms "about", "substantially", or "approximate" are used in this specification in connection with a numerical value, it means that the relevant numerical value includes the manufacturing or operating tolerances around the stated numerical value (e.g., ±10%). Further, when the words "about", "substantially", or "approximate" are used in connection with a geometric shape, it means that geometric precision is not required, but the tolerance of the shape is within the scope of the present disclosure. Further, whether or not a numerical value or a shape is modified by "about" or "substantially", it will be understood that these numerical values and shapes should be interpreted as including the manufacturing or operating tolerances around the stated numerical value or shape (e.g., ±10%).

[0023] As used herein, when a phrase such as "at least one of..." is located after a column of elements, it modifies the entire column of elements and not an individual element within the column. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0024] Figure 1 is a block diagram showing a semiconductor device 10 according to an example embodiment.

[0025] Referring to Figure 1, the semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ……, BLKn. Each of the plurality of memory cell blocks (BLK1, BLK2, ……, BLKn) may include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, ……, BLKn may be connected to the peripheral circuit 30 through a plurality of bit lines BL, a plurality of word lines WL, a plurality of string selection lines SSL, and a ground selection line GSL.

[0026] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output circuit 36, and a control logic 38. Although Figure 1 not shown in the figure, the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

[0027] The memory cell array 20 may be connected to the page buffer 34 through a plurality of bit lines BL, and may be connected to the row decoder 32 through a plurality of word lines WL, a plurality of string selection lines SSL, and a ground selection line GSL. The plurality of memory cells included in the memory cell blocks BLK1, BLK2, ……, BLKn in the memory cell array 20 may be flash memory cells. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells connected to a plurality of word lines WL vertically stacked on a substrate.

[0028] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor device 10, and may receive data DATA from an external device separated from the semiconductor device 10 and send data DATA to it.

[0029] The row decoder 32 may select at least one of the plurality of memory cell blocks BLK1, BLK2, ……, BLKn in response to the address ADDR, and may select the word lines WL, string selection lines SSL, and ground selection line GSL of the selected memory cell block. The row decoder 32 may send a voltage for operating the memory to the word lines WL of the selected memory cell block.

[0030] The page buffer 34 may be connected to the memory cell array 20 through a plurality of bit lines BL. The page buffer 34 may apply a voltage according to the data DATA to be stored in the memory cell array 20 as a write driver during a programming operation to the bit lines BL, and may detect the data DATA stored in the memory cell array 20 as a sense amplifier during a read operation. The page buffer 34 may operate in response to a control signal PCTL provided by the control logic 38.

[0031] The data input / output circuit 36 can be connected to the page buffer 34 through a plurality of data lines DL. The data input / output circuit 36 can receive data DATA from a memory controller (not shown) during a programming operation, and provide programming data DATA to the page buffer 34 based on a column address C_ADDR provided by the control logic 38. The data input / output circuit 36 can provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided by the control logic 38 during a read operation.

[0032] The data input / output circuit 36 can send an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 can further include an electrostatic discharge (ESD) circuit and a pull-up / pull-down driver.

[0033] The control logic 38 can receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 can provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data input / output circuit 36. The control logic 38 can generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL. For example, when performing a memory operation such as a programming operation or an erase operation, the control logic 38 can adjust the voltage levels provided to the plurality of word lines WL and the plurality of bit lines BL.

[0034] Figure 2 is an equivalent circuit diagram of a memory cell array 20 of a semiconductor device according to an exemplary embodiment.

[0035] Referring to Figure 2 , the memory cell array 20 can include a plurality of memory cell strings MS. The memory cell array 20 can include a plurality of bit lines BL (BL1, BL2,..., BLm), a plurality of word lines WL (WL1, WL2,..., WLn-1 and WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS can be formed between the plurality of bit lines BL (BL1, BL2,..., BLm) and the common source line CSL. Although Figure 2 shows a case where each of the plurality of memory cell strings MS includes two string selection lines SSL, the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MS can include one string selection line SSL.

[0036] Each of a plurality of memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, …, MCn−1, and MCn. A drain region of the string select transistor SST may be connected to a bit line BL (BL1, BL2, …, or BLm), and a source region of the ground select transistor GST may be connected to a common source line CSL. Source regions of the plurality of ground select transistors GST may be commonly connected to the common source line CSL.

[0037] The string select transistor SST may be connected to a string select line SSL, and the ground select transistor GST may be connected to a ground select line GSL. The plurality of memory cell transistors MC1, MC2, …, MCn−1, and MCn may be respectively connected to a plurality of word lines WL (WL1, WL2, …, WLn−1, and WLn).

[0038] Figure 3 is a perspective view schematically showing a semiconductor device 10 according to an exemplary embodiment.

[0039] The semiconductor device 10 may include a cell array structure CS and a peripheral circuit structure PS overlapping each other in a vertical direction (Z direction). The cell array structure CS may include a memory cell array 20 described with reference to Figure 1 and Figure 2 The peripheral circuit structure PS may include a peripheral circuit 30 described with reference to Figure 1 description.

[0040] The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, …, BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, …, BLKn may include three-dimensionally arranged memory cells.

[0041] Figure 4 is a cross-sectional view showing a semiconductor device 100 according to an exemplary embodiment. Figure 5 is showing Figure 4 a layout diagram of a peripheral circuit structure of the semiconductor device 100. Figure 6 is a cross-sectional view taken along line A-A' of Figure 5 description. Figure 7 is Figure 4 an enlarged cross-sectional view of a portion EX of

[0042] With reference to Figures 4 to 7 The semiconductor device 100 may include a peripheral circuit structure PS and a cell array structure CS, and the cell array structure CS overlaps the peripheral circuit structure PS in a vertical direction (Z direction) on the peripheral circuit structure PS.

[0043] The peripheral circuit structure PS may include a substrate 50, peripheral circuit transistors PTR on the substrate 50, and a peripheral circuit wiring structure 80 that connects the peripheral circuit transistors PTR to each other or connects the peripheral circuit transistors PTR to components in the cell array structure CS, respectively.

[0044] The substrate 50 may include a semiconductor material, such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI oxide semiconductor. For example, the Group-IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In an exemplary embodiment, the substrate 50 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0045] Active regions AC1, AC2, and AC3 on the substrate 50 may be defined by a device isolation layer 60. The device isolation layer 60 may be in device isolation trenches 60T formed in the substrate 50. In some exemplary embodiments, the device isolation layer 60 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0046] The peripheral circuit transistors PTR may be formed on the active regions AC1, AC2, and AC3, respectively. The peripheral circuit transistors PTR may configure a plurality of peripheral circuits included in the peripheral circuit structure PS. The plurality of peripheral circuits configured with the peripheral circuit transistors PTR may include various circuits included in the peripheral circuit 30 described with reference to Figure 1 In some exemplary embodiments, the plurality of peripheral circuits may include Figure 1 the row decoder 32, page buffer 34, data input / output circuit 36, and control logic 38 shown, as well as a common source line driver (not shown).

[0047] The peripheral circuit transistors PTR may include a first transistor TR1, a second transistor TR2, and a third transistor TR3. The first transistor TR1 is on the first active region AC1, the second transistor TR2 is on the second active region AC2, and the third transistor TR3 is on the third active region AC3. In some exemplary embodiments, the upper surfaces ACS1 of the first active region AC1, ACS2 of the second active region AC2, and ACS3 of the third active region AC3 may be placed at a lower vertical level than the upper surface of the device isolation layer 60.

[0048] In some example embodiments, the upper surface ACS1 of the first active region AC1 may be placed at a vertical level lower than the upper surface ACS2 of the second active region AC2 and the upper surface ACS3 of the third active region AC3. The reason may be that a first region R1 of the substrate 50 corresponding to the first active region AC1 is etched to form a first gate insulating layer GI1 of the first transistor TR1 and a first semiconductor layer Py1 included in the first gate electrode GE1 of the first transistor TR1, as described below with reference to Figure 9A and Figure 9B described.

[0049] In some example embodiments, the upper surface ACS2 of the second active region AC2 may be at the same vertical level as the upper surface ACS3 of the third active region AC3.

[0050] In some example embodiments, the first transistor TR1 may have a first threshold voltage, the second transistor TR2 may have a second threshold voltage lower than the first threshold voltage, and the third transistor TR3 may have a third threshold voltage lower than the first and second threshold voltages.

[0051] In some example embodiments, the first transistor TR1 may be located in a high-voltage region (not shown) of the peripheral circuit structure PS, the second transistor TR2 may be located in a medium-voltage region (not shown) of the peripheral circuit structure PS, and the third transistor TR3 may be located in a low-voltage region (not shown) of the peripheral circuit structure PS.

[0052] The first transistor TR1 may include a first gate structure GS1. The first gate structure GS1 may include a first gate insulating layer GI1, a first gate electrode GE1, a gate capping layer 71, and a gate spacer 73.

[0053] The first gate insulating layer GI1 may cover the entire upper surface ACS1 of the first active region AC1. Accordingly, the first gate insulating layer GI1 may be in contact with the sidewalls of the device isolation layer 60. However, the inventive concept is not limited thereto, and the first gate insulating layer GI1 may cover only a part of the upper surface ACS1 of the first active region AC1. The first gate insulating layer GI1 may include at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0054] The first gate electrode GE1 may be on the first gate insulating layer GI1. The first gate electrode GE1 may include a first semiconductor layer Py1, a second semiconductor layer Py2, a first metal layer BM, and a second metal layer GM. The first semiconductor layer Py1 and the second semiconductor layer Py2 may each include, for example, doped polysilicon. The first metal layer BM may include, for example, a titanium nitride film, a titanium silicon nitride film, or a combination thereof. The second metal layer GM may include, for example, tungsten, aluminum, molybdenum, titanium, or a combination thereof.

[0055] Although Figures 4 to 6 not shown, source / drain regions (not shown) may be further formed on both sides of the first gate structure GS1 in the first active region AC1. For example, the source / drain regions may be doped with impurities.

[0056] The gate capping layer 71 may be on the first gate electrode GE1, and the gate spacer 73 may be on sidewalls of each of the first gate insulating layer GI1, the first gate electrode GE1, and the gate capping layer 71. The gate capping layer 71 and the gate spacer 73 may each include silicon nitride.

[0057] The second transistor TR2 may include a second gate structure GS2. The second gate structure GS2 may include a second gate insulating layer GI2, a work function metal layer WF, a second gate electrode GE2, a gate capping layer 71, and a gate spacer 73.

[0058] The second gate insulating layer GI2 may cover only a part of the upper surface ACS2 of the second active region AC2. Thus, the second gate insulating layer GI2 may be horizontally separated from the sidewall of the device isolation layer 60, and the interlayer insulating layer 90 may be therebetween. However, the inventive concept is not limited thereto, and the second gate insulating layer GI2 may cover the entire upper surface ACS2 of the second active region AC2.

[0059] The second gate insulating layer GI2 may include a first insulating layer MX and a second insulating layer HK sequentially stacked on the second active region AC2. For example, the first insulating layer MX may include at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the second insulating layer HK may include a high-k dielectric film having a higher dielectric constant than the silicon oxide film. For example, the high-k dielectric film may include at least one selected from a hafnium oxide film, a hafnium silicon oxide film, a hafnium aluminum oxide film, a lanthanum oxide film, a zirconium oxide film, a tantalum oxide film, and a titanium oxide film. In some exemplary embodiments, an interface layer (not shown) may be between the first insulating layer MX and the second insulating layer HK. For example, the interface layer may include at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0060] The work function metal layer WF may be on the second gate insulating layer GI2. The work function metal layer WF may perform a function of adjusting the work function of the second gate electrode GE2. The work function metal layer WF may include at least one selected from, for example, a titanium nitride film, a titanium carbonitride film, a tungsten nitride film, and a tungsten carbonitride film.

[0061] The second gate electrode GE2 may be on the work function metal layer WF. The second gate electrode GE2 may include a second semiconductor layer Py2, a first metal layer BM, and a second metal layer GM. The second semiconductor layer Py2, the first metal layer BM, and the second metal layer GM of the second gate electrode GE2 may each include the same or substantially similar materials as the second semiconductor layer Py2, the first metal layer BM, and the second metal layer GM of the first gate electrode GE1.

[0062] Although Figures 4 to 6 not shown, source / drain regions (not shown) may be further formed on both sides of the second gate structure GS2 in the second active region AC2. For example, the source / drain regions may be doped with impurities.

[0063] The gate capping layer 71 may be on the second gate electrode GE2, and the gate spacer 73 may be on the sidewalls of each of the second gate insulating layer GI2, the work function metal layer WF, the second gate electrode GE2, and the gate capping layer 71.

[0064] The third transistor TR3 may include a third gate structure GS3. The third gate structure GS3 may include a third gate insulating layer GI3, a work function metal layer WF, a third gate electrode GE3, a gate capping layer 71, and a gate spacer 73.

[0065] The third gate insulating layer GI3 may cover only a part of the upper surface ACS3 of the third active region AC3. Thus, the third gate insulating layer GI3 may be horizontally separated from the sidewalls of the device isolation layer 60, and the interlayer insulating layer 90 is therebetween. However, the inventive concept is not limited thereto, and the third gate insulating layer GI3 may cover the entire upper surface ACS3 of the third active region AC3.

[0066] The third gate insulating layer GI3 may include the same or substantially similar materials as the second insulating layer HK of the second gate insulating layer GI2. For example, the third gate insulating layer GI3 may include a high-k dielectric film having a dielectric constant higher than that of a silicon oxide film. In some example embodiments, an interface layer (not shown) may be between the third gate insulating layer GI3 and the third active region AC3. For example, the interface layer may include at least one selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0067] The work function metal layer WF may be on the third gate insulating layer GI3. The work function metal layer WF may perform a function of adjusting the work function of the third gate insulating layer GI3. The work function metal layer WF of the third gate structure GS3 may include the same or substantially similar materials as the work function metal layer WF of the second gate structure GS2.

[0068] The third gate electrode GE3 can be on the work function metal layer WF. The third gate electrode GE3 can include a second semiconductor layer Py2, a first metal layer BM, and a second metal layer GM. The second semiconductor layer Py2, the first metal layer BM, and the second metal layer GM of the third gate electrode GE3 can each include materials that are the same as or substantially similar to the materials in the second semiconductor layer Py2, the first metal layer BM, and the second metal layer GM of the first gate electrode GE1.

[0069] Although Figures 4 to 6 not shown, source / drain regions (not shown) can be further formed on both sides of the third gate structure GS3 in the third active region AC3. For example, the source / drain regions can be doped with impurities.

[0070] The gate capping layer 71 can be on the third gate electrode GE3, and the gate spacers 73 can be on the sidewalls of each of the third gate insulating layer GI3, the work function metal layer WF, the third gate electrode GE3, and the gate capping layer 71.

[0071] In some example embodiments, the vertical thickness GI1t of the first gate insulating layer GI1 is greater than the vertical thickness GI2t of the second gate insulating layer GI2. The vertical thickness GI2t can be greater than the vertical thickness GIt3 of the third gate insulating layer GI3.

[0072] In some example embodiments, the horizontal width of the first gate structure GS1 can be greater than the horizontal widths of the second gate structure GS2 and the third gate structure GS3. In some example embodiments, the horizontal width of the second gate structure GS2 can be equal to the horizontal width of the third gate structure GS3.

[0073] In some example embodiments, the upper surfaces of the first gate structure GS1, the second gate structure GS2, and the third gate structure GS3 can all be at the same vertical level.

[0074] In some example embodiments, the upper surface of the first gate insulating layer GI1 of the first gate structure GS1 can be at a vertical level lower than the upper surface ACS2 of the second active region AC2 and the upper surface ACS3 of the third active region AC3. Accordingly, the lower surface of the first semiconductor layer Py1 of the first gate structure GS1 that contacts the upper surface of the first gate insulating layer GI1 of the first gate structure GS1 can also be at a vertical level lower than the upper surface ACS2 of the second active region AC2 and the upper surface ACS3 of the third active region AC3.

[0075] In some example embodiments, the upper surface of the first semiconductor layer Py1 of the first gate structure GS1 may be at the same vertical level as the upper surface of the first insulating layer MX of the second gate structure GS2 and the upper surface of the third gate insulating layer GI3 of the third gate structure GS3.

[0076] The peripheral circuit wiring structure 80 may include a plurality of contacts 82 and a plurality of wiring layers 84. The plurality of wiring layers 84 may have a multilayer structure including a plurality of metal layers at different vertical levels. At least some of the plurality of wiring layers 84 may be electrically connected to the peripheral circuit transistors PTR. The plurality of contacts 82 may connect the peripheral circuit transistors PTR to some selected from the plurality of wiring layers 84.

[0077] The interlayer insulating layer 90 may cover the peripheral circuit transistors PTR and the peripheral circuit wiring structure 80. The interlayer insulating layer 90 may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof.

[0078] The common source plate 110 may be on the interlayer insulating layer 90. The common source plate 110 may be used as a common source line CSL (see Figure 2 ), which supplies current to the vertical memory cells formed in the cell array structure CS. The common source plate 110 may have an opening 120H.

[0079] In some example embodiments, the common source plate 110 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. In some example embodiments, the common source plate 110 may include a doped semiconductor. For example, the common source plate 110 may include polysilicon doped with an n-type impurity. In some example embodiments, the common source plate 110 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline.

[0080] The insulating plug 120 may fill the inside of the opening 120H of the common source plate 110. The insulating plug 120 may have an upper surface at the same vertical level as the upper surface of the common source plate 110. The insulating plug 120 may include, for example, silicon oxide.

[0081] A plurality of gate lines 130 and a plurality of insulating layers 132 may be alternately stacked in the vertical direction (Z direction) on the common source plate 110.

[0082] Multiple gate lines 130 may each include a metal such as tungsten, nickel, cobalt, or tantalum, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide, doped polysilicon, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof. The multiple insulating layers 132 may each include silicon oxide.

[0083] In some example embodiments, the multiple gate lines 130 may correspond to a ground selection line GSL (see Figure 2 ) that forms a memory cell string MS (see Figure 2 ), word lines WL (WL1, WL2, ……, WLn-1, and WLn) (see Figure 2 ), and at least one string selection line SSL (see Figure 2 ). For example, the bottom gate line 130 may be used as the ground selection line GSL, the top two gate lines 130 may be used as the string selection lines SSL, and the other gate lines 130 may be used as word lines WL. Accordingly, a memory cell string MS (see Figure 2 ) may be provided in which a ground selection transistor GST (see Figure 2 ), memory cell transistors MC1, MC2, ……, MCn-1, and MCn (see Figure 2 ), and a string selection transistor SST (see Figure 2 ) are connected in series. In some example embodiments, at least one of the multiple gate lines 130 may be used as a dummy word line, but the inventive concept is not limited thereto.

[0084] The multiple channel structures 140 may extend in a vertical direction (Z direction) from an upper surface of a common source plate 110 through the multiple gate lines 130 and the multiple insulating layers 132. The multiple channel structures 140 may be arranged to be separated from each other at a desired (or alternatively, predetermined) interval in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The multiple channel structures 140 may each include a gate insulating layer 142, a channel layer 144, a buried insulating layer 146, and a conductive plug 148 provided in a channel hole 140H.

[0085] The gate insulating layer 142 and the channel layer 144 may be sequentially arranged on sidewalls of the channel hole 140H. For example, the gate insulating layer 142 may be conformally arranged on the sidewalls of the channel hole 140H, and the channel layer 144 may be conformally arranged on the sidewalls and a bottom surface of the channel hole 140H.

[0086] As Figure 7 shown, the gate insulating layer 142 may include a tunneling dielectric layer 142A, a charge storage layer 142B, and a blocking dielectric layer 142C sequentially arranged on an outer wall of the channel layer 144. The relative thicknesses of the tunneling dielectric layer 142A, the charge storage layer 142B, and the blocking dielectric layer 142C forming the gate insulating layer 142 are not limited to Figure 7Rather than the thickness shown, it can be changed in various ways.

[0087] The tunnel dielectric layer 142A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and the like. The charge storage layer 142B may be a region where electrons tunneling through the tunnel dielectric layer 142A from the channel layer 144 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or doped polysilicon. The blocking dielectric layer 142C may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant higher than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0088] The channel layer 144 may be cylindrical in shape. The channel layer 144 may include doped polysilicon or undoped polysilicon. In some exemplary embodiments, the channel layer 144 may contact the upper surface of the common source electrode plate 110 at the bottom of the channel hole 140H. In some exemplary embodiments, as Figure 4 shown, the bottom surface of the channel layer 144 may be at a vertical level lower than the upper surface of the common source electrode plate 110, but the inventive concept is not limited thereto.

[0089] The buried insulating layer 146 may fill the internal space of the channel layer 144. The buried insulating layer 146 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some exemplary embodiments, the buried insulating layer 146 may be omitted. In this case, the channel layer 144 may have a columnar shape without an internal space.

[0090] The conductive plug 148 may contact the channel layer 144 on the upper side of the channel hole 140H and may block the entrance of the channel hole 140H. The conductive plug 148 may include, for example, a doped polysilicon film.

[0091] As the distance from the upper surface of the common source electrode plate 110 increases, the plurality of gate lines 130 may extend to have a shorter length in the first horizontal direction (X direction). That is, the plurality of gate lines 130 may have a stepped shape. In this case, the edge portions of the plurality of gate lines 130 arranged in a stepped shape may be referred to as a pad structure PAD. The covering insulating layer 134 may be on the pad structure PAD, and the upper insulating layer 136 may be on the plurality of insulating layers 132 and the covering insulating layer 134. The covering insulating layer 134 and the upper insulating layer 136 may each include an oxide film, a nitride film, or a combination thereof.

[0092] The cell contact 182 connected to the pad structure PAD may be located in the cell contact hole 182H that penetrates the overlying insulating layer 134 and the upper insulating layer 136, and the conductive through-via 184 may be located in the through-hole 184H that penetrates the overlying insulating layer 134, the upper insulating layer 136, and the insulating plug 120. Each cell contact 182 may be connected to one of the plurality of gate lines 130 selected therefrom. The cell contact 182 may contact the pad structure PAD of the selected one of the gate lines 130 and be connected to the selected one of the gate lines 130 through the pad structure PAD. The conductive through-via 184 may be connected to the peripheral circuit transistor PTR through the wiring layer 84. The cell contact 182 and the conductive through-via 184 may each include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0093] The bit line contact BLC may penetrate the upper insulating layer 136 to be connected to the channel structure 140. The bit line BL may be on the upper insulating layer 136 and connected to the bit line contact BLC. In addition, the first wiring ML1 connected to the cell contact 182 and the second wiring ML2 connected to the conductive through-via 184 may be disposed on the upper insulating layer 136.

[0094] Generally, the peripheral circuit structure PS may include various peripheral circuit transistors PTR that supply power and signals to the cell array structure CS to drive the cell array structure CS. In this case, in order to increase the capacitance of the transistor and reduce the leakage current, the transistors included in the medium voltage region (e.g., the second transistor TR2) and the transistors included in the low voltage region (e.g., the third transistor TR3) may each be formed to have a gate insulating layer including a high dielectric film and a gate electrode including a metal layer. In addition, in order to improve the operation reliability, the transistors included in the high voltage region (e.g., the first transistor TR1) may include an insulating material such as a silicon oxide film and may be formed to have a gate insulating layer with a relatively large thickness and a gate electrode formed of polysilicon. To form the transistors, an insulating material such as a silicon oxide film may be formed for the transistors included in the high voltage region, a high dielectric material layer and a metal material layer may be formed for the transistors included in the medium voltage region and the transistors included in the low voltage region, the portions of the high dielectric material layer and the metal material layer formed in the high voltage region may be removed, and then a polysilicon layer may be formed for the transistors included in the high voltage region. In this case, in the process of removing the portions of the high dielectric material layer and the metal material layer formed in the high voltage region, the insulating material formed in the high voltage region may be damaged. In this case, the thickness distribution of the gate insulating layer formed of the insulating material of the transistors included in the high voltage region may deteriorate due to the damage, and thus, the operation reliability of the transistors included in the high voltage region may be reduced.

[0095] However, the semiconductor device 100 according to some example embodiments may be formed as follows: forming an insulating material layer constituting a first gate insulating layer GI1, forming a semiconductor material layer constituting a first semiconductor layer Py1 on the insulating material layer, forming a high-k film constituting a second gate insulating layer GI2 and a third gate insulating layer GI3, forming a work function metal layer WF, and removing portions of the high-k film and the work function metal layer WF formed on a first region R1 (see Figure 9A ) corresponding to a high-voltage region. Accordingly, during the process of removing portions of the high-k layer and the work function metal layer WF formed on the first region R1 (see Figure 9A ) corresponding to the high-voltage region, the semiconductor material layer forming the first semiconductor layer Py1 may protect the insulating material layer forming the first gate insulating layer GI1. Thus, the thickness distribution of the first gate insulating layer GI1 may be improved, and the operation reliability of a first transistor TR1 including the first gate insulating layer GI1 may be enhanced.

[0096] Figure 8 FIG. 8 is a cross-sectional view showing a semiconductor device 200 according to an example embodiment. Figure 8 Each component of the semiconductor device 200 shown in FIG. 9 is the same as or substantially similar to each component of the semiconductor device 100 described with reference to Figures 4 to 7 FIG. 10. Accordingly, the following description focuses on the differences between them.

[0097] Referring to Figure 8 FIG. 11, the semiconductor device 200 may include a peripheral circuit structure PS and a cell array structure CS. The cell array structure CS is located on the peripheral circuit structure PS and overlaps the peripheral circuit structure PS in a vertical direction (Z direction).

[0098] In one example embodiment, the semiconductor device 200 may have a chip-to-chip (C2C) structure. The C2C structure may be a structure obtained by: forming the cell array structure CS on a first wafer, forming the peripheral circuit structure PS on a second wafer different from the first wafer, and then connecting the cell array structure CS to the peripheral circuit structure PS by using a bonding method. For example, the bonding method may refer to a method of electrically connecting or physically connecting a first bonding pad BP1 of the peripheral circuit structure PS to a second bonding pad BP2 of the cell array structure CS. In some example embodiments, when each of the first bonding pad BP1 and the second bonding pad BP2 includes copper (Cu), the bonding method may be a Cu-Cu bonding method. In some example embodiments, each of the first bonding pad BP1 and the second bonding pad BP2 may also include aluminum (Al) or tungsten (W).

[0099] The peripheral circuit structure PS may include a substrate 50, peripheral circuit transistors on the substrate 50, and a peripheral circuit wiring structure 80 for connecting the peripheral circuit transistors to each other or connecting the peripheral circuit transistors to components in the cell array structure CS. The peripheral circuit transistors may include a first transistor TR1, a second transistor TR2, and a third transistor TR3. Each component of the peripheral circuit structure PS may be the same as or substantially similar to each component of the peripheral circuit structure PS of the semiconductor device 100 described with reference to Figure 4 and Figure 7 described.

[0100] A plurality of first bonding pads BP1 may be disposed within the interlayer insulating layer 90. The plurality of first bonding pads BP1 may be connected to the peripheral circuit wiring structure 80 through first bonding vias BV1. In an exemplary embodiment, the upper surface of the first bonding pad BP1 may be on the same surface as the upper surface of the interlayer insulating layer 90. The first bonding pad BP1 may include a conductive material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof.

[0101] The cell array structure CS may include a plurality of gate lines 230 and a plurality of insulating layers 232 alternately stacked in the vertical direction (Z direction). The plurality of gate lines 230 and the plurality of insulating layers 232 may be the same as or substantially similar to the plurality of gate lines 130 and the plurality of insulating layers 132 described with reference to Figures 4 to 7 described.

[0102] A plurality of channel structures 240 may extend in the vertical direction (Z direction) from the lower surface of the substrate 210 through the plurality of gate lines 230 and the plurality of insulating layers 232. Each of the plurality of channel structures 240 may include a gate insulating layer 242, a channel layer 244, a buried insulating layer 246, and a conductive plug 248 disposed in a channel hole 240H. The gate insulating layer 242, the channel layer 244, the buried insulating layer 246, and the conductive plug 248 constituting each of the plurality of channel structures 240 may be the same as or substantially similar to the gate insulating layer 142, the channel layer 144, the buried insulating layer 146, and the conductive plug 148 constituting each of the plurality of channel structures 140 described with reference to Figures 4 to 7 described.

[0103] As the distance from the substrate 210 increases, the plurality of gate lines 230 may extend to have a shorter length in the first horizontal direction (X direction). That is, the plurality of gate lines 230 may have an inverted stepped shape. In this case, the edge portions of the plurality of gate lines 230 arranged in the inverted stepped shape may be referred to as the pad structure PAD. The cover insulating layer 234 may be on the pad structure PAD, and the lower insulating layer 236 may be on the plurality of insulating layers 232 and the cover insulating layer 234. The cover insulating layer 234 and the lower insulating layer 236 may each include materials that are the same as or substantially similar to the materials of the plurality of cover insulating layers 134 and the upper insulating layer 136 described with reference to Figures 4 to 7 the description.

[0104] The unit contact 282 connected to the pad structure PAD may be located in the unit contact hole penetrating the cover insulating layer 234 and the lower insulating layer 236, and the conductive via 284 may be located in the via hole penetrating the cover insulating layer 234 and the lower insulating layer 236 and extending into the substrate 210. Each unit contact 282 may contact the pad structure PAD of one gate line 230 selected from the plurality of gate lines 230 and be connected to the selected one gate line 230 through the pad structure PAD. The conductive via 284 may extend into the substrate 210 and be connected to the substrate 210.

[0105] The bit line contact BLC may pass through the lower insulating layer 236 and be connected to the channel structure 240. The bit line BL may be on the lower surface of the lower insulating layer 236 and be connected to the bit line contact BLC. In addition, the first wiring ML1 connected to the unit contact 282 and the second wiring ML2 connected to the conductive via 284 may be arranged on the lower insulating layer 236.

[0106] At least a part of the lower surface of each of the bit line BL, the first wiring ML1, and the second wiring ML2 may contact the second bonding via BV2. The second bonding via BV2 may connect the second bonding pad BP2 in the interlayer insulating layer 260 to at least a part of each of the bit line BL, the first wiring ML1, and the second wiring ML2. The lower surface of the second bonding pad BP2 may contact the upper surface of the first bonding pad BP1. The second bonding pad BP2 may include a conductive material such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof.

[0107] Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25 and Figure 26 are cross-sectional views showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0108] Referring to Figure 9A and Figure 9B , first, a substrate 50 having a first region R1, a second region R2, and a third region R3 may be provided. The first region R1 is a region where a first transistor TR1 (see Figure 4 ) is formed, the second region R2 is a region where a second transistor TR2 (see Figure 4 ) is formed, and the third region R3 is a region where a third transistor TR3 (see Figure 4 ) is formed. Next, a photoresist pattern PR1 having an opening (not shown) exposing the first region R1 is formed on the substrate 50, and by using the photoresist pattern PR1 as an etching mask, the upper surface of the first region R1 of the substrate 50 may be removed to a desired (or alternatively, preset) thickness. By removing the upper surface of the first region R1 of the substrate 50 to a desired (or alternatively, preset) thickness, the upper surface of the first active region AC1 to be formed in the first region R1 may be located at a lower vertical level than the upper surface of the second active region AC2 to be formed in the unetched second region R2 and the upper surface of the third active region AC3 to be formed in the unetched third region R3.

[0109] Referring to Figure 10A and Figure 10B , the first photoresist pattern PR1 may be removed from the Figure 9A and Figure 9B results. Next, a first insulating material layer OX1 and a first semiconductor material layer Pym1 may be sequentially formed on the upper surfaces of the first region R1, the second region R2, and the third region R3 of the substrate 50. The first insulating material layer OX1 may be associated with reference to Figures 4 to 7The material for forming the first gate insulating layer GI1 of the first transistor TR1 is the same or substantially similar. The first semiconductor material layer Pym1 can be the same as or substantially similar to the material of the first semiconductor layer Py1 of the first transistor TR1. In some example embodiments, the first insulating material layer OX1 and the first semiconductor material layer Pym1 can be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a low-pressure CVD (LPCVD) process, etc. The first insulating material layer OX1 can be formed such that the upper surface of the first insulating material layer OX1 in the first region R1 is at a vertical level lower than the upper surface of the substrate 50 in the second region R2 and the third region R3. The first semiconductor material layer Pym1 can be formed such that the upper surface of the first semiconductor material layer Pym1 in the first region R1 is at a vertical level higher than the upper surface of the substrate 50 in the second region R2 and the third region R3.

[0110] Referring to Figure 11A and Figure 11B , a second photoresist pattern PR2 having an opening (not shown) can be formed on the substrate 50, and the opening exposes each of the second region R2 and the third region R3 on the substrate 50. Next, the first insulating material layer OX1 and the first semiconductor material layer Pym1 formed on the second region R2 and the third region R3 of the substrate 50 can be removed by using the second photoresist pattern PR2 as an etching mask. By performing the above process, the first insulating material layer OX1 and the first semiconductor material layer Pym1 can be retained only on the first region R1 of the substrate 50.

[0111] Referring to Figure 12A and Figure 12B , the second photoresist pattern PR2 can be removed from Figure 11A and Figure 11B the results of. Next, a mask material layer MK1 can be formed on the first region R1, the second region R2, and the third region R3 of the substrate 50. The mask material layer MK1 can cover the upper surface of the second region R2, the upper surface of the third region R3, and the upper surface of the first semiconductor material layer Pym1 formed in the first region R1. The mask material layer MK1 can include, for example, silicon nitride.

[0112] Referring to Figure 13A and Figure 13B , in Figure 12A and Figure 12BIn the result, a mask pattern MP1 can be formed by patterning a mask material layer MK1, and a device isolation layer trench 60T can be formed by using the mask pattern MP1 as an etching mask to remove a part of each of the first insulating material layer OX1, the first semiconductor material layer Pym1, and the substrate 50 on the first region R1.

[0113] A first active region AC1 can be defined in the first region R1 of the substrate 50 through the device isolation layer trench 60T formed by the above process, a second active region AC2 can be defined in the second region R2 of the substrate 50, and a third active region AC3 can be defined in the third region R3 of the substrate 50.

[0114] Referring to Figure 14A and Figure 14B , in Figure 13A and Figure 13B In the result, a device isolation layer 60 can be formed by filling the device isolation layer trench 60T with an insulating material and planarizing the insulating material. In this case, the device isolation layer 60 can be formed such that the upper surface of the device isolation layer 60 is at a higher vertical level than the upper surfaces of the first active region AC1, the second active region AC2, and the third active region AC3. Next, the mask pattern MP1 can be removed from the first active region AC1, the second active region AC2, and the third active region AC3. The mask pattern MP1 can be removed by, for example, a lift-off process.

[0115] Referring to Figure 15A and Figure 15B , a second insulating material layer OX2 can be formed to cover the upper surfaces of each of the second active region AC2, the third active region AC3, the device isolation layer 60, and the first semiconductor material layer Pym1. The second insulating material layer OX2 can include a material that is the same as or substantially similar to the material of the first insulating layer MX included in forming the second gate insulating layer GI2 of the second transistor TR2 described in the reference Figures 4 to 7 .

[0116] In some example embodiments, the second insulating material layer OX2 can be formed by an ALD process, a CVD process, a PECVD process, an LPCVD process, etc. The second insulating material layer OX2 can be formed such that the upper surface of the second insulating material layer OX2 on the second active region AC2 is at the same vertical level as the upper surface of the first semiconductor material layer Pym1 on the first active region AC1.

[0117] Referring to Figure 16A and Figure 16B, a third photoresist pattern PR3 having an opening (not shown) exposing the third active region AC3 may be formed on the substrate 50. Next, by using the third photoresist pattern PR3 as an etching mask, the second insulating material layer OX2 formed on the third active region AC3 of the substrate 50 may be removed. By performing the above process, the second insulating material layer OX2 may remain only on the first active region AC1 and the second active region AC2 of the substrate 50.

[0118] Referring to Figure 17A and Figure 17B , in Figure 16A and Figure 16B As a result, the third photoresist pattern PR3 may be removed from the upper surface of the second insulating material layer OX2. Next, a high-k dielectric material layer HKM and a work function metal material layer WFM may be sequentially formed on the third active region AC3 and the second insulating material layer OX2 on the second active region AC2 and the first active region AC1. The high-k dielectric material layer HKM may include a material that is the same as or substantially similar to the material of the second insulating layer HK formed in the second gate insulating layer GI2 of the second transistor TR2 described in Figures 4 to 7 , and the work function metal material layer WFM may include a material that is the same as or substantially similar to the material of each of the work function metal layer WF of the second transistor TR2 and the work function metal layer WF of the third transistor TR3 described in Figures 4 to 7 . In some example embodiments, the high-k dielectric material layer HKM and the work function metal material layer WFM may each be formed by an ALD process, a CVD process, a PECVD process, an LPCVD process, or the like. The high-k dielectric material layer HKM may be formed such that the upper surface of the high-k dielectric material layer HKM on the third active region (AC3) is at the same vertical level as the upper surface of the first semiconductor material layer Pym1 on the first active region AC1 and the upper surface of the second insulating material layer OX2 on the second active region AC2.

[0119] Referring to Figure 18A and Figure 18B , a fourth photoresist pattern PR4 having an opening (not shown) exposing the first active region AC1 may be formed on the substrate 50. Next, the second insulating material layer OX2 formed on the first active region AC1 of the substrate 50 may be removed by using the fourth photoresist pattern PR4 as an etching mask. By performing the above process, the second insulating material layer OX2 may remain only on the second active region AC2 of the substrate 50, and the first semiconductor material layer Pym1 may be exposed.

[0120] Referring to Figure 19A and Figure 19B , in Figure 18A and Figure 18BIn the result, the fourth photoresist pattern PR4 can be removed from the upper surfaces of the work function metal material layers WFM on the second active region AC2 and the third active region AC3. Next, a second semiconductor material layer Pym2, a first metal material layer BMM, a second metal material layer GMM, and a capping material layer 71M can be sequentially formed on the first semiconductor material layer Pym1 and the work function metal material layers WFM on the second active region AC2 and the third active region AC3.

[0121] The second semiconductor material layer Pym2 can include a material that is the same as or substantially similar to the material of the second semiconductor layer Py2 included in the first, second, and third gate electrodes GE1, GE2, and GE3 of the first, second, and third transistors TR1, TR2, and TR3 described with reference to Figures 4 to 7 The first metal material layer BMM can include a material that is the same as or substantially similar to the material of the first metal layer BM included in the first, second, and third gate electrodes GE1, GE2, and GE3 of the first, second, and third transistors TR1, TR2, and TR3 described with reference to Figures 4 to 7 The second metal material layer GMM can include a material that is the same as or substantially similar to the material of the second metal layer GM included in the first, second, and third gate electrodes GE1, GE2, and GE3 of the first, second, and third transistors TR1, TR2, and TR3 described with reference to Figures 4 to 7 The capping material layer 71M can include a material that is the same as or substantially similar to the material of the gate capping layer 71 of the first, second, and third transistors TR1, TR2, and TR3 described with reference to Figures 4 to 7 In some example embodiments, the second semiconductor material layer Pym2, the first metal material layer BMM, the second metal material layer GMM, and the capping material layer 71M can each be formed by an ALD process, a CVD process, a PECVD process, an LPCVD process, or the like.

[0122] The capping material layer 71M can be formed such that the upper surface of the capping material layer 71M can be at the same vertical level in each of the first active region AC1, the second active region AC2, and the third active region AC3.

[0123] With reference to

[0124] and Figure 20A and Figure 20B In Figure 19A and Figure 19BIn the result, the second gate insulating layer GI2, the third gate insulating layer GI3, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the gate capping layer 71 can be formed by patterning the first semiconductor material layer Pym1, the second insulating material layer OX2, the high-k dielectric material layer HKM, the work function metal material layer WFM, the second semiconductor material layer Pym2, the first metal material layer BMM, the second metal material layer GMM, and the capping material layer 71M. In this case, the first insulating material layer OX1 may not be patterned and used as the first gate insulating layer GI1. Next, an insulating layer (not shown) covering the sidewalls of each of the second gate insulating layer GI2, the third gate insulating layer GI3, the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the gate capping layer 71 can be formed, and the gate spacer 73 can be formed by performing an anisotropic etching process on the insulating layer.

[0125] By performing the above processes, the first gate structure GS1 can be formed on the first active region AC1, the second gate structure GS2 can be formed on the second active region AC2, and the third gate structure GS3 can be formed on the third active region AC3.

[0126] Referring to Figure 21 , a peripheral circuit wiring structure 80 and an interlayer insulating layer 90 electrically connected to the first, second, and third gate structures GS1, GS2, and GS3 and the first, second, and third active regions AC1, AC2, and AC3 can be formed.

[0127] Referring to Figure 22 , a common source plate 110 can be formed on the interlayer insulating layer 90. Next, a mask pattern (not shown) can be formed on the common source plate 110, and an opening 120H can be formed by removing a part of the common source plate 110 using the mask pattern as an etching mask. Next, an insulating layer (not shown) can be formed on the common source plate 110 to fill the opening 120H, and an insulating plug 120 can be formed by planarizing the upper portion of the insulating layer until the upper surface of the common source plate 110 is exposed.

[0128] Referring to Figure 23 , a plurality of insulating layers 132 and a plurality of sacrificial layers S130 can be alternately formed on the common source plate 110. In some exemplary embodiments, the plurality of insulating layers 132 may each include an insulating material such as silicon oxide or silicon oxynitride, and the plurality of sacrificial layers S130 may each include silicon nitride, silicon oxynitride, or doped polysilicon, etc.

[0129] Referring to Figure 24, the pad structure PAD can be formed by successively patterning a plurality of insulating layers 132 and a plurality of sacrificial layers S130. In some example embodiments, the pad structure PAD can be formed to have a stepped shape that has a difference in the upper surface level in the first horizontal direction (X direction) (see Figure 4 ). Next, a covering insulating layer 134 covering the pad structure PAD can be formed.

[0130] Referring to Figure 25 , a mask pattern (not shown) can be formed on the plurality of insulating layers 132 and the covering insulating layer 134, and the channel holes 140H can be formed by patterning the plurality of insulating layers 132 and the plurality of sacrificial layers S130 using the mask pattern as an etching mask. Next, a channel structure 140 including a gate insulating layer 142, a channel layer 144, a buried insulating layer 146, and a conductive plug 148 can be formed on the inner wall of the channel holes 140H.

[0131] Although Figure 25 is not shown, a dummy channel structure (not shown) passing through the pad structure PAD can also be formed during the formation of the channel structure 140.

[0132] Next, an upper insulating layer 136 can be formed to cover the uppermost one of the plurality of insulating layers 132, the covering insulating layer 134, and the channel structure 140.

[0133] Referring to Figure 26 , a mask pattern (not shown) can be formed on the upper insulating layer 136, and a gate stack isolation opening (not shown) can be formed by removing portions of the plurality of insulating layers 132 and the plurality of sacrificial layers S130 using the mask pattern as an etching mask. Next, the plurality of sacrificial layers S130 exposed by the inner wall of the gate stack isolation opening can be removed. In some example embodiments, the process of removing the plurality of sacrificial layers S130 can be a wet etching process using a phosphoric acid solution as an etchant. By removing the plurality of sacrificial layers S130, a part of the sidewall of the channel structure 140 can be exposed.

[0134] Next, a plurality of gate lines 130 can be formed in the space where the plurality of sacrificial layers S130 are removed. Thereafter, the inside of the gate stack isolation opening can be filled with an insulating material.

[0135] Next, a bit line contact BLC passing through the upper insulating layer 136 can be formed. In addition, a cell contact hole 182H can be formed to pass through the upper insulating layer 136 and the covering insulating layer 134, and a cell contact 182 can be formed in the cell contact hole 182H. In addition, a conductive through-path 184 can be formed in a through-hole 184H penetrating the upper insulating layer 136, the covering insulating layer 134, and the insulating plug 120.

[0136] Next, a bit line BL connected to the bit line contact BLC may be formed on the upper insulating layer 136, a first wiring ML1 connected to the cell contact 182 and a second wiring ML2 connected to the conductive through-via 184 may be formed, whereby the semiconductor device 100 as shown may be manufactured. Figures 4 to 7 The semiconductor device 100 as shown.

[0137] Figure 27 FIG. is a diagram schematically showing an electronic system including a semiconductor device according to an exemplary embodiment.

[0138] Referring to Figure 27 , an electronic system 1000 according to an exemplary embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at least one semiconductor device 1100.

[0139] The semiconductor device 1100 may be a non-volatile storage device. For example, the semiconductor device 1100 may be a NAND flash memory device including at least one of the structures described above with reference to Figures 4 to 8 the semiconductor devices 100 and 200. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some exemplary embodiments, the first structure 1100F may also be on one side of the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a plurality of bit lines BL, a common source line CSL, a plurality of word lines WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a plurality of memory cell strings CSTR between the plurality of bit lines BL and the common source line CSL.

[0140] In the second structure 1100S, each of the plurality of memory cell strings CSTR may include a first lower transistor LT1 and a second lower transistor LT2 adjacent to the common source line CSL, an upper transistor UT1 and an upper transistor UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary according to exemplary embodiments.

[0141] In some example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The first lower gate line LL1 and the second lower gate line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The plurality of word lines WL may be gate electrodes of the plurality of memory cell transistors MCT, respectively, and the first upper gate line UL1 and the second upper gate line UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0142] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the plurality of word lines WL, and the first upper gate line UL1 and the second upper gate line UL2 may be electrically connected to the decoder circuit 1110 through a plurality of first connection lines extending from the first structure 1100F to the second structure 1100S. The plurality of bit lines BL may be electrically connected to the page buffer 1120 through a plurality of second connection lines extending from the first structure 1100F to the second structure 1100S.

[0143] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform control operations on at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130.

[0144] The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection lines extending from the first structure 1100F to the second structure 1100S.

[0145] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. Depending on the example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0146] The processor 1210 may control all operations of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to preset firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface (I / F) 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, control commands for controlling the semiconductor device 1100, data to be stored in the plurality of memory cell transistors MCT of the semiconductor device 1100, data to be read from the plurality of memory cell transistors MCT of the semiconductor device 1100, etc. may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0147] Figure 28 is a perspective view schematically showing an electronic system including a semiconductor device according to an exemplary embodiment.

[0148] Referring to Figure 28 , the electronic system 2000 according to an exemplary embodiment may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a plurality of wiring patterns 2005 formed on the main board 2001.

[0149] The main board 2001 may include a connector 2006 that includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins included in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some exemplary embodiments, the electronic system 2000 may communicate with an external host according to any one of interfaces such as USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and Universal Flash Storage M-Phy (UFS). In some exemplary embodiments, the electronic system 2000 may operate using power supplied from an external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0150] The controller 2002 may write data to or read data from the semiconductor package 2003 and may increase the operating speed of the electronic system 2000.

[0151] The DRAM 2004 can be a buffer memory for reducing the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 can operate as a cache memory and can also provide a space for temporarily storing data during the control operation of the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 can further include a DRAM controller for controlling the DRAM 2004.

[0152] The semiconductor package 2003 can include a first semiconductor package 2003a and a second semiconductor package 2003b that are separated from each other. The first semiconductor package 2003a and the second semiconductor package 2003b can each include a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b can each include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 for electrically connecting the plurality of semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 on the package substrate 2100 that covers the plurality of semiconductor chips 2200 and the connection structure 2400.

[0153] The package substrate 2100 can be a printed circuit board including a plurality of package top pads 2130. Each of the plurality of semiconductor chips 2200 can include input / output pads 2210. The input / output pads 2210 can correspond to Figure 27 the input / output pads 1101. Each of the plurality of semiconductor chips 2200 can include a plurality of gate stacks and a plurality of channel structures. Each of the plurality of semiconductor chips 2200 can include at least one of the structures described above with reference to Figures 4 to 8 the semiconductor devices 100 and 200.

[0154] In some example embodiments, the connection structure 2400 can include bonding wires that electrically connect the input / output pads 2210 to the package top pads 2130, respectively. Thus, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 can be electrically connected to each other by the bonding wire method and can be electrically connected to the package top pads 2130 of the package substrate 2100. In some example embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 can also be electrically connected to each other by a connection structure including a through electrode (through-silicon via (TSV)) instead of the connection structure 2400 of the bonding wire method.

[0155] In some example embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some example embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main board 2001, and the controller 2002 may also be connected to the plurality of semiconductor chips 2200 through wires formed on the interposer substrate.

[0156] Figure 29 is a cross-sectional view schematically showing a semiconductor package according to an example embodiment. Figure 29 More specifically shown along Figure 28 the configuration taken along line II-II'.

[0157] Referring to Figure 29 , the package substrate 2100 of the semiconductor package 2003 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a plurality of package upper pads 2130 disposed on the upper surface of the package substrate body 2120 (see Figure 28 ), a plurality of lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface of the package substrate body 2120, and a plurality of internal wires 2135 inside the package substrate body 2120 that electrically connect the plurality of upper pads 2130 to the plurality of lower pads 2125. The plurality of upper pads 2130 may be electrically connected to the plurality of connection structures 2400 (see Figure 28 ). The plurality of lower pads 2125 may be connected to a plurality of wiring patterns 2005 on the main board 2001 of the electronic system 2000 shown in Figure 28 through a plurality of conductive connectors 2800.

[0158] Each of the plurality of semiconductor chips 2200 may include a semiconductor substrate and a first structure and a second structure sequentially stacked on the semiconductor substrate. The first structure may include a peripheral circuit region that includes a plurality of peripheral wires. The second structure may include a common source line, a gate stack on the common source line, a channel structure passing through the gate stack, a plurality of bit lines electrically connected to the channel structure, and gate connection wires that are electrically connected through contacts to a plurality of word lines (WL in Figure 27 ) included in the gate stack. In some example embodiments, each of the plurality of semiconductor chips 2200 may include at least one of the structures described above with reference to Figures 4 to 8 for the semiconductor devices 100 and 200.

[0159] Multiple semiconductor chips 2200 may each include multiple peripheral wires electrically connected to a first structure and extending to through-wires in a second structure. The through-wires may be disposed outside the gate stack. In some example embodiments, the semiconductor package 2003 may further include through-wires that pass through the gate stack. Multiple semiconductor chips 2200 may each further include input / output pads ( Figure 28 2210 in

[0160] Any functional blocks shown in the figures and described above may be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0161] As described above, some example embodiments are disclosed in the drawings and the specification. Although certain terms are used to describe the example embodiments in the inventive concept, this is only for the purpose of describing the technical idea of the inventive concept and not for limiting the meaning or scope of the inventive concept as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent example embodiments can be derived therefrom. Therefore, the true technical protection scope of the inventive concept should be determined by the technical idea of the appended claims.

[0162] Although the inventive concept has been specifically shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0163] Cross-reference to Related Applications

[0164] This application is based on and claims priority to Korean Patent Application No. 10-2023-0197639, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A substrate including a first active region, a second active region and a third active region defined by a device isolation layer; a first transistor on the first active region, the first active region comprising a first gate structure, the first gate structure comprising a first gate insulating layer on the first active region and a first gate electrode on the first gate insulating layer; a second transistor on the second active region, the second active region comprising a second gate structure, the second gate structure comprising a second gate insulating layer on the second active region, a work function metal layer on the second gate insulating layer, and a second gate electrode on the work function metal layer, the second gate insulating layer comprising a high dielectric layer, and the second gate electrode comprising a metal; and a third transistor on the third active region, the third active region comprising a third gate structure, the third gate structure comprising a third gate insulating layer on the third active region, a work function metal layer on the third gate insulating layer, and a third gate electrode on the work function metal layer, the third gate insulating layer comprising a high dielectric layer, and the third gate electrode comprising a metal, The first gate electrode includes a first semiconductor layer and a second semiconductor layer which are sequentially located on the first gate insulating layer and each include polysilicon.

2. The semiconductor device according to claim 1, wherein An upper surface of the first gate structure is at the same vertical level as upper surfaces of the second gate structure and upper surfaces of the third gate structure.

3. The semiconductor device according to claim 1, wherein An upper surface of the first gate insulating layer is at a lower vertical level than upper surfaces of the second active region and upper surfaces of the third active region.

4. The semiconductor device according to claim 1, wherein: The second gate insulating layer includes a first insulating layer on the second active region and a second insulating layer on the first insulating layer, the first insulating layer includes silicon oxide, and the second insulating layer includes a high dielectric layer.

5. The semiconductor device according to claim 4, wherein: An upper surface of the first semiconductor layer is at the same vertical level as an upper surface of the first insulating layer.

6. The semiconductor device according to claim 1, wherein An upper surface of the first semiconductor layer and an upper surface of the third gate insulating layer are at the same vertical level.

7. The semiconductor device according to claim 1, wherein The thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer, and the thickness of the second gate insulating layer is greater than the thickness of the third gate insulating layer.

8. The semiconductor device according to claim 1, wherein The first transistor has a first threshold voltage, the second transistor has a second threshold voltage lower than the first threshold voltage, and the third transistor has a third threshold voltage lower than the second threshold voltage.

9. A semiconductor device comprising: A peripheral circuit structure on a substrate; as well as a cell array structure on the peripheral circuit structure, the cell array structure comprising a plurality of memory cells provided in a vertical direction perpendicular to an upper surface of the substrate, The peripheral circuit structure includes: a device isolation layer on the substrate and defining a first active region, a second active region and a third active region, a first gate structure on the first active region, the first gate structure comprising a first gate insulating layer and a first gate electrode on the first gate insulating layer, a second gate structure on the second active region, the second gate structure comprising a second gate insulating layer, a work function metal layer on the second gate insulating layer, and a second gate electrode on the work function metal layer, the second gate insulating layer comprising a high dielectric layer, the second gate electrode comprising a metal, and a third gate structure on the third active region, the third gate structure comprising a third gate insulating layer, a work function metal layer on the third gate insulating layer, and a third gate electrode on the work function metal layer, the third gate insulating layer comprising a high dielectric layer, the third gate electrode comprising a metal, and The first gate electrode includes a first semiconductor layer and a second semiconductor layer which are sequentially formed on the first gate insulating layer and each include polysilicon.

10. The semiconductor device according to claim 9, wherein The cell array structure comprises: a common source plate on the peripheral circuit structure; a plurality of gate electrodes on the common source plate and separated from each other in the vertical direction; and A channel structure extends from an upper surface of the common source plate along the vertical direction by passing through the plurality of gate electrodes.

11. The semiconductor device according to claim 9, wherein The cell array structure further includes a plurality of first bonding pads, The peripheral circuit structure further includes a plurality of second bonding pads, and The first bonding pads are bonded to corresponding second bonding pads of the second bonding pads, respectively.

12. The semiconductor device according to claim 9, wherein: An upper surface of the first gate structure is at the same vertical level as upper surfaces of the second gate structure and upper surfaces of the third gate structure.

13. The semiconductor device according to claim 9, wherein: An upper surface of the first gate insulating layer is at a lower vertical level than upper surfaces of the second active region and upper surfaces of the third active region.

14. The semiconductor device according to claim 13, wherein The second gate insulating layer includes a first insulating layer on the second active region and a second insulating layer on the first insulating layer, the first insulating layer includes silicon oxide, the second insulating layer includes a high dielectric layer, and An upper surface of the first semiconductor layer is at the same vertical level as an upper surface of the first insulating layer.

15. The semiconductor device according to claim 9, wherein: An upper surface of the first semiconductor layer and an upper surface of the third gate insulating layer are at the same vertical level.

16. The semiconductor device according to claim 9, wherein: The thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer, and the thickness of the second gate insulating layer is greater than the thickness of the third gate insulating layer.

17. The semiconductor device according to claim 9, wherein: The first active region and the first gate structure constitute a first transistor having a first threshold voltage, the second active region and the second gate structure constitute a second transistor having a second threshold voltage lower than the first threshold voltage, and the third active region and the third gate structure constitute a third transistor having a third threshold voltage lower than the second threshold voltage.

18. An electronic system comprising: Motherboard; A semiconductor device on the main board; as well as a controller electrically connected to the semiconductor device on the main board, The semiconductor device comprises: Peripheral circuit structures on the substrate, and a cell array structure on the peripheral circuit structure, the cell array structure comprising a plurality of memory cells provided in a vertical direction perpendicular to an upper surface of the substrate, The peripheral circuit structure includes: a device isolation layer on the substrate and defining a first active region, a second active region and a third active region, a first gate structure on the first active region, the first gate structure comprising a first gate insulating layer and a first gate electrode on the first gate insulating layer, the first gate insulating layer comprising a silicon oxide film, a second gate structure on the second active region, the second gate structure comprising a second gate insulating layer, a work function metal layer on the second gate insulating layer, and a second gate electrode on the work function metal layer, the second gate insulating layer comprising a first insulating layer and a second insulating layer, the first insulating layer comprising a silicon oxide film, the second insulating layer comprising a high dielectric film, the second gate electrode comprising a metal, and a third gate structure on the third active region, the third gate structure comprising a third gate insulating layer, a work function metal layer on the third gate insulating layer, and a third gate electrode on the work function metal layer, the third gate insulating layer comprising a high dielectric layer, and the third gate electrode comprising a metal, wherein the first gate electrode comprises a first semiconductor layer and a second semiconductor layer which are sequentially formed on the first gate insulating layer and each comprise polysilicon, and The upper surface of the first semiconductor layer is at the same vertical level as the upper surfaces of the first insulating layer and the third gate insulating layer. 19 . The electronic system of claim 18 , wherein an upper surface of the first gate structure is at the same vertical level as upper surfaces of the second gate structure and of the third gate structure.

20. The electronic system according to claim 18, wherein: The first active region and the first gate structure constitute a first transistor having a first threshold voltage, the second active region and the second gate structure constitute a second transistor having a second threshold voltage lower than the first threshold voltage, and the third active region and the third gate structure constitute a third transistor having a third threshold voltage lower than the second threshold voltage.

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