Multi-gate transistor and preparation method thereof

Abstract

The invention discloses a multi-gate transistor and a preparation method thereof. The multi-gate transistor comprises a semiconductor epitaxial structure, a gate electrode, a source electrode matched with the gate electrode and a drain electrode, the semiconductor epitaxial structure is provided with an active region and a non-active region at least partially surrounding the active region; the grid electrode comprises a grid bar and N grid fingers, the grid bar is arranged in the non-active region and extends in the first direction, and the grid fingers are electrically connected with the grid bar and extend to the active region in the second direction; the first direction is intersected with the second direction; the extending length of the grid bars in the first direction is larger than a first preset value. The maximum oscillation frequency of the multi-gate transistor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a multi-gate finger transistor and a manufacturing method thereof. Background Art

[0002] Multi-gate finger transistors have important applications in the field of modern semiconductor technology and have good performance at high frequencies. However, as the operating frequency becomes higher and higher, how to further improve the maximum oscillation frequency of multi-gate finger transistors has become a technical problem to be solved urgently. Summary of the Invention

[0003] The present invention provides a multi-gate finger transistor and a manufacturing method thereof to improve the maximum oscillation frequency of the multi-gate finger transistor.

[0004] According to one aspect of the present invention, a multi-gate finger transistor is provided. The multi-gate finger transistor includes a semiconductor epitaxial structure, a gate, a source electrode and a drain electrode that cooperate with the gate;

[0005] The semiconductor epitaxial structure has an active region and a non-active region that at least partially surrounds the active region;

[0006] The gate includes a gate bar and N gate fingers. The gate bar is disposed in the non-active region and extends along a first direction. The gate fingers are electrically connected to the gate bar and extend along a second direction to the active region; the first direction intersects the second direction;

[0007] The length of the gate bar extending along the first direction is greater than a first preset value.

[0008] Optionally, the first preset value is the length of the gate bar along the first direction in the originally designed multi-gate finger transistor.

[0009] Optionally, N is greater than a second preset value, and the second preset value is the number of gate fingers in the originally designed multi-gate finger transistor; the sum of the lengths of the N gate fingers extending along the second direction is a third preset value, and the third preset value is the sum of the lengths of all the gate fingers along the second direction in the originally designed multi-gate finger transistor; the length of the gate finger extending along the second direction is less than a fourth preset value, and the fourth preset value is the length of the gate finger along the second direction in the originally designed multi-gate finger transistor.

[0010] Optionally, when the length of the gate finger extending along the second direction is greater than or equal to half of the fourth preset value, N is less than or equal to 2 times the second preset value.

[0011] Optionally, the N gate fingers are evenly distributed.

[0012] Optionally, the source includes a plurality of source fingers extending in the second direction; the drain includes a drain bar and a plurality of drain fingers, the drain bar extends in the first direction and is located in the non-active region; the drain fingers are electrically connected to the drain bar and extend in the second direction to the active region;

[0013] The drain bar and the gate bar are respectively located in the non-active regions on both sides of the active region.

[0014] According to another aspect of the present invention, a method for manufacturing a multi-gate finger transistor is provided, including:

[0015] Obtain the design parameters of the original designed multi-gate finger transistor, wherein the design parameters include a first preset value, and the first preset value is the length of the gate bar along the first direction in the original designed multi-gate finger transistor;

[0016] Form an active region and at least a partially surrounding non-active region on the semiconductor epitaxial structure;

[0017] Form a gate bar and a plurality of gate fingers constituting the gate on the semiconductor epitaxial structure; wherein the gate bar is disposed in the non-active region and extends in the first direction, the gate fingers are electrically connected to the gate bar and extend in the second direction to the active region; the first direction intersects the second direction; the length of the gate bar extending along the first direction is greater than the first preset value.

[0018] Optionally, forming the gate on the semiconductor epitaxial structure includes:

[0019] Form N gate fingers with the sum of the lengths extending in the second direction being a third preset value, and the third preset value is the sum of the lengths of all the gate fingers extending in the second direction in the original designed multi-gate finger transistor; the length of the gate fingers extending in the second direction is less than a fourth preset value, and the fourth preset value is the length of the gate fingers extending in the second direction in the original designed multi-gate finger transistor; N is greater than a second preset value, and the second preset value is the number of gate fingers in the original designed multi-gate finger transistor.

[0020] Optionally, when the length of the gate fingers extending in the second direction is greater than or equal to half of the fourth preset value, N is less than or equal to 2 times the second preset value.

[0021] Optionally, forming the gate bar and a plurality of gate fingers constituting the gate on the semiconductor epitaxial structure includes:

[0022] Form the plurality of gate fingers to be evenly distributed.

[0023] The technical solution of the embodiment of the present invention adopts a multi-gate finger transistor, which includes a semiconductor epitaxial structure, a gate, a source electrode and a drain electrode that cooperate with the gate; the semiconductor epitaxial structure has an active region and a non-active region that at least partially surrounds the active region; the gate includes a gate bar and N gate fingers, the gate bar is arranged in the non-active region and extends along a first direction, the gate fingers are electrically connected to the gate bar and extend along a second direction to the active region; the first direction intersects with the second direction; the length of the gate bar extending along the first direction is greater than a first preset value. Since the gate bar has a relatively large length in the direction perpendicular to its current flow direction, that is, a relatively large cross-sectional area, the resistance of the gate bar is reduced, so that the gate resistance is small, and the maximum oscillation frequency of the multi-gate finger transistor can be improved. In addition, it is not necessary to increase the thickness of the gate metal, so it is not necessary to modify the process parameters of gate manufacturing, and only the mask needs to be changed, and the cost is also low. At the same time, reducing the gate resistance can also improve the device efficiency and device performance.

[0024] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 It is a schematic structural diagram of a multi-gate finger transistor provided by an embodiment of the present invention;

[0027] Figure 2 is Figure 1 A cross-sectional view along the A1A2 direction;

[0028] Figure 3 is Figure 1 A cross-sectional view along the A3A4 direction;

[0029] Figure 4 It is a schematic diagram of the equivalent resistance of the gate in the multi-gate finger transistor;

[0030] Figure 5 It is a flowchart of a preparation method of a multi-gate finger transistor provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0033] Figure 1 It is a schematic structural diagram of a multi-gate finger transistor provided by an embodiment of the present invention. Figure 2 is Figure 1 a cross-sectional view along the A1A2 direction. Figure 3 is Figure 1 a cross-sectional view along the A3A4 direction, combined with Figures 1 to 3 The multi-gate finger transistor includes a semiconductor epitaxial structure 1, a gate 2, a source electrode and a drain electrode 3 that cooperate with the gate 2; the semiconductor epitaxial structure 1 has an active region 11 and a non-active region 12 that at least partially surrounds the active region 11; the gate 2 includes a gate bar 21 and N gate fingers 22, the gate bar 21 is disposed in the non-active region 12 and extends along the first direction Y, the gate fingers 22 are electrically connected to the gate bar 21 and extend along the second direction X to the active region 11; the first direction Y intersects the second direction X; the length of the gate bar 22 extending along the first direction Y is greater than a first preset value.

[0034] Specifically, a multi-finger gate transistor has an active region 11 and a non-active region 12. There is a conductive channel inside the active region 11, while there is generally no conductive channel in the non-active region 12. The active region 11 and the non-active region 12 can be formed by processes such as etching, or can be formed by means such as ion implantation. The active region 11 contains multiple source regions, drain regions, and gate regions, making the equivalent transistor have a large width (w width) on the order of hundreds of micrometers, and can instantaneously discharge the current caused by a large amount of static electricity. Therefore, it has important applications in fields such as ESD protection. In related technologies, the length of the gate bar 21 along the first direction Y in the multi-finger gate transistor is relatively short, and it generally does not exceed a first preset value. As Figure 4 shown, Figure 4 is the schematic diagram of the gate equivalent resistance in the multi-finger gate transistor, where Rg2 is the resistance of the gate bar 21, and Rg1 is the resistance of the finger 22. In the multi-finger gate transistor, the current direction in the active region 11 is along the first direction Y, that is, the current direction in the finger 22 is the first direction Y; in the gate bar 21, the current direction is the second direction X. Therefore, the total resistance of the gate 2 is the parallel total resistance of N fingers 22 in series with the resistance of the gate bar 21, that is Figure 4 in the circuit connection structure. According to the highest cut-off frequency formula of the transistor: where f max is the highest cut-off frequency, f T is the transistor characteristic frequency; R g is the gate resistance; C gd is the gate-drain parasitic capacitance; G ds is the output conductance; R in is the input resistance. It can be seen from the above formula that the smaller the gate resistance, the larger the highest cut-off frequency, that is, the larger the highest oscillation frequency.

[0035] In related technologies, due to the short length of the gate bar 21 along the first direction Y, according to the resistance formula, the cross-sectional area of the gate bar 21 is small, which results in a large resistance of the gate bar 21. In this embodiment, by setting the length of the gate bar 21 along the first direction Y to be greater than the first preset value, the resistance of the gate bar is made smaller, which also makes the gate resistance smaller, and thus the highest oscillation frequency of the transistor can be improved.

[0036] The technical solution of this embodiment uses a multi-gate finger transistor, which includes a semiconductor epitaxial structure, a gate, a source electrode and a drain electrode that cooperate with the gate; the semiconductor epitaxial structure has an active region and a non-active region that at least partially surrounds the active region; the gate includes a gate bar and N gate fingers, the gate bar is arranged in the non-active region and extends along a first direction, the gate fingers are electrically connected to the gate bar and extend along a second direction to the active region; the first direction intersects the second direction; the length of the gate bar extending along the first direction is greater than a first preset value. Since the length of the gate bar in the direction perpendicular to its current flow direction is relatively large, that is, the cross-sectional area is relatively large, the resistance of the gate bar is reduced, so that the gate resistance is small, and the maximum oscillation frequency of the multi-gate finger transistor can be increased. In addition, there is no need to increase the thickness of the gate metal, so there is no need to modify the process parameters of gate manufacturing. Only the mask needs to be changed, and the cost is also low. At the same time, reducing the gate resistance can also improve the device efficiency and device performance.

[0037] Optionally, the first preset value is the length of the gate bar along the first direction in the original designed multi-gate finger transistor. The multi-gate finger transistor of this application can be improved based on the original designed multi-gate finger transistor. In the original design, the length of the gate bar generally does not exceed the first preset value, which results in a relatively large gate resistance. In this embodiment, the length of the gate bar is increased based on the original design, thereby reducing the gate resistance and increasing the maximum oscillation frequency of the multi-gate finger transistor.

[0038] Optionally, N is greater than a second preset value, and the second preset value is the number of gate fingers in the original designed multi-gate finger transistor; the sum of the lengths of the N gate fingers extending along the second direction X is a third preset value, and the third preset value is the sum of the lengths of all the gate fingers in the original designed multi-gate finger transistor extending along the second direction X; the length of the gate finger 22 extending along the second direction Y is less than a fourth preset value, and the fourth preset value is the length of the gate finger in the original designed multi-gate finger transistor extending along the second direction X.

[0039] Specifically, according to the characteristic frequency formula of the transistor wherein, v sat is the channel electron saturation velocity, L gLet \(L_g\) be the gate length. It can be known that the characteristic frequency is related to the gate length of the transistor. When the characteristic parameters of the transistor are determined, its gate length is also fixed. The solution of this embodiment can increase the maximum cut-off frequency of the multi-gate finger transistor without changing the gate length. Specifically, in the original design of the multi-gate finger transistor, assume there are \(M\) gate fingers, that is, the second preset value is \(M\), and the length of each gate finger extending along the second direction \(X\) is \(L_1\), that is, the fourth preset value is \(L_1\). Then the gate length in the original design of the multi-gate finger transistor is \(M\times L_1\), that is, the third preset value is \(M\times L_1\). In this embodiment, on this basis, the length of the gate finger is truncated so that the length of the gate finger is \(L_2\), \(L_2\lt L_1\). Of course, preferably, the lengths of all gate fingers extending along the second direction \(X\) are equal. And control \(N\times L_2 = M\times L_1\), so as to increase the maximum cut-off frequency of the multi-gate finger transistor without increasing the gate length. And if the length of the gate finger extending along the second direction remains unchanged and only the length of the gate bar extending along the first direction is increased, the area of the multi-gate finger transistor will increase, which is not conducive to improving the integration degree. In this embodiment, the length of the gate finger extending along the second direction is shortened, so that the size of the multi-gate finger transistor in the second direction becomes smaller. Therefore, although its size in the first direction becomes larger, it will not increase too much or will not increase the overall size of the multi-gate finger transistor, thus ensuring that the multi-gate finger transistor has a high integration degree.

[0040] In the above embodiment, the size of the gate finger in the second direction becomes smaller and the number of gate fingers increases, but it will not increase the overall resistance after all gate fingers are connected in parallel. The reason is that: as Figure 4 shown, assume that the resistance of the gate finger in the original design is \(R_{g1y}\), and the total resistance \(R_1\) after \(M\) resistors are connected in parallel satisfies After improvement, the total resistance \(R_2\) after \(N\) gate fingers are connected in parallel satisfies Substitute the resistance formula into the above two formulas to get: According to the above analysis of the current flow direction, in the formula, \(L\) is the width of the gate finger along the first direction \(X\), and the size of \(L\) remains unchanged in the original design and after improvement. And \(S_1 = L_1\times h\), \(S_2 = L_2\times h\), where \(h\) is the thickness of the gate finger, and \(h\) is also the same in the original design and after improvement. Finally, we can get Also, because \(N\times L_2 = M\times L_1\), we can get That is, \(R_1 = R_2\), that is, the total resistance of the gate finger after improvement remains unchanged, but because the resistance of the gate bar becomes smaller, the total resistance of the gate electrode becomes smaller.

[0041] In summary, it can be seen from the above analysis that this embodiment reduces the total resistance of the gate electrode without increasing the total length of the gate finger extending along the second direction \(X\), that is, it improves the maximum cut-off frequency of the multi-gate finger transistor without changing the characteristic parameters of the multi-gate finger transistor and stabilizing the radio frequency performance.

[0042] Optionally, in the above embodiments, when the length of the improved gate finger 22 extending along the second direction X is greater than or equal to half of the fourth preset value, N is less than or equal to twice the second preset value M, that is, N≤2*M. In this embodiment, if the length of the improved gate finger 22 extending along the second direction X is equal to half of the fourth preset value, the improved design can be understood as truncating the design length of the gate fingers in the original multi-gate finger transistor by half, and then arranging the truncated gate fingers along the first direction with the original gate fingers to form new gate fingers, that is, N = 2*M. If the length of the improved gate finger 22 extending along the second direction X is greater than half of the fourth preset value, the improved design can be understood as combining the extracted parts from the gate fingers and arranging them with the original gate fingers to form new gate fingers, that is, N < 2*M. In this embodiment, the length of the gate finger extending along the second direction is not too short, which can avoid a large parasitic capacitance caused by the close distance between the gate bar 21 and the drain bar.

[0043] Optionally, in the above embodiments, the multiple gate fingers are evenly distributed. In other words, the distances between the improved gate fingers are equal, so that the electric field distribution in the multi-gate finger transistor can be relatively uniform, thereby improving the working stability of the multi-gate finger transistor.

[0044] Optionally, continuing to refer to Figures 1 to 3 , the source electrode includes multiple source fingers 42 extending along the second direction X; the drain electrode 3 includes a drain bar 31 and multiple drain fingers 32. The drain bar 31 extends along the first direction Y and is located in the non-active region; the drain fingers 32 are electrically connected to the drain bar 31 and extend along the second direction X to the active region 11; the drain bar 31 and the gate bar 21 are respectively located in the non-active regions 12 on both sides of the active region 11.

[0045] Specifically, in this embodiment, the adjacent source fingers 42, gate fingers 22, and drain fingers 32 form the three poles corresponding to the sub-transistor. The numbers of the source fingers 42, gate fingers 22, and drain fingers 32 can be the same. It can also be as shown in Figure 1 that the number of gate fingers is the largest, while the numbers of drain fingers and source fingers are smaller due to the reuse between adjacent sub-transistors, which can further improve the integration. In this embodiment, the source electrode and the drain electrode can be formed by metal high-temperature annealing, or by ion implantation, or by regrowth of heavily doped N-type GaN.

[0046] Optionally, the gate electrode can form a Schottky contact with a metal material (such as nickel tungsten and other metals) and AlGaN / GaN, or can form a Schottky contact with a metal and a p-GaN / AlGaN / GaN heterostructure.

[0047] Optionally, the semiconductor epitaxial structure 1 can be a semiconductor structure such as an aluminum gallium nitride / gallium nitride heterostructure, an aluminum gallium arsenide / gallium arsenide heterostructure, a silicon carbide structure, or silicon.

[0048] An embodiment of the present invention also provides a method for manufacturing a multi-gate finger transistor, which is improved based on the original design of the multi-gate finger transistor. As Figure 5 shown, Figure 5 FIG. 4 is a flowchart of a method for manufacturing a multi-gate finger transistor provided by an embodiment of the present invention. The method includes:

[0049] Step S110, obtaining design parameters of the original design multi-gate finger transistor; wherein, the design parameters include a first preset value, and the first preset value is the length of the gate bar along the first direction in the original design multi-gate finger transistor;

[0050] Step S120, forming an active region and at least a partially surrounding non-active region on the semiconductor epitaxial structure;

[0051] Step S130, forming gate bars and a plurality of gate fingers constituting the gate on the semiconductor epitaxial structure; wherein, the gate bars are arranged in the non-active region and extend along the first direction, the gate fingers are electrically connected to the gate bars and extend along the second direction to the active region; the first direction intersects the second direction; the length of the gate bar extending along the first direction is greater than the first preset value.

[0052] Specifically, the method for manufacturing a multi-gate finger transistor in this embodiment can manufacture the multi-gate finger transistor provided in any embodiment of the present invention. Among them, the active region 11 and the non-active region 12 can be formed by processes such as etching, or can be formed by means such as ion implantation. In the related art, since the length of the gate bar 21 along the first direction Y is short, according to the resistance formula, the cross-sectional area of the gate bar 21 is small, which results in a large resistance of the gate bar 21. In this embodiment, by setting the length of the gate bar 21 along the first direction Y to be greater than the first preset value, the resistance of the gate bar is made smaller, and thus the gate resistance is made smaller, which can further improve the maximum oscillation frequency of the transistor.

[0053] The technical solution of this embodiment, for the multi-gate finger transistor manufactured by the method for manufacturing a multi-gate finger transistor adopted, since the length of the gate bar along the direction perpendicular to its current flow direction is large, that is, the cross-sectional area is large, the resistance of the gate bar is reduced, so that the gate resistance is small, and the maximum oscillation frequency of the multi-gate finger transistor can be improved. In addition, there is no need to increase the thickness of the gate metal, so there is no need to modify the process parameters of gate manufacturing. Only the mask needs to be changed, and the cost is also low. At the same time, reducing the gate resistance can also improve the device efficiency and device performance.

[0054] Optionally, in this embodiment, obtaining the design parameters of the original designed multi-gate finger transistor further includes obtaining a second preset value, a third preset value, and a fourth preset value. The second preset value is the number of gate fingers in the original designed multi-gate finger transistor; the third preset value is the sum of the lengths of all the gate fingers in the original designed multi-gate finger transistor extending along the second direction; the length of the gate finger extending along the second direction is less than the fourth preset value, and the fourth preset value is the length of the gate finger in the original designed multi-gate finger transistor extending along the second direction.

[0055] Forming a gate on the semiconductor epitaxial structure further includes:

[0056] Forming N gate fingers with the sum of the lengths extending along the second direction being the third preset value.

[0057] Specifically, the solution of this embodiment can increase the maximum cut-off frequency of the multi-gate finger transistor without changing the gate length. Specifically, assume there are M gate fingers in the original designed multi-gate finger transistor, that is, the second preset value is M, and the length of each gate finger extending along the second direction X is L1, that is, the fourth preset value is L1. Then the gate length in the original designed multi-gate finger transistor is M * L1, that is, the third preset value is M * L1. In this embodiment, on this basis, the length of the gate finger is truncated so that the length of the gate finger is L2, L2 < L1. Of course, preferably, the lengths of all the gate fingers extending along the second direction X are equal. And control N * L2 = M * L1, thereby increasing the maximum cut-off frequency of the multi-gate finger transistor without increasing the gate length. And if the length of the gate finger extending along the second direction remains unchanged and only the length of the gate bar extending along the first direction is increased, the area of the multi-gate finger transistor will increase, which is not conducive to improving the integration degree. In this embodiment, the length of the gate finger extending along the second direction is shortened, so that the size of the multi-gate finger transistor in the second direction becomes smaller. Therefore, although its size in the first direction becomes larger, it will not increase or will not increase the overall size of the multi-gate finger transistor too much, thereby ensuring that the multi-gate finger transistor has a high integration degree.

[0058] In the above-mentioned embodiment, the size of the gate finger in the second direction becomes smaller, and the number of gate fingers increases, and it will not increase the overall resistance after all the gate fingers are connected in parallel. The reason is as described in the part of the multi-gate finger transistor structure of this invention embodiment, which will not be elaborated here.

[0059] Based on the above analysis, it can be seen that this embodiment reduces the total gate resistance without increasing the total length of the gate fingers extending along the second direction X. That is, without changing the characteristic parameters of the multi-gate finger transistor and stabilizing the radio frequency performance, the maximum cut-off frequency of the multi-gate finger transistor is increased.

[0060] Optionally, in the above embodiments, the length of the improved gate finger 22 extending along the second direction X is greater than or equal to half of the fourth preset value. In this embodiment, if the length of the improved gate finger 22 extending along the second direction X is equal to half of the fourth preset value, the improved design can be understood as truncating the design length of the gate fingers in the original multi-gate finger transistor by half, and then arranging the truncated gate fingers along the first direction with the original gate fingers to form new gate fingers. If the length of the improved gate finger 22 extending along the second direction X is greater than half of the fourth preset value, the improved design can be understood as combining the extracted parts from the gate fingers and arranging them with the original gate fingers to form new gate fingers. In this embodiment, the length of the gate finger extending along the second direction is not too short, which can avoid a large parasitic capacitance caused by a short distance between the gate bar 21 and the drain bar.

[0061] Optionally, in the above embodiments, the multiple gate fingers are evenly distributed. In other words, the distances between the improved gate fingers are equal, so that the electric field distribution in the multi-gate finger transistor is relatively uniform, thereby improving the working stability of the multi-gate finger transistor.

[0062] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0063] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A multi-gate finger transistor, characterized in that, The multi-gate finger transistor includes a semiconductor epitaxial structure, a gate, a source electrode and a drain electrode that cooperate with the gate; The semiconductor epitaxial structure has an active region and a non-active region that at least partially surrounds the active region; The gate includes a gate bar and N gate fingers. The gate bar is disposed in the non-active region and extends along a first direction. The gate fingers are electrically connected to the gate bar and extend along a second direction to the active region; the first direction intersects the second direction; The length of the gate bar extending along the first direction is greater than a first preset value.

2. The multi-gate finger transistor according to claim 1, wherein The first preset value is the length of the gate bar along the first direction in the original designed multi-gate finger transistor.

3. The multi-gate finger transistor according to claim 2, characterized in that, N is greater than a second preset value, and the second preset value is the number of gate fingers in the original designed multi-gate finger transistor; the sum of the lengths of the N gate fingers extending along the second direction is a third preset value, and the third preset value is the sum of the lengths of all the gate fingers in the original designed multi-gate finger transistor extending along the second direction; the length of the gate finger extending along the second direction is less than a fourth preset value, and the fourth preset value is the length of the gate finger in the original designed multi-gate finger transistor extending along the second direction.

4. The multi-gate finger transistor according to claim 3, characterized in that, When the length of the gate finger extending along the second direction is greater than or equal to half of the fourth preset value, N is less than or equal to 2 times the second preset value.

5. The multi-gate finger transistor according to claim 1, characterized in that, The N gate fingers are evenly distributed.

6. The multi-gate finger transistor according to claim 1, characterized in that, The source electrode includes a plurality of source fingers extending along the second direction; the drain electrode includes a drain bar and a plurality of drain fingers. The drain bar extends along the first direction and is located in the non-active region; the drain fingers are electrically connected to the drain bar and extend along the second direction to the active region; The drain bar and the gate bar are respectively located in the non-active regions on both sides of the active region.

7. A method for manufacturing a multi-gate finger transistor, characterized in that, Comprising: Obtain the design parameters of the original designed multi-gate finger transistor, wherein the design parameters include a first preset value, and the first preset value is the length of the gate bar along the first direction in the original designed multi-gate finger transistor; Form an active region and a non-active region that at least partially surrounds the active region on the semiconductor epitaxial structure; Form a gate bar and a plurality of gate fingers that constitute a gate on the semiconductor epitaxial structure; wherein, the gate bar is disposed in the non-active region and extends along a first direction, the gate fingers are electrically connected to the gate bar and extend along a second direction to the active region; the first direction intersects the second direction; the length of the gate bar extending along the first direction is greater than the first preset value.

8. The manufacturing method of the multi-gate finger transistor according to claim 7, characterized in that, The forming the gate on the semiconductor epitaxial structure includes: Form N gate fingers whose sum of the lengths extending along the second direction is a third preset value, and the third preset value is the sum of the lengths of all the gate fingers in the original designed multi-gate finger transistor extending along the second direction; the length of the gate finger extending along the second direction is less than a fourth preset value, and the fourth preset value is the length of the gate finger in the original designed multi-gate finger transistor extending along the second direction; N is greater than a second preset value, and the second preset value is the number of gate fingers in the original designed multi-gate finger transistor.

9. The manufacturing method of the multi-gate finger transistor according to claim 8, characterized in that, When the length of the gate finger extending along the second direction is greater than or equal to half of the fourth preset value, N is less than or equal to 2 times the second preset value.

10. The manufacturing method of the multi-gate finger transistor according to claim 7, characterized in that, Forming the gate bars and a plurality of gate fingers constituting the gate on the semiconductor epitaxial structure includes: Forming the plurality of gate fingers with uniform distribution.

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