Image sensor and preparation method thereof

Abstract

According to the image sensor disclosed by the invention, the functions of at least two transistors in adjacent pixel sub-arrays are set to be the same, and at least one transistor with the same function is set to share one grid, so that the requirements on the shape and the size of an opening of an isolation groove are avoided, and the process difficulty of an isolation groove flow is greatly reduced; the isolation distance between the function tube and the surrounding vertical transfer transistor, the floating diffusion region and the like can be larger, meanwhile, the number of needed metal connecting wires is greatly reduced, the layout of a metal layer is simplified, the area of an image sensor chip is reduced, and the production cost is reduced; the symmetry and compactness of the whole layout of the image sensor array are improved, the yield loss caused by asymmetry is reduced, and the production cost is reduced; and the compatibility degree in the aspects of structural design, manufacturing process and the like of pixels shared by different photodiode numbers is improved.

Description

Technical Field

[0001] The present invention relates to the field of sensors, and particularly to an image sensor and a method for manufacturing the same. Background Art

[0002] With the rapid development and wide application of image sensors, the performance requirements for image sensors are increasing day by day. In order to meet the high pixel requirements of image sensors, the size of sensor pixels is getting smaller and smaller, and the requirements for the process are also getting higher and higher. Based on the current process design, in the pixel layout design of existing image sensors, transistors with corresponding required functions are usually designed specifically for corresponding pixels. Since multiple transistors arranged in the pixel interval area need to meet different functions, it is difficult to manufacture them, and the manufactured image sensors do not have advantages in terms of size, quality, etc. The current pixel layout design has formed bottlenecks in improving sensor quality, reducing costs, etc.

[0003] For example, as Figure 1a-1b shown, Figure 1a is an equivalent circuit diagram of an existing 3T 4shared (3T: that is, having a source follower transistor (SF), a gain conversion transistor (DCG), and an RST (reset transistor), without a selection transistor (SEL); 4shared: that is, 4 photodiodes share 3T). Figure 1b is a partial layer schematic diagram of the layout design of an existing 3T 4shared image sensor array, Figure 1c is a schematic diagram of different transistors on both sides of the corresponding isolation trench, Figure 1d is based on Figure 1b a simplified schematic diagram (note: Figure 1d is only a schematic diagram, and the boundary lines do not represent the actual boundary). Define a pixel unit p. A pixel sub-array s-pa includes 4 shared pixel units p. Multiple pixel sub-arrays s-pa are arranged in an array along the horizontal and vertical directions to form the photosensitive array of the image sensor. Among them, a pixel unit p may include a photodiode, and the pixel unit p may also include a transfer transistor Tx. It can be seen that in the layout of the existing pixel sub-array s-pa, the source follower transistor (SF) is placed on one side of the floating diffusion region column direction, the gate is connected to the floating diffusion region, the drain is connected to the high voltage, and the source is used as the output signal terminal PXD; the gain conversion transistor (DCG) and the reset transistor (RST) are placed on one side of the floating diffusion region row direction. The source of the gain conversion transistor (DCG) is connected to the floating diffusion region, the drain of the gain conversion transistor (DCG) is connected to the source of the reset transistor (RST), and the drain of the reset transistor (RST) is connected to the high voltage terminal. Among them, as Figure 1c-1dAs shown, the DCG (Gain Conversion Transistor) and RST (Reset Transistor) are respectively arranged on both sides of the same trench PBT (Isolation Trench Structure (PBTrench, PBT), and PBT can be a deep trench or a shallow trench). Their gates G1 and G2 are separated by a distance L through the trench PBT, and the sources S1, S2 and the drains D1, D2 are also separated by the trench PBT. For adjacent pixel sub-arrays, transistors with different functions are respectively on both sides of the trench. The gates of the same-function transistors in the same row are led out by a single row selection line, and the gates of the same-function transistors in different rows are respectively led out by their respective row selection lines. Taking the Figure 1c-1d schematically shown DCG and RST as an example, since the DCG (Gain Conversion Transistor) and RST (Reset Transistor) have different functions, they need to have different operating timings. For a certain function transistor, a single row selection line is required for each row. In such a layout requirement, during the manufacturing process, the gates of these two transistors need to be cut using an etching process. Due to the resolution limitations of photolithography and etching, sufficient distance L needs to be considered reserved between the gates of these two adjacent transistors to ensure that the two gates can be completely etched and disconnected during the process; however, due to density limitations, in the existing design, only the groove width dimension can be designed to be larger than the isolation limit of the existing surrounding pixel units, and the isolation interval of the pixel units needs to be designed even larger to meet the requirement of reserving sufficient distance L. This significantly affects the layout utilization rate of the components in the optical sensor array, hinders the improvement of the pixel density of the image sensor, and is not conducive to the further reduction of the size of the image sensor. On the other hand, the larger trench opening line width also brings difficulties to the polysilicon filling step. Since it is difficult to ensure the same growth rate at different depths throughout the groove during the trench filling growth process, a large opening is likely to cause some areas in the groove to be unfilled, leaving cavities with uncontrollable sizes. Such cavities have a serious impact on the cleanliness and consistency of subsequent processes.

[0004] Furthermore, in order to balance device quality, production cost, etc., different numbers of pixel units are usually designed to be shared. The aforementioned problems existing in the 3T 4shared form of image sensors also exist in image sensors with further increased shared pixel units. Moreover, in the prior art, dedicated circuit layout arrangements and manufacturing processes are usually designed corresponding to different pixel unit sharing forms one by one, and different pixel unit sharing forms are difficult to be compatible with each other. This has led to a doubling of both the circuit layout design cost and the subsequent device manufacturing process cost, bringing great difficulties to the cost reduction and mass production of enterprises.

[0005] Therefore, it has become increasingly urgent to re-think the pixel layout design scheme to solve the aforementioned series of problems in order to improve the quality of the image sensor and reduce costs. Summary of the Invention

[0006] To solve the above problems, the present disclosure provides an image sensor. The image sensor includes an image sensor photosensitive array composed of a plurality of pixel sub-arrays. The pixel sub-array includes a plurality of pixel units and transistors with different functions. The pixel unit includes a photodiode. At least one type of transistor with the same function in adjacent pixel sub-arrays shares a common gate to optimize the process and wiring of the image sensor. Among them, the transistors include one or more of a source follower transistor, a reset transistor, a gain conversion transistor, and a selection transistor.

[0007] In a preferred embodiment, the transistors with the same function sharing a common gate include at least two, and the at least two transistors with the same function achieve channel isolation through isolation trenches.

[0008] In a preferred embodiment, the channels of the two transistors with the same function sharing a common gate are parallel to each other.

[0009] In a preferred embodiment, the sources and drains of the two transistors with the same function sharing a common gate are isolated through isolation trenches.

[0010] In a preferred embodiment, the shared common gate extends along the row direction, or along the column direction, or along a direction at a 45° angle to the row or column direction.

[0011] In a preferred embodiment, the source follower transistor is exclusive to its corresponding pixel sub-array.

[0012] In a preferred embodiment, for at least one of the reset transistor, the gain conversion transistor, and the selection transistor, there are transistors with the same function sharing a common gate for adjacent pixel sub-arrays.

[0013] In a preferred embodiment, the manner in which the transistors with the same function share a common gate for adjacent pixel sub-arrays includes: Two transistors with the same function sharing a common gate are respectively exclusive to adjacent different pixel sub-arrays; Or, two transistors with the same function sharing a common gate are jointly shared by adjacent different pixel sub-arrays.

[0014] In a preferred embodiment, the adjacent includes adjacent in the row direction and / or adjacent in the column direction.

[0015] In a preferred embodiment, each pixel sub-array includes one reset transistor, one gain conversion transistor, one or two source follower transistors, and 4 shared pixel units.

[0016] In a preferred embodiment, in the first direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate.

[0017] In a preferred embodiment, there are adjacent first pixel sub-array and second pixel sub-array with different transistor functional arrangement positions. The first pixel sub-array and the second pixel sub-array form a pixel module. The image sensor photosensitive array is formed by repeatedly arranging the pixel module in the first direction and the second direction, and the first direction and the second direction are orthogonal.

[0018] In a preferred embodiment, in the first pixel sub-array, the reset transistor is located on the first side in the first direction of the first pixel sub-array, and the gain conversion transistor is located on the second side in the first direction of the first pixel sub-array; in the second pixel sub-array, the reset transistor is located on the second side in the first direction of the second pixel sub-array, and the gain conversion transistor is located on the first side in the first direction of the second pixel sub-array; and the reset transistor and the gain conversion transistor are located in the same row.

[0019] In a preferred embodiment, the source follower transistor is located on one of the two sides in the second direction of the pixel sub-array.

[0020] In a preferred embodiment, each pixel sub-array includes a plurality of the reset transistors, a plurality of gain conversion transistors, a plurality of source follower transistors, a plurality of selection transistors, and 8, or 9, or 16 shared pixel units.

[0021] In a preferred embodiment, the plurality of gain conversion transistors of each pixel sub-array includes a plurality of first gain conversion transistors and a plurality of second gain conversion transistors; When the pixel sub-array includes 8 shared pixel units, each pixel sub-array includes a reset transistor, a first gain conversion transistor reset transistor, and a second gain conversion transistor; When the pixel sub-array includes 9 shared pixel units, each pixel sub-array includes a reset transistor and a first gain conversion transistor, and the plurality of second gain conversion transistors includes a plurality of first sub-gain conversion transistors and a plurality of second sub-gain conversion transistors; When the pixel sub-array includes 16 shared pixel units, the plurality of gain conversion transistors further includes two third gain conversion transistors, and each pixel sub-array includes two reset transistors, two first gain conversion transistors, two second gain conversion transistors, and two third gain conversion transistors.

[0022] In a preferred embodiment, when the pixel sub-array includes 9 shared pixel units, the pixel sub-arrays adjacent in the first direction share the plurality of second sub-gain conversion transistors, and the pixel sub-arrays adjacent in the second direction share the plurality of first sub-gain conversion transistors; When the pixel sub-array includes 16 shared pixel units, in the second direction, the third gain conversion transistors of the adjacent pixel sub-arrays are shared, and / or, in the first direction, the second gain conversion transistors of the adjacent pixel sub-arrays are shared.

[0023] In a preferred embodiment, when the pixel sub-array includes 8 shared pixel units, the reset transistor and the first gain conversion transistor are respectively located on two sides of the first direction of the pixel sub-array and in the same row, and the second gain conversion transistor is located on one side of the second direction of the pixel sub-array and is not in the same row or column as the reset transistor and the first gain conversion transistor; When the pixel sub-array includes 9 shared pixel units, the reset transistor and the first sub-gain conversion transistor are respectively located on two sides of the second direction of the pixel sub-array and are not in the same row or column, and the first gain conversion transistor and the plurality of second sub-gain conversion transistors are respectively located on two sides of the first direction of the pixel sub-array and are not in the same row or column; When the pixel sub-array includes 16 shared pixel units, the two reset transistors are in the same row and are located on one side of the second direction of the pixel sub-array, the two first gain conversion transistors are in the same row and are respectively located on two sides of the first direction of the pixel sub-array, the two second gain conversion transistors are in the same row and are respectively located on two sides of the first direction of the pixel sub-array, and the two third gain conversion transistors are in the same row and are located on the other side of the second direction of the pixel sub-array; wherein, the reset transistor, the first gain conversion transistor, the second gain conversion transistor, and the third gain conversion transistor are respectively in different rows.

[0024] In a preferred embodiment, when the pixel sub-array includes 8 shared pixel units, in the first direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate; in the second direction, the second gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate; When the pixel sub-array includes 9 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a common gate, and every two of the shared second sub-gain conversion transistors share a common gate; in the second direction, the reset transistors respectively located in adjacent pixel sub-arrays share a common gate, and every two of the shared first sub-gain conversion transistors share a common gate; When the pixel sub-array includes 16 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a common gate, and the second gain conversion transistors respectively located in adjacent pixel sub-arrays share a common gate; in the second direction, the reset transistors respectively located in adjacent pixel sub-arrays share a common gate, and the third gain conversion transistors respectively located in adjacent pixel sub-arrays share a common gate.

[0025] In a preferred embodiment, when the pixel sub-array includes 8 shared pixel units, the pixel sub-array includes two source follower transistors and two selection transistors exclusive to it, the two source follower transistors share a common gate, and the two selection transistors share a common gate, and the selection transistors are not in the same row as the source follower transistors, reset transistors, first gain conversion transistors, and second gain conversion transistors; When the pixel sub-array includes 9 shared pixel units, the pixel sub-array includes two source follower transistors and two selection transistors exclusive to it, the two source follower transistors share a common gate, and the two selection transistors share a common gate, the source follower transistors are in the same row as the first gain conversion transistors, and the selection transistors are in the same column as the reset transistors; When the pixel sub-array includes 16 shared pixel units, the pixel sub-array includes six source follower transistors and two selection transistors exclusive to it, every two of the source follower transistors share a common gate to form a group, and the two selection transistors share a common gate, the source follower transistors are either in the same row as the first gain conversion transistors, or in the same row as the second gain conversion transistors, or in the same column as the reset transistors and third gain conversion transistors, and the selection transistors are in the same column as the reset transistors and third gain conversion transistors that are not in the same column as the source follower transistors; or, the pixel sub-array includes four source follower transistors and four selection transistors exclusive to it, every two of the source follower transistors share a common gate to form a group, and every two of the two selection transistors share a common gate, the source follower transistors are either in the same row as the first gain conversion transistors, or in the same row as the second gain conversion transistors, and the selection transistors are in the same column as the reset transistors and third gain conversion transistors.

[0026] In a preferred embodiment, when the pixel sub-array includes 8 shared pixel units, the source follower transistor is located inside the pixel sub-array, and the selection transistor is located on one side of the pixel sub-array in the first direction; when the pixel sub-array includes 9 or 16 shared pixel units, both the source follower transistor and the selection transistor are located inside the pixel sub-array.

[0027] In a preferred embodiment, the gate terminal of the first sub-gain conversion transistor is connected to a control signal; the gate terminal of the second sub-gain conversion transistor is grounded.

[0028] In a preferred embodiment, when the pixel sub-array includes 8 shared pixel units, each pixel sub-array further includes a reserved function transistor. In the second direction, the second gain conversion transistor and the reserved function transistor are respectively located on both sides of the pixel sub-array. Among them, the gate, source, and drain terminals of the reserved function transistor are all connected to a high level for controlling interface leakage.

[0029] In a preferred embodiment, there are a first pixel sub-array, a second pixel sub-array, a third pixel sub-array, and a fourth pixel sub-array with different transistor function arrangement positions. The first pixel sub-array, the second pixel sub-array, the third pixel sub-array, and the fourth pixel sub-array form a pixel module. The image sensor photosensitive array is formed by repeatedly arranging the pixel modules in the first direction and the second direction.

[0030] In a preferred embodiment, in the first direction, the first pixel sub-array and the second pixel sub-array are adjacent, and the third pixel sub-array and the fourth pixel sub-array are adjacent; in the second direction, the first pixel sub-array and the third pixel sub-array are adjacent, and the second pixel sub-array and the fourth pixel sub-array are adjacent; the first direction is orthogonal to the second direction; the pixel module is symmetric about the boundary adjacent line of any two of the first pixel sub-array, the second pixel sub-array, the third pixel sub-array, and the fourth pixel sub-array.

[0031] In a preferred embodiment, when 8 shared pixel units are shared, the 8 shared pixel units are arranged in 4 rows and 2 columns; when 9 shared pixel units are shared, the 9 shared pixel units are arranged in 3 rows and 3 columns; when 16 shared pixel units are shared, the 16 shared pixel units are arranged in 4 rows and 4 columns.

[0032] In addition, a method for manufacturing an image sensor is also provided, which is used to manufacture the image sensor described in any of the foregoing embodiments. Among them, transistors with at least one same function in adjacent pixel sub-arrays are arranged on both sides of a trench, and a common gate electrode of the transistors with the same function is fabricated to optimize the process and wiring of the image sensor.

[0033] The image sensor provided by the present disclosure sets the functions of at least two adjacent transistors to be the same, and transistors with at least one same function in adjacent pixel sub-arrays are set to share one gate, having the following beneficial effects: (1) It avoids separating the gates of two adjacent transistors to avoid the requirements for the opening shape of the isolation trench during the fabrication of transistors, greatly reducing the process difficulty of the isolation trench process.

[0034] (2) It reduces the layout size, enabling a larger isolation distance between the functional transistors and the surrounding vertical transfer transistors, floating diffusion regions, etc., and can improve the fabrication density of the device.

[0035] (3) Due to the merging of the gates of transistors with the same function, the number of control lines required can be greatly reduced, simplifying the layout of the metal layer layout and reducing production costs.

[0036] (4) Setting transistors with at least one same function to share one gate can make the functional transistors arranged symmetrically, uniformly, and consistently, thereby improving the symmetry and compactness of the entire layout of the image sensor array, reducing the yield loss caused by asymmetry differences, shrinking the area of the image sensor chip, and reducing the production cost of the image sensor.

[0037] (5) By setting the functions of at least two transistors in adjacent pixel sub-arrays to be the same and sharing one gate, the structural design, manufacturing process, etc. shared by different pixel unit numbers can be highly compatible, greatly promoting cost reduction and mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described by way of exemplary embodiments, which will be described in detail through the drawings. These embodiments are not restrictive. In these embodiments, the same numbers represent the same structures, where: Figure 1a is a schematic diagram of the equivalent circuit of the sensor in the prior art.

[0039] Figure 1b is a schematic layout diagram of the sensor in the prior art.

[0040] Figure 1c is a simplified schematic diagram of the transistors on both sides of the isolation trench in the prior art.

[0041] Figure 1d is a simplified schematic diagram of the pixel arrangement of the sensor in the prior art.

[0042] Figure 2a is a simplified schematic diagram of the pixel arrangement of the sensor of the present disclosure.

[0043] Figure 2bSchematic diagram of transistors with the same function in the present disclosure sharing a gate.

[0044] Figure 3a Schematic diagram of the equivalent circuit of multiple pixel sub-arrays of the sensor according to the first embodiment of the present disclosure.

[0045] Figure 3b Schematic diagram of the circuit layout of the sensor according to the first embodiment of the present disclosure.

[0046] Figure 3c Simplified schematic diagram of the pixel arrangement of the sensor according to the first embodiment of the present disclosure.

[0047] Figure 3d Schematic diagram of the circuit layout according to the first embodiment of the present disclosure.

[0048] Figure 4a Schematic diagram of the basic equivalent circuit of 4T8shared.

[0049] Figure 4b Schematic diagram of the equivalent circuit of a pixel sub-array according to the second embodiment of the present disclosure.

[0050] Figure 4c Schematic diagram of the equivalent circuit of multiple pixel sub-arrays of the sensor according to the second embodiment of the present disclosure.

[0051] Figure 4d Simplified schematic diagram of the pixel arrangement according to the second embodiment of the present disclosure.

[0052] Figure 4e Schematic diagram of the circuit layout according to the second embodiment of the present disclosure.

[0053] Figure 5a Schematic diagram of the basic equivalent circuit of 4T9shared.

[0054] Figure 5b Schematic diagram of the equivalent circuit of a pixel sub-array according to the third embodiment of the present disclosure.

[0055] Figure 5c Schematic diagram of the equivalent circuit of multiple pixel sub-arrays of the sensor according to the third embodiment of the present disclosure.

[0056] Figure 5d Simplified schematic diagram of the pixel arrangement according to the third embodiment of the present disclosure.

[0057] Figure 5e Schematic diagram of the circuit layout according to the third embodiment of the present disclosure.

[0058] Figure 6a-1 Schematic diagram of an equivalent circuit of a pixel sub-array according to the fourth embodiment of the present disclosure.

[0059] Figure 6a-2Another equivalent circuit diagram of a pixel sub-array according to the fourth embodiment of the present disclosure.

[0060] Figure 6b-1 An equivalent circuit diagram of multiple pixel sub-arrays of a sensor according to the fourth embodiment of the present disclosure.

[0061] Figure 6b-2 Another equivalent circuit diagram of multiple pixel sub-arrays of a sensor according to the fourth embodiment of the present disclosure.

[0062] Figure 6c-1 A simplified schematic diagram of pixel arrangement according to the fourth embodiment of the present disclosure.

[0063] Figure 6c-2 Another simplified schematic diagram of pixel arrangement according to the fourth embodiment of the present disclosure.

[0064] Figure 6d -1~6d-4 is an example of a circuit layout schematic diagram according to the fourth embodiment of the present disclosure. Detailed implementation manners

[0065] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, the present invention can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structures or operations.

[0066] Regarding the problems mentioned in the background art, specific embodiments will be described below for illustration.

[0067] The present disclosure provides an image sensor, as Figure 2a (Note: This drawing is only a schematic diagram, used to indicate the existence of each structure. The line directions do not represent the actual boundary traces, and the spacing distances do not represent the actual situation) shown, which is a simplified schematic diagram of the pixel arrangement of the sensor of the present disclosure. Tr represents a module where at least two transistors with the same function share a gate, corresponding to forming a group of transistors Tr, attached Figure 2aAmong them, the extending direction of the long side of the module schematically shown by the transistor group Tr represents the arranging direction of two or more transistors with the same function sharing a gate, and also represents the extending direction of the shared gate of the transistor group Tr. The shared gate can extend along the row direction, or along the column direction, or along a direction at a 45° angle to the row or column direction, and can be reasonably designed according to the specific situation of the spacing area between the pixel units p. p represents a pixel unit. A pixel sub-array can include several pixel units p and several transistors with different functions. Multiple pixel sub-arrays can form an image sensor photosensitive array, and the image sensor photosensitive array is used to form an image sensor. Among them, the pixel unit p can include a photodiode and can also include a transfer transistor Tx. Among them, at least one type of transistor with the same function in adjacent pixel sub-arrays shares a gate, and a group of transistors Tr sharing a gate is used to provide one or more functions including but not limited to a source follower transistor, a reset transistor, a gain conversion transistor, and a selection transistor to optimize the process and wiring of the image sensor.

[0068] Further, as Figure 2a shown, the pixel units p are arranged in an array by repeating in the first direction (row direction, or X direction) and the second direction (column direction, or Y direction), and a pixel spacing is formed between adjacent pixel units p. Among them, the first transistor group Tr-x formed by arranging two or more transistors with the same function in the first direction (i.e., the shared gate extends along the row direction) is arranged in columns at an interval of two rows of pixel units p in the second direction and is arranged in rows at an interval of two columns of pixel units p in the first direction; the second transistor group Tr-y formed by arranging two or more transistors with the same function in the second direction (i.e., the shared gate extends along the column direction) is arranged in columns at an interval of two rows of pixel units p in the second direction and is arranged in rows at an interval of two columns of pixel units p in the first direction; moreover, the first transistor group Tr-x and the second transistor group Tr-y are not in the same row and not in the same column, and the first transistor group Tr-x and the second transistor group Tr-y are formed in the pixel spacing area formed between adjacent pixel units p. By setting the functions of adjacent transistors on both sides of the trench to be the same, the requirement for the opening shape of the isolation trench during the manufacture of transistors is avoided by separating the gates of two adjacent transistors, and the process difficulty of the isolation trench process is greatly reduced. According to this appendix Figure 2aThe shown layout can significantly improve the symmetry and compactness of the entire layout of the image sensor array, reduce the yield loss caused by asymmetric differences, shrink the area of the image sensor chip, and lower the production cost of the image sensor. Moreover, this layout can be adapted to image sensors designed and fabricated with different numbers of shared pixel units p. During the layout design phase, only the functions of the transistor groups Tr around the pixel units p need to be reasonably designed according to the circuits required for the actual number of shared pixel units p. This process only requires changing the wiring of the metal layer. During the process of fabrication, only the metal layer wiring needs to be concerned. That is to say, except for the wiring metal layer, other structural designs and manufacturing processes required to implement image sensors with different numbers of shared pixel units can be compatible, which can greatly promote the cost reduction and mass production of image sensors. Moreover, due to the merging of the gates of transistors with the same function in the transistor group Tr, the number of control lines required can be greatly reduced, and the metal layer wiring can also be greatly simplified, which can further shrink the device size and lower the production cost. (Note: The situation of the number of rows in the interval is only for the relatively simplified schematic diagram. In the actual layout, the rows and columns of different components often have curved profiles and are mutually interlocked. Therefore, the intervals mentioned throughout this article are not limited to the absolute interval situation. For example, for two adjacent Tr-x in the first row, there is actually no absolute interval of two columns, but they are respectively formed within the intervals of two columns of pixel units p.) As Figure 2b shown, it is a schematic diagram of a transistor group Tr formed by two transistors with the same function sharing a gate. The two transistors with the same function respectively include source-drain electrodes S1, D1, and S2, D2, and the two transistors with the same function share a gate G. The transistor group Tr only represents that the transistors with the same function within the group share a gate and does not represent a specific function. That is, the transistor group Tr and another transistor group Tr can have the same function or different functions. Figure 2a schematically shows that the transistor groups Tr are arranged in sequence within the intervals of each pixel unit p, which is the most preferred situation. However, in other specific embodiments, for the number of rows or columns in each direction interval, it may not be limited to the aforementioned two rows and two columns. For example: in the first direction, the transistor groups Tr are arranged with an interval of greater than or equal to two columns of pixel units p, and in the second direction, the transistor groups Tr are arranged with an interval of greater than or equal to two rows of pixel units p; and the column positions where the transistor groups Tr are located in the first direction are separated from the column positions where the transistor groups Tr are located in the second direction by an interval of greater than or equal to 1 column. For ease of understanding, it can be as Figure 2a shown, the closest-positioned first transistor group Tr-x and second transistor group Tr-y are separated by an interval of greater than or equal to 1 column. Moreover, it is not limited to such as Figure 2aThe global arrangement of the shown sensor array is made. In other embodiments, according to actual needs, only a part of the layout of the sensor array can be arranged in this way. For example, only the periphery or a part of the corners of the sensor array can be arranged as described above, or only the center of the sensor array can be arranged as described above.

[0069] Preferably, transistors with the same function share a gate. For example, it can be one or more of the following: two source-follower transistors share a gate, two reset transistors for resetting share a gate, two gain-conversion transistors for gain conversion share a gate, two selection transistors for selection output share a gate. It can also be other transistors with the same function sharing a gate. Preferably, the number of transistors with the same function sharing a gate is not limited to two, and can also be more than two, such as three, four, etc.

[0070] Preferably, the group of transistors Tr with the same function sharing a gate includes at least two, and the channels of at least two transistors with the same function are isolated by isolation trenches. Among them, the channels of two transistors with the same function sharing a gate are parallel to each other. Optionally, the channels of two transistors with the same function sharing a gate can also form a certain angle on both sides of the isolation trench respectively. For example, the channels of the transistors extend at a certain angle along the direction of the extension of the isolation trench, such as extending in the direction of a 45° angle. Preferably, the channels of two transistors with the same function sharing a gate are symmetric about the isolation trench.

[0071] Preferably, the source and drain of two transistors with the same function sharing a gate are also isolated by isolation trenches. Among them, two transistors with the same function sharing a gate are located on both sides of the isolation trench respectively. Preferably, two transistors with the same function sharing a gate are substantially symmetric about the isolation trench. For example, substantial symmetry can include: at least one of the source, channel, and drain of two transistors with the same function is substantially symmetric about the isolation trench, and / or the shared gate of two transistors with the same function is also substantially symmetric about the isolation trench. Through the symmetric arrangement, the symmetry of the photosensitive array can be improved, the utilization rate of the area can be increased, and the defects caused by the symmetry difference of the devices can be reduced.

[0072] Preferably, the shared gate of two transistors with the same function sharing a gate extends in the row direction, or in the column direction, or in a direction forming a certain angle with the row or column direction. For example, it extends in a direction forming an angle of 45° with the row or column direction. Among them, the extending direction of the isolation trench can also extend roughly in the row direction, or in the column direction, or in a direction forming a certain angle with the row or column direction. For example, it extends in a direction forming an angle of 45° with the row or column direction. Preferably, the shared gate of two transistors with the same function sharing a gate is orthogonal to the extending direction of the isolation trench; optionally, the shared gate of two transistors with the same function sharing a gate forms a certain angle with the extending direction of the isolation trench, such as an angle of 30°, 45°, 60°, etc., so as to make better use of the spacing area between pixel units p and improve the area utilization rate.

[0073] Preferably, the pixel sub-array includes a source follower transistor SF, and the source follower transistor SF is exclusively used by its corresponding pixel sub-array. Among them, the source follower transistor SF exclusively used by the corresponding pixel sub-array can be one transistor or multiple transistors. Preferably, each pixel sub-array exclusively uses at least two source follower transistors SF, and every two source follower transistors SF are respectively located on both sides of the isolation trench and share a gate, so as to ensure the symmetry of the photosensitive array.

[0074] Preferably, the pixel sub-array includes a reset transistor (RST), a gain conversion transistor (DCG / TCG / QCG), and a selection transistor (SEL), and there is at least one type of transistors with the same function sharing a gate to form a transistor group Tr for sharing by adjacent pixel sub-arrays.

[0075] Preferably, the sharing method of the transistor group Tr formed by transistors with the same function sharing a gate for adjacent pixel sub-arrays can include: The first type: Two transistors with the same function sharing a gate are respectively exclusively used by adjacent different pixel sub-arrays. That is, the two transistors in the transistor group Tr only share a gate, but the two transistors are respectively used for adjacent different pixel sub-arrays.

[0076] The second type: Multiple transistors with the same function sharing a gate are jointly shared by adjacent different pixel sub-arrays. That is, the multiple transistors in the transistor group Tr not only share a gate, but the multiple transistors in the transistor group Tr are also simultaneously used for the corresponding pixel sub-arrays, that is, adjacent different pixel sub-arrays also share the transistor group Tr.

[0077] Preferably, adjacent pixel sub-arrays include pixel sub-arrays adjacent in the row direction and / or pixel sub-arrays adjacent in the column direction. The sharing of the transistor group Tr by the foregoing adjacent different pixel sub-arrays can occur in pixel sub-arrays adjacent in the row direction and / or pixel sub-arrays adjacent in the column direction.

[0078] Preferably, the number of shared pixel units p included in the pixel sub-array of the present disclosure can be 4, 8, 9, 16, etc. Sensors formed by different numbers of shared pixel units p are compatible in terms of design and technology except for metal leads. See the appendix Figure 2a For example, only by selecting and setting the functions corresponding to the transistor group Tr, the functional transistors required for pixel sub-arrays formed by 4, 8, 9, 16, etc. numbers of shared pixel units p can be satisfied, and different image sensors can be realized. Each pixel sub-array includes a plurality of reset transistors, a plurality of gain conversion transistors, a plurality of source follower transistors, and a plurality of selection transistors. The following will further elaborate on these pixel designs in detail.

[0079] Embodiment 1 As Figure 3a shown, it is a schematic equivalent circuit diagram of multiple pixel sub-arrays of the sensor according to the first embodiment of the present disclosure (only 3 pixel sub-arrays are schematically shown due to limited layout). It relates to multiple pixel sub-arrays of an image sensor with 3T4shared, Figure 3b which is a schematic circuit layout diagram of the sensor according to the first embodiment of the present disclosure (not all layers are shown). As Figure 3c shown, it is a simplified schematic diagram of the pixel arrangement of the image sensor according to the first embodiment of the present disclosure. In this embodiment, all transistors spanning the isolation trench are of the same function, and the common (e.g., polysilicon material) gate directly spans the trench. Among them, two parallel transistors serve as source follower transistors SF and are placed on one side of the floating diffusion region in the column direction. The gate of the source follower transistor SF is connected to the floating diffusion region, the drain end is connected to high voltage, and the source end serves as the output signal terminal PXD; DCG (gain conversion transistor), RST (reset transistor) are placed at the boundary of the pixel sub-array. The DCG of this pixel sub-array shares a gate with the DCG of the pixel sub-array in the adjacent column on one side, such as Figure 3b DCG*2-G shown in Figure 3bRST*2-G shown in [Figure]. Since all functional transistors are placed at the pixel sub-array boundary, by mirroring the sub-array layout, the same functional transistors in different pixel sub-arrays can be located adjacent to each other. At this time, two parallel functional transistors (including DCG / RST in the left and right columns) share a gate and are led out through a row selection line, thus realizing the normal timing function of the sub-array and significantly reducing the number of metal contacts and metal leads inside the image sensor array.

[0080] For the 3T4shared image sensor, its pixel sub-array s-pa includes a reset transistor RST, a gain conversion transistor DCG, a source follower transistor SF, and 4 shared pixel units p. According to the idea of the present disclosure, the gates of the same functional transistors are set as a whole across the isolation trench to share. In order to form a 3T4shared image sensor, transistor groups located on both sides in the first direction (row direction) of the pixel sub-array s-pa can be selected to form the reset transistor and the gain conversion transistor respectively, such as Figure 3c the RST*2-G and DCG*2-G shown in [Figure]. In the second direction (column direction) orthogonal to the first direction, the transistor group Tr located on one side of the pixel sub-array is selected as the source follower transistor, such as Figure 3c the SF*2-G shown in [Figure]. And the source follower transistor SF*2-G is exclusive to the corresponding pixel sub-array. The reset transistor RST*2-G includes two reset transistors RST, and the gain conversion transistor DCG*2-G includes two gain conversion transistors DCG. However, only one of RST*2-G and DCG*2-G is used for the corresponding pixel sub-array, and the other is used for the pixel sub-array adjacent to the corresponding pixel sub-array. Specifically, refer to Figure 3c shown in [Figure]. In the pixel sub-array s-pa, one of the two transistors in the gain conversion transistor DCG*2-G is used for the pixel sub-array s-pa in the dotted line, and the other is used for the pixel sub-array adjacent to the left of the pixel sub-array s-pa in the dotted line; one of the two transistors in the reset transistor RST*2-G is used for the pixel sub-array s-pa in the dotted line, and the other is used for the pixel sub-array adjacent to the right of the pixel sub-array s-pa in the dotted line. Optionally, the aforementioned reset transistor RST*2-G and gain conversion transistor DCG*2-G can also be located on both sides in the column direction of the pixel sub-array. At this time, the source follower transistor SF*2-G can be on one side in the row direction of the pixel sub-array.

[0081] Preferably, as shown in the appendix Figure 3cAs shown, there are adjacent first pixel sub-arrays 01 and second pixel sub-arrays 02 with different transistor function arrangement positions. The first pixel sub-array 01 and the second pixel sub-array 02 form a pixel module 1. The image sensor photosensitive array is formed by repeatedly arranging the pixel module 1 in a first direction X and a second direction Y, and the first direction and the second direction are orthogonal. In the first pixel sub-array 01, the reset transistor RST is located on the first side of the first pixel sub-array 01 in the first direction X, and the gain conversion transistor DCG is located on the second side of the first pixel sub-array 01 in the first direction; in the second pixel sub-array 02, the reset transistor RST is located on the second side of the second pixel sub-array 02 in the first direction, and the gain conversion transistor DCG is located on the first side of the second pixel sub-array 02 in the first direction; and the reset transistor and the gain conversion transistor are located in the same row. The source follower transistor SF is located on one of the two sides of the pixel sub-array in the second direction.

[0082] As Figure 3d is a circuit layout schematic diagram of the first embodiment of the present disclosure. It can be seen that its metal lines (ML) are arranged in an orderly manner, with short wire lengths and small numbers, and there is sufficient space between the metal leads, which can avoid parasitic capacitance.

[0083] In summary, for the 3T4shared image sensor, through the arrangement of the aforementioned RST, DCG, and SF transistors, process bottlenecks such as trenches and small-sized transistors can be avoided, the number of leads used can be reduced, and the symmetry of the pixels can be greatly improved. The formed image sensor is beneficial to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce the layout area of the image sensor, and reduce costs. Embodiment 2

[0084] As Figure 4a shown, it is a basic equivalent circuit schematic diagram of a 4T8shared (4T: that is, having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and a selection transistor (SEL); 8 shared: that is, 8 pixel units share the 4T). To be compatible with the Figure 2a arrangement of the attached Figure 4b example, as shown, it is a specific equivalent circuit schematic diagram of a pixel sub-array according to the second embodiment of the present disclosure. Each pixel sub-array s-pa includes 1 first gain conversion transistor DCG, 1 second gain conversion transistor TCG, 1 reset transistor RST, 2 source follower transistors SF, two selection transistors SEL, and a reserved transistor. The function of the reserved transistor can be selected according to actual needs. Preferably, the gate, source, and drain terminals of the reserved function transistor are all connected to a high level to control interface leakage while taking into account the compatibility of the arrangement array.

[0085] As Figure 4c shown, it is a schematic diagram of the equivalent circuit of multiple pixel sub-arrays of the sensor according to the second embodiment of the present disclosure. To simplify the drawings, some circuit diagrams in the attached Figure 4b drawings are simplified, such as cell, Res. As Figure 4d shown, it is a simplified schematic diagram of the pixel arrangement according to the second embodiment of the present disclosure. The 8 shared pixel units p are arranged in 4 rows and 2 columns.

[0086] As Figure 4e shown, it is a schematic diagram of the circuit layout according to the second embodiment of the present disclosure. It can be seen that two parallel transistors are used as source follower transistors SF*2-G and are placed on one side of the floating diffusion region in the column direction. Two parallel transistors are used as selection transistors SEL*2-G and are placed in the adjacent column to the source follower transistor SF*2-G. The gate of the source follower transistor SF*2-G is connected to the floating diffusion region, the drain end is connected to the high voltage, the source end is connected to the drain end of the selection transistor SEL, and the source end of the selection transistor SEL*2-G is used as the output signal terminal PXD; The first gain conversion transistor DCG, the reset transistor RST, and the second gain conversion transistor TCG are placed at the boundary of the pixel sub-array s-pa, and the source follower transistor SF*2-G is placed inside the pixel sub-array. Since all DCG / RST / TCG are placed at the boundary of the pixel sub-array, the DCG / RST / TCG of adjacent pixel sub-arrays can share a gate, as Figure 4d shown by DCG*2-G, TCG*2-G, RST*2-G in the figure. By mirroring the sub-array s-pa, the same functional transistors of different pixel sub-arrays can be located adjacent to each other. At this time, two parallel functional transistors (including DCG / RST in the left and right columns, and TCG in the upper and lower rows) share a gate and are led out through a row selection line, so that the normal timing function of the sub-array can be realized, and the number of metal contacts and metal leads inside the image sensor can be significantly reduced.

[0087] Refer to the attached Figure 4d figure. The reset transistor RST and the first gain conversion transistor DCG are respectively located on both sides of the first direction of the pixel sub-array s-pa and in the same row, and the second gain conversion transistor TCG is located on one side of the second direction of the pixel sub-array s-pa and is in a different row or column from the reset transistor RST and the first gain conversion transistor DCG.

[0088] In the first direction, the reset transistors RST respectively located in adjacent pixel sub-arrays share a gate, and the first gain conversion transistors DCG respectively located in adjacent pixel sub-arrays share a gate; in the second direction, the second gain conversion transistors TCG respectively located in adjacent pixel sub-arrays share a gate.

[0089] Two source follower transistors SF share a common gate, and two select transistors SEL share a common gate, which are exclusive to the pixel sub-array s-pa. The select transistor SEL is not in the same row as the source follower transistor SF, the reset transistor RST, the first gain conversion transistor DCG, and the second gain conversion transistor TCG. The source follower transistor SF is located inside the pixel sub-array, and the select transistor SEL is located on one side of the two sides of the pixel sub-array in the first direction.

[0090] As Figure 4c-4d shown, each pixel sub-array s-pa further includes a reserved function transistor Res. In the second direction, the second gain conversion transistor TCG and the reserved function transistor Res are respectively located on both sides of the pixel sub-array. Among them, the gate, source, and drain terminals of the reserved function transistor Res are all connected to a high level for controlling interface leakage. Moreover, the reserved function transistors Res included in the pixel sub-arrays s-pa of the upper and lower two rows share a common gate, which is arranged in the interval area between the pixel sub-arrays s-pa of the upper and lower two rows, and can further improve the quality of the 4T8shared type image sensor array.

[0091] Preferably, further referring to the appendix Figure 4d , there are a first pixel sub-array 01, a second pixel sub-array 02, a third pixel sub-array 03, and a fourth pixel sub-array 04 with different transistor function arrangement positions. The first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04 form a pixel module 1, and the image sensor photosensitive array is formed by repeatedly arranging the pixel module 1 in the first direction and the second direction.

[0092] In the first direction, the first pixel sub-array 01 and the second pixel sub-array 02 are adjacent, and the third pixel sub-array 03 and the fourth pixel sub-array 04 are adjacent. In the second direction, the first pixel sub-array 01 and the third pixel sub-array 03 are adjacent, and the second pixel sub-array 02 and the fourth pixel sub-array 04 are adjacent. Among them, the first direction is orthogonal to the second direction. The pixel module is symmetric about the boundary adjacent line of any two of the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04.

[0093] As Figure 4e is the circuit layout schematic diagram of the second embodiment of the present disclosure. It can be seen that its metal leads ML are arranged in an orderly manner, with short wire lengths and small numbers, and there is enough space between the metal leads to avoid parasitic capacitance.

[0094] In summary, for the 4T8shared image sensor, through the arrangement of the aforementioned RST, DCG, TCG, SF, and SEL transistors, process bottlenecks such as trenches and small-sized transistors can be avoided, the number of leads used can be reduced, and the symmetry of the pixels can be greatly improved. The formed image sensor is beneficial to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce the layout area of the image sensor, and reduce costs. Embodiment III

[0095] As Figure 5a shown, it is a schematic diagram of the basic equivalent circuit of a 4T9shared (4T: that is, having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and a selection transistor (SEL); 9shared: that is, 9 pixel units share 4T). As Figure 5b shown, it is a schematic diagram of the equivalent circuit of a pixel sub-array s-pa of the third embodiment of the present disclosure. According to the concept of the present disclosure, it is designed that each pixel sub-array s-pa includes 2 exclusive source follower transistors SF, 2 selection transistors SEL, and 9 shared pixel units p. In addition, the pixel sub-array s-pa further includes at least 1 reset transistor RST, 1 first gain conversion transistor DCG, and several second gain conversion transistors TCG. Multiple pixel sub-arrays are used to form the photosensitive array of the image sensor. As Figure 5c shown, it is a schematic diagram of the equivalent circuit of multiple pixel sub-arrays of the sensor of the third embodiment of the present disclosure. The several gain conversion transistors included in each pixel sub-array include a first gain conversion transistor DCG and several second gain conversion transistors TCG. The several second gain conversion transistors TCG include a first sub-gain conversion transistor with its gate terminal connected to the TCG control signal and a second sub-gain conversion transistor with its gate terminal grounded. Among them, the upper and lower two pixel sub-arrays s-pa share three first sub-gain conversion transistors in the second manner described above, and the left and right two pixel sub-arrays s-pa share three second sub-gain conversion transistors in the second manner described above.

[0096] As Figure 5d~5eAs shown, the reset transistor RST and the first sub-gain conversion transistor DCG are respectively located on both sides of the second direction of the pixel sub-array and are in different rows or different columns. The first gain conversion transistor DCG and several second sub-gain conversion transistors TCG are respectively located on both sides of the first direction of the pixel sub-array and are in different rows or different columns. Two parallel transistors serve as the source follower transistor SF and are placed on one side of the floating diffusion region in the column direction. Two parallel transistors serve as the selection transistor SEL and are placed in the column adjacent to the source follower transistor SF. The gate of the source follower transistor SF is connected to the floating diffusion region, the drain terminal is connected to the high voltage, and the source terminal is connected to the drain terminal of the selection transistor. The source terminal of the selection transistor SEL serves as the output signal terminal PXD; the first gain conversion transistor DCG, the reset transistor RST, and the second gain conversion transistor TCG are placed at the boundary of the pixel sub-array s-pa. Since the DCG / RST / TCG transistors are all placed at the boundary of the pixel sub-array, by mirroring the layout of the pixel sub-array, the same functional transistors in different sub-arrays can be located adjacent to each other. At this time, two parallel functional transistors (including the DCG in the left and right columns and the RST / TCG in the upper and lower rows) share a gate and are led out through a row selection line, so that the normal timing function of the sub-array can be realized, and the number of metal contacts and metal leads inside the image sensor can be significantly reduced.

[0097] As Figure 5d shown, in the first direction, the first gain conversion transistors DCG respectively located in adjacent pixel sub-arrays share a gate to form a transistor group, such as the Figure 5d 01-DCG, 02-DCG, 03-DCG, 04-DCG shown. Every two of the shared second sub-gain conversion transistors share a gate, such as the transistor groups 21 to 24 shown in the Figure 5d figure; in the second direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, such as the Figure 5d 31 to 34 shown. Every two of the shared first sub-gain conversion transistors share a gate, such as the Figure 5d 31 to 34 shown.

[0098] As Figure 5d shown, taking the first pixel sub-array 01 as an example, it includes two parallel source follower transistors SF with a shared gate exclusive to it, that is, 01-SF, and two parallel selection transistors SEL with a shared gate exclusive to it, that is, 01-SEL. The source follower transistor SF is in the same row as the first gain conversion transistor DCG, and the selection transistor SEL is in the same column as the reset transistor RST.

[0099] Preferably, in the photosensitive array of the image sensor, there are a first pixel sub-array 01, a second pixel sub-array 02, a third pixel sub-array 03, and a fourth pixel sub-array 04 with different arrangements of transistor functions. As Figure 5d shown, the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04 are used to form a pixel module 1, and the photosensitive array of the image sensor is formed by repeatedly arranging the pixel module 1 in a first direction and a second direction.

[0100] Among them, in the first direction, the first pixel sub-array 01 and the second pixel sub-array 02 are adjacent, and the third pixel sub-array 03 and the fourth pixel sub-array 04 are adjacent; in the second direction, the first pixel sub-array 01 and the third pixel sub-array 03 are adjacent, and the second pixel sub-array 02 and the fourth pixel sub-array 04 are adjacent; the first direction is orthogonal to the second direction; the pixel module 1 is symmetric about the boundary adjacent line of any two of the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04.

[0101] As Figure 5d shown, the source follower transistors SF and the selection transistors SEL corresponding to the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04 are all located within their corresponding pixel sub-arrays and are exclusively owned by the corresponding pixel sub-arrays. For example, the source follower transistor 01-SF and the selection transistor 01-SEL are exclusively owned by the first pixel sub-array 01; the source follower transistor 02-SF and the selection transistor 02-SEL are exclusively owned by the second pixel sub-array 02; the source follower transistor 03-SF and the selection transistor 03-SEL are exclusively owned by the third pixel sub-array 03; the source follower transistor 04-SF and the selection transistor 04-SEL are exclusively owned by the fourth pixel sub-array 04.

[0102] Preferably, the 9 shared pixel units p included in the pixel sub-array are arranged in a 3-row and 3-column array, and the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04 form a pixel module 1 including an array of 6 rows and 6 columns of pixel units p.

[0103] Preferably, in the pixel module 1, the second gain conversion transistor TCG is located at any adjacent area of the first, second, third, and fourth pixel sub-arrays of the pixel module 1, that is, in the pixel module, the second gain conversion transistor TCG (11~14, 21~24) is arranged on the "cross" area of the pixel module 1. As Figure 5dAs shown in the figure. First gain conversion transistors DCG, namely 01-DCG group, 02-DCG group, 03-DCG group, and 04-DCG group, are respectively set corresponding to the first, second, third, and fourth pixel sub-arrays. Among them, the 01-DCG group and 03-DCG group are located on the left side of pixel module 1, and the 02-DCG group and 04-DCG group are located on the right side of pixel module 1. In pixel module 1, the first group of first gain conversion transistors 01-DCG and the second group of first gain conversion transistors 02-DCG are located in the area between the pixel units p in the 1st and 2nd rows; the third group of first gain conversion transistors 03-DCG and the fourth group of first gain conversion transistors 04-DCG are located in the area between the pixel units p in the 5th and 6th rows; and the first group of first gain conversion transistors 01-DCG, the second group of first gain conversion transistors 02-DCG, the third group of first gain conversion transistors 03-DCG, and the fourth group of first gain conversion transistors 04-DCG all include two transistors sharing a gate. The first gain conversion transistor that is farther away from pixel module 1 among the two first gain conversion transistors is used for the pixel sub-array in the adjacent pixel module and adjacent to the corresponding pixel sub-array. Specifically, one of the transistors in the 01-DCG group is used for the first pixel sub-array 01, and the other transistor is used for the pixel sub-array in the first quadrant of the pixel module adjacent to the left side of pixel module 1; one of the transistors in the 02-DCG group is used for the second pixel sub-array 02, and the other transistor is used for the pixel sub-array in the second quadrant of the pixel module adjacent to the right side of pixel module 1; one of the transistors in the 03-DCG group is used for the third pixel sub-array 03, and the other transistor is used for the pixel sub-array in the fourth quadrant of the pixel module adjacent to the left side of pixel module 1; one of the transistors in the 04-DCG group is used for the fourth pixel sub-array 04, and the other transistor is used for the pixel sub-array in the third quadrant of the pixel module adjacent to the right side of pixel module 1.

[0104] Preferably, in pixel module 1, as Figure 5d shown, the second gain conversion transistor TCG is set on the "cross" area of pixel module 1. Moreover, the second gain conversion transistor TCG includes first sub-gain conversion transistors 11~14 and second sub-gain conversion transistors 21~24. All the first sub-gain conversion transistors 11~14 are arranged along the row direction (the first direction) of the "cross" area; all the second sub-gain conversion transistors are arranged along the column direction (the second direction) of the "cross" area.

[0105] Preferably, in pixel module 1, the first sub-gain conversion transistor relates to the first group 11, the second group 12, the third group 13, and the fourth group 14; among them, the first to fourth groups of first TCG gain conversion transistors are located in the adjacent areas of the upper and lower rows of adjacent pixel sub-arrays of the pixel module, and in the areas between every two columns of pixel units p.

[0106] Preferably, each group of second gain conversion transistors TCG includes two transistors sharing a common gate. Among them, in the first and fourth groups of first sub-gain conversion transistors 11 and 14, one of the two TCG gain conversion transistors included in each is for the corresponding pixel sub-array in pixel module 1, and the other is for the adjacent pixel sub-array of the adjacent pixel module in the first direction corresponding to it; and, in the second and third groups of first sub-gain conversion transistors 12 and 13, both of the two transistors included in each are shared by the adjacent pixel sub-arrays in the second direction of the corresponding pixel module. Specifically, as Figure 5d shown, the first group 11 includes two transistors, and the second group 12 also includes two transistors. The first pixel sub-array 01 and the third pixel sub-array 03 share the two transistors included in the second group 12 and one of the transistors in the first group 11 in the second way. And the other transistor in the first group 11 is shared by the pixel sub-arrays in the first and fourth quadrants of the pixel module adjacent to the left side of pixel module 1. Similarly, the third group 13 includes two transistors, and the fourth group 14 also includes two transistors. The second pixel sub-array 02 and the fourth pixel sub-array 04 share the two transistors included in the third group 13 and one of the transistors in the fourth group 14. And the other transistor in the fourth group 14 is shared by the pixel sub-arrays in the second and third quadrants of the pixel module adjacent to the right side of pixel module 1. Preferably, the gate terminal of the first sub-gain conversion transistor TCG is connected to the TCG control signal.

[0107] Preferably, the second sub-gain conversion transistor relates to the first group 21, the second group 22, the third group 23, and the fourth group 24, where the first to fourth groups are located in the adjacent areas of the left and right column pixel sub-arrays of the pixel module, and in the inter-row area between every two rows of pixel units p.

[0108] Preferably, each group of second sub-gain conversion transistors includes two transistors sharing a common gate. Among them, one of the two transistors included in the first and fourth groups is for its corresponding pixel sub-array, and the other is for the adjacent pixel sub-arrays of the adjacent pixel modules in the second direction of its corresponding pixel sub-array; the two TCG gain conversion transistors included in the second and third groups are shared by the adjacent pixel sub-arrays corresponding to them. Similarly, the first group 21 includes two transistors, and the second group 22 also includes two transistors. The first pixel sub-array 01 and the second pixel sub-array 02 share the two transistors included in the second group 22 and one of the transistors in the first group 21. And the other transistor in the first group 21 is shared by the pixel sub-arrays in the third and fourth quadrants of the pixel module adjacent to the upper side of the pixel module 1. Similarly, the third group 23 includes two transistors, and the fourth group 24 also includes two transistors. The third pixel sub-array 03 and the fourth pixel sub-array 04 share the two transistors included in the third group 23 and one of the transistors in the fourth group 24. And the other transistor in the fourth group 24 is shared by the pixel sub-arrays in the first and second quadrants of the pixel module adjacent to the lower side of the pixel module 1. Preferably, the gate of the second sub-gain conversion transistor TCG is grounded.

[0109] Preferably, a plurality of reset transistors RST are located at the adjacent positions of adjacent pixel modules in the column direction (second direction) of the pixel module 1 and are shared by the adjacent pixel sub-arrays located in the adjacent pixel modules respectively. In the pixel module 1, the reset transistor RST groups are arranged along the second direction, and it includes the first group 31, the second group 32, the third group 33, and the fourth group 34. Each of the first, second, third, and fourth groups includes two transistors sharing a common gate. One of the two transistors is respectively for its corresponding pixel sub-array, and the other is for the adjacent pixel sub-arrays of the corresponding adjacent module of its corresponding pixel sub-array. As Figure 5d shown, one of the two transistors included in the reset transistor RST group 31 is for the pixel sub-array 01, and the other is for the pixel sub-array in the third quadrant of its upper adjacent pixel module. One of the two transistors included in the reset transistor RST group 32 is for the pixel sub-array 02, and the other is for the pixel sub-array in the fourth quadrant of its upper adjacent pixel module. One of the two transistors included in the reset transistor RST group 33 is for the pixel sub-array 03, and the other is for the pixel sub-array in the second quadrant of its lower adjacent pixel module. One of the two transistors included in the reset transistor RST group 34 is for the pixel sub-array 04, and the other is for the pixel sub-array in the first quadrant of its lower adjacent pixel module.

[0110] Preferably, the first and third groups of reset transistors are correspondingly located in the area between the pixel units p in the 1st and 2nd columns of the pixel module; the second and fourth groups of reset transistors are located in the area between the pixel units p in the 5th and 6th columns.

[0111] Preferably, two source follower transistors SF are arranged along the first direction and share a gate, and are located inside the pixel sub-array. Among them, in pixel module 1: the first group of source follower transistors 01-SF of the first pixel sub-array 01 is located between the pixel units p in the 1st and 2nd rows and in the area between the pixel units p in the 2nd and 3rd columns; the second group of source follower transistors 02-SF of the second pixel sub-array 02 is located between the pixel units p in the 1st and 2nd rows and in the area between the pixel units p in the 4th and 5th columns; the third group of source follower transistors 03-SF of the third pixel sub-array 03 is located between the pixel units p in the 5th and 6th rows and in the area between the pixel units in the 2nd and 3rd columns; the fourth group of source follower transistors 04-SF of the fourth pixel sub-array 04 is located between the pixel units p in the 5th and 6th rows and in the area between the pixel units p in the 4th and 5th columns.

[0112] Preferably, two select transistors SEL are arranged along the second direction and share a gate, and are located inside the pixel sub-array. Among them, in pixel module 1, the first group of select transistors 01-SEL of the first pixel sub-array 01 is located between the pixel units p in the 1st and 2nd columns and in the area between the pixel units p in the 2nd and 3rd rows; the second group of select transistors 02-SEL of the second pixel sub-array 02 is located between the pixel units p in the 5th and 6th columns and in the area between the pixel units p in the 2nd and 3rd rows; the third group of select transistors 03-SEL of the third pixel sub-array 03 is located between the pixel units p in the 1st and 2nd columns and in the area between the pixel units p in the 4th and 5th rows; the fourth group of select transistors 04-SEL of the fourth pixel sub-array 04 is located between the pixel units p in the 5th and 6th columns and is arranged in the area between the pixel units p in the 4th and 5th rows along the second direction.

[0113] As Figure 5e shown, it is a schematic diagram of the circuit layout of the third embodiment of the present disclosure. It can be seen that the layout of its metal leads ML is orderly, and most of the metal leads ML have short threads, and the number of metal leads ML with long threads is small, which can provide sufficient space for layout between the metal leads, can avoid parasitic capacitance, and is beneficial to reducing the size of the device.

[0114] In summary, for the image sensor of 4T9shared, through the arrangement of the aforementioned RST, DCG, TCG, SF, and SEL transistors, process bottlenecks such as trenches and small-sized transistors can be avoided, the number of leads used can be reduced, and the symmetry of the pixels can be greatly improved. The formed image sensor is conducive to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce the layout area of the image sensor, and reduce costs. Embodiment 4

[0115] As Figure 6a-1 shown, it is an equivalent circuit diagram of a pixel sub-array of the fourth embodiment of the present disclosure. Figure 6a-2 It is another equivalent circuit diagram of a pixel sub-array of the fourth embodiment of the present disclosure. This embodiment relates to two equivalent circuit diagrams of a pixel sub-array of an image sensor of 4T16shared (4T: that is, having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and a selection transistor (SEL); 16shared: that is, 16 pixel units share 4T). The pixel sub-array in this sensor includes a reset transistor RST, a gain conversion transistor DCG / TCG / QCG (i.e., the first / second / third), a source follower transistor SF, a selection transistor SEL, and 16 shared pixel units p. Multiple pixel sub-arrays are used to form the photosensitive array of the image sensor.

[0116] As Figure 6b-1 shown, it is an equivalent circuit diagram of multiple pixel sub-arrays of the sensor of the fourth embodiment of the present disclosure. As Figure 6b-2 is another equivalent circuit diagram of multiple pixel sub-arrays of the sensor of the fourth embodiment of the present disclosure. The difference between the two is that Figure 6b-1 in, the pixel sub-arrays in the upper and lower rows share the third gain conversion transistor QCG in the second manner described above; Figure 6b-2 in, the pixel sub-arrays in the upper and lower rows share the third gain conversion transistor QCG in the second manner described above, and the pixel sub-arrays in the left and right columns share the second gain conversion transistor TCG in the second manner described above. In other embodiments, it is also possible that the pixel sub-arrays in the upper and lower rows do not share the third gain conversion transistor QCG in the second manner described above, but the pixel sub-arrays in the left and right columns share the second gain conversion transistor TCG in the second manner described above, but preferably the embodiments as Figure 6b-1 As Figure 6b-2 shown.

[0117] As Figure 6c-1 、 6c-2, which is an example of a simplified schematic diagram of pixel arrangement according to the fourth embodiment of the present disclosure. Among them, the gain conversion transistors DCG / TCG / QCG (i.e., the first / second / third) and the reset transistor RST are placed at the boundary of the pixel sub-array. Since the DCG / RST / TCG / QCG transistors are all placed at the boundary of the pixel sub-array, by mirroring the pixel sub-array arrangement, the same-function transistors in different sub-arrays can be located adjacent to each other. At this time, two parallel functional transistors (including DCG / TCG in the left and right columns and RST / QCG in the upper and lower rows) share a gate and are led out through a row selection line, so that the normal timing function of the sub-array can be realized, and the number of metal contacts and metal leads inside the image sensor can be significantly reduced.

[0118] Each pixel sub-array s-pa (such as pixel sub-arrays 01, 02, 03, 04) includes 16 shared pixel units p arranged in 4 rows and 4 columns. Each pixel sub-array s-pa includes 2 reset transistors RST, several gain conversion transistors (DCG / TCG / QCG), at least 2 source follower transistors, and at least 2 selection transistors. Preferably, in order to improve the pixel symmetry of the sensor array, each pixel sub-array s-pa includes 6 source follower transistors SF and 2 selection transistors SEL, as Figure 6c-1 shown; more preferably, each pixel sub-array s-pa includes 4 source follower transistors SF and 4 selection transistors SEL, as Figure 6c-2 shown, so that the pixel symmetry of the sensor array can be further improved.

[0119] The several gain conversion transistors of each pixel sub-array s-pa may include several first gain conversion transistors DCG, several second gain conversion transistors TCG; and several third gain conversion transistors QCG. Specifically, each pixel sub-array s-pa may include 2 first gain conversion transistors DCG, 2 second gain conversion transistors TCG, and 2 third gain conversion transistors QCG.

[0120] Furthermore, as Figure 6c-1 , 6c-2 shown, the two reset transistors RST are located in the same row and on one side of the second direction of the pixel sub-array s-pa, and the two third gain conversion transistors QCG are located in the same row and on the other side of the second direction of the pixel sub-array; the two first gain conversion transistors DCG are located in the same row and on both sides of the first direction of the pixel sub-array s-pa, and the two second gain conversion transistors TCG are located in the same row and on both sides of the first direction of the pixel sub-array s-pa; among them, the reset transistor RST, the first gain conversion transistor DCG, the second gain conversion transistor TCG, and the third gain conversion transistor QCG are located in different rows.

[0121] In a first direction, first gain conversion transistors DCG respectively located in adjacent pixel sub-arrays s-pa share a common gate, and second gain conversion transistors TCG respectively located in adjacent pixel sub-arrays s-pa share a common gate; in a second direction, reset transistors RST respectively located in adjacent pixel sub-arrays s-pa share a common gate, and third gain conversion transistors QCG respectively located in adjacent pixel sub-arrays share a common gate.

[0122] As Figure 6c-1 shown, the pixel sub-array s-pa includes 6 source follower transistors SF and 2 selection transistors SEL that are exclusive to it. Every two source follower transistors SF share a common gate to form a group, and the two selection transistors SEL share a common gate. The source follower transistors SF are either in the same row as the first gain conversion transistor DCG, or in the same row as the second gain conversion transistor TCG, or in the same column as the reset transistor RST and the third gain conversion transistor QCG. The selection transistor SEL is in the same column as the reset transistor RST and the third gain conversion transistor QCG that are not in the same column as the source follower transistors SF.

[0123] Preferably, as Figure 6c-2 shown, the pixel sub-array s-pa may include 4 source follower transistors SF and 4 selection transistors SEL that are exclusive to it. Every two source follower transistors SF share a common gate to form a group, and every two selection transistors SEL share a common gate. The source follower transistors SF are either in the same row as the first gain conversion transistor DCG, or in the same row as the second gain conversion transistor TCG. The selection transistor SEL is in the same column as the reset transistor RST and the third gain conversion transistor QCG. By setting the source follower transistors SF and the selection transistors SEL to each include 4, the symmetry of the photosensitive array can be further improved.

[0124] As Figure 6c-1 、 6c-2 shown, there are a first pixel sub-array 01, a second pixel sub-array 02, a third pixel sub-array 03, and a fourth pixel sub-array 04 with different transistor function arrangement positions, which are used to form a pixel module 1. The photosensitive array of the image sensor is formed by repeatedly arranging the pixel module 1 in the first direction and the second direction.

[0125] In the first direction, the first pixel sub-array 01 and the second pixel sub-array 02 are adjacent, and the third pixel sub-array 03 and the fourth pixel sub-array 04 are adjacent; in the second direction, the first pixel sub-array 01 and the third pixel sub-array 03 are adjacent, and the second pixel sub-array 02 and the fourth pixel sub-array 04 are adjacent; the first direction is orthogonal to the second direction; the pixel module 1 is symmetric about the boundary adjacent line of any two of the first pixel sub-array 01, the second pixel sub-array 02, the third pixel sub-array 03, and the fourth pixel sub-array 04.

[0126] The fourth embodiment of the present disclosure also relates to the layout of multiple specific embodiments. By way of example, as Figure 6d shown, it is a schematic circuit layout diagram of the fourth embodiment of the present disclosure. It is based on the Figure 6b-1 shared form shown, and the Figure 6a-1 metal wire design is carried out according to the pixel sub-array circuit shown. It can be seen that its metal leads ML are arranged in an orderly manner, most of the ML leads have short threads, and the number of long metal leads ML is small. In this way, there is enough space between the metal leads, which is beneficial to avoiding parasitic capacitance.

[0127] In summary, for the 4T16shared image sensor, through the arrangement of the aforementioned RST, DCG, TCG, QCG, SF, and SEL transistors, process bottlenecks such as trenches and small-sized transistors can be avoided, the number of leads used can be reduced, and the symmetry of the pixels can be greatly improved. The formed image sensor is beneficial to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce the layout area of the image sensor, and reduce costs.

[0128] In addition, the present disclosure also provides a method for manufacturing an image sensor for manufacturing the image sensor involved in any of the foregoing embodiments. Wherein, the method includes arranging at least one type of transistors with the same function in adjacent pixel sub-arrays on both sides of a trench, and manufacturing the common gate of the transistors with the same function to optimize the process and wiring of the image sensor.

[0129] In the embodiments of the present disclosure, by changing the idea of transistor arrangement in the layout, at least one type of transistors with the same function is set to share a common gate, and even only transistors with a common gate exist in the pixel sub-array. Furthermore, by connecting the gates, the number of row selection lines is significantly reduced, and the layout of the layout is simplified; the requirements for the opening shape and size of the isolation trench are avoided, and the process difficulty of the isolation trench process is greatly reduced; moreover, the differences in the implementation of pixel layouts with different sharing numbers only lie in the differences in the layout of the metal lead layer, and the others can be made compatible, which significantly reduces the cost. At the same time, the pixel layout of the present disclosure is also beneficial to improving pixel symmetry, eliminating differential defects, beneficial to reducing pixel density, reducing the area of the image sensor, and can greatly improve the quality of the image sensor and reduce the production cost. The solution of the present disclosure is of great significance for the production of small-pixel large-array image sensors.

[0130] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to the present invention. Such modifications, improvements, and corrections are proposed in the present invention, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention.

[0131] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be regarded as consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. An image sensor, the image sensor comprising an image sensor photosensitive array composed of a plurality of pixel sub-arrays, the pixel sub-arrays including a plurality of pixel units and transistors with different functions, the pixel units including photodiodes, characterized in that, Transistors with at least one same function in adjacent pixel sub - arrays share a gate to optimize the process and wiring of the image sensor; Among them, the transistors include one or more of source - follower transistors, reset transistors, gain - conversion transistors, and selection transistors.

2. The image sensor according to claim 1, characterized in that, There are at least two transistors with the same function sharing a gate, and the at least two transistors with the same function achieve channel isolation through isolation trenches.

3. An image sensor according to claim 1 or 2, characterized in that, The channels of two transistors with the same function sharing a gate are parallel to each other.

4. An image sensor according to claim 1 or 2, characterized in that, The sources and drains of two transistors with the same function sharing a gate are isolated through isolation trenches.

5. An image sensor according to claim 1, wherein The shared gate extends along the row direction, or along the column direction, or along a direction at a 45° angle to the row or column direction.

6. An image sensor according to claim 1 or 2, characterized in that, The source - follower transistor is exclusive to its corresponding pixel sub - array.

7. An image sensor according to claim 1 or 2, characterized in that, For at least one of the reset transistor, gain - conversion transistor, and selection transistor, there are transistors with the same function sharing a gate for adjacent pixel sub - arrays.

8. An image sensor according to claim 7, characterized in that, The manner in which transistors with the same function share a gate for adjacent pixel sub - arrays includes: Two transistors with the same function sharing a gate are respectively exclusive to adjacent different pixel sub - arrays; Or, two transistors with the same function sharing a gate are jointly shared by adjacent different pixel sub - arrays.

9. An image sensor according to claim 8, characterized in that, The adjacent includes adjacent in the row direction and / or adjacent in the column direction.

10. An image sensor according to any one of claims 1 to 9, characterized in that, Each pixel sub - array includes one reset transistor, one gain - conversion transistor, one or two source - follower transistors, and 4 shared pixel units.

11. An image sensor according to claim 10, wherein, In the first direction, the reset transistors located in adjacent pixel sub - arrays share a gate respectively, and the gain - conversion transistors located in adjacent pixel sub - arrays share a gate respectively.

12. An image sensor according to any one of claims 10 to 11, characterized in that, There are adjacent first pixel sub - array and second pixel sub - array with different arrangements of transistor functions. The first pixel sub - array and the second pixel sub - array form a pixel module. The photosensitive array of the image sensor is formed by repeatedly arranging the pixel module in the first direction and the second direction, and the first direction and the second direction are orthogonal.

13. An image sensor according to claim 12, characterized in that, In the first pixel sub - array, the reset transistor is located on the first side of the first direction of the first pixel sub - array, and the gain - conversion transistor is located on the second side of the first direction of the first pixel sub - array; in the second pixel sub - array, the reset transistor is located on the second side of the first direction of the second pixel sub - array, and the gain - conversion transistor is located on the first side of the first direction of the second pixel sub - array; and the reset transistor and the gain - conversion transistor are in the same row.

14. An image sensor according to claim 13, characterized in that, The source - follower transistor is located on one of the two sides of the second direction of the pixel sub - array.

15. An image sensor according to any one of claims 1 to 9, characterized in that, Each pixel sub - array includes several reset transistors, several gain - conversion transistors, several source - follower transistors, several selection transistors, and 8, or 9, or 16 shared pixel units.

16. An image sensor according to claim 15, characterized in that, The several gain - conversion transistors of each pixel sub - array include several first gain - conversion transistors and several second gain - conversion transistors; When the pixel sub-array includes 8 shared pixel units, each pixel sub-array includes a reset transistor, a first gain conversion transistor, and a second gain conversion transistor; When the pixel sub-array includes 9 shared pixel units, each pixel sub-array includes a reset transistor, a first gain conversion transistor, and the plurality of second gain conversion transistors include a plurality of first sub-gain conversion transistors and a plurality of second sub-gain conversion transistors; When the pixel sub-array includes 16 shared pixel units, the plurality of gain conversion transistors further include two third gain conversion transistors, and each pixel sub-array includes two reset transistors, two first gain conversion transistors, two second gain conversion transistors, and two third gain conversion transistors.

17. An image sensor according to claim 16, wherein When the pixel sub-array includes 9 shared pixel units, the pixel sub-arrays adjacent in the first direction share the plurality of second sub-gain conversion transistors, and the pixel sub-arrays adjacent in the second direction share the plurality of first sub-gain conversion transistors; When the pixel sub-array includes 16 shared pixel units, in the second direction, the third gain conversion transistors of the adjacent pixel sub-arrays are shared, and / or, in the first direction, the second gain conversion transistors of the adjacent pixel sub-arrays are shared.

18. An image sensor according to claim 16 or 17, wherein When the pixel sub-array includes 8 shared pixel units, the reset transistor and the first gain conversion transistor are respectively located on both sides of the pixel sub-array in the first direction and in the same row, and the second gain conversion transistor is located on one side of the pixel sub-array in the second direction and is in a different row or column from the reset transistor and the first gain conversion transistor; When the pixel sub-array includes 9 shared pixel units, the reset transistor and the first sub-gain conversion transistor are respectively located on both sides of the pixel sub-array in the second direction and are in different rows or columns, and the first gain conversion transistor and the plurality of second sub-gain conversion transistors are respectively located on both sides of the pixel sub-array in the first direction and are in different rows or columns; When the pixel sub-array includes 16 shared pixel units, the two reset transistors are in the same row and are located on one side of the pixel sub-array in the second direction, the two first gain conversion transistors are in the same row and are respectively located on both sides of the pixel sub-array in the first direction, the two second gain conversion transistors are in the same row and are respectively located on both sides of the pixel sub-array in the first direction, and the two third gain conversion transistors are in the same row and are located on the other side of the pixel sub-array in the second direction; wherein, the reset transistor, the first gain conversion transistor, the second gain conversion transistor, and the third gain conversion transistor are respectively in different rows.

19. An image sensor according to claim 18, wherein When the pixel sub-array includes 8 shared pixel units, in the first direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate; in the second direction, the second gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate. When the pixel sub-array includes 9 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate, and every two of the shared several second sub-gain conversion transistors share a gate; in the second direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and every two of the shared several first sub-gain conversion transistors share a gate. When the pixel sub-array includes 16 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate, and the second gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate; in the second direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the third gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate.

20. An image sensor according to any one of claims 15 to 19, wherein When the pixel sub-array includes 8 shared pixel units, the pixel sub-array includes two source follower transistors and two selection transistors exclusive to it. The two source follower transistors share a gate, and the two selection transistors share a gate. The selection transistors are not in the same row as the source follower transistors, reset transistors, first gain conversion transistors, and second gain conversion transistors. When the pixel sub-array includes 9 shared pixel units, the pixel sub-array includes two source follower transistors and two selection transistors exclusive to it. The two source follower transistors share a gate, and the two selection transistors share a gate. The source follower transistors are in the same row as the first gain conversion transistors, and the selection transistors are in the same column as the reset transistors. When the pixel sub-array includes 16 shared pixel units, the pixel sub-array includes six source follower transistors and two selection transistors that are exclusive to it. Every two of the source follower transistors share a gate to form a group, and the two selection transistors share a gate. The source follower transistors are either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor, or in the same column as the reset transistor and the third gain conversion transistor. The selection transistors are in the same column as the reset transistor and the third gain conversion transistor that are not in the same column as the source follower transistors; or, when the pixel sub-array includes four source follower transistors and four selection transistors that are exclusive to it, every two of the source follower transistors share a gate to form a group, and every two of the two selection transistors share a gate. The source follower transistors are either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor. The selection transistors are in the same column as the reset transistor and the third gain conversion transistor.

21. An image sensor according to any one of claims 15 to 20, characterized in that, When the pixel sub-array includes 8 shared pixel units, the source follower transistors are located inside the pixel sub-array, and the selection transistors are located on one side of the pixel sub-array in the first direction; when the pixel sub-array includes 9 or 16 shared pixel units, both the source follower transistors and the selection transistors are located inside the pixel sub-array.

22. An image sensor according to claim 16, wherein The gate terminal of the first sub-gain conversion transistor is connected to a control signal; the gate terminal of the second sub-gain conversion transistor is grounded.

23. An image sensor according to claim 16, characterized in that, When the pixel sub-array includes 8 shared pixel units, each pixel sub-array further includes a reserved function transistor. In the second direction, the second gain conversion transistor and the reserved function transistor are respectively located on both sides of the pixel sub-array. Among them, the gate, source, and drain terminals of the reserved function transistor are all connected to a high level for controlling interface leakage.

24. An image sensor according to any one of claims 15 to 23, characterized in that, There are a first pixel sub-array, a second pixel sub-array, a third pixel sub-array, and a fourth pixel sub-array with different transistor function layout positions. The first pixel sub-array, the second pixel sub-array, the third pixel sub-array, and the fourth pixel sub-array form a pixel module. The image sensor photosensitive array is formed by repeatedly arranging the pixel module in the first direction and the second direction.

25. An image sensor according to claim 24, characterized in that, In the first direction, the first pixel sub-array and the second pixel sub-array are adjacent, and the third pixel sub-array and the fourth pixel sub-array are adjacent; in the second direction, the first pixel sub-array and the third pixel sub-array are adjacent, and the second pixel sub-array and the fourth pixel sub-array are adjacent; the first direction is orthogonal to the second direction; the pixel module is symmetric about the boundary adjacent line of any two of the first pixel sub-array, the second pixel sub-array, the third pixel sub-array, and the fourth pixel sub-array.

26. An image sensor according to claim 24, wherein, When 8 shared pixel units are shared, the 8 shared pixel units are arranged in 4 rows and 2 columns; when 9 shared pixel units are shared, the 9 shared pixel units are arranged in 3 rows and 3 columns; when 16 shared pixel units are shared, the 16 shared pixel units are arranged in 4 rows and 4 columns.

27. A method for manufacturing an image sensor, for manufacturing the image sensor according to any one of claims 1 to 26, characterized in that, Transistors with at least one same function in adjacent pixel sub-arrays are arranged on both sides of a trench, and a common gate for the transistors with the same function is fabricated to optimize the process and wiring of an image sensor.

Images