Transparent display device

Abstract

There is provided a transparent display device including: a substrate including a non-transmissive area and a transmissive area, the non-transmissive area including a light emitting area provided with a light emitting element; a plurality of data lines disposed in the non-transmissive area on the substrate and extending in a first direction; at least one gate line passing through the non-transmissive region and the transmissive region in a second direction intersecting the first direction on the substrate; and at least one power line overlapping with at least a portion of the plurality of data lines on the substrate via at least one insulating layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0197390, filed in Korea on December 29, 2023, the entire contents of which are hereby incorporated by reference in their entirety. Technical field

[0003] The present disclosure relates to a transparent display device. Background art

[0004] As the information age progresses, the demand for display devices for displaying images has increased in various forms. Therefore, recently, various types of display devices such as liquid crystal display (LCD) devices, organic light - emitting diode (OLED) devices, micro - light - emitting diode (LED) display devices, and quantum dot display (QD) devices have been in use.

[0005] Recently, research on transparent display devices that display images for users and enable users to view objects or images located on the opposite side through transmitted light has been actively conducted. The transparent display device includes a display area on which an image is displayed and a non - display area, wherein the display area may include a transmissive area capable of transmitting external light and a non - transmissive area. The transparent display device may have a high light transmittance in the display area through the transmissive area. Summary of the invention

[0006] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a transparent display device that can have a high light transmittance.

[0007] In addition to the object of the present disclosure described above, other objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0008] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a transparent display device including: a substrate including a non - transmissive area and a transmissive area, the non - transmissive area including a light - emitting area provided with a light - emitting element; a plurality of data lines disposed in the non - transmissive area of the substrate and extending in a first direction; at least one gate line passing through the non - transmissive area and the transmissive area on the substrate in a second direction intersecting the first direction; and at least one power line overlapping at least a part of the plurality of data lines on the substrate with at least one insulating layer therebetween.

[0009] A transparent display device according to one or more embodiments of the present disclosure may include: a substrate including a display area and a non-display area surrounding the display area, wherein the display area may include a plurality of light-emitting areas arranged in a first direction; a plurality of data lines among the plurality of light-emitting areas on the substrate, the plurality of data lines extending in the first direction; a plurality of gate lines on the substrate, the plurality of gate lines extending in a second direction intersecting the first direction; and a power line on the substrate, the power line overlapping at least a part of the plurality of data lines with an insulating layer therebetween.

[0010] According to an embodiment of the present disclosure, a transparent display device having a high light transmittance may be provided.

[0011] The effects of the present disclosure are not limited to the foregoing, and other effects not described herein will be clearly understood by those skilled in the art from the following description.

[0012] The details of the technical problems, technical solutions, and beneficial effects described in the present disclosure do not define the essential features of the claims, and thus, the scope of the claims is not limited by the details described in the detailed description of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this application, showing embodiments of the present disclosure, and together with the description are used to explain the principles of the present disclosure.

[0014] Figure 1 is a view showing a transparent display device according to an embodiment of the present disclosure;

[0015] Figure 2 is a circuit diagram of a sub-pixel showing a transparent display device according to an embodiment of the present disclosure;

[0016] Figure 3 is a view showing an area A shown in Figure 1 according to an embodiment of the present disclosure;

[0017] Figure 4 is a view showing an area B shown in Figure 3 according to an embodiment of the present disclosure;

[0018] Figure 5 is a cross-sectional view taken along line I-I' shown in Figure 4 according to an embodiment of the present disclosure;

[0019] Figure 6 is a view showing an area B shown in Figure 3 according to an embodiment of the present disclosure;

[0020] Figure 7 is a cross-sectional view taken along a line according to an embodiment of the present disclosureFigure 6 A cross-sectional view taken along line II-II' shown in

[0021] Figure 8 It is a cross-sectional view taken along line II-II' according to another embodiment of the present disclosure Figure 6 shown in

[0022] Figure 9 It is a cross-sectional view taken along line II-II' according to another embodiment of the present disclosure Figure 6 shown in

[0023] Figure 10 It is a cross-sectional view taken along line III-III' according to another embodiment of the present disclosure Figure 6 shown in

[0024] Figure 11 It is a cross-sectional view taken along line III-III' according to another embodiment of the present disclosure Figure 6 shown in

[0025] Figure 12 It is a plan view showing a power line and a data line according to an embodiment of the present disclosure

[0026] Figure 13 It is a plan view showing a power line and a data line according to another embodiment of the present disclosure

[0027] Figure 14 It is a plan view showing a power line and a data line according to another embodiment of the present disclosure

[0028] Figure 15 It is a plan view showing a power line and a data line according to another embodiment of the present disclosure

[0029] Figure 16 It is a plan view showing a power line and a data line according to another embodiment of the present disclosure

[0030] Figure 17 It is a plan view showing a power line and a data line according to another embodiment of the present disclosure

[0031] Figure 18 It is a cross-sectional view showing a transparent display device according to an embodiment of the present disclosure

[0032] Figure 19 It is a cross-sectional view showing a transparent display device according to another embodiment of the present disclosure

[0033] In all the accompanying drawings and the detailed descriptions, unless otherwise specified, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and / or convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, as well as the depictions thereof, may be exaggerated. Detailed Description

[0034] The advantages and features of the present disclosure and the methods for realizing them are illustrated by the embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are examples and are provided so that the present disclosure can be thorough and complete, to help those skilled in the art understand the inventive concept without limiting the scope of the present disclosure.

[0035] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), ratios, angles, quantities, etc. disclosed herein (including those illustrated in the accompanying drawings) are merely examples, and thus, the present disclosure is not limited to the details illustrated. Any embodiment described herein as an "example" is not necessarily to be construed as preferred or superior to other embodiments. However, it should be noted that the relative dimensions of the components illustrated in the accompanying drawings are part of the present disclosure.

[0036] When terms such as "comprising", "including", "having", "containing", "constituting", "made of", "formed of", etc. are used with respect to one or more elements, one or more other elements may be added, unless terms such as "only" are used. The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the scope of the present disclosure. Singular forms of terms may include plural forms unless the context clearly indicates otherwise.

[0037] When interpreting an element, even if it is not explicitly described, the element is also interpreted as including an error range.

[0038] When describing positional relationships, for example, when the positional order is described as "on", "above", "under", "below", and "adjacent", cases where there is no contact therebetween may be included, unless "only" or "direct" is used.

[0039] When it is mentioned that a first element is "on" a second element, it does not mean that the first element is substantially above the second element in the drawing. The upper and lower parts of an object may change according to the orientation of the object. Therefore, the case where a first element is "on" a second element includes the case where the first element is "below" the second element and the case where the first element is "above" the second element in the drawing or in the actual configuration.

[0040] When describing temporal relationships, for example, when the chronological order is described as "after", "subsequently", "next", and "before", discontinuous cases may be included, unless "only" or "directly" is used.

[0041] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0042] When describing the elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to identify the corresponding elements from other elements, and these terms do not define the nature, basis, order, or quantity of the elements.

[0043] For the expressions such as an element "connected to", "coupled to", "attached to", "adhered to", etc. another element, the element can not only be directly connected to, coupled to, attached to, adhered to, etc. another element, but also be indirectly connected to, coupled to, attached to, adhered to, etc. another element when one or more intermediate elements are disposed or inserted between the elements, unless otherwise specified.

[0044] For the expressions such as an element "contacting", "overlapping", etc. another element, the element can not only be directly contacting, overlapping, etc. another element, but also be indirectly contacting, overlapping, etc. another element when one or more intermediate elements are disposed or inserted between the elements or layers.

[0045] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of the first element, the second element, and the third element" may include all combinations of more than two selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0046] The features of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, can be technically related to each other, and can be operably different, linked, or driven together. The embodiments of the present disclosure can be implemented or carried out independently of each other, or can be implemented or carried out together in a co-dependent or related relationship. In one or more aspects, the components of each device according to the various embodiments of the present disclosure are operably combined and configured.

[0047] In the following description, various exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Regarding the reference numerals assigned to the elements in each drawing, the same elements may be illustrated in other drawings, and similar reference numerals may refer to similar elements, unless otherwise specified. The same or similar elements may be denoted by the same reference numerals even if they are depicted in different drawings. In addition, for convenience of description, the ratios, dimensions, sizes, and thicknesses of each of the elements illustrated in the drawings may be different from the actual ratios, dimensions, sizes, and thicknesses, and thus, the embodiments of the present disclosure are not limited to the ratios, dimensions, sizes, and thicknesses shown in the drawings.

[0048] Figure 1 is a view showing a transparent display device according to an embodiment of the present disclosure. Figure 2 is a circuit diagram of sub-pixels of a transparent display device according to an embodiment of the present disclosure.

[0049] Hereinafter, the X-axis represents the direction parallel to the scan line, the Y-axis represents the direction parallel to the data line, and the Z-axis represents the height direction of the transparent display device.

[0050] Although a transparent display device according to an embodiment of the present disclosure may be described as being implemented as an organic light-emitting display (OLED), it may also be implemented as a liquid crystal display (LCD), a micro LED display, a quantum dot display (QD), or the like.

[0051] Referring to Figure 1 and Figure 2 , a transparent display device according to an embodiment of the present disclosure may include a transparent display panel 110, which includes a display area DA in which pixels are configured to display an image and a non-display area NDA that does not display an image.

[0052] The display area DA of the transparent display panel 110 may include a first signal line SL1, a second signal line SL2, and pixels, and the non-display area NDA of the transparent display panel 110 may include a pad area PA in which pads are provided and at least one gate driver 205.

[0053] The first signal line SL1 may extend in a first direction (or the Y-axis direction) and may cross the second signal line SL2 in the display area DA. The second signal line SL2 may extend in a second direction (or the X-axis direction). The pixels may be provided in an area where the first signal line SL1 and the second signal line SL2 cross each other and may emit light of a predetermined color to display an image.

[0054] The gate driver 205 may be connected to the scan lines to supply scan signals. The gate driver 205 may be implemented on a non-display area NDA outside one or both sides of the display area DA of the transparent display panel 110 by an in-panel gate (GIP) method or a tape automated bonding (TAB) method.

[0055] The source driver integrated circuit, circuit board, or timing controller connected through a flexible circuit film may be electrically connected to the pad area PA of the transparent display panel 110.

[0056] Referring Figure 2 , each of the pixels includes a plurality of sub-pixels constituting a unit pixel, and each of the sub-pixels includes circuit elements having a 3T1C structure (three transistors and one capacitor) (including a first switching transistor TR1, a second switching transistor TR2, a driving transistor DTR, and a capacitor Cst), and a light-emitting element ED, but is not limited thereto. Each sub-pixel may further include a compensation circuit, and in this case, may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0057] Each of the transistors DTR, TR1, and TR2 of each sub-pixel may include a gate, a source, and a drain. Since the source and the drain are not fixed and may change according to the current direction and the voltage applied to the gate, one of the source and the drain may be represented as a first electrode and the other may be represented as a second electrode. The transistors DTR, TR1, and TR2 of each sub-pixel may use at least one of a polysilicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor. The transistors DTR, TR1, and TR2 may be P-type or N-type transistors, or P-type and N-type transistors may be used interchangeably.

[0058] The first switching transistor TR1 may be used to supply the data voltage Vdata supplied from the data line DL to the driving transistor DTR. For example, the first switching transistor TR1 may charge the capacitor Cst with the data voltage Vdata supplied from the data line DL. To this end, the gate of the first switching transistor TR1 may be connected to the scan line SCANL (or gate line), and its first electrode may be connected to the data line DL. In addition, the second electrode of the first switching transistor TR1 may be connected to one end of the capacitor Cst and the gate of the driving transistor DTR.

[0059] The first switching transistor TR1 may be turned on in response to a scan signal Scan applied through the scan line SCANL (or gate line). When the first switching transistor TR1 is turned on, the data voltage Vdata applied through the data line DL may be transmitted to one end of the capacitor Cst.

[0060] The second switching transistor TR2 can be used to supply the reference voltage Vref supplied from the reference line REFL to the driving transistor DTR. For example, the gate of the second switching transistor TR can be connected to the scan line SCANL (or gate line), and its first electrode can be connected to the reference line REFL. In addition, the first electrode of the second switching transistor TR2 can be connected to the first electrode of the driving transistor DTR and the other end of the capacitor Cst.

[0061] The second switching transistor TR2 can be turned on in response to the scan signal Scan applied through the scan line SCANL (or gate line). When the second switching transistor TR2 is turned on, the reference voltage Vref applied through the reference line REFL can be transmitted to the other end of the capacitor Cst. In addition, the reference voltage Vref can be applied to the source of the driving transistor DTR.

[0062] The capacitor Cst can be used to maintain the data voltage Vdata supplied to the driving transistor DTR for one frame. For example, the first electrode of the capacitor Cst can be connected to the gate of the driving transistor DTR, and its second electrode can be connected to the source of the driving transistor DTR. The capacitor Cst can store the voltage corresponding to the data voltage Vdata transmitted through the first switching transistor TR1, and can turn on the driving transistor DTR with the stored voltage.

[0063] The driving transistor DTR can generate a data current using the first power supply EVDD supplied from the pixel power supply line VDDL (or the first power supply line) and supply the generated data current to the anode of the light-emitting element ED. For example, the gate of the driving transistor DTR can be connected to one end of the capacitor Cst, and its first electrode can be connected to the pixel power supply line VDDL. In addition, the second electrode of the driving transistor DTR can be connected to the anode of the light-emitting element ED.

[0064] The driving transistor DTR can be turned on according to the data voltage charged in the capacitor Cst. When the driving transistor DTR is turned on, the first power supply EVDD applied through the pixel power supply line VDDL can be transmitted to the anode of the light-emitting element ED.

[0065] The light-emitting element ED may include an anode connected to a driving transistor DTR, a cathode receiving a second power supply EVSS from a common power supply line VSSL (or a second power supply line), and a light-emitting layer between the anode and the cathode. The anode is an independent electrode for each light-emitting element, but the cathode may be a common electrode shared by the entire light-emitting element. When a driving current is provided from the driving transistor DTR, electrons from the cathode can be injected into the light-emitting layer and holes from the anode can be injected into the light-emitting layer, such that the light-emitting element ED can cause a fluorescent or phosphorescent material to emit light through recombination of electrons and holes in the light-emitting layer, thereby emitting light with a brightness proportional to the current value of the driving current.

[0066] The anode of the light-emitting element ED may be connected to a second electrode of the driving transistor DTR and its cathode may be connected to the common power supply line VSSL. The light-emitting element ED may emit light in response to a driving current generated by the driving transistor DTR.

[0067] Figure 3 is a view showing Figure 1 region A shown in Figure 4 is a view showing Figure 3 region B shown in Figure 5 is a cross-sectional view taken along Figure 4 line I-I' shown in

[0068] Referring to Figures 3 to 5 and combining Figure 1 and Figure 2 According to an embodiment of the present disclosure, the transparent display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may be an area that transmits most of the light incident from the outside, and the non-transmissive area NTA may be an area that does not transmit most of the light incident from the outside. For example, the transmissive area TA may be an area having a light transmittance greater than α%, and the non-transmissive area NTA may be an area having a light transmittance less than β. In this case, α may be a value greater than β. Due to the transmissive area TA, a user can see an object or a background located on the back surface (or the rear surface) of the transparent display panel 110.

[0069] The non-transmissive area NTA may include a first non-transmissive area NTA1, a second non-transmissive area NTA2, and a pixel P.

[0070] The first non-transmissive region NTA1 extends in the first direction (or the Y-axis direction) in the display region DA, and may be set to overlap at least a part of the light-emitting regions EA1, EA2, EA3, and EA4. A plurality of first non-transmissive regions NTA1 may be configured. The plurality of first non-transmissive regions NTA1 may extend in the first direction (or the Y-axis direction), and may be set to be spaced apart from each other in the second direction (or the X-axis direction). Two adjacent first non-transmissive regions NTA1 may be set to be spaced apart from each other (with the transmissive region TA interposed therebetween). For example, the transmissive region TA may be provided between two adjacent first non-transmissive regions NTA1. The first signal line SL1 extending in the first direction (or the Y-axis direction) may be provided in the first non-transmissive region NTA1. For example, the first signal line SL1 may be provided to overlap with the first non-transmissive region NTA1.

[0071] The first signal line SL1 may include at least one of a pixel power supply line VDDL (or a first power supply line), a common power supply line VSSL (or a second power supply line), a reference line REFL, and data lines DL1, DL2, DL3, and DL4. For example, the first signal line SL1 may further include a touch sensor line, but embodiments of the present disclosure are not limited thereto.

[0072] The pixel power supply line VDDL (or the first power supply line) may supply a first power supply EVDD to a driving transistor DTR of each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display region DA.

[0073] The common power supply line VSSL (or the second power supply line) may supply a second power supply EVSS to the cathodes of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display region DA. In this case, the second power supply EVSS may be a common power supply commonly supplied to the sub-pixels SP1, SP2, SP3, and SP4.

[0074] The reference line REFL may supply an initialization voltage (or a reference voltage) to a driving transistor DTR of each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display region DA. For example, the reference line REFL may be provided between a plurality of data lines DL1, DL2, DL3, and DL4. For example, the reference line REFL may be provided in the middle of a plurality of data lines DL1, DL2, DL3, and DL4.

[0075] Each of data lines DL1, DL2, DL3, and DL4 may supply a data voltage Vdata to sub-pixels SP1, SP2, SP3, and SP4. For example, the first data line DL1 may supply a first data voltage to a first driving transistor of the first sub-pixel SP1, the second data line DL2 may supply a second data voltage to a second driving transistor of the second sub-pixel SP2, the third data line DL3 may supply a third data voltage to a third driving transistor of the third sub-pixel SP3, and the fourth data line DL4 may supply a fourth data voltage to a fourth driving transistor of the fourth sub-pixel SP4.

[0076] The second non-transmissive region NTA2 may extend from the display region DA in a second direction (or X-axis direction), and may be set to overlap at least a part of the light-emitting regions EA1, EA2, EA3, and EA4. For example, the second non-transmissive region NTA2 may extend in the second direction (or X-axis direction) between two adjacent first non-transmissive regions NTA1. A plurality of second non-transmissive regions NTA2 may be configured. The plurality of second non-transmissive regions NTA2 may extend in the second direction (or X-axis direction), and may be set to be spaced apart from each other in a first direction (or Y-axis direction). Two adjacent second non-transmissive regions NTA2 may be set to be spaced apart from each other (a transmissive region TA is interposed therebetween). For example, the transmissive region TA may be provided between two adjacent second non-transmissive regions NTA2. A second signal line SL2 extending in the second direction (or X-axis direction) may be provided in the second non-transmissive region NTA2. For example, the second signal line SL2 may be provided to overlap with the second non-transmissive region NTA2.

[0077] The second signal line SL2 may extend in the second direction (or X-axis direction), and may include a scan line SCANL (or gate line). The scan line SCANL may supply a scan signal to sub-pixels SP1, SP2, SP3, and SP4 of the pixel P.

[0078] The pixel P can be disposed in each intersection region where the first non-transmissive region NTA1 and the second non-transmissive region NTA2 intersect each other, and can emit light to display an image. Each pixel P is disposed between adjacent transmissive regions TA, and the pixel P may include light-emitting regions EA1, EA2, EA3, and EA4 in which light-emitting elements are disposed to emit light. The light-emitting regions EA1, EA2, EA3, and EA4 may correspond to the regions in the pixel P that emit light. Since the area of the non-transmissive region NTA in the transparent display panel 110 is small, circuit elements can be disposed to overlap with the light-emitting regions EA1, EA2, EA3, and EA4. For example, the light-emitting regions EA1, EA2, EA3, and EA4 may at least partially overlap with circuit regions CA1, CA2, CA3, and CA4 in which circuit elements are disposed. For example, the circuit regions CA1, CA2, CA3, and CA4 may include a first circuit region CA1 in which circuit elements connected to the first sub-pixel SP1 are disposed, a second circuit region CA2 in which circuit elements connected to the second sub-pixel SP2 are disposed, a third circuit region CA3 in which circuit elements connected to the third sub-pixel SP3 are disposed, and a fourth circuit region CA4 in which circuit elements connected to the fourth sub-pixel SP4 are disposed.

[0079] Each pixel P is disposed in the first non-transmissive region NTA1 and can emit light to display an image. Each pixel P may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. The first sub-pixel SP1 may include a first light-emitting region EA1 that emits light of a first color, the second sub-pixel SP2 may include a second light-emitting region EA2 that emits light of a second color, the third sub-pixel SP3 may include a third light-emitting region EA3 that emits light of a third color, and the fourth sub-pixel SP4 may include a fourth light-emitting region EA4 that emits light of a fourth color. The first to fourth sub-pixels SP1, SP2, SP3, and SP4 may be disposed in a quadrilateral matrix along a first direction (or Y-axis direction) and a second direction (or X-axis direction). For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be disposed adjacent to a pixel power line VDDL (or a first power line), and the third sub-pixel SP3 and the fourth sub-pixel SP4 may be disposed adjacent to a common power line VSSL (or a second power line). A scan line SCANL (or a gate line) may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0080] The first to fourth light-emitting regions EA1, EA2, EA3, and EA4 may emit light of different colors. For example, the first light-emitting region EA1 may emit green light, the second light-emitting region EA2 may emit blue light, the third light-emitting region EA3 may emit white light, and the fourth light-emitting region EA4 may emit red light, but the embodiments of the present disclosure are not limited thereto. For example, various modifications may be made in the arrangement order or arrangement form of the respective sub-pixels SP1, SP2, SP3, and SP4.

[0081] A transparent display panel 110 according to an embodiment of the present disclosure may include light-emitting regions, wherein a plurality of light-emitting regions EA1, EA2, EA3, and EA4 respectively included in a plurality of sub-pixels SP1, SP2, SP3, and SP4 are divided into a plurality of light-emitting regions. For example, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first divided electrode 121 and a second divided electrode 122 in which first electrodes 120 (or anodes) of light-emitting elements are spaced apart from each other. Each of the first divided electrode 121 and the second divided electrode 122 may correspond to a divided light-emitting region. For example, the first light-emitting region EA1 provided in the first sub-pixel SP1 may include a first divided light-emitting region EA11 and a second divided light-emitting region EA12 corresponding to the first divided electrode 121 and the second divided electrode 122, and the second light-emitting region EA2 provided in the second sub-pixel SP2 may include a first divided light-emitting region EA21 and a second divided light-emitting region EA22 corresponding to the first divided electrode 121 and the second divided electrode 122. The third light-emitting region EA3 provided in the third sub-pixel SP3 may include a first divided light-emitting region EA31 and a second divided light-emitting region EA32 corresponding to the first divided electrode 121 and the second divided electrode 122. The fourth light-emitting region EA4 provided in the fourth sub-pixel SP4 may include a first divided light-emitting region EA41 and a second divided light-emitting region EA42 corresponding to the first divided electrode 121 and the second divided electrode 122.

[0082] The first divided electrode 121 and the second divided electrode 122 can be electrically connected to each other through a divided connection pattern DCP. The divided connection pattern DCP can be used to repair any dark spot of the first divided electrode 121 and the second divided electrode 122. For example, the divided connection pattern DCP can electrically connect the first divided electrode 121 and the second divided electrode 122 to the circuit regions CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4. For example, the divided connection pattern DCP can be set in the form of a "T". One end of the divided connection pattern DCP can branch out to both sides to be electrically connected to the first divided electrode 121 and the second divided electrode 122 respectively, and the other end of the divided connection pattern DCP can be electrically connected to the circuit regions CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4. When particles appear in any one of the first divided electrode 121 and the second divided electrode 122, the divided connection pattern DCP can block the electrical connection between the divided electrode with particles and the circuit regions CA1, CA2, CA3, and CA4, thereby being used to repair the divided electrode so that only the divided electrode with particles becomes a dark spot and the remaining divided electrodes work normally.

[0083] Referring to Figure 5 and in combination with Figure 4 , the transparent display panel 110 according to an embodiment of the present disclosure may include a first signal line (e.g., a data line DL, a pixel power supply line VDDL, and a common power supply line VSSL) disposed in the non-transmissive region NTA and extending along a first direction (or the Y-axis direction), a first electrode 120 (or an anode) of a light-emitting element, and a divided connection pattern DCP connecting the first divided electrode 121 and the second divided electrode 122 connected to the first electrode 120.

[0084] Specifically, at least one of the data line DL, the pixel power supply line VDDL, the common power supply line VSSL, or the reference line REFL of the first signal line may be disposed on the substrate 111. For example, as Figure 5 shown, the data line DL and the pixel power supply line VDDL may be disposed on the substrate 111. The data line DL and the pixel power supply line VDDL may be formed of the same material on the same layer on the substrate 111. The data line DL and the pixel power supply line VDDL may extend parallel to each other in the first direction (or the Y-axis direction) in the non-transmissive region NTA. The data line DL and the pixel power supply line VDDL may be arranged to be spaced apart from each other on the same layer. For example, the data line DL may be arranged adjacent to the pixel power supply line VDDL. In addition, the data line DL may be arranged adjacent to the common power supply line VSSL.

[0085] The data line DL and the pixel power supply line VDDL (or the common power supply line VSSL) can be disposed at the lowermost portion of the substrate 111. The data line DL and the pixel power supply line VDDL (or the common power supply line VSSL) can be formed of the same material as the light-shielding layer provided on the substrate 111 on the same layer. For example, the light-shielding layer can be used to shield external light incident on the active layer of the thin-film transistor. The light-shielding layer can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy of the foregoing materials. For example, the first signal line formed of the same material as the light-shielding layer on the substrate 111 on the same layer can be at least one of the data line DL, the pixel power supply line VDDL, the common power supply line VSSL, or the reference line REFL, but the embodiments of the present disclosure are not limited thereto.

[0086] The buffer layer BF can be disposed on the substrate 111 on which the data line DL, the pixel power supply line VDDL (or the common power supply line VSSL), and the light-shielding layer are provided. The buffer layer BF is used to protect the thin-film transistor from moisture that penetrates through the substrate 111 (which may be easily penetrated by moisture), and can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), nitrogen oxide (SiN X ), and aluminum oxide (Al2O3).

[0087] At least one insulating layer, a thin-film transistor, and at least one signal line can be disposed on the buffer layer BF. For example, as Figure 5 shown, the first passivation layer PAS1 can be disposed on the buffer layer BF. The second passivation layer PAS2 can be disposed on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), nitrogen oxide (SiN X ), and aluminum oxide (Al2O3).

[0088] The split connection pattern DCP can be disposed on the first passivation layer PAS1. For example, the split connection pattern DCP can be disposed between the first passivation layer PAS1 and the second passivation layer PAS2. The split connection pattern DCP can include a transparent or opaque conductive material. For example, the split connection pattern DCP can be a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi), and indium tin oxide (ITO) or a multiple layer including at least two of the foregoing materials, but the embodiments of the present disclosure are not limited thereto.

[0089] A planarization layer PLN for planarizing the step difference caused by thin film transistors and multiple signal lines may be provided on the second passivation layer PAS2. The planarization layer PLN may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0090] The first electrode, the light-emitting layer, and the second electrode constituting the light-emitting element may be provided on the planarization layer PLN. For example, as Figure 5 shown, the first electrode 120 (or anode) may be provided on the planarization layer PLN. The first electrode 120 may be electrically connected to the split connection pattern DCP through a contact hole passing through at least one insulating layer interposed therebetween. For example, the first electrode 120 may be electrically connected to the split connection pattern DCP through a contact hole passing through the planarization layer PLN and the second passivation layer PAS2. According to an embodiment of the present disclosure, the first electrode 120 may include a first split electrode 121 and a second split electrode 122 spaced apart from each other, and the first split electrode 121 and the second split electrode 122 of the first electrode 120 may be electrically connected to the split connection pattern DCP. The split connection pattern DCP may be used to repair a dark spot in any one of the first split electrode 121 and the second split electrode 122.

[0091] A transparent display panel 110 according to an embodiment of the present disclosure includes a non-transmissive region NTA provided with a light-emitting element and a transmissive region TA through which light can pass. The first electrode 120 of the light-emitting element is divided into a first split electrode 121 and a second split electrode 122, the first split electrode 121 and the second split electrode 122 are electrically connected to each other through a split connection pattern DCP, and a dark spot in any one of the first split electrode 121 and the second split electrode 122 can be repaired through a repair process of the split connection pattern DCP, thereby implementing or realizing the transparent display panel 110. In the transparent display panel 110 according to an embodiment of the present disclosure, the area of the transmissive region TA may be a main factor for increasing the light transmittance. Therefore, the inventors of the present disclosure invented a transparent display device having a new structure that can enlarge the transmissive region TA of the transparent display panel 110 through various studies and experiments.

[0092] Hereinafter, with reference to Figures 6 to 18 a more specific description will be given of a transparent display device according to another embodiment of the present disclosure that can increase the light transmittance by enlarging the transmissive region.

[0093] Figure 6 is a view showing the region B shown in Figure 3 according to an embodiment of the present disclosure, Figure 7 is a cross-sectional view taken along line II-II' shown in Figure 6 according to an embodiment of the present disclosure. In Figure 6 andFigure 7 In, with reference to Figures 1 to 5 the data line DL, pixel power supply line VDDL, common power supply line VSSL, and split connection pattern DCP in the transparent display panel 110 described in Figures 1 to 5 are modified. Accordingly, in the following description, the same reference numerals will be assigned to other identical elements except for the modified elements, and their redundant descriptions will be omitted or briefly described.

[0094] With reference to Figure 6 and Figure 7 and in combination with Figures 1 to 3 , a transparent display panel 110 according to another embodiment of the present disclosure may include a display area DA and a non-display area NDA, and the display area DA may include a transmissive area TA and a non-transmissive area NTA.

[0095] A transparent display panel 110 according to another embodiment of the present disclosure may include a first signal line SL1 (e.g., data line DL, pixel power supply line VDDL, and common power supply line VSSL) disposed in the non-transmissive area NTA and extending in a first direction (or Y-axis direction), a second signal line SL2 (e.g., scan line SCANL) disposed in the non-transmissive area NTA and the transmissive area TA and horizontally penetrating the transmissive area TA in a second direction (e.g., X-axis direction), a first electrode 120 of a light-emitting element including a first split electrode 121 and a second split electrode 122, and a split connection pattern DCP connecting the first split electrode 121 and the second split electrode 122 of the first electrode 120.

[0096] The first signal line SL1 may include at least one of a pixel power supply line VDDL (or a first power supply line), a common power supply line VSSL (or a second power supply line), a reference line, or data lines DL1, DL2, DL3, and DL4. The second signal line SL2 may include a scan line SCANL (or a gate line). For example, the first signal line SL1 may further include a touch sensor line, but embodiments of the present disclosure are not limited thereto.

[0097] The pixel power supply line VDDL (or the first power supply line) may supply a first power source EVDD to a driving transistor DTR of each of the sub-pixels SP1, SP2, SP3, and SP4 disposed in the display area DA. For example, the pixel power supply line VDDL may be disposed on one side (or the left side) in a second direction (or X-axis direction) of the plurality of sub-pixels SP1, SP2, SP3, and SP4. The first sub-pixel SP1 and the second sub-pixel SP2 among the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be disposed adjacent to the pixel power supply line VDDL.

[0098] The pixel power supply line VDDL may overlap at least a part of a plurality of data lines DL1, DL2, DL3, and DL4 (with at least one insulating layer interposed therebetween). The pixel power supply line VDDL may extend parallel to the plurality of data lines DL1, DL2, DL3, and DL4 in a first direction (or the Y-axis direction). For example, the pixel power supply line VDDL may be arranged to overlap the first data line DL1 and the second data line DL2 among the plurality of data lines DL1, DL2, DL3, and DL4. The width of the pixel power supply line VDDL may be equal to or greater than the widths of the first data line DL1 and the second data line DL2. For example, the width of the pixel power supply line VDDL may be configured to be greater than the combined width of the first data line DL1 and the second data line DL2.

[0099] The common power supply line VSSL (or the second power supply line) may supply a second power supply EVSS to the cathodes of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. In this case, the second power supply EVSS may be a common power supply commonly supplied to the sub-pixels SP1, SP2, SP3, and SP4. For example, the common power supply line VSSL may be provided on the other side (or the right side) in a second direction (or the X-axis direction) of the plurality of sub-pixels SP1, SP2, SP3, and SP4. The third sub-pixel SP3 and the fourth sub-pixel SP4 among the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be arranged adjacent to the common power supply line VSSL.

[0100] The common power supply line VSSL may overlap at least a part of a plurality of data lines DL1, DL2, DL3, and DL4 (with at least one insulating layer interposed therebetween). The common power supply line VSSL may extend parallel to the plurality of data lines DL1, DL2, DL3, and DL4 in a first direction (or the Y-axis direction). For example, the common power supply line VSSL may be arranged to overlap the third data line DL3 and the fourth data line DL4 among the plurality of data lines DL1, DL2, DL3, and DL4. The width of the common power supply line VSSL may be equal to or greater than the widths of the third data line DL3 and the fourth data line DL4. For example, the width of the common power supply line VSSL may be configured to be greater than the combined width of the third data line DL3 and the fourth data line DL4.

[0101] The reference line REFL can supply an initialization voltage (or reference voltage) to each of the driving transistors DTR of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. For example, the reference line REFL can be provided between the sub-pixels SP1, SP2, SP3, and SP4. The reference line REFL can be provided in the middle of the sub-pixels SP1, SP2, SP3, and SP4. For example, the reference line REFL can extend in a first direction (or Y-axis direction) between the first sub-pixel SP1 and the third sub-pixel SP3 and between the second sub-pixel SP2 and the fourth sub-pixel SP4.

[0102] Each of the data lines DL1, DL2, DL3, and DL4 can supply a data voltage Vdata to the sub-pixels SP1, SP2, SP3, and SP4. For example, the first data line DL1 and the second data line DL2 among the data lines DL1, DL2, DL3, and DL4 can be provided on one side (or the left side) of the plurality of sub-pixels SP1, SP2, SP3, and SP4 in a second direction (or X-axis direction). The first data line DL1 can supply a first data voltage to the first driving transistor of the first sub-pixel SP1, and the second data line DL2 can supply a second data voltage to the second driving transistor of the second sub-pixel SP2. The third data line DL3 and the fourth data line DL4 among the data lines DL1, DL2, DL3, and DL4 can be provided on the other side (or the right side) of the plurality of sub-pixels SP1, SP2, SP3, and SP4 in a second direction (or X-axis direction). The third data line DL3 can supply a third data voltage to the third driving transistor of the third sub-pixel SP3, and the fourth data line DL4 can supply a fourth data voltage to the fourth driving transistor of the fourth sub-pixel SP4.

[0103] The first data line DL1 and the second data line DL2 among the data lines DL1, DL2, DL3, and DL4 can overlap with the pixel power supply line VDDL (or the first power supply line). The first data line DL1 and the second data line DL2 can be spaced apart (with at least one insulating layer interposed therebetween) from the pixel power supply line VDDL in a vertical direction (or Z-axis direction or thickness direction). The first data line DL1 and the second data line DL2 can be spaced apart from each other in the width direction (or X-axis direction) of the pixel power supply line VDDL. For example, the spacing distance between the first data line DL1 and the second data line DL2 can be equal to or greater than the width of each of the first data line DL1 and the second data line DL2.

[0104] The third data line DL3 and the fourth data line DL4 among the data lines DL1, DL2, DL3, and DL4 may overlap with the common power supply line VSSL (or the second power supply line). The third data line DL3 and the fourth data line DL4 may be spaced apart from the common power supply line VSSL in the vertical direction (or the Z-axis direction or the thickness direction) (with at least one insulating layer interposed therebetween). The third data line DL3 and the fourth data line DL4 may be spaced apart from each other in the width direction (or the X-axis direction) of the common power supply line VSSL. For example, the spacing distance between the third data line DL3 and the fourth data line DL4 may be equal to or greater than the width of each of the third data line DL3 and the fourth data line DL4.

[0105] The scan line SCANL (or the gate line) may provide a scan signal to each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. The scan line SCANL may be provided in the non-transmissive area NTA and the transmissive area TA, and may be provided to horizontally penetrate the transmissive area TA in the second direction (or the X-axis direction). The scan line SCANL may be provided between the first sub-pixel SP1 and the second sub-pixel SP2 in the first direction (or the Y-axis direction), and may be provided between the third sub-pixel SP3 and the fourth sub-pixel SP4.

[0106] The split connection pattern DCP according to another embodiment of the present disclosure may be used to repair a dark spot in any one of the first split electrode 121 and the second split electrode 122. For example, the split connection pattern DCP may electrically connect the first split electrode 121 and the second split electrode 122 to the circuit areas CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4. For example, the split connection pattern DCP may be provided in the form of a "1" shape. The split connection pattern DCP branches to one end and the other end based on the middle part to be electrically connected to each of the first split electrode 121 and the second split electrode 122, and the middle part of the split connection pattern DCP may be electrically connected to the circuit areas CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4 through a connection pattern provided on a layer different from the split connection pattern DCP. The split connection pattern DCP may be formed of the same material as the pixel power supply line VDDL and the common power supply line VSSL on the same layer. When a particle appears in any one of the first split electrode 121 and the second split electrode 122, the split connection pattern DCP may block the electrical connection between the split electrode where the particle appears and the circuit areas CA1, CA2, CA3, and CA4, thereby being used to repair the split electrode so that only the split electrode where the particle appears becomes a dark spot and the remaining split electrodes operate normally.

[0107] Refer to Figure 7 And in combination with Figure 6, the data lines DL1, DL2, DL3, and DL4 can be disposed on the substrate 111. For example, as Figure 6 shown, on the substrate 111, the first data line DL1 and the second data line DL2 among the data lines DL1, DL2, DL3, and DL4 can be disposed adjacent to each other, and the third data line DL3 and the fourth data line DL4 can be disposed adjacent to each other.

[0108] The data lines DL1, DL2, DL3, and DL4 can be disposed at the lowermost end of the substrate 111. The data lines DL1, DL2, DL3, and DL4 can be formed of the same material as the light-shielding layer disposed on the substrate 111 on the same layer. For example, the light-shielding layer can be used to shield external light incident on the active layer of the thin-film transistor. The light-shielding layer can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of the foregoing materials. For example, the first signal line made of the same material as the light-shielding layer on the substrate 111 on the same layer can be at least one of the data lines DL1, DL2, DL3, and DL4 or the reference line REFL, but the embodiments of the present disclosure are not limited thereto.

[0109] The buffer layer BF can be disposed on the substrate 111 on which the data lines DL1, DL2, DL3, and DL4 and the light-shielding layer are disposed. The buffer layer BF is used to protect the thin-film transistor from moisture that penetrates through the substrate 111 (which may be easily penetrated by moisture), and can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3).

[0110] At least one insulating layer, a thin-film transistor, and at least one signal line can be disposed on the buffer layer BF. For example, as Figure 6 shown, the first passivation layer PAS1 can be disposed on the buffer layer BF. The second passivation layer PAS2 can be disposed on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3).

[0111] The pixel power supply line VDDL (or the first power supply line) and the common power supply line VSSL (or the second power supply line) can be disposed on the first passivation layer PAS1. The pixel power supply line VDDL and the common power supply line VSSL can be disposed between the first passivation layer PAS1 and the second passivation layer PAS2. The pixel power supply line VDDL and the common power supply line VSSL can be a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi), and indium tin oxide (ITO), or a multi-layer including at least two of the foregoing materials, but the embodiments of the present disclosure are not limited thereto.

[0112] The pixel power supply line VDDL and the common power supply line VSSL can overlap at least a part of the plurality of data lines DL1, DL2, DL3, and DL4 (with the first passivation layer PAS1 and the buffer layer BF interposed therebetween). For example, the pixel power supply line VDDL can overlap with the first data line DL1 and the second data line DL2 (with the first passivation layer PAS1 and the buffer layer BF interposed therebetween). The common power supply line VSSL can overlap with the third data line DL3 and the fourth data line DL4 (with the first passivation layer PAS1 and the buffer layer BF interposed therebetween).

[0113] The thickness of the pixel power supply line VDDL and the common power supply line VSSL can be equal to or different from the thickness of the plurality of data lines DL1, DL2, Dl3, and DL4. For example, the plurality of data lines DL1, DL2, DL3, and DL4 can be configured to have a first thickness T1, and the pixel power supply line VDDL and the common power supply line VSSL can be configured to have a second thickness T2. The first thickness T1 can be equal to or different from the second thickness T2.

[0114] The pixel power supply line VDDL and the common power supply line VSSL can be spaced apart from the plurality of data lines DL1, DL2, DL3, and DL4 by a first distance D1 in the vertical direction (or the Z-axis direction or the thickness direction) through the first passivation layer PAS1 and the buffer layer BF. The first passivation layer PAS1 and the buffer layer BF can have a thickness equal to or greater than the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. For example, the first passivation layer PAS1 and the buffer layer BF can have a thickness several times greater than the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. Therefore, the first distance D1 between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL1, DL2, DL3, and DL4 can be equal to or greater than several times the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4, and can be configured to reduce the influence of parasitic capacitance.

[0115] Figure 8 and Figure 9 is along another embodiment of the present disclosure Figure 6A cross-sectional view taken along line II-II' shown in the figure. In Figure 8 and Figure 9 , at least one insulating layer shown in Figure 7 is modified. Therefore, in the following description, the same reference numerals will be given to other identical elements except for the modified elements, and their repeated descriptions will be omitted or briefly described.

[0116] Referring to Figure 8 , a first planarization layer PLN1 may be provided on the buffer layer BF. The first planarization layer PLN1 is used to planarize the step difference caused by thin film transistors and a plurality of signal lines inserted between the first planarization layer PLN and the substrate 111, and may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0117] A pixel power supply line VDDL (or a first power supply line) and a common power supply line VSSL (or a second power supply line) may be provided on the first planarization layer PLN1. A passivation layer PAS and a second planarization layer PLN2 may be provided on the first planarization layer PLN1 on which the pixel power supply line VDDL and the common power supply line VSSL are provided. The passivation layer PAS may be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3). The second planarization layer PLN2 may be formed of the same material as the first planarization layer PLN1. The pixel power supply line VDDL and the common power supply line VSSL may be provided between the first planarization layer PLN1 and the passivation layer PAS.

[0118] The pixel power supply line VDDL and the common power supply line VSSL may overlap at least a part of a plurality of data lines DL1, DL2, DL3, and DL4 (with the first planarization layer PLN1 and the buffer layer BF interposed therebetween). For example, the pixel power supply line VDDL may overlap the first data line DL1 and the second data line DL2 (with the first planarization layer PLN1 and the buffer layer BF interposed therebetween). The common power supply line VSSL may overlap the third data line DL3 and the fourth data line DL4 (with the first planarization layer PLN1 and the buffer layer BF interposed therebetween).

[0119] The pixel power supply line VDDL and the common power supply line VSSL can be spaced apart from the plurality of data lines DL1, DL2, DL3, and DL4 by a second distance D2 in the vertical direction (or Z-axis direction or thickness direction) through the first planarization layer PLN1 and the buffer layer BF. The first planarization layer PLN1 and the buffer layer BF can have a thickness equal to or greater than the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. For example, the first planarization layer PLN1 and the buffer layer BF can have a thickness that is several times the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. For example, the second distance D2 can be equal to or greater than Figure 7 the first distance D1 shown. Therefore, the second distance D2 between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL1, DL2, DL3, and DL4 can be equal to or greater than several times the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4, and can be configured to further reduce the influence of the parasitic capacitance.

[0120] Referring to Figure 9 , the passivation layer PAS can be disposed on the buffer layer BF. The passivation layer PAS can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3).

[0121] The first planarization layer PLN1 can be disposed on the buffer layer BF. The first planarization layer PLN1 is used to planarize the step difference caused by the thin film transistors and the plurality of signal lines inserted between the first planarization layer PLN1 and the substrate 111, and can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0122] The pixel power supply line VDDL (or the first power supply line) and the common power supply line VSSL (or the second power supply line) can be disposed on the first planarization layer PLN1. The second planarization layer PLN2 can be disposed on the first planarization layer PLN1 on which the pixel power supply line VDDL and the common power supply line VSSL are disposed. The second planarization layer PLN2 can be formed of the same material as the first planarization layer PLN1. The pixel power supply line VDDL and the common power supply line VSSL can be disposed between the first planarization layer PLN1 and the second planarization layer PLN2.

[0123] The pixel power supply line VDDL and the common power supply line VSSL can overlap at least a part of the plurality of data lines DL1, DL2, DL3, and DL4 (with the first planarization layer PLN1, the passivation layer, and the buffer layer BF interposed therebetween). For example, the pixel power supply line VDDL can overlap with the first data line DL1 and the second data line DL2 (with the first planarization layer PLN1, the passivation layer PAS, and the buffer layer BF interposed therebetween). The common power supply line VSSL can overlap with the third data line DL3 and the fourth data line DL4 (with the first planarization layer PLN1, the passivation layer PAS, and the buffer layer BF interposed therebetween).

[0124] The pixel power supply line VDDL and the common power supply line VSSL can be spaced apart from the plurality of data lines DL1, DL2, DL3, and DL4 by a third distance D3 in the vertical direction (or Z-axis direction or thickness direction) through the first planarization layer PLN1, the passivation layer PAS, and the buffer layer BF. The first planarization layer PLN1, the passivation layer PAS, and the buffer layer BF can have a thickness equal to or greater than the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. For example, the first planarization layer PLN1, the passivation layer PAS, and the buffer layer BF can have a thickness several times that of the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4. For example, the third distance D3 can be equal to or greater than the first distance D1 or the second distance D2 as Figure 7 and Figure 8 shown. Therefore, the third distance D3 between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL1, DL2, DL3, and DL4 can be equal to or longer than several times the first thickness T1 of the plurality of data lines DL1, DL2, DL3, and DL4, and can be configured to further reduce the influence of parasitic capacitance.

[0125] Figure 10 is a cross-sectional view taken along line III-III' shown in another embodiment according to the present disclosure. In Figure 6 , in reference to Figure 10 , the data lines DL, the pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP in the transparent display panel 110 described in Figures 1 to 5 are modified. Therefore, in the following description, the same reference numerals will be given to other identical elements except for the modified elements, and their repeated descriptions will be omitted or briefly described.

[0126] Referring to Figure 10 and in combination with Figure 6, the data line DL can be disposed on the substrate 111. For example, among the data lines DL, the first data line DL1 and the second data line DL2 can be disposed adjacent to each other, and the third data line DL3 and the fourth data line DL4 can be disposed adjacent to each other.

[0127] The data line DL can be disposed at the lowermost end of the substrate 111 and can be formed of the same material as the light-shielding layer on the substrate 111 on the same layer.

[0128] A buffer layer BF can be disposed on the substrate 111 on which the data line DL and the light-shielding layer are disposed.

[0129] At least one insulating layer, a thin film transistor, and at least one signal line can be disposed on the buffer layer BF. For example, as Figure 10 shown, a connection pattern CP can be disposed on the buffer layer BF. The connection pattern CP can electrically connect the divided connection pattern DCP to the circuit regions CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4. The divided connection pattern DCP can be electrically connected to the circuit regions CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4 through the connection pattern CP. For example, the connection pattern CP can be disposed in the form of a "1" shape. The connection pattern CP can extend perpendicular to the divided connection pattern DCP. For example, the divided connection pattern DCP can be configured to extend along a first direction (or Y-axis direction), and the connection pattern CP can be configured to extend along a second direction (or X-axis direction) intersecting the first direction. The connection pattern CP can be disposed to overlap the middle portion of the divided connection pattern DCP. The connection pattern CP can be connected to the middle portion of the divided connection pattern DCP. The connection pattern CP can be disposed to cross the data line DL, the pixel power supply line VDDL, and the common power supply line VSSL. The connection pattern CP can be disposed on a layer different from the data line DL, the pixel power supply line VDDL, and the common power supply line VSSL. The connection pattern CP can be disposed on a different layer between the pixel power supply line VDDL and the common power supply line VSSL and the data line DL. For example, the connection pattern CP can be formed of the same material as the gate of the thin film transistor disposed on the buffer layer BF or the scan line SCANL on the same layer, but the embodiments of the present disclosure are not limited thereto.

[0130] An interlayer insulating layer ILD can be disposed on the buffer layer BF on which the connection pattern CP is disposed. For example, the interlayer insulating layer ILD can be disposed between the gate and the source / drain of the thin film transistor. The interlayer insulating layer ILD can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3).

[0131] The first passivation layer PAS1 may be provided on the interlayer insulating layer ILD. The second passivation layer PAS2 may be provided on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 may be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ), and aluminum oxide (Al2O3).

[0132] The pixel power supply line VDDL (or the first power supply line) and the common power supply line VSSL (or the second power supply line) may be provided on the first passivation layer PAS1. The pixel power supply line VDDL and the common power supply line VSSL may be provided between the first passivation layer PAS1 and the second passivation layer PAS2. The split connection pattern DCP may be provided on the same layer as the pixel power supply line VDDL and the common power supply line VSSL on the first passivation layer PAS1. The split connection pattern DCP may be provided in the transmissive area TA. The split connection pattern DCP may be provided between the first passivation layer PAS1 and the second passivation layer PAS2.

[0133] The split connection pattern DCP may be used to repair a dark spot in any one of the first split electrode 121 and the second split electrode 122. For example, the split connection pattern DCP may electrically connect the first split electrode 121 and the second split electrode 122 to the circuit areas CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4 through the connection pattern CP. For example, the split connection pattern DCP may be set in the form of a "1" shape. The split connection pattern DCP branches to one end and the other end based on the middle part to be electrically connected to each of the first split electrode 121 and the second split electrode 122, and the middle part of the split connection pattern DCP may be electrically connected to the circuit areas CA1, CA2, CA3, and CA4 of the sub-pixels SP1, SP2, SP3, and SP4 through the connection pattern CP provided on a layer different from the split connection pattern DCP. The split connection pattern DCP may be electrically connected to the connection pattern CP through a contact hole passing through the first passivation layer PAS1 and the interlayer insulating layer ILD.

[0134] The pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP may be a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi), and indium tin oxide (ITO), or may be a multilayer including at least two of the foregoing materials. For example, the pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP may have a multilayer structure including a transparent metal layer and an opaque metal layer. For example, the pixel power supply line VDDL may include a first layer VDDLa made of a transparent metal layer and a second layer VDDLb laminated on the first layer VDDLa and made of an opaque metal layer. The split connection pattern DCP may include a first layer DCPa made of a transparent metal layer and a second layer VDDLb laminated on the first layer DCPb and made of an opaque metal layer. For example, the first layers VDDLa and DCPa of the pixel power supply line VDDL and the split connection pattern DCP may be made of indium tin oxide (ITO), but the embodiments of the present disclosure are not limited thereto. The second layers VDDLb and DCPb of the pixel power supply line VDDL and the split connection pattern DCP may be a single layer including at least one of molybdenum (Mo), copper (Cu), or molybdenum titanium (MoTi), or a multilayer including at least two of the foregoing materials, but the embodiments of the present disclosure are not limited thereto. Although Figure 10 only the pixel power supply line VDDL is shown in

[0135] a planarization layer PLN for planarizing the step difference caused by the thin film transistor and the plurality of signal lines may be provided on the second passivation layer PAS2. The planarization layer PLN may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0136] The first electrode, the light emitting layer, and the second electrode constituting the light emitting element may be provided on the planarization layer PLN. For example, as Figure 10 shown, the first electrode 120 (or anode) may be provided on the planarization layer PLN. The first electrode 120 may be electrically connected to the split connection pattern DCP through a contact hole passing through the planarization layer PLN and the second passivation layer PAS2 inserted between the first electrode and the split connection pattern DCP.

[0137] Figure 11 is a cross-sectional view taken along the line III-III' shown in another embodiment of the present disclosure. In Figure 6 shown, Figure 11 in Figure 10 the split connection pattern shown in

[0138] Reference Figure 11 Referring to Figure 11 , the divided connection pattern DCP may be disposed on the first passivation layer PAS1. The divided connection pattern DCP may be disposed in the transmissive region TA. The divided connection pattern DCP may be formed of a transparent metal layer to increase the light transmittance of the transmissive region TA. At least a part of the pixel power line VDDL and the common power line VSSL disposed in the non-transmissive region NTA may be formed of the same material as the divided connection pattern DCP. For example, the pixel power line VDDL may include a first layer VDDLa made of a transparent metal layer and a second layer VDDLb stacked on the first layer VDDLa and made of an opaque metal layer. The divided connection pattern DCP may include a first layer DCPa made of a transparent metal layer. For example, the first layer VDDLa of the pixel power line VDDL and the divided connection pattern DCP and the DCPa may be made of indium tin oxide (ITO), but embodiments of the present disclosure are not limited thereto. The second layer VDDLb of the pixel power line VDDL may be a single layer including at least one of molybdenum (Mo), copper (Cu), or molybdenum titanium (MoTi) or may be formed of multiple layers including at least two of the foregoing materials, but embodiments of the present disclosure are not limited thereto. For example, the pixel power line VDDL and the divided connection pattern DCP are formed simultaneously through the same process and the second layer of the divided connection pattern DCP is removed by selective etching, whereby the divided connection pattern DCP made only of the transparent first layer DCPa may be implemented or realized.

[0139] Figure 12 is a plan view showing a power line and a data line according to an embodiment of the present disclosure.

[0140] Reference Figure 12 Referring to Figure 12 , the pixel power line VDDL and the common power line VSSL according to an embodiment of the present disclosure may overlap at least a part of the plurality of data lines DL. The pixel power line VDDL, the common power line VSSL, and the plurality of data lines DL may be disposed in parallel in a first direction (or Y-axis direction).

[0141] The widths of the pixel power line VDDL and the common power line VSSL may be equal to or wider than the plurality of data lines DL. For example, the pixel power line VDDL and the common power line VSSL may be configured to have a first width W1, and each of the plurality of data lines DL may be configured to have a second width W2. The first width W1 may be equal to or wider than the second width W2. For example, the first width W1 may be several times wider than the second width W2.

[0142] Multiple data lines DL overlapping with each of the pixel power supply line VDDL and the common power supply line VSSL may be spaced apart from each other in the width direction (or X-axis direction or second direction) of the pixel power supply line VDDL and the common power supply line VSSL. The spacing distance SD1 between the multiple data lines DL may be equal to or greater than the width W2 of each of the multiple data lines DL. For example, the multiple data lines DL may not overlap with the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction). The multiple data lines DL may be symmetrically arranged with respect to the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction).

[0143] Figures 13 to 17 is a plan view showing a power supply line and a data line according to another embodiment of the present disclosure. In Figures 13 to 17 as Figure 12 shown, the power supply line and the data line are modified. Accordingly, in the following description, the same reference numerals will be given to other identical elements except for the modified elements, and their repeated descriptions will be omitted or briefly described.

[0144] Referring to Figure 13 , the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure may overlap at least a portion of the multiple data lines DL.

[0145] The multiple data lines DL may be arranged to be adjacent to one edge of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction). The multiple data lines DL may not overlap with the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction). For example, the multiple data lines DL may be arranged to be adjacent to the left edge of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction). Alternatively, the multiple data lines DL may be arranged to be adjacent to the right edge of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction).

[0146] Referring to Figure 14 , the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure may overlap at least a portion of the multiple data lines DL.

[0147] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a grid pattern including a grid. For example, the pixel power supply line VDDL and the common power supply line VSSL may be configured as a stepped grid pattern.

[0148] The pixel power supply line VDDL and the common power supply line VSSL may include a first grid line VL1 extending in a first direction (or the Y-axis direction) and a second grid line VL2 extending in a second direction (or the X-axis direction) intersecting the first direction (or the X-axis direction). The first grid line VL1 may include a pair of lines parallel to each other in the first direction (or the Y-axis direction) and spaced apart from each other in the second direction (or the X-axis direction) (a plurality of data lines DL are inserted therebetween). The second grid line VL2 may be disposed between the pair of first grid lines VL1 and may be formed of a plurality of lines spaced apart from each other in the first direction.

[0149] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a third width W3, and each of the plurality of data lines DL may be configured to have a second width W2. The third width W3 may be the same as or wider than the second width W2. For example, the third width W3 may be several times wider than the second width W2.

[0150] The plurality of data lines DL overlapping each of the pixel power supply line VDDL and the common power supply line VSSL may be spaced apart from each other in the width direction (or the X-axis direction or the second direction) of the pixel power supply line VDDL and the common power supply line VSSL. The spacing distance SD1 between the plurality of data lines DL may be equal to or greater than the width W2 of each of the plurality of data lines DL. For example, the plurality of data lines DL may not overlap the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or the X-axis direction or the second direction) and may be symmetrically disposed with respect to the middle portion CL. For example, the plurality of data lines DL may not overlap the first grid line VL1 of the pixel power supply line VDDL1 and the common power supply line VSSL. The plurality of data lines DL may be spaced apart from the first grid line VL1. The spacing distance SD2 between the plurality of data lines DL and the first grid line VL1 may be equal to or shorter than the width W2 of each of the plurality of data lines DL.

[0151] Since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, the overlapping regions of the pixel power supply line VDDL, the common power supply line VSSL, and the plurality of data lines DL with each other can be reduced, thereby reducing the influence of parasitic capacitance. In addition, since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, when a contact defect occurs between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL, a repair structure capable of repairing the contact defect by cutting the first grid line VL1 and / or the second grid line VL2 around the data line DL having the contact defect can be provided.

[0152] Refer to Figure 15, according to another embodiment of the present disclosure, the pixel power supply line VDDL and the common power supply line VSSL may overlap at least a portion of the plurality of data lines DL.

[0153] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a grid pattern including a polygonal shape. For example, the pixel power supply line VDDL and the common power supply line VSSL may be configured as a hexagonal grid pattern.

[0154] The pixel power supply line VDDL and the common power supply line VSSL may include a first grid line VL1 extending in a first direction (or Y-axis direction) and a second grid line VL2 extending in a second direction (or X-axis direction) intersecting the first direction (or X-axis direction). The first grid line VL1 may extend in a zigzag pattern in the first direction (or Y-axis direction) and may include a pair of lines spaced apart from each other in the second direction (or X-axis direction) (with the plurality of data lines DL inserted therebetween). The second grid line VL2 may include a plurality of lines disposed between the pair of first grid lines VL1 and spaced apart from each other in the first direction.

[0155] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a fourth width W4, and each of the plurality of data lines DL may be configured to have a second width W2. The fourth width W4 may be the same as or wider than the second width W2. For example, the fourth width W4 may be several times wider than the second width W2.

[0156] The plurality of data lines DL do not overlap with the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction), and may be symmetrically disposed with respect to the middle portion CL. For example, the plurality of data lines DL may not overlap with the first grid line VL1 of the pixel power supply line VDDL and the common power supply line VSSL. The plurality of data lines DL may be spaced apart from the first grid line VL1. The maximum spacing distance SD3 between the plurality of data lines DL and the first grid line VL1 may be equal to or greater than the width W2 of each of the plurality of data lines DL.

[0157] Since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, the overlapping area of the pixel power supply line VDDL, the common power supply line VSSL, and the plurality of data lines DL can be reduced, thereby reducing the influence of parasitic capacitance. In addition, since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, when a contact defect occurs between the pixel power supply line VDDL, the common power supply line VSSL, and the plurality of data lines DL, a repair structure capable of repairing the contact defect by cutting the first grid line VL1 and / or the second grid line VL2 around the data line DL having the contact defect can be provided.

[0158] Referring to Figure 16 , the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure may overlap at least a portion of the plurality of data lines DL.

[0159] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a grid pattern including a circular shape. For example, the pixel power supply line VDDL and the common power supply line VSSL may be configured as a circular grid pattern.

[0160] The pixel power supply line VDDL and the common power supply line VSSL may include partially circular first grid lines VL1 extending in a first direction (or Y-axis direction) and partially circular second grid lines VL2 extending in a second direction (or X-axis direction) intersecting the first direction. The first grid lines VL1 and the second grid lines VL2 may be formed of substantially circular lines. The first grid lines VL1 and the second grid lines VL2 may be formed of circular lines that overlap each other in the first direction (or Y-axis direction) while repeating.

[0161] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a fifth width W5, and each of the plurality of data lines DL may be configured to have a second width W2. The fifth width W5 may be the same as or wider than the second width W2. For example, the fifth width W5 may be several times wider than the second width W2.

[0162] The plurality of data lines DL do not overlap the middle portion CL of the pixel power supply line VDDL and the common power supply line VSSL in the width direction (or X-axis direction or second direction), and may be symmetrically arranged with respect to the middle portion CL. For example, the plurality of data lines DL may not overlap the first grid lines VL1 of the pixel power supply line VDDL and the common power supply line VSSL. The plurality of data lines DL may be spaced apart from the first grid lines VL1. The maximum spacing distance SD4 between the plurality of data lines DL and the first grid lines VL1 may be equal to or greater than the width W2 of each of the plurality of data lines DL.

[0163] Since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, the overlapping area of the pixel power supply line VDDL, the common power supply line VSSL, and the plurality of data lines DL can be reduced, thereby reducing the influence of parasitic capacitance. In addition, since the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, when a contact defect occurs between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL, a repair structure capable of repairing the contact defect by cutting the first grid line VL1 and / or the second grid line VL2 around the data line DL having the contact defect can be provided.

[0164] Referring to Figure 17 , the pixel power supply line VDDL and the common power supply line VSSL according to another embodiment of the present disclosure may overlap at least a portion of the plurality of data lines DL.

[0165] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a grid pattern including a polygonal shape. For example, the pixel power supply line VDDL and the common power supply line VSSL may be configured as a shaped grid pattern. For example, the pixel power supply line VDDL and the common power supply line VSSL may be configured as a rhombic grid pattern.

[0166] The pixel power supply line VDDL and the common power supply line VSSL may include a first grid line VL1 extending in a diagonal direction between a first direction (or Y-axis direction) and a second direction (or X-axis direction) and a second grid line VL2 extending in another diagonal direction crossing the diagonal direction of the first grid line VL1. The first grid line VL1 and the second grid line VL2 may be configured to cross each other.

[0167] The pixel power supply line VDDL and the common power supply line VSSL may be configured to have a fifth width W5, and each of the plurality of data lines DL may be configured to have a second width W2. The fifth width W5 may be the same as or wider than the second width W2. For example, the fifth width W5 may be several times wider than the second width W2.

[0168] A plurality of data lines DL may not overlap with an intermediate portion CL of a pixel power supply line VDDL and a common power supply line VSSL in a width direction (or an X-axis direction or a second direction), and may be symmetrically disposed with respect to the intermediate portion CL. For example, the plurality of data lines DL and the pixel power supply line VDDL and the common power supply line VSSL may be spaced apart from each other at an outer intersection where a first grid line VL1 and a second grid line VL2 are connected to each other. A spacing distance SD4 between intersections of the plurality of data lines DL with the first grid line VL1 and the second grid line VL2 may be equal to or shorter than a width W2 of each of the plurality of data lines DL.

[0169] Since a pixel power supply line VDDL and a common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, an overlapping region between the pixel power supply line VDDL, the common power supply line VSSL, and the plurality of data lines DL can be reduced, thereby reducing the influence of parasitic capacitance. In addition, since a pixel power supply line VDDL and a common power supply line VSSL according to another embodiment of the present disclosure are configured to have a grid pattern, when a contact defect occurs between the pixel power supply line VDDL and the common power supply line VSSL and the plurality of data lines DL, a repair structure capable of repairing the contact defect by cutting the first grid line VL1 and / or the second grid line VL2 around the data line DL having the contact defect can be provided.

[0170] Figure 18 is a cross-sectional view showing a transparent display device according to an embodiment of the present disclosure.

[0171] Referring to Figure 18 and in conjunction with Figures 1 to 3 , a transparent display panel 110 according to an embodiment of the present disclosure may include a display area DA and a pad area PA on a substrate 111. For example, the pad area PA may be a part of a non-display area NDA near the display area DA.

[0172] A transparent display panel 110 according to an embodiment of the present disclosure may include a substrate 111, a light-shielding layer LS, a plurality of data lines DL1, DL2, DL3, and DL4, a reference line REFL, a pad electrode PE, a buffer layer BF, an active layer ACT of a thin-film transistor, a gate insulating layer GI, a gate GE, a first source / drain SDE1, a second source / drain SED2, an interlayer insulating layer ILD, a first passivation layer PAS1, a pixel power supply line VDDL, a common power supply line VSSL, a split connection pattern DCP, a second passivation layer PAS2, a planarization layer PLN, a light-emitting element ED, a bank layer BA, etc.

[0173] The substrate 111 is a base substrate and can be made of a glass material or a plastic material. For example, the substrate 111 is formed of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polycarbonate (PC), and thus may have flexible characteristics, but the embodiments of the present disclosure are not limited thereto.

[0174] The first signal line SL1 and the second signal line SL2, circuit elements including thin film transistors DTR, TR1, and TR2, and a storage capacitor Cst. The storage capacitor Cst can be formed on the substrate 111 for each of a plurality of sub-pixels SP1, SP2, SP3, and SP4. For example, the first signal line SL1 may include a pixel power supply line VDDL (or a first power supply line), a common power supply line VSSL (or a second power supply line), a reference line REFL, and data lines DL1, DL2, DL3, and DL4. The second signal line SL2 may include a scan line SCANL (or a gate line). The thin film transistors DTR, TR1, and TR2 may include a driving transistor DTR, a first switching transistor TR1, and a second switching transistor TR2, but the embodiments of the present disclosure are not limited thereto.

[0175] The light shielding layer LS, a plurality of data lines DL1, DL2, DL3, and DL4, and the reference line REFL may be provided in the display area DA on the substrate 111. The light shielding layer LS may overlap at least a part of the thin film transistors DTR, TR1, and TR2. For example, the light shielding layer LS may overlap the active layer ACT of the thin film transistor. The light shielding layer LS may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of the foregoing materials. For example, the light shielding layer LS, the plurality of data lines DL1, DL2, DL3, and DL4, and the reference line REFL on the substrate 111 may be formed of the same material on the same layer. For example, the light shielding layer LS, the plurality of data lines DL1, DL2, DL3, and DL4, and the reference line REFL may be formed simultaneously through the same process, but the embodiments of the present disclosure are not limited thereto. For example, the reference line REFL may be provided between adjacent sub-pixels SP1, SP2, SP3, and SP4, and the first data line DL1 and the second data line DL2 among the data lines DL1, DL2, DL3, and DL4 may be provided on one side of the sub-pixels SP1, SP2, SP3, and SP4, and the third data line DL3 and the fourth data line DL4 among the data lines DL1, DL2, DL3, and DL4 may be provided on the other side of the sub-pixels SP1, SP2, SP3, and SP4.

[0176] A buffer layer BF can be provided on the substrate 111 to cover the light-shielding layer LS, the plurality of data lines DL1, DL2, DL3, and DL4, and the reference line REFL. The buffer layer BF protects the thin-film transistors from moisture that penetrates through the substrate 111 (which may be easily penetrated by moisture), and can be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ) and nitrogen oxide (SiN X ) and aluminum oxide (Al2O3).

[0177] The buffer layer BF can be provided on the entire upper surface of the substrate 111 or a part of the upper surface of the substrate 111 to block ions or impurities diffusing from the substrate 111 and block moisture from penetrating through the substrate 111 into the light-emitting element ED. For example, the buffer layer BF can be formed on the entire display area DA of the substrate 111 and may not be formed in the non-display area NDA of the substrate 111, but embodiments of the present disclosure are not limited thereto.

[0178] At least one insulating layer, a thin-film transistor, and at least one signal line can be provided on the buffer layer BF. For example, the thin-film transistor can be provided on the buffer layer BF. The thin-film transistor can include an active layer ACT provided on the buffer layer BF, a gate GE, a first source / drain SDE1, and a second source / drain SDE2.

[0179] A gate insulating layer GI can be provided between the active layer ACT and the gate GE. The gate insulating layer GI can be patterned only in the area where the gate GE is provided, or can be formed to cover the active layer ACT, but embodiments of the present disclosure are not limited thereto.

[0180] An interlayer insulating layer ILD can be provided between the gate GE and the first source / drain SDE1 and the second source / drain SDE2. The first source / drain SDE1 and the second source / drain SDE2 of the thin-film transistor can be electrically connected to the active layer ACT through contact holes passing through the interlayer insulating layer ILD.

[0181] The active layer ACT can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. The gate GE, the first source / drain SDE1, and the second source / drain SDE2 can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of the foregoing materials, but embodiments of the present disclosure are not limited thereto.

[0182] The gate insulating layer GI and the interlayer insulating layer ILD can be formed of an inorganic insulating material including, for example, silicon oxide (SiO X ) and nitrogen oxide (SiN X) and a single layer or multiple layers of an inorganic insulating material of aluminum oxide (Al2O3) are formed, but the embodiments of the present disclosure are not limited thereto.

[0183] The first passivation layer PAS1 may be disposed on the interlayer insulating layer ILD provided with the first source / drain SDE1 and the second source / drain SDE2 of the thin film transistor. The second passivation layer PAS2 may be disposed on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 may be formed of a single layer or multiple layers of an inorganic insulating material including, for example, silicon oxide (SiO X ), silicon oxynitride (SiN X ) and aluminum oxide (Al2O3).

[0184] The pixel power supply line VDDL (or the first power supply line) and the common power supply line VSSL (or the second power supply line) may be disposed on the first passivation layer PAS1 of the display area DA. The pixel power supply line VDDL and the common power supply line VSSL may be disposed between the first passivation layer PAS1 and the second passivation layer PAS2. For example, the pixel power supply line VDDL and the common power supply line VSSL may be disposed in the non-transmissive area NTA of the display area DA. For example, the pixel power supply line VDDL may be disposed to overlap with the first data line DL1 and the second data line DL2, and the common power supply line VSSL may be disposed to overlap with the third data line DL3 and the fourth data line DL4.

[0185] On the first passivation layer PAS1 of the display area DA, a split connection pattern DCP made of the same material as the pixel power supply line VDDL and the common power supply line VSSL may be disposed on the same layer as the pixel power supply line VDDL and the common power supply line VSSL. For example, the split connection pattern DCP may be disposed in the transmissive area TA of the display area DA.

[0186] The pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP may be made of a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi), and indium tin oxide (ITO), or multiple layers including at least two of the foregoing materials, but the embodiments of the present disclosure are not limited thereto.

[0187] A planarization layer PLN for planarizing the step difference caused by the thin film transistor and the multiple signal lines may be disposed on the second passivation layer PAS2. The planarization layer PLN may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0188] A light-emitting element ED including a first electrode 120, an organic light-emitting layer 130, and a second electrode 140, and a bank layer BA may be disposed on a planarization layer PLN. For example, the first electrode 120 may be provided for each of the sub-pixels SP1, SP2, SP3, and SP4, and the first electrode 120 may be disposed in a non-transmissive region NTA. The first electrode 120 may be formed of a metal material having a high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTiAg alloy, a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a stacked structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be an anode of the light-emitting element ED. The organic light-emitting layer 130 and the second electrode 140 may be disposed on the first electrode 120. The first electrode 120, the organic light-emitting layer 130, and the second electrode 140 may constitute the light-emitting element ED.

[0189] The bank layer BA may be disposed on the planarization layer PLN. The bank layer BA may be disposed between the first electrodes 120. For example, the bank layer BA may be configured to cover an edge in each of the first electrodes 120 and expose a part of each of the first electrodes 120. The bank layer BA may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0190] The organic light-emitting layer 130 may be disposed on the first electrode 120. The organic light-emitting layer 130 may include a hole transport layer, a light-emitting material layer, and an electron transport layer. For example, when a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move to the organic light-emitting layer 130 through the hole transport layer and the electron transport layer, respectively, and may combine with each other in the light-emitting layer to emit light.

[0191] The second electrode 140 may be a common layer formed in the sub-pixels SP1, SP2, SP3, and SP4 together to apply the same voltage. The second electrode 140 may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 140 is formed of a semi-transmissive metal material, the light-emitting efficiency may be increased by a microcavity. The second electrode 140 may be a cathode of the light-emitting element ED.

[0192] The non-display area NDA on the substrate 111 may include a pad area PA. Pad electrodes PE may be disposed in the pad area PA on the substrate 111. The pad electrodes PE may include a first pad electrode PE1 and a second pad electrode PE2. At least a portion of the pad electrodes PE may be formed of the same material as the pixel power line VDDL, the common power line VSSL, and the split connection pattern DCP disposed in the display area DA on the substrate 111.

[0193] The first pad electrode PE1 made of the same material as the gate insulating layer GI and the gate GE may be disposed in the pad area PA on the substrate 111. For example, the first pad electrode PE1 may be formed of the same material as the gate insulating layer GI and the gate GE of the thin film transistor on a layer different from the gate insulating layer GI and the gate GE.

[0194] The second pad electrode PE2 may be disposed on the first pad electrode PE1. For example, the second pad electrode PE2 may be configured to cover the first pad electrode PE1 and the gate insulating layer GI. The second pad electrode PE2 may be formed of the same material as at least a portion of the pixel power line VDDL, the common power line VSSL, and the split connection pattern DCP. For example, the second pad electrode PE2 may be formed of the same material as the pixel power line VDDL, the common power line VSSL, and the split connection pattern DCP on a layer different from the pixel power line VDDL, the common power line VSSL, and the split connection pattern DCP.

[0195] The second passivation layer PAS2 and the bank layer BA may be disposed on the second pad electrode PE2. For example, the second passivation layer PAS2 and the bank layer BA may be configured to cover the edge of the second pad electrode PE2.

[0196] Figure 19 is a cross-sectional view showing a transparent display device according to another embodiment of the present disclosure. In Figure 19 In, the pixel power line VDDL, the common power line VSSL, the split connection pattern DCP, and the pad electrodes PE in the transparent display panel 110 described with reference to Figure 18 are modified. Therefore, in the following description, the same reference numerals will be given to other identical elements except for the modified elements, and their repeated descriptions will be omitted or briefly described.

[0197] Referring to Figure 19 According to another embodiment of the present disclosure, the pixel power line VDDL and the common power line VSSL may include, as Figure 11As shown, a first layer made of a transparent metal layer and a second layer stacked on the first layer and made of an opaque metal layer. The pixel power supply line VDDL and the common power supply line VSSL may be disposed in the non-transmissive area NTA of the display area DA. At least a part of the pixel power supply line VDDL and the common power supply line VSSL may be formed of the same material as that of the split connection pattern DCP. The split connection pattern DCP may be disposed in the transmissive area TA of the display area DA.

[0198] The split connection pattern DCP may include a first layer made of a transparent metal layer. For example, the first layer of each of the pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP may be formed of indium tin oxide (ITO), but embodiments of the present disclosure are not limited thereto. The second layer of the pixel power supply line VDDL and the common power supply line VSSL may be a single layer including at least one of molybdenum (Mo), copper (Cu), or molybdenum titanium (MoTi) or may be formed of a multi-layer including at least two of the foregoing materials, but embodiments of the present disclosure are not limited thereto. For example, the pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP are formed simultaneously by the same process, and the second layer of the split connection pattern DCP is removed by selective etching, whereby the split connection pattern DCP made only of the transparent first layer can be implemented or realized.

[0199] The pad electrode PE may be disposed in the pad area PA on the substrate 111. The pad electrode PE may include a first pad electrode PE1, a second pad electrode PE2, and a third pad electrode PE3. At least a part of the pad electrode PE may be formed of the same material as that of the pixel power supply line VDDL, the common power supply line VSSL, and the split connection pattern DCP disposed in the display area DA on the substrate 111.

[0200] The first pad electrode PE1 made of the same material as that of the gate insulating layer GI and the gate GE may be disposed in the pad area PA on the substrate 111. For example, the first pad electrode PE1 may be formed of the same material as that of the gate insulating layer GI and the gate GE of the thin film transistor on a layer different from the gate insulating layer GI and the gate GE.

[0201] The second pad electrode PE2 and the third pad electrode PE3 may be disposed on the first pad electrode PE1. For example, the second pad electrode PE2 and the third pad electrode PE3 may be configured to cover the first pad electrode PE1 and the gate insulating layer GI.

[0202] The second pad electrode PE2 may be formed of the same material as at least a part of the pixel power supply line VDDL, the common power supply line VSSL, and the divided connection pattern DCP. For example, the second pad electrode PE2 may be formed of the same material as the transparent first layer of the pixel power supply line VDDL, the common power supply line VSSL, and the divided connection pattern DCP. For example, the second pad electrode PE2 may be formed of the same material as the transparent first layer on a layer different from the transparent first layer of the pixel power supply line VDDL, the common power supply line VSSL, and the divided connection pattern DCP.

[0203] The third pad electrode PE3 may be formed of the same material as at least a part of the pixel power supply line VDDL and the common power supply line VSSL. For example, the third pad electrode PE3 may be formed of the same material as the opaque second layer of the pixel power supply line VDDL and the common power supply line VSSL. For example, the third pad electrode PE3 may be formed of the same material as the opaque second layer on a layer different from the opaque second layer of the pixel power supply line VDDL and the common power supply line VSSL.

[0204] The second passivation layer PAS2 and the bank layer BA may be disposed on the third pad electrode PE3. For example, the second passivation layer PAS2 and the bank layer BA may be configured to cover the edge of the third pad electrode PE3.

[0205] A transparent display device according to one or more embodiments of the present disclosure will be described below.

[0206] A transparent display device according to one or more embodiments of the present disclosure may include: a substrate including a non-transmissive region and a transmissive region, the non-transmissive region including a light-emitting region where light-emitting elements are provided; a plurality of data lines in the non-transmissive region on the substrate, the plurality of data lines extending in a first direction; at least one gate line on the substrate, the at least one gate line extending in a second direction intersecting the first direction through the non-transmissive region and the transmissive region; and at least one power supply line on the substrate, the at least one power supply line overlapping at least a part of the plurality of data lines with at least one insulating layer therebetween.

[0207] According to one or more embodiments of the present disclosure, at least one power supply line may be parallel to the plurality of data lines in the first direction.

[0208] According to one or more embodiments of the present disclosure, the width of at least one power supply line may be equal to or wider than the width of the plurality of data lines.

[0209] According to one or more embodiments of the present disclosure, the plurality of data lines may overlap with at least one power supply line.

[0210] According to one or more embodiments of the present disclosure, the plurality of data lines may be spaced apart from each other in the width direction of at least one power supply line.

[0211] According to one or more embodiments of the present disclosure, the spacing distance between multiple data lines may be equal to or greater than the width of each of the multiple data lines.

[0212] According to one or more embodiments of the present disclosure, multiple data lines may not overlap with the middle portion of at least one power line in the width direction.

[0213] According to one or more embodiments of the present disclosure, multiple data lines may be symmetric about the middle portion of at least one power line in the width direction.

[0214] According to one or more embodiments of the present disclosure, multiple data lines may be adjacent to one edge of at least one power line in the width direction.

[0215] According to one or more embodiments of the present disclosure, at least one power line may be spaced apart from multiple data lines by at least one insulating layer.

[0216] According to one or more embodiments of the present disclosure, the thickness of at least one power line may be equal to or not equal to the thickness of multiple data lines.

[0217] According to one or more embodiments of the present disclosure, the thickness of at least one insulating layer may be equal to or greater than the thickness of multiple data lines.

[0218] According to one or more embodiments of the present disclosure, the thickness of at least one insulating layer may be equal to or greater than several times the thickness of multiple data lines.

[0219] According to one or more embodiments of the present disclosure, at least one insulating layer may include at least one of an inorganic insulating material and an organic insulating material.

[0220] According to one or more embodiments of the present disclosure, at least one power line may have a grid pattern including a polygon, a circle, or a grid.

[0221] According to one or more embodiments of the present disclosure, at least one power line may be a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi), and indium tin oxide (ITO), or a multi-layer including at least two of Mo, Cu, MoTi, and ITO.

[0222] According to one or more embodiments of the present disclosure, a light-emitting element may include: a first divided electrode and a second divided electrode that are divided and spaced apart from each other; and a divided connection pattern that electrically connects the first divided electrode and the second divided electrode.

[0223] According to one or more embodiments of the present disclosure, at least one power line may be on the same layer as the divided connection pattern.

[0224] According to one or more embodiments of the present disclosure, at least a portion of at least one power supply line may include the same material as the partition connection pattern.

[0225] According to one or more embodiments of the present disclosure, the division connection patterns may be in a transmissive region on the substrate.

[0226] According to one or more embodiments of the present disclosure, the transparent display device may further include: a pad electrode in the pad area on the substrate, and at least a portion of the pad electrode may include the same material as the at least one power line.

[0227] According to one or more embodiments of the present disclosure, at least one power line may include a first power line and a second power line, the transparent display device may further include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel between the first power line and the second power line, and the plurality of data lines may include a first data line, a second data line, a third data line and a fourth data line respectively connected to the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel.

[0228] According to one or more embodiments of the present disclosure, the first and second data lines may overlap with the first power line, and the third and fourth data lines may overlap with the second power line.

[0229] According to one or more embodiments of the present disclosure, the first sub-pixel and the second sub-pixel may be adjacent to the first power line, and the third sub-pixel and the fourth sub-pixel may be adjacent to the second power line.

[0230] According to one or more embodiments of the present disclosure, at least one gate line may be disposed between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel.

[0231] According to one or more embodiments of the present disclosure, a transparent display device may include: a substrate, the substrate including a display area and a non-display area surrounding the display area, wherein the display area may include a plurality of light-emitting areas arranged along a first direction; a plurality of data lines in the plurality of light-emitting areas on the substrate, the plurality of data lines extending along the first direction; a plurality of gate lines on the substrate, the plurality of gate lines extending along a second direction intersecting the first direction; and a power line on the substrate, the power line overlapping at least a portion of the plurality of data lines via an insulating layer.

[0232] According to one or more embodiments of the present disclosure, the power line may be above the plurality of data lines.

[0233] According to one or more embodiments of the present disclosure, the width of the power line may be equal to or wider than the width of the plurality of data lines.

[0234] It will be apparent to those skilled in the art that various modifications and variations can be made to the apparatus of the present disclosure without departing from the scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure provided they are within the scope of the claims and their equivalents.

Claims

1. A transparent display device, comprising: A substrate, the substrate comprising a non-transmission area and a transmission area, the non-transmission area comprising a light-emitting area provided with a light-emitting element; a plurality of data lines, wherein the plurality of data lines extend along a first direction in the non-transmission region on the substrate; at least one gate line, on the substrate, the at least one gate line extending through the non-transmission area and the transmission area along a second direction intersecting the first direction; as well as At least one power line, on the substrate, the at least one power line overlaps with at least a portion of the plurality of data lines via at least one insulating layer.

2. The transparent display device according to claim 1, wherein: The at least one power line is parallel to the plurality of data lines in the first direction.

3. The transparent display device according to claim 1, wherein: The at least one power line has a width equal to or wider than that of the plurality of data lines.

4. The transparent display device according to claim 1, wherein: The plurality of data lines overlap the at least one power line.

5. The transparent display device according to claim 1, wherein: The plurality of data lines are spaced apart from each other in a width direction of the at least one power line.

6. The transparent display device according to claim 5, wherein: The spacing distance between the plurality of data lines is equal to or greater than a width of each of the plurality of data lines.

7. The transparent display device according to claim 1, wherein: The plurality of data lines do not overlap a middle portion of the at least one power line in a width direction.

8. The transparent display device according to claim 1, wherein: The plurality of data lines are symmetrical about a middle portion of the at least one power line in a width direction.

9. The transparent display device according to claim 1, wherein: The plurality of data lines are adjacent to one edge of the at least one power line in a width direction.

10. The transparent display device according to claim 1, wherein: The at least one power line is spaced apart from the plurality of data lines via at least one insulating layer.

11. The transparent display device according to claim 1, wherein: The thickness of the at least one power line is equal to or different from the thickness of the plurality of data lines.

12. The transparent display device according to claim 1, wherein: The at least one insulating layer has a thickness equal to or greater than a thickness of the plurality of data lines.

13. The transparent display device according to claim 12, wherein: The thickness of the at least one insulating layer is equal to or greater than several times the thickness of the plurality of data lines.

14. The transparent display device according to claim 1, wherein: The at least one insulating layer includes at least one of an inorganic insulating material and an organic insulating material.

15. The transparent display device according to claim 1, wherein: The at least one power line has a mesh pattern including a polygon, a circle, or a mesh.

16. The transparent display device according to claim 1, wherein: The at least one power supply line is a single layer including at least one of molybdenum (Mo), copper (Cu), molybdenum titanium (MoTi) and indium tin oxide (ITO) or a multilayer including at least two of Mo, Cu, MoTi and ITO.

17. The transparent display device according to claim 1, wherein: The light emitting element comprises: first split electrodes and second split electrodes, the first split electrodes and the second split electrodes being spaced apart from each other; and A split connection pattern is provided, wherein the split connection pattern electrically connects the first split electrode and the second split electrode.

18. The transparent display device according to claim 17, wherein: The at least one power supply line is on the same layer as the division connection pattern.

19. The transparent display device according to claim 17, wherein: At least a portion of the at least one power supply line includes the same material as the divided connection pattern.

20. The transparent display device according to claim 17, wherein: The division connection pattern is in the transmission region on the substrate.

21. The transparent display device according to claim 1, further comprising: a pad electrode, in the pad region on the substrate, Wherein, at least a portion of the pad electrode comprises the same material as that of the at least one power line.

22. The transparent display device according to claim 1, wherein: The at least one power line includes a first power line and a second power line, The transparent display device further includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel between the first power line and the second power line, and The plurality of data lines include a first data line, a second data line, a third data line and a fourth data line respectively connected to the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel.

23. The transparent display device according to claim 22, wherein: The first data line and the second data line overlap the first power line, and the third data line and the fourth data line overlap the second power line.

24. The transparent display device according to claim 22, wherein: The first sub-pixel and the second sub-pixel are adjacent to the first power line, and the third sub-pixel and the fourth sub-pixel are adjacent to the second power line.

25. The transparent display device according to claim 22, wherein: The at least one gate line is between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel.

26. A transparent display device, comprising: A substrate, the substrate comprising a display area and a non-display area surrounding the display area, wherein the display area comprises a plurality of light emitting areas arranged along a first direction; a plurality of data lines, wherein the plurality of light emitting regions on the substrate extend along the first direction; a plurality of gate lines extending on the substrate along a second direction intersecting the first direction; and A power line is provided on the substrate, and the power line overlaps at least a portion of the plurality of data lines via an insulating layer.

27. The transparent display device according to claim 26, wherein: The power line is above the plurality of data lines.

28. The transparent display device according to claim 26, wherein: The width of the power line is equal to or wider than the width of the plurality of data lines.

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