Totem pole power factor correction system

Abstract

A mechanism for facilitating quasi square wave control of a totem-pole power factor correction system that utilizes rectifier diodes in a rectification system and includes a synchronous boost PFC converter. The mechanism includes a boost input decoupler formed of a pair of clamping diodes and a decoupling capacitor that decouples an input of a synchronous boost PFC converter from an input interface that receives an AC input signal for conversion.

Description

Technical Field

[0001] The present invention relates to the field of power factor correction systems. Background Art

[0002] Power factor correction (PFC) systems are increasingly used in a wide variety of electrical articles in order to improve the efficiency of such electrical devices. In fact, power factor correction systems are generally regarded as necessary or indispensable for many electrical devices in order to achieve the power factor required by the (one or more) electrical devices. An example of a power factor correction system is a totem pole power factor correction system, which is sometimes referred to as an asymmetric bridgeless boost rectifier.

[0003] There is an increasing interest in different control schemes for power factor correction systems, and recently, new operating modes have been introduced. These modes include: continuous conduction mode (CCM), discontinuous conduction mode (DCM), boundary / transition conduction mode (BCM), and quasi-square wave (QSW) mode.

[0004] There is a continuing desire to improve the performance and reliability of PFC systems (and particularly totem pole PFC systems). Summary of the Invention

[0005] The present invention is defined by the claims.

[0006] According to an example of one aspect of the present invention, there is provided a totem pole power factor correction system for driving a load.

[0007] The totem pole power factor correction circuit includes: an input interface including a first input node and a second input node for receiving an AC input signal from an external power source, and an impedance connecting the first input node to the second input node; an output interface for providing a drive signal to the load, the output interface including: a first output node and a second output node for connecting to the load; and an output capacitor connected between the first output node and the second output node; a synchronous boost PFC converter including: an inductor coupled between the first input node and an intermediate node; a first switch connected between the intermediate node and the first output node; and a second switch connected between the intermediate node and the second output node; a rectification system including: a first rectifier diode connected between the second input node and the first output node; and a second rectifier diode connected between the second output node and the second input node; and a boost input decoupler.

[0008] The boost input decoupler includes: a first clamping diode connected between a first input node and a first output node; a second clamping diode connected between a second output node and the first input node; and one or more decoupling capacitors, where each decoupling capacitor is: connected between the first input node and the first output node; or connected between the first input node and the second output node.

[0009] The present disclosure proposes a mechanism that is used to decouple the input (i.e., the first input node) of a synchronous boost PFC converter from a rectifier and an input interface, which not only facilitates QSW control technology but also uses rectifier diodes for a rectification system (of a totem-pole-based system).

[0010] This modification means that the voltage at the input of the synchronous boost PFC converter is decoupled from the AC input signal itself.

[0011] One or more decoupling capacitors may include: a first decoupling capacitor connected between the first input node and the first output node; and a second decoupling capacitor connected between the first input node and the second output node.

[0012] The input interface includes an EMI filter for performing EMI filtering on the AC input signal received by the input interface. Using the EMI filter will reduce the electromagnetic interference in the AC input signal.

[0013] The proposed concept is particularly advantageous when the PFC system includes such an EMI filter.

[0014] Operating a power factor correction system typically results in a large voltage step at the first input node for each zero-crossing of the AC input signal. The magnitude of this voltage step may cause significant problems, such as significant problems regarding component wear.

[0015] Furthermore, if operating in QSW mode (and in the absence of the proposed boost input decoupler herein), a reverse current is induced in the corresponding forward-biased rectifying component (e.g., the corresponding rectifier diode) for each switching cycle of the synchronous boost PFC converter. If one or more rectifier diodes are used, this may result in a voltage step of several volts at the first input node. This will generate continuous high-frequency excitation of the input interface.

[0016] Traditional totem-pole designs overcome these problems by using MOSFETs (instead of diodes) to perform the rectification by the rectification system. These MOSFETs remain conducting throughout the corresponding mains half-cycle.

[0017] In the proposed solution, the proposed boost input decoupler is used to handle large voltage steps. The decoupler also greatly attenuates secondary (HF, LV) effects.

[0018] However, if the voltage at the first input node is controlled, these input capacitors do not appear as PFC input capacitors, although this effectively reduces the burden on the EMI filter. In this way, the capacitance of the filter capacitor can be much smaller.

[0019] In a preferred example, the synchronous boost PFC converter includes a control system for controlling the operation of the switches using a quasi-square wave control technique. Compared with other existing technologies, the quasi-square wave technique facilitates or allows a higher switching frequency for the first switch and the second switch. The proposed system allows QSW mode operation.

[0020] In some examples, the synchronous boost PFC converter includes a transition control system for controlling the operation of the first switch and the second switch during the positive-to-negative zero crossing of the voltage provided by the AC input signal.

[0021] The transition control system can be configured to control the voltage at the first input node to reach a high voltage level by controlling the operation of the first switch and the second switch during the positive-to-negative zero crossing of the voltage provided by the AC input signal.

[0022] This method prevents the voltage at the input of the synchronous boost PFC converter from being uncontrolled. Conceptually, during the conventional control of the synchronous boost converter, at this position, two large voltage steps will occur in each cycle of the AC input signal. Each of these large voltage steps will have a voltage as large as the voltage at the first output node. This may lead to unexpected errors or operations in the PFC system. Specifically, this may lead to excessive or destructive currents in the boost converter, as well as the excitation of excessive ringing in the rectification system and the EMI filter (when present).

[0023] By controlling the voltage at this node during the transition to reach the voltage at the first output in two or more steps, larger voltage steps can thus be avoided. This reduces the current flowing through the inductor of the synchronous boost PFC converter, thereby improving the robustness and stability of the inductor.

[0024] The transition control system can be configured to control the voltage at the first input node to reach a high voltage level before the power provided by the AC input signal to the second input node can forward bias the first rectifying diode during the positive-to-negative zero crossing of the voltage provided by the AC input signal.

[0025] The transition control system can be configured to control the voltage at the first input node to reach a high voltage level by resonantly charging the first input node via the inductor of the synchronous boost converter during the positive-to-negative zero crossing of the voltage provided by the AC input signal.

[0026] The transition control system can be configured to control the voltage at the first input node to reach a high voltage level during the positive-to-negative zero crossing of the voltage provided by the AC input signal, wherein the control is configured to keep the magnitude of the current through the inductor of the synchronous boost converter below a threshold current.

[0027] The transition control system can be configured to control the voltage at the first input node to reach a high voltage level in two or more voltage steps by controlling the operations of the first switch and the second switch during the positive-to-negative zero crossing of the voltage provided by the AC input signal.

[0028] In some examples, the transition control system is configured to, during the positive-to-negative zero crossing of the voltage provided by the AC input signal: enter a first control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained; after the first control phase, enter a second control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node reaches a high voltage level; and after the voltage at the first input node reaches the high voltage level, enter a third control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained at the high voltage level.

[0029] In some examples, the transition control system is further configured to control the operations of the first switch and the second switch during the negative-to-positive zero crossing of the voltage provided by the AC input signal.

[0030] The transition control system can be configured to control the voltage at the first input node to reach a low voltage level by controlling the operations of the first switch and the second switch during the negative-to-positive zero crossing of the voltage provided by the AC input signal.

[0031] In some examples, the transistor control system is configured to, during the negative-to-positive zero crossing of the voltage provided by the AC input signal: enter the third control phase; after the third control phase, enter the second control phase; and after the second control phase, enter the first control phase.

[0032] The transistor control system can be configured to, during the negative-to-positive zero-crossing of the voltage provided by the AC input signal: enter a fourth control phase, during which the commutation control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained; after the fourth control phase, enter a fifth control phase, during which the commutation control system controls the operations of the first switch and the second switch such that the voltage at the first input node reaches a low voltage level; and after the voltage at the first input node reaches the low voltage level, enter a sixth control phase, during which the commutation control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained at the low voltage level.

[0033] In some examples, the commutation control system is configured to: during the negative-to-positive zero-crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the low voltage level in two or more steps by controlling the operations of the first switch and the second switch.

[0034] Optionally, the commutation control system is configured to control the operations of the first switch and the second switch in response to the amplitude of the voltage provided by the AC input signal dropping below a first predetermined threshold. This can be used to prevent the voltage at the input of the synchronous boost PFC converter from dropping to the minimum operable voltage for performing the boost function, thereby improving the reliability of the system.

[0035] The commutation control system can be configured to relinquish control of the operations of the first switch and the second switch in response to the amplitude of the voltage provided by the AC input signal rising above a first predetermined threshold.

[0036] In some examples, the commutation control system is configured to: during the positive-to-negative zero-crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the voltage at the first output node in three or more steps by controlling the operations of the first switch and the second switch.

[0037] In some examples, during the first control phase, the commutation control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained at a predetermined voltage level.

[0038] Preferably, the capacitance of the output capacitor is more than 100 times the capacitance of the first decoupling capacitor and / or the second decoupling capacitor.

[0039] In some examples, the first switch and / or the second switch of the synchronous boost PFC converter includes a MOSFET. By way of example, the MOSFET can be a silicon MOSFET, or more preferably a SiC MOSFET. In some other examples, the first switch and / or the second switch of the synchronous boost PFC converter is a FET, such as a GaN HEMT.

[0040] An electronic device apparatus is also proposed, which includes: an electronic device configured to draw less than 10 kW; and any totem-pole power factor correction system proposed herein.

[0041] These and other aspects of the invention will be apparent from and will be elucidated with reference to the (one or more) embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] For a better understanding of the present invention, and in order to more clearly show how the present invention may be put into practice, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0043] Figure 1 An existing totem-pole power factor correction circuit is shown;

[0044] Figure 2 The proposed totem-pole power factor correction circuit is shown;

[0045] Figure 3 Waveforms at various nodes within the proposed or existing totem-pole power factor correction circuit are shown;

[0046] Figure 4 Waveforms during the zero-crossing of the AC input signal for the proposed control scheme are shown;

[0047] Figure 5 A state plane diagram of the inductor of the synchronous boost PFC converter used in the proposed totem-pole power factor correction circuit is provided; and

[0048] Figure 6 Currents into the inductor and the output capacitor during the transition are shown. DETAILED DESCRIPTION

[0049] The present invention will be described with reference to the accompanying drawings.

[0050] It should be understood that the detailed description and specific examples, although indicating exemplary embodiments of the apparatus, system, and method, are only for illustrative purposes and are not intended to limit the scope of the present invention. These and other features, aspects, and advantages of the apparatus, system, and method of the present invention will become better understood from the following description, the appended claims, and the drawings. It should be understood that the drawings are only schematic and not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to indicate the same or similar parts.

[0051] The present invention provides a totem-pole power factor correction system that utilizes rectifier diodes in a rectification system and includes a synchronous boost PFC converter. The mechanism includes a boost input decoupler formed by a pair of clamping diodes and a decoupling capacitor that decouples the input of the synchronous boost PFC converter from an input interface that receives an AC input signal for conversion.

[0052] Figure 1 An existing totem-pole power factor correction system 100 is shown to assist in providing background to the present invention.

[0053] System 100 includes an input interface 110 that includes a first input node 111 and a second input node 112 for receiving an AC input signal S from an external power supply 190. The input interface 110 includes an impedance connecting the first input node and the second input node, here being: a filter capacitor Cf. AC The input interface may include an EMI filter for performing EMI filtering (i.e., electromagnetic interference filtering) on the AC input signal received by the input interface. The purpose of the EMI filter is to suppress or attenuate any interference generated by the power factor correction system 100 to remain below a permitted level to which the external power supply may be exposed. The EMI filter includes a filter capacitor Cf connected between the first input node 111 and the second input node 112 and a filter inductor Lf connected between the first input node 111 and a third input node 113. The input interface 110 is configured such that the AC input signal S is received between the second input node 112 and the third input node 113.

[0054] Of course, the EMI filter may include additional filtering components, such as those well-established in the art. The illustrated EMI filter describes the minimum components generally considered necessary to effectively perform EMI filtering of differential-mode noise. AC .

[0055] Certainly, the EMI filter may contain additional filtering components, such as those well-established in the art. The illustrated EMI filter describes the minimum components generally considered necessary to effectively perform EMI filtering of differential-mode noise.

[0056] System 100 also includes an output interface 120 for providing a drive signal V(Co) to a load (not shown). The output interface 120 includes a first output node 121 and a second output node 122 for connection to the load. The output interface 120 also includes an output capacitor Co connected between the first output node 121 and the second output node 122.

[0057] The voltage V(Co) between the first output node 121 and the second output node 122 is the bus voltage Vb. The second output node 122 is connected to ground GND or a reference voltage and is thus at ground voltage GND.

[0058] System 100 also includes a synchronous boost PFC converter 130 that includes an inductor L coupled between a first input node 111 and an intermediate node 135. The synchronous boost PFC converter 130 also includes: a first switch S1 connected between the intermediate node 135 and the first output node 121; and a second switch S2 connected between the intermediate node 135 and the second output node 122.

[0059] An alternative label for the first input node 111 is the boost input node 111. An alternative label for the second input node 112 is the rectifier node 112. An alternative label for the first output node 121 is the bus node 121. An alternative label for the second output node 122 is the ground node 122. An alternative label for the intermediate node 135 is the switch node 135 or the boost converter switch node 135.

[0060] The voltage Vz at the first input node 111 can be labeled as the boost input voltage Vz. The voltage Vy at the second input node 112 can be labeled as the rectifier node voltage Vy. The voltage Vb at the first output node 121 can be labeled as the bus voltage Vb. The voltage at the second output node 122 can be labeled as the ground voltage GND. The voltage Vx at the intermediate node 135 can be labeled as the intermediate voltage Vx or the switch voltage Vx.

[0061] Throughout this specification, these labels will be used interchangeably.

[0062] The system also includes a rectification system 140 that includes: a first rectification switch SLF1 connected between the second input node 112 and the first output node 121; and a second rectification switch SLF2 connected between the second output node 122 and the second input node 112. Each rectification switch can be, for example, a MOSFET.

[0063] The totem pole device for the rectification system 140 can reduce the losses in the rectification system. Compared with more traditional rectification systems that utilize full-bridge diode rectifiers, in order to ensure low-loss operation, the AC input signal current S AC should be controlled to flow through only a single rectification switch at a time. This can be achieved by appropriate control of the switches. For example, the switches SLF1, SLF2 are operated to operate / switch at the frequency of the AC input signal S AC .

[0064] Due to this relatively low-frequency operation process, the relatively large output capacitance of the rectification switch has previously been considered unimportant. It is also relatively common to label the rectification switch as a "low-frequency switch".

[0065] The synchronous boost PFC converter 130 can be controlled in at least four operating modes, which are well known to those skilled in the art. These modes include: continuous conduction mode (CCM), discontinuous conduction mode (DCM), boundary / transition conduction mode (BCM), and quasi-square wave (QSW) mode. The quasi-square wave mode is sometimes labeled as the triangular current mode.

[0066] Specifically, the control system 132 of the synchronous boost PFC converter 130 can be configured to control the switching of the first switch S1 and the second switch S2 according to one of these modes. The selection of the mode can depend on design requirements or user preferences.

[0067] Generally, the control system 132 is configured such that only one of the first switch S1 and the second switch S2 conducts at the same time, resulting in synchronous control. More specifically, the control system can be configured such that current can always flow between the intermediate node 135 and the first output node 121 or the second output node 122.

[0068] Methods for controlling the synchronous boost PFC converter 130 according to CCM are well established. Example methods are disclosed by Zhou, Bo in "CCM totem pole bridgeless PFC with ultra fast IGBT" (Diss. Virginia Tech, 2014) and by Huang, Qingyun and Alex Q. Huang in "Review of GaN totem-pole bridgeless PFC" (CPS S Transactions on Power Electronics and Applications 2.3 (2017): 187-196). Another method is disclosed by Mai, Leonardo S. et al. in "Totem-Pole Bridgeless PFC Converter in DCM with Synchronous Rectification" (2019 IEEE 15th Brazilian Power Electronics Conference and 5th IEEE Southern Power Electronics Conference (COBEP / SPEC). IEEE, 2019).

[0069] Methods for controlling the synchronous boost PFC converter 130 according to DCM are also well established. Example methods are disclosed by Mai, Leonardo S. et al. in "Totem-Pole Bridgeless PFC Converter in DCM with Synchronous Rectification" (2019 IEEE 15th Brazilian Power Electronics Conference and 5th IEEE Southern Power Electronics Conference (COBEP / SPEC). IEEE, 2019).

[0070] A method for controlling a synchronous boost PFC converter 130 according to boundary conduction mode has been established. For example, a method is disclosed by Huber, Laszlo, Brian T. Irving, and Milan M. Jovanovic in "Open-loop control methods for interleaved DCM / CCM boundary boost PFC converters" (IEEE Transactions on Power Electronics 23.4 (2008): 1649-1657). Another method is disclosed by Choi, Hangseok, and Laszlo Balogh in "A cross-coupled master–slave interleaving method for boundary conduction mode (BCM) PFC converters" (IEEE Transactions on Power Electronics 27.10 (2012): 4202-4211). Yet another method is proposed by Su, Bin, Junming Zhang, and Zhengyu Lu in "Totem-pole boost bridgeless PFC rectifier with simple zero-current detection and full-range ZVS operating at the boundary of DCM / CCM" (IEEE Transactions on Power Electronics 26.2 (2010): 427-435).

[0071] Methods for controlling a synchronous boost PFC converter 130 according to a quasi-square-wave mode have been established in the prior art, as disclosed by Vorpérian, Vatché in "Quasi-square-wave converters: topologies and analysis" (IEEE Transactions on Power Electronics 3.2 (1988): 183-191) and C. Margit, J. Biela, and J. W. Kolar in "Interleaved triangular current mode (TCM) resonant transition, single phase PFC rectifier with high efficiency and high power density" (Proc. Int. Power Electronics Conf., ECCE ASIA, Jun. 2010, pp. 1725–1732).

[0072] One problem with CCM, DCM, and BCM is that they all exhibit hard switching over at least a portion of the operating range. In contrast, the QSW mode facilitates or provides zero-voltage switching (ZVS) over the entire load and input voltage range, thus allowing the highest switching frequencies without damaging the first and second switches and / or affecting efficiency.

[0073] Operating in the quasi-square-wave mode results in greater values of current at the first input node 111 and the intermediate node 135, such as greater root mean square values. This means that even smaller output capacitances for switches S1 and S2 are required for higher efficiency of converter 130. This requires the use of more advanced switches, e.g., switches formed from more advanced and expensive materials such as SiC or GaN instead of standard silicon (Si).

[0074] Regardless of the operating mode of the synchronous boost PFC converter 130, the rectifying switches SLF1, SLF2 typically operate as synchronous rectifiers in the third quadrant of their output characteristics. Nevertheless, even if the rectifying switches remain permanently in the OFF mode, their body diodes will still be able to provide the necessary rectifier function. Thus, conceptually, each rectifying switch can be replaced with a rectifying diode. This would be advantageous because rectifying switches are much more expensive in terms of material than rectifying diodes and require additional gate drive and control circuitry.

[0075] However, in the current system, successful replacement of the two rectifying switches with rectifying diodes can be achieved (at a lower / acceptable noise level) only for CCM or DCM.

[0076] Specifically, if the synchronous boost PFC converter 130 operates in the QSW mode, the instantaneous current at the second input node 112 will become negative, and one of the rectifier diodes can be reverse-biased. Specifically, the rectifier diode replacing SLF1 can be reverse-biased during the negative half-cycle of the AC input signal S AC and the rectifier diode replacing SLF2 can be reverse-biased during the negative half-cycle of the AC input signal S AC This effect is particularly evident when the average AC input signal current is low. This reverse-biasing effect can result in both common-mode noise and differential-mode noise.

[0077] Currently, if QSW mode operation is desired, the way to address this reverse-biasing effect or problem is to retain the use of the rectifier switches SLF1, SLF2 to form the rectifying device 140 (i.e., instead of using rectifier diodes). Here, the relevant rectifier switches are kept conducting throughout the corresponding mains half-cycle, thereby maintaining the voltage at the second input node at the ground voltage GND or the bus voltage Vb.

[0078] Some of the disadvantages of using rectifier switches have been described previously and include higher material costs as well as the need for additional gate drive and control devices / circuits. Additionally, if relatively large devices are employed, the conduction losses of such switches can only be kept lower than those of diodes. Large devices are accompanied by large output capacitors, and the switching of the rectifier switches at the mains voltage zero-crossing can cause ringing at the first input node 111 and the second input node 112. Moreover, all / any ripple current of the AC input signal must pass through the EMI filter, which can result in an oversized filter component and lead to not equal to one, especially in the case of high impedance or light load.

[0079] The present disclosure provides techniques for overcoming these problems, allowing rectifier diodes to replace the rectifier switches SLF1, SFL2 while still allowing the synchronous boost PFC converter to operate in the QSW mode to achieve a high switching frequency. The proposed method also permits a significant reduction in the size of the EMI filter.

[0080] Figure 2 A totem-pole power factor correction system 200 according to the proposed method is shown. For the sake of brevity, only those elements that are different from the previously described system 100 are described and indicated.

[0081] For this method, the switches S1 and S2 can be embodied as MOSFETs, but other suitable types of switches will be apparent to those skilled in the art.

[0082] The rectifying switch (of the previously described system 100) has been replaced by rectifying diodes D1, D2.

[0083] System 200 also includes a boost input decoupler 250, which includes: a first clamping diode Dz1 connected between a first input node 111 and a first output node 121; and a second clamping diode Dz2 connected between a second output node 122 and the first input node 121.

[0084] The boost input decoupler 250 also includes: a first decoupling capacitor Cz1 connected between the first input node 111 and the first output node 121; and a second decoupling capacitor Cz2 connected between the first input node 111 and the second output node 122. In some variations of this embodiment, one of these decoupling capacitors may be omitted.

[0085] Thus, if present, the first clamping diode Dz1 and the first decoupling capacitor Cz1 are connected in parallel with each other, just as the second clamping diode Dz2 and the second decoupling capacitor Cz2 are connected in parallel with each other.

[0086] The proposed method thus decouples the boost input Vz from the rectifying system 140 and the EMI filter Cf, Lf. This prevents the rectifying diodes D1, D2 from becoming reverse-biased.

[0087] Specifically, the boost input decoupler provides an additional or alternative current path for any high-frequency current ripple. Thus, this ripple current no longer needs to flow through the rectifying diode(s) D1, D2, which means they can remain forward-biased.

[0088] More specifically, in order to reduce the effect of the current flowing into the rectifier node 112, one or more decoupling capacitors are provided such that the current will flow to the capacitor(s) rather than the rectifier node 122. This can be achieved by defining the capacitance of each decoupling capacitor to be much larger than the junction capacitance of the rectifying diode (e.g., more than 100 times the junction capacitance of the rectifying diode).

[0089] It is also recognized that it would be preferable if the boost input voltage Vz (and thus, the rectifier node voltage Vy) were not controlled. Sudden or abrupt voltage changes can be significant at the first input node 111 and / or the second input node 112, especially at the transition or zero-crossing of the AC input signal. At these transitions, the amplitude of the voltage step can reach the amplitude of the bus voltage Vb. Thus, if the boost input voltage Vz is not controlled, then at the AC input signal S ACIn each cycle of the , a voltage step that is not less than twice the bus voltage may exist at the first input node 111. This will result in large currents and ringing throughout the input interface. For the proposed technology, due to the additional capacitance of one or more decoupling capacitors Cz1, Cz2 of the boost input decoupler 250, this may lead to significant losses.

[0090] These voltage steps are generated by the control of the converter 130 according to known or existing control schemes.

[0091] More specifically, when the AC input signal experiences a zero crossing, it is inevitable that there will be a voltage step (or vice versa) between the bus voltage Vb and the ground / reference voltage GND at the rectifier node 112. This is the case regardless of whether system 100 or 200 is used. This is because the periodically reversed AC input signal will change which rectifying device (e.g., rectifying switch or rectifying diode) is forward biased at the zero crossing. Therefore, the voltage Vy at the rectifier node 112 will inevitably switch between the bus voltage Vb and the ground / reference voltage GND.

[0092] The effect of this voltage step at the rectifier node 112 is ringing of the input interface. If one or more decoupling capacitors Cz1, Cz2 are coupled to the first input node 111 / when one or more decoupling capacitors Cz1, Cz2 are coupled to the first input node 111, the resulting ringing becomes more severe. This is because in the traditional case, the voltage at the first input node 111 will follow the voltage step at the rectifier input node 112. This means that there will be extremely high currents (and thus high voltages across it) through the filter capacitor Cf (or other impedance connecting the first input node 111 to the second input node 112).

[0093] It has been identified that the boost input voltage Vz can be controlled such that there is no significant voltage difference across the EMI filter capacitor Cf after the zero crossing of the mains AC signal. This will reduce / attenuate any noise / ringing at the zero crossing of the AC mains signal in the input interface.

[0094] It has also been identified that if the boost input voltage Vz is appropriately controlled to avoid or reduce these large voltage steps, the decoupling capacitors do not actually provide input capacitance to the synchronous boost PFC converter 130, thus avoiding or mitigating any losses through the additional capacitance.

[0095] In addition, the additional capacitance provided by the decoupling capacitors can be considered to reduce the size of the EMI filter capacitor Cf. In other words, this additional capacitance can be used to at least partially perform the function of the EMI filter capacitor in the EMI filter. This means that the size of the EMI filter can be significantly reduced.

[0096] To improve context understanding, Figure 3 an idealized waveform of system 100 or 200 is shown, plotting the AC input signal S provided to the first input node 111 AC for voltage V AC , the first input node voltage Vz and the second input node voltage Vz (switching at twice the mains frequency), and the bus voltage Vb.

[0097] Figure 3 An individual cycle of the AC input signal S AC is shown, having a period of Tm such that the voltage of the AC input signal S AC crosses zero every Tm / 2.

[0098] Specifically, Figure 3 a normal or conventional control scheme for system 100 or system 200 is shown. This more clearly demonstrates the significant voltage steps (on the voltage Vz at the first input node and the voltage Vy at the second input node) occurring at the zero crossing or transition of the AC input signal S AC .

[0099] During conventional operation (specifically, between the zero crossings of the AC input signal S AC ), a synchronous boost PFC converter is used to control the (average) bus voltage Vb and the current of the AC input signal. This can be performed, for example, using a cascaded feedback control loop.

[0100] Specifically, the control system 132 can perform control of switches S1 and S2 to control the bus voltage Vb and the current of the AC input signal S AC . This control can be performed to be proportional to the AC input voltage and, preferably, results in a power factor equal to one. Preferably, this is performed using the QSW control mode previously described.

[0101] Although these control aspects are related to the overall PFC performance in terms of the achievable power factor, since they are well established in the field of power factor control, these control aspects will not be elaborated further. Generally, control of the boost input voltage Vz can be achieved by measuring the boost input voltage Vz and maintaining the boost input voltage at a desired voltage. Feedback for the control of the current of the AC input signal can be performed by monitoring the boost current I L (i.e., the current of the signal at the first input node 111). Alternatively, the current of the AC input signal can be directly measured, for example, in rectifier diodes D1 and D2, using a shunt referenced to ground or the bus voltage.

[0102] The present disclosure also presents a transition control system 134 for controlling the operation of a first switch and a second switch during the zero crossing or transition of the voltage provided by an AC input signal. Thus, the transition control system 134 controls the operation of the first switch and the second switch during the transition between a positive voltage and a negative voltage and during the transition between a negative voltage and a positive voltage.

[0103] The transition control system 134 may, for example, form part of an overall control system 132 of a synchronous boost PFC converter 130. However, in other examples, the transition control system 134 is formed as a separate entity.

[0104] The proposed transition control system 134 may be configured to attenuate, mitigate, or reduce the occurrence of large voltage differences or voltage drops across the EMF filter capacitor Cf or other impedances coupling the first input node and the second input node. This is achieved by controlling the voltage Vz at the boost input node 111 at the transition of the AC input signal S AC from a positive to a negative voltage or from a negative to a positive voltage.

[0105] Specifically, at the transition of the AC input signal S AC the transition control system 134 may be configured to commutate the boost input voltage Vz at the boost input node 111 by controlling the first switch S1 and the second switch S2. The voltage Vy at the rectifier node 112 will follow the boost input voltage Vz via the impedance Cf (since the boost input voltage effectively acts as a power source). In other words, the transition control system 134 controls the boost input voltage Vz as the leading voltage, while the rectifier node voltage Vy is the lagging voltage (with respect to the boost input voltage).

[0106] By commuting the voltage Vz at the boost input node 111 and the voltage Vy at the rectifier node, large voltage differences across the EMF filter capacitor previously caused by the transition of the mains current are avoided. This significantly reduces noise and ringing in the input interface.

[0107] Using the first switch S1 and the second switch S2 to control the voltage at the boost input node 111 (and thus the voltage at the rectifier node 112) will control these voltages to have a less steep slope / gradient than that provided when left uncontrolled (e.g., when made to respond only to the AC input signal).

[0108] This control scheme processes and controls the transition of the voltage at the boost input node 111 to avoid / reduce both losses and ringing.

[0109] This control scheme also facilitates low-voltage switching at the second input node 112, thereby further reducing noise and / or ringing.

[0110] More specifically, the sources of both differential-mode interference and common-mode interference are attenuated. Differential-mode interference is reduced by keeping the current across the transimpedance Cf relatively low (i.e., by avoiding a sudden voltage drop across the transimpedance Cf). Common-mode interference is reduced by reducing the steepness of the voltage transitions at the boost input node 111 and the rectifier node 112.

[0111] This means that the size and / or (one or more) component values of the EMI filter can be reduced compared to the size and / or (one or more) component values of previously available EMI filters.

[0112] The transition control system 134 is configured to control the operation of the first switch S1 and the second switch S2 in response to the amplitude of the voltage provided by the AC input signal S AC dropping below a first predetermined threshold. This will indicate an upcoming transition between the positive and negative voltages (or vice versa) of the AC input signal S AC .

[0113] Similarly, the transition control system can be configured to relinquish control of the operation of the first switch and the second switch in response to the amplitude of the voltage provided by the AC input signal rising above the first predetermined threshold.

[0114] It will be apparent that the transition control system can effectively "override" the normal operation of the synchronous boost PFC converter 130 during the transition period. Thus, the control system 132 can include a normal control system (not shown) that is used to control the operation of the switches S1, S2 between transitions or during periods between which the transition control system 134 performs control of the operation of the first switch and the second switch.

[0115] The transition control system is configured to control the voltage at the first input node to reach a high voltage level during (e.g., any / all) positive-to-negative zero crossings of the voltage provided by the AC input signal to the first input node, by controlling the operation of the first switch and the second switch.

[0116] This method thus uses the first switch and the second switch to increase the voltage Vz at the first input node 111. This is achieved by controllably connecting the intermediate node 135 to the first output node 121. The voltage at the intermediate node 135 in turn charges the first input node 111. Thus, the transition control system is configured to charge the voltage Vz at the first input node 111 using the voltage V(Co) across the output capacitor Co via the first and / or second switch.

[0117] The rectifier node voltage Vy will follow the boost input voltage Vz. By controlling the boost input voltage Vz to a high voltage level, this will similarly control the rectifier node voltage Vy to that high voltage level.

[0118] The high voltage level may be the bus voltage Vb or a biased version thereof, such as Vb-Vbi (where Vbi is the bias voltage). The bias voltage may be the minimum boost input voltage Vz min , which represents the minimum input of the boost PFC converter 130 for achieving zero voltage switching control of the boost PFC converter.

[0119] Minimum boost input voltage Vz min is defined by the minimum duty cycle and can be estimated by the following equation:

[0120]

[0121] Qoss is the output charge of switches S1 and S2, L is the boost inductor, and fs min is the minimum operating frequency of switches S1, S2. The minimum operating frequency is a design choice and may be adapted to, for example, the control loop of the boost input voltage. Equation (1) assumes that the synchronous boost PFC converter 130 is to operate at the minimum root mean square (rms) current required to ensure zero voltage switching (ZVS) of the intermediate node 135.

[0122] By way of example only, at an average bus voltage Vb0 of 700 V, Vz min is about 16V, where fs min =150kHz, Qoss=50nC, L=40μH, V b = 700 V. For practical reasons, the threshold value chosen is 20 V.

[0123] It will be appreciated that by further reducing fs min To reduce the minimum boost input voltage Vz min For example, fs min This is usually considered to be about 10% of the maximum rated frequency.

[0124] Preferably, the transition control system is configured to: during (e.g., any) positive to negative zero crossing of the voltage provided by the AC input signal to the first input node, control the voltage Vz at the first input node 111 to reach a high voltage level before the power provided by the AC input signal to the second input node is able to forward bias the first rectifier diode.

[0125] Since the rectifier node voltage Vy follows the boost input voltage Vz, the rectifier node voltage Vy is thus similarly controlled to reach a high voltage level before the power provided by the AC input signal to the second input node can forward bias the first rectifier diode.

[0126] This facilitates zero-voltage or low-voltage switching of the second input node 112 (rectifier node 112), i.e., zero-voltage or low-voltage switching when the AC input signal changes to forward bias the first rectifier diode (placing the rectifier node voltage Vy at the bus voltage Vb or close to the bus voltage Vb). This method significantly reduces noise and / or ringing in the input interface.

[0127] The transition control system 134 is preferably configured to control the voltage at the first input node 111 to reach a high voltage level during (e.g., any) positive-to-negative zero-crossing of the voltage provided by the AC input signal to the first input node by resonantly charging the first input node via the inductor of the synchronous boost converter.

[0128] This method effectively "soft-charges" the voltage at the input node such that it gradually increases over time rather than suddenly stepping to a high voltage level. This reduces noise in the entire power factor correction system. In other words, this method effectively avoids a rapid voltage step in / at the first input node and instead configures the voltage change at the first input node as a resonant transition that has well-defined component values and thus a well-defined steepness / rate of change of the voltage Vz at the first input node 111.

[0129] The transition control system 134 can be configured to control the voltage at the first input node to reach a high voltage level during the positive-to-negative zero-crossing of the voltage provided by the AC input signal to the first input node, wherein the control is configured such that the current I through the inductor L of the synchronous boost converter 130 L has an amplitude that remains below a threshold current I TH .

[0130] The threshold current I TH is preferably below the saturation current I of the inductor L SAT . The threshold current I TH can represent the maximum permitted current through the inductor L to avoid noise or ringing at the first input node 111.

[0131] The maximum possible current I in the inductor L-PK can be defined by the following equation:

[0132]

[0133] Where (for the purposes of Equation 2), Cz is the total capacitance of one or more decoupling capacitors, and L is the inductance of inductor L. Thus, if the one or more decoupling capacitors include a first decoupling capacitor Cz1 and a second decoupling capacitor Cz2, then Cz = Cz1 + Cz2 - where Cz1 represents the capacitance of decoupling capacitor Cz1, and Cz2 represents the capacitance of decoupling capacitor Cz2. BF is a bias factor, such as sqrt(3 / 4) - which is valid for linear capacitors, and other component types will affect the bias factor accordingly.

[0134] The threshold current can be set to be equal to a value that is less than or equal to the maximum possible current I L-PK , such as being the maximum possible current I L-PK of a predetermined fraction.

[0135] The method aims to perform a lossless or near-lossless voltage transition of the first input node 111, and to maintain / reserve the ZVS of the synchronous boost PFC converter 130.

[0136] To maintain the current I L below the threshold current I TH , the control of the first switch and the second switch can utilize a modulated control of the voltage Vx at the intermediate node 135. Specifically, the voltage at the intermediate node 135 can be controlled to perform one or more switching cycles, so as to move the boost input voltage Vz to a high voltage level.

[0137] In addition to using the maximum possible current I in the inductor L-PK , the maximum rate of change dVz / dt of the voltage at the boost input node can also be defined, which also results in a minimum number of switching cycles. Then the corresponding maximum number of cycles can be selected.

[0138] The switching cycle includes a connection phase and a disconnection phase. The connection phase includes connecting the intermediate node 135 to the first output node 121 (and disconnecting the intermediate node from the second output node 122), thereby charging / increasing the boost input voltage and increasing the magnitude of the current I L through the inductor. The disconnection phase includes connecting the intermediate node 135 to the second output node 122 (and disconnecting the intermediate node from the first output node) to dissipate the current through inductor L.

[0139] The connection phase can be maintained until the magnitude of the inductor current I L reaches or is predicted to reach the threshold current. The disconnection phase can be maintained until the magnitude of the inductor current I L reaches or is predicted to reach 0 or the minimum current for zero voltage switching of the boost converter.

[0140] The number of switching cycles required to commutate the voltage at the boost input node can depend on the characteristics of the one or more decoupling capacitors Cz1, Cz2 and / or the inductor L. If the circuit parameters involved are known, the control of the second control phase can use a predefined switching pattern. Specifically, if the inductance of the inductor L and the capacitances of the decoupling capacitors Cz1, Cz2 (and optionally the junction capacitances of the rectifier diodes D1, D2, Dz1 and Dz2, and the filter capacitor Cf) are known, then a switching pattern for achieving the transition of the voltage Vz at the first input node 111 to a high voltage level can be predetermined, while the current through the inductor L does not exceed a threshold current.

[0141] Alternatively, the boost input voltage Vz and / or the inductor current I L can be compared with a preset threshold to generate switching signals for switches S1 and S2 to move the boost input voltage Vz to a high voltage level, while the current I L through the inductor L does not exceed the threshold current I TH .

[0142] To ensure that the magnitude of the current I L remains below the threshold current, it may be necessary to perform controlled switching of the first switch and the second switch, e.g., such that the voltage Vz at the first input node 111 is incrementally charged or increased. For example, this requirement can depend on the exact component values of the components in the boost PFC converter.

[0143] In this way, the transition control system 134 is configured to control the voltage at the first input node to reach the voltage at the first output node in two or more steps by controlling the operation of the first switch and the second switch during the positive to negative zero crossing of the voltage provided by the AC input signal.

[0144] Thus, the transition of the boost input voltage to a high voltage level can be effectively split into a series of smaller voltage steps. This approach facilitates the specific control of the peak value of the inductor current I L during the transition (i.e., during the zero crossing of the AC input signal), thereby reducing or attenuating the oscillations at the boost input node 111.

[0145] It will be apparent that the minimum number of steps can be defined by the maximum allowable current in the inductor L. Specifically, the maximum allowable current can be defined such that saturation of the inductor L is not permitted, as saturation will result in an even higher current, which in turn may damage the inverter. The more steps used, the lower the inductor current I L .

[0146] The transition control system 134 can be configured to perform a three - stage sequence of a step or control phase during the positive - to - negative zero - crossing (i.e., transition) of the voltage provided by the AC input signal. Thus, during the transition of the AC input signal from positive to negative voltage, the transition control system can be configured to operate in a first control phase, followed by a second control phase, and then a third control phase.

[0147] For improved understanding, Figure 4 voltage waveforms at the first input node 111 (voltage Vz) and the intermediate node 135 (voltage Vx) during the first control phase 410, the second control phase 420, and the third control phase 430 (during the positive - to - negative zero - crossing) are shown.

[0148] In the first control phase 410, the transition control system can control the operation of the first switch and the second switch such that the voltage at the first input node is maintained (e.g., at the level at the entry to the first control phase, which can be the minimum boost input voltage).

[0149] In the second control phase 420, the transition control system can control the operation of the first switch and the second switch such that the voltage at the first input node reaches a high voltage level. Correspondingly, this will place the voltage at the second input node at a high voltage level.

[0150] The method for performing the second control phase has been described previously. Thus, the second control phase represents the phase during which the voltage at the first input node 111 is placed at a high voltage level.

[0151] As previously described, the second control phase can be performed using two or more steps. This can be achieved by appropriate control of the switches such that the intermediate node is modulated such that the voltage at the first input node 111 gradually steps up to the voltage Vb at the first output node 121 in two or more steps (e.g., three or more steps).

[0152] However, depending on component values, for example, the voltage at the first input node does not have to increase in multiple steps - and some embodiments may only require a single step.

[0153] Specifically, during the second control phase, the transition control system can be configured to connect the intermediate node 135 to the first output node 121 for increasingly longer time periods. This will cause the voltage at the first input node 111 to gradually step up to the voltage at the first output node 121.

[0154] In the third control phase 430, the transition control system can control the operation of the first switch and the second switch such that the voltage at the first input node is maintained at the voltage Vb of the first output node 121.

[0155] During the positive-to-negative zero-crossing period, when the voltage of the AC input signal S AC drops below a first predetermined voltage, the transition control system can enter a first control phase. This can cover the conventional or normal operation of switches S1, S2.

[0156] During the positive-to-negative zero-crossing period, the transition control system can move from the first control phase to the second control phase at any point after the voltage of the AC input signal has dropped below 0V (i.e., performed zero-crossing). This can be performed by monitoring or measuring the voltage of the AC input signal, or can simply be performed after a period of time after starting the first control phase, after which the voltage of the AC input signal may have dropped below 0. Since the converter is decoupled via the boost input decoupler and / or the voltage at the boost input node 111 is controlled, precise zero-crossing does not need to be satisfied.

[0157] During the positive-to-negative zero-crossing period, the transition control system can move from the second control phase to the third control phase in response to the voltage at the first input node reaching the voltage at the first output node or the voltage at the first output node minus a bias value (e.g., the first input node reaches the maximum boost input voltage).

[0158] During the first control phase and the third control phase (which are actually "idle modes" during which the voltage is maintained), the transition control system is configured to maintain / perform the periodic switching of switches S1 and S2. Due to the oscillatory energy involved, this increases the ease and smoothness of restarting the switching process (e.g., for the second phase or for entering normal operation).

[0159] It will be appreciated that in some embodiments, the first phase and / or the third phase may be omitted.

[0160] As previously described, for the positive-to-negative zero-crossing of the voltage of the AC input signal, the first control phase can be initiated in response to the voltage of the AC input signal S AC dropping below a first predetermined voltage. The first predetermined voltage can be defined, for example, by the minimum boost input voltage (Vz min ) presented in equation (1) above. The actual value of the first predetermined voltage can be defined based on the minimum boost input voltage, for example, equal to the minimum boost input voltage or a feasible value close to (but greater than) the minimum boost input voltage. The advantage of setting the first predetermined voltage (which can also optionally define a second predetermined voltage) is that this prevents the converter from attempting to operate when the boost input voltage Vx is below the minimum required voltage for performing the necessary boost operation. By doing so, this can maintain zero-voltage switching at the switch node 135.

[0161] In any case, during the first control phase, the transition control system effectively controls the synchronous boost PFC converter 130 to operate in the idle mode to maintain the voltage Vz at the first input node 111 at Vz min at.

[0162] It will be appreciated that the maximum boost input voltage Vz max is given by V zmax = Vb - Vz min .

[0163] In the example shown by Figure 4 , the timing pattern of the second control phase includes three switching cycles (i.e., steps) with seven switching times, thereby reducing the peak current (i.e., the number of steps is 3). Of course, in other embodiments, the number of steps or the number of switching cycles can be 2, or can be a number greater than 3. The number of steps or the number of switching cycles can also be 1, but this is not preferred because it would require components with a higher rated current.

[0164] In the example shown, the value of Vz is changed to Vb using three steps, which can reduce the maximum current through the inductor by no less than two-thirds. For example, this can allow the current through the inductor to drop below the rated value of normal operation.

[0165] It will be appreciated that the size of the decoupling capacitor will affect the value of the maximum possible current.

[0166] Figure 5 A state floor plan is provided, which indicates the negative limit of the maximum inductor current I L during the transition of the AC input signal from positive to negative voltage. The negative peak of the inductor current I L can not exceed -I L-min , and the positive peak must slightly exceed I L-ZVS , which gives the (voltage-related) ZVS limit of the inverter.

[0167] Of course, in the case of a negative-to-positive transition (i.e., in the case where the boost input voltage Vz must commutate from Vb to V Zmin ), then both the trajectory direction and the inductor current axis I L are reversed.

[0168] Under normal operating conditions, it is preferred not to use the clamping diodes Dz1 and Dz2 at all (i.e., they do not conduct current). For example, as shown in Figure 4 , if properly controlled, the voltage Vz at the first input node 111 will not exceed the bus voltage Vb and will not become negative (i.e., drop below the ground voltage GND). In other words, the instantaneous inductor current I L at the end of the transition is close to zero.

[0169] However, there are situations in which these requirements will not be met and the clamping diodes will conduct current. For example, this can occur if, in the case of any overvoltage in the AC input signal or due to any EMI filter ringing, the timing of the switching sequence during the second control phase is not well adapted to the component parameters (L, Cz). Therefore, in order to account for these non-ideal events and to relax the requirements for the timing accuracy of the control during at least the second control phase, the clamping diodes Dz1 and Dz2 are used to clamp the voltage within a safe limit.

[0170] During the transition, the second control phase of the control stabilizes the boost input voltage Vz near the value of the bus voltage Vb without overshoot or undershoot. This can lead to unwanted ringing. To overcome this problem, a third control phase is used to effectively operate the synchronous boost PFC converter in an idle mode until the voltage difference Vb - V AC drops below a predetermined threshold voltage (where V AC is the voltage of the AC input signal S AC ). During this phase, the transition control system can relinquish its control and the traditional or normal operating process (e.g., QSW mode) can start again.

[0171] After the third control phase, when normal PFC operation continues, the second input node 112 is charged via an EMI capacitor, for example, after the first input node 111, before the first rectifier diode D1 is forward biased by the current of the AC input signal.

[0172] Figure 6 The current Ib flowing into the output capacitor Co during the transition is shown. This indicates that the energy required to initiate and perform the transition of the voltage at the first input node to the bus voltage Vb comes from the output capacitor. This charge eventually reaches equilibrium, indicating a lossless or near-lossless transition.

[0173] Figure 6 The current I L through the inductor is also shown. The control of the operation of the switch is preferably configured such that this current does not (or is predicted not to) exceed a threshold current. As previously explained, this may require two or more switching cycles, depending on the parameters of the circuit components.

[0174] The method for controlling the switch during the negative-to-positive zero crossing of the voltage provided by the AC input signal is similar to the method for the positive-to-negative zero crossing described above.

[0175] However, instead of controlling the voltage at the boost input node to reach a high voltage level (e.g., the voltage at the first output node or a biased version thereof), the voltage is controlled to reach a low voltage level (e.g., the minimum boost input voltage as presented in Equation (1)). This is achieved by controlling the discharge of the voltage at the boost input node towards the second output node (i.e., ground GND).

[0176] Preferably, the transition control system is configured to: during (e.g., any) negative-to-positive zero-crossing of the voltage provided by the AC input, control the voltage Vz at the first input node 111 to reach a low voltage level before the power provided by the AC input signal to the second input node can forward-bias the second rectifying diode.

[0177] The transition control system 134 is preferably configured to: during (e.g., any) negative-to-positive zero-crossing of the voltage provided by the AC input signal to the first input node, control the voltage at the first input node 111 to reach a low voltage level by resonantly discharging the first input node via the inductor of the synchronous boost converter.

[0178] This method effectively performs a "soft discharge" of the voltage at the input node, such that it gradually decreases over time rather than suddenly stepping to a low voltage level. This reduces the noise in the overall power factor correction system.

[0179] The transition control system 134 can be configured to: during negative-to-positive zero-crossing of the voltage provided by the AC input signal to the first input node, control the voltage at the first input node to reach a low voltage level, wherein the control is configured such that the current I L through the inductor L of the synchronous boost converter 130 TH remains below a threshold current I

[0180] A method for controlling a switch during negative-to-positive zero-crossing of the voltage provided by the AC input signal can include a stepped three-stage sequence similar to the three-stage sequence described for positive-to-negative zero-crossing, but in reverse order - i.e., performing the third control stage, followed by the second control stage, followed by the first control stage.

[0181] For negative-to-positive zero-crossing, in the second control stage, the switching period is adjusted such that the connection stage includes connecting the intermediate node 135 to the second output node 122 (and disconnecting the intermediate node from the first output node 121), thereby discharging / reducing the boost input voltage while increasing the magnitude of the current I L through the inductor (but in the opposite direction compared to during positive-to-negative zero-crossing). Similarly, the disconnection stage includes connecting the intermediate node 135 to the first output node 121 (and disconnecting the intermediate node from the second output node) to dissipate the current through the inductor L.

[0182] During the negative-to-positive zero crossing, the transition control system can enter a third control phase in response to the voltage of the AC input signal rising to a second predetermined voltage. The second predetermined voltage can have the same magnitude as the first predetermined voltage but with an opposite polarity (i.e., negative).

[0183] During the negative-to-positive zero crossing, the transition control system can move from the third control phase to the second control phase at any point after the voltage of the AC input signal rises above 0 V (i.e., performs a zero crossing). This can be performed by monitoring or measuring the voltage of the AC input signal, or can simply be performed after a period of time after starting the third control phase, after which the voltage of the AC input signal may have risen above 0.

[0184] During the negative-to-positive zero crossing, the transition control system can move from the second control phase to the first control phase in response to the voltage at the first input node reaching a minimum boost input voltage.

[0185] It will be appreciated that in some embodiments, the first stage and / or the third stage may be omitted.

[0186] The transition control system 134 can be configured to: during the negative-to-positive zero crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the minimum boost input voltage at the first output node in two or more steps (i.e., using two or more switching cycles) by controlling the operation of the first switch and the second switch.

[0187] Turning back Figure 2 , additional optional features of the proposed system are described below.

[0188] Preferably, the capacitance of the output capacitor is more than 100 times the capacitance of the first decoupling capacitor and / or the second decoupling capacitor. This reduces the stress / strain on the (one or more) decoupling capacitors.

[0189] It is possible that the totem-pole power factor correction system can include a plurality of synchronous boost PFC converters (with corresponding multiple output interfaces).

[0190] An electronic device apparatus is also proposed, which includes any totem-pole power factor correction system proposed herein and an electronic device, and the electronic device is configured to draw power from the totem-pole power factor correction system. Preferably, the electronic device is configured to draw power less than 10 kW.

[0191] By studying the drawings, the disclosure and the appended claims, those skilled in the art can understand and implement variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the words "a" or "an" do not exclude a plurality.

[0192] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used advantageously.

[0193] If the term "adapted to" is used in the claims or the specification, it should be noted that the term "adapted to" is intended to be equivalent to the term "configured to". If the term "arrangement" is used in the claims or the specification, it should be noted that the term "arrangement" is intended to be equivalent to the term "system", and vice versa.

[0194] Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A totem-pole power factor correction system for driving a load, the totem-pole power factor correction circuit comprising: An input interface, which includes: A first input node and a second input node for receiving an AC input signal from an external power supply; and An impedance connecting the first input node to the second input node; An output interface for providing a drive signal to the load, the output interface including: a first output node and a second output node for connecting to the load; and an output capacitor connected between the first output node and the second output node; A synchronous boost PFC converter, which includes: an inductor coupled between the first input node and an intermediate node; a first switch connected between the intermediate node and the first output node; and a second switch connected between the intermediate node and the second output node; A rectification system, which includes: a first rectifier diode connected between the second input node and the first output node; and a second rectifier diode connected between the second output node and the second input node; and A boost input decoupler, which includes: A first clamping diode connected between the first input node and the first output node; A second clamping diode connected between the second output node and the first input node; and One or more decoupling capacitors, where each decoupling capacitor: Is connected between the first input node and the first output node; or is connected between the first input node and the second output node.

2. The totem-pole power factor correction system according to claim 1, wherein the one or more decoupling capacitors include: A first decoupling capacitor connected between the first input node and the first output node; And A second decoupling capacitor connected between the first input node and the second output node.

3. The totem-pole power factor correction system according to claim 1 or 2, wherein the input interface includes an EMI filter for performing EMI filtering on the AC input signal received by the input interface.

4. The totem-pole power factor correction system according to any one of claims 1 to 3, wherein the synchronous boost PFC converter includes a transition control system for controlling the operation of the first switch and the second switch during a positive-to-negative zero crossing of the voltage provided by the AC input signal to the first input node, The transition control system is configured to: during a positive-to-negative zero crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach a high voltage level by controlling the operation of the first switch and the second switch.

5. The totem-pole power factor correction system according to claim 4, wherein the transition control system is configured to: during the positive-to-negative zero crossing of the voltage provided by the AC input signal to the first input node, control the voltage at the first input node to reach the high voltage level before the power provided by the AC input signal to the second input node can forward bias the first rectifier diode.

6. The totem-pole power factor correction system according to claim 4 or 5, wherein the transition control system is configured to: during the positive-to-negative zero crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the high voltage level by resonantly charging the first input node via the inductor of the synchronous boost converter.

7. The totem-pole power factor correction system according to any one of claims 4 to 6, wherein the transition control system is configured to: during the positive-to-negative zero crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the high voltage level, wherein the control is configured such that the magnitude of the current through the inductor of the synchronous boost converter remains below a threshold current.

8. The totem-pole power factor correction system according to any one of claims 4 to 7, wherein the transition control system is configured to: during the positive-to-negative zero crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the high voltage level in two or more voltage steps by controlling the operation of the first switch and the second switch.

9. The totem-pole power factor correction system according to any one of claims 4 to 8, wherein the transition control system is configured to, during the positive-to-negative zero crossing of the voltage provided by the AC input signal to the first input node: Enter a first control phase, during which the transition control system controls the operation of the first switch and the second switch such that the voltage at the first input node is maintained; After the first control phase, enter a second control phase, during which the transition control system controls the operation of the first switch and the second switch such that the voltage at the first input node reaches the high voltage level; and After the voltage at the first input node reaches the high voltage level, enter a third control phase, during which the transition control system controls the operation of the first switch and the second switch such that the voltage at the first input node is maintained at the high voltage level.

10. The totem-pole power factor correction system according to any one of claims 4 to 9, wherein the transition control system is further configured to control the operation of the first switch and the second switch during the negative-to-positive zero crossing of the voltage provided by the AC input signal to the first input node. The transition control system is configured to control the voltage at the first input node to reach a low voltage level by controlling the operations of the first switch and the second switch during the negative-to-positive zero-crossing of the voltage provided by the AC input signal to the first input node.

11. The totem-pole power factor correction system according to claim 10, wherein the transistor control system is configured to, during the negative-to-positive zero-crossing of the voltage provided by the AC input signal to the first input node: Enter a fourth control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained; After the fourth control phase, enter a fifth control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node reaches the low voltage level; And After the voltage at the first input node reaches the low voltage level, enter a sixth control phase, during which the transition control system controls the operations of the first switch and the second switch such that the voltage at the first input node is maintained at the low voltage level.

12. The totem-pole power factor correction system according to any one of claims 10 or 11, wherein the transition control system is configured to: during the negative-to-positive zero-crossing of the voltage provided by the AC input signal, control the voltage at the first input node to reach the low voltage level in two or more steps by controlling the operations of the first switch and the second switch.

13. The totem-pole power factor correction system according to any one of claims 4 to 12, wherein the transition control system is configured to control the operations of the first switch and the second switch in response to the amplitude of the voltage provided by the AC input signal dropping below a first predetermined threshold.

14. The totem-pole power factor correction system according to claim 13, wherein the transition control system is configured to abandon the control of the operations of the first switch and the second switch in response to the amplitude of the voltage provided by the AC input signal rising above the first predetermined threshold.

15. An electronic device apparatus, comprising: An electronic device configured to draw less than 10 kW; And The totem-pole power factor correction system according to any one of claims 1 to 14.

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