Mismatch test structure and forming method, test method and modeling method thereof

Abstract

The invention discloses a mismatch test structure and a forming method, a test method and a modeling method thereof, and the forming method comprises the steps: providing a to-be-tested device which comprises a substrate and a semiconductor device layer, and forming an array comprising a plurality of repeated device units in the semiconductor device layer, and selecting MOS transistors of the same type from the adjacent device unit groups as a to-be-tested mismatch module, wherein each MOS transistor in the to-be-tested mismatch module is provided with an adjacent MOS transistor which is commonly connected with the source end of the MOS transistor when the device works normally and an adjacent MOS transistor which is not commonly connected with the source end of the MOS transistor when the device works normally. MOS transistors of the same type are selected from adjacent device unit groups to serve as a to-be-tested mismatch module, each MOS transistor is provided with an adjacent transistor which is connected with a source end in common mode and is not provided with a source end in common mode, and the mismatch characteristics of the source end of each MOS transistor in a common connection state and a non-common connection state are tested at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a mismatch test structure, a forming method thereof, a testing method, and a modeling method. Background Art

[0002] With the continuous development of integrated circuit technology, the number of semiconductor devices integrated in a single chip is increasing. When designing an integrated circuit, semiconductor devices with several identical electrical parameters are usually required. For example, when designing a memory cell of a Static Random Access Memory (SRAM), several MOS transistors with identical electrical parameters are needed. In an actual product, the electrical parameters of nominally identical MOS transistors in an SRAM memory cell often drift, resulting in a mismatch of the electrical parameters of MOS transistors that should originally be the same, that is, the matching characteristics decrease, which may cause problems such as a slow SRAM storage speed, increased power consumption, and clock chaos.

[0003] However, currently, the efficiency and accuracy of identifying transistor mismatch defects need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the efficiency and accuracy of identifying transistor mismatch defects.

[0005] To solve the above technical problem, an embodiment of the present invention provides a mismatch test structure, a forming method thereof, a testing method, and a modeling method, including: providing a device under test, where the device under test includes a substrate and a semiconductor device layer, and an array including several repeated device units is formed in the semiconductor device layer, and each device unit contains several MOS transistors; selecting the same type of MOS transistors from adjacent device unit groups as the mismatch modules to be tested, where the adjacent device unit groups include several adjacent device units in the device under test, and each MOS transistor in the mismatch modules to be tested has an adjacent MOS transistor whose source terminal is commonly connected to its source terminal during normal device operation and an adjacent MOS transistor whose source terminal is not commonly connected to its source terminal during normal device operation; providing a bonding pad for connecting the mismatch modules to be tested to a test system for mismatch testing.

[0006] Optionally, the forming method of the mismatch test structure further includes: forming a first metal layer on the semiconductor device layer to respectively lead out the source terminal, drain terminal, and gate terminal of the MOS transistors in the mismatch modules to be tested; the first metal layer electrically connects the source terminals of the MOS transistors in the mismatch modules to be tested that share a contact hole for the source terminal during normal device operation to form a common source terminal.

[0007] Optionally, the method for forming the mismatch test structure further includes: forming a second metal layer on the first metal layer to respectively lead out the common source terminal, the drain terminal other than the common source terminal, and the gate terminal of the mismatch module to be tested; the second metal layer electrically connects the common source terminal, the gate terminal, and the drain terminal of the mismatch module to be tested to the transfer pads respectively, so as to test the mismatch conditions of each MOS transistor in the mismatch module to be tested in two states of source terminal common connection and non-common connection.

[0008] Optionally, the method for forming the mismatch test structure further includes: the second metal layer electrically connects the gate terminals of adjacent MOS transistors whose source terminals are commonly connected during normal operation of the device in the mismatch module to be tested to form a common gate terminal; the second metal layer electrically connects the common source terminal, the common gate terminal, and the drain terminal of the mismatch module to be tested to the transfer pads respectively, so as to test the mismatch conditions of each MOS transistor in the mismatch module to be tested in two states of source terminal common connection and non-common connection.

[0009] Optionally, in the mismatch module to be tested, the drain terminals of MOS transistors whose drain terminals are electrically connected during normal operation are electrically isolated from each other.

[0010] Optionally, the number of the transfer pads is greater than or equal to 8.

[0011] Optionally, the number of MOS transistors in the mismatch module to be tested is greater than or equal to 4.

[0012] Optionally, the MOS transistors of the same type refer to MOS transistors with the same function in each device unit.

[0013] Optionally, the types of the MOS transistors include NPD transistors, NPG transistors or PPU transistors.

[0014] Optionally, the device to be tested is an SRAM or a CMOS image sensor.

[0015] The present invention also provides a mismatch test structure, including: a mismatch module to be tested, which is a part of the device to be tested, the device to be tested includes a substrate and a semiconductor device layer, an array including several repeated device units is formed in the semiconductor device layer, and each device unit contains several MOS transistors; the mismatch module to be tested is MOS transistors of the same type in adjacent device unit groups, the adjacent device unit groups include several adjacent device units in the device to be tested, and each MOS transistor in the mismatch module to be tested has an adjacent MOS transistor whose source terminal is commonly connected to its source terminal during normal operation of the device and an adjacent MOS transistor whose source terminal is not commonly connected to its source terminal during normal operation of the device; transfer pads, which are used to connect the mismatch module to be tested to a test system for mismatch testing.

[0016] Optionally, the mismatch test structure further includes: a first metal layer located on the semiconductor device layer for leading out the source terminal, drain terminal, and gate terminal of the MOS transistor in the mismatch module to be tested respectively; the first metal layer electrically connects the source terminals of the transistors whose source terminals are commonly connected to one contact hole during normal device operation in the mismatch module to be tested, forming a common source terminal.

[0017] Optionally, the mismatch test structure further includes: a second metal layer located on the first metal layer for leading out the common source terminal, drain terminals other than the common source terminal, and gate terminal of the mismatch module to be tested respectively; the second metal layer electrically connects the common source terminal, gate terminal, and drain terminal of the mismatch module to be tested to the transfer pads respectively to test the mismatch conditions of each MOS transistor in the mismatch module to be tested in two states where the source terminals are commonly connected and not commonly connected.

[0018] Optionally, the mismatch test structure further includes: the second metal layer electrically connects the gate terminals of adjacent MOS transistors whose source terminals are commonly connected during normal device operation in the mismatch module to be tested, forming a common gate terminal; the second metal layer electrically connects the common source terminal, common gate terminal, and drain terminal of the mismatch module to be tested to the transfer pads respectively to test the mismatch conditions of each MOS transistor in the mismatch module to be tested in two states where the source terminals are commonly connected and not commonly connected.

[0019] Optionally, the mismatch test structure further includes: electrical isolation of the drain terminals between MOS transistors whose drain terminals are electrically connected during normal operation in the mismatch module to be tested.

[0020] The present invention also provides a mismatch test method, including: performing a mismatch test step on at least one adjacent device unit group, including: selecting a first mismatch module to be tested from a first adjacent device unit group, the first adjacent device unit being a part of the device to be tested, the device to be tested including an array of several repeated device units, the first adjacent device unit group including several adjacent device units in the device to be tested, the first mismatch module to be tested being the same type of MOS transistors in the adjacent device units, each MOS transistor in the first mismatch module to be tested having an adjacent MOS transistor whose source terminal is commonly connected to its source terminal during normal device operation and an adjacent MOS transistor whose source terminal is not commonly connected to its source terminal during normal device operation; providing transfer pads, connecting the first mismatch module to be tested to a test system to perform a first mismatch test; repeating the above steps until the mismatch tests of each type of MOS transistor in the first adjacent device unit group are completed.

[0021] Optionally, performing the first mismatch test includes: obtaining the electrical parameters of each MOS transistor in the mismatch test structure in two states where the source terminals are commonly connected and not commonly connected.

[0022] Optionally, the electrical parameters include one or more of the following: threshold voltage, saturation drain current, cut-off drain current, on-resistance, gate current, transconductance, source conductance, voltage amplification factor.

[0023] Optionally, the mismatch test structures obtained from the device under test at least once are several device units located at the center of the array of the device under test.

[0024] Optionally, it further includes a step of performing a mismatch test on other adjacent device unit groups within the device under test.

[0025] The present invention also provides a modeling method, including: performing modeling using the results obtained by the above-mentioned mismatch test method.

[0026] Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

[0027] In the method for forming a mismatch test structure in the technical solution of the present invention, by selecting the same type of MOS transistor as the mismatch module to be tested in adjacent device unit groups, the mismatch characteristics of several MOS transistors can be tested simultaneously, increasing the number of MOS transistors tested, improving the efficiency of identifying the mismatch characteristics of MOS transistors, and each MOS transistor has adjacent transistors with and without a common source terminal connected thereto, enabling the simultaneous testing of the mismatch characteristics of the source terminal of each MOS transistor in two states of being connected and not connected in common, which can accurately reflect the process fluctuations of the device under test, and thus improving the accuracy of the test results.

[0028] Furthermore, each MOS transistor in the mismatch module to be tested in the embodiments of the present invention also has at least one adjacent transistor with a common gate terminal connected thereto, which can achieve the common connection of the gate terminals of several MOS transistors, reducing the number of test pads and the interconnection traces of the gate terminals, thereby reducing the parasitic resistance value in the device under test, and further improving the accuracy of the test results.

[0029] Furthermore, the test structure in the embodiments of the present invention can be used to test SRAM devices or CMOS image sensor devices, increasing the diversity of the application scenarios of the test structure.

[0030] Furthermore, in the mismatch module to be tested in the embodiments of the present invention, the drain terminals of MOS transistors that are electrically connected to each other during normal operation are electrically isolated, avoiding the increase in the drain terminal voltage during the test process from affecting the test results, and thus improving the accuracy of the test results.

[0031] The mismatch test method in the embodiment of the present invention tests the drain terminal, gate terminal and common source terminal of the same type of MOS transistors in the adjacent device units through the transfer pad, thereby realizing simultaneous testing of the electrical parameters of several MOS tubes, improving the efficiency of identifying the mismatch characteristics of MOS transistors, and each MOS transistor has two states of common source connection and non-common source connection, thereby improving the accuracy of the test result, and through the mismatch test of each type of MOS transistor in the first adjacent device unit group, it is possible to realize the mismatch test of each device unit in the adjacent device unit group, further improving the accuracy of the test result.

[0032] The modeling method in the embodiment of the present invention establishes a mismatch model according to the mismatch conditions of a plurality of MOS transistors, thereby increasing the number of parameters for model establishment, thereby increasing the fitting ability of the mismatch model to electrical parameters and improving the performance of the mismatch model; in addition, by obtaining the mismatch conditions of each MOS transistor in the two states of common connection and non-common connection of the source end, the accuracy and stability of the established mismatch model are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic structural diagram of a device under test circuit in an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of a device under test layout in an embodiment of the present invention;

[0035] Figures 3 to 5 is a schematic diagram of a layout structure of a mismatch test structure in an embodiment of the present invention;

[0036] Figures 6 to 8 is a schematic diagram of the layout structure of another mismatch test structure in an embodiment of the present invention;

[0037] Figures 9 to 11 is a schematic diagram of a layout structure of another mismatch test structure in an embodiment of the present invention;

[0038] Figure 12 4 is a flow chart of a mismatch testing method in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0040] The current test structure for the mismatch characteristics of SRAM memory cells is to select a MOS transistor to be tested in each of the two-bit memory cells and test the mismatch characteristics of the two MOS transistors to be tested. It can be seen that the number of MOS transistors to be tested in the current test scheme is small, the efficiency of identifying the mismatch characteristics of the MOS transistors to be tested is not high, and the test results of the two MOS transistors to be tested can only reflect the mismatch characteristics within the two-bit memory cells, reducing the accuracy of the test results.

[0041] To solve the above technical problems, the present invention provides a method for forming a mismatch test structure. The MOS transistors of the same type in the adjacent device unit groups are included in the mismatch module to be tested, so as to simultaneously test the mismatch characteristics of a plurality of MOS transistors, increase the number of MOS transistors tested, improve the efficiency of identifying the mismatch characteristics of the MOS transistors, and each MOS transistor has adjacent transistors with and without a common source terminal connected to its source terminal, so as to simultaneously test the mismatch characteristics of the source terminal of each MOS transistor in two states of common connection and non-common connection, which can accurately reflect the process fluctuations of the device to be tested, and thus improve the accuracy of the test results.

[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0043] An embodiment of the present invention provides a method for forming a mismatch test structure, including: providing a device to be tested, the device to be tested including a substrate and a semiconductor device layer, an array including a plurality of repeated device units is formed in the semiconductor device layer, and each device unit contains a plurality of MOS transistors; selecting MOS transistors of the same type from adjacent device unit groups as the mismatch module to be tested, the adjacent device unit groups including a plurality of adjacent device units in the device to be tested, and each MOS transistor in the mismatch module to be tested has an adjacent transistor with its source terminal commonly connected during normal device operation and an adjacent transistor with its source terminal not commonly connected during normal device operation; providing a transfer pad for connecting the mismatch module to be tested to a test system for mismatch testing.

[0044] Among them, the common connection of the source terminal is characterized in that the source terminals of a plurality of MOS transistors are connected to the same transfer pad, and subsequently, the same test voltage is applied to the source terminals of the plurality of MOS transistors. Specifically, the common connection of the source terminal is that the source terminals of a plurality of MOS transistors are commonly connected to a contact hole.

[0045] Among them, the non-common connection of the source terminal is characterized in that the source terminals of a plurality of MOS transistors are respectively connected to different transfer pads, and subsequently, different test voltages are respectively applied to the source terminals of the plurality of MOS transistors. Specifically, the common connection of the source terminal is that the source terminals of a plurality of MOS transistors are not commonly connected to a contact hole.

[0046] In some embodiments of the present invention, the MOS transistors of the same type refer to the MOS transistors with the same function in each device unit.

[0047] In some embodiments of the present invention, the number of device units in the adjacent device unit groups is greater than or equal to 4, the number of MOS transistors in the mismatch module to be measured is greater than or equal to 4, and the number of transfer pads is greater than or equal to 8.

[0048] Among them, the number of device units in the adjacent device unit groups is the same as the number of MOS transistors in the mismatch module to be measured, that is, one MOS transistor is obtained from each device unit to form the mismatch module to be measured.

[0049] In some embodiments of the present invention, the transfer pads are arranged in sequence along the same direction.

[0050] It should be noted that the mismatch test is characterized by applying a test voltage to the transfer pads to obtain the mismatch situation in the mismatch module to be measured at one time.

[0051] In some embodiments of the present invention, the device to be measured is a SRAM.

[0052] In other embodiments of the present invention, the device to be measured is a CMOS image sensor.

[0053] In the above solution, by selecting MOS transistors of the same type in the adjacent device unit groups as the mismatch module to be measured, the mismatch characteristics of several MOS transistors can be tested simultaneously, increasing the number of MOS transistors tested, improving the efficiency of identifying the mismatch characteristics of MOS transistors, and each MOS transistor has adjacent transistors with and without a common source terminal connected thereto, realizing the simultaneous test of the mismatch characteristics of the source terminal of each MOS transistor in two states of being commonly connected and not being commonly connected, which can accurately reflect the process fluctuation of the device to be measured, and further improving the accuracy of the test results.

[0054] In addition, the test structure in the embodiments of the present invention can test SRAM devices or CMOS image sensor devices, increasing the diversity of the application scenarios of the test structure.

[0055] In a specific embodiment, in combination with Figure 1 , taking Figure 1 as an example of the schematic diagram of the circuit structure of the device to be measured, the circuit structure of the device to be measured is described.

[0056] It should be noted that Figure 1 the circuit of the device to be measured in

[0057] The SRAM circuit includes: a first inverter and a second inverter which are cross-coupled, and a first selection transistor and a second selection transistor M6. The output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the second inverter is connected to the input terminal of the first inverter. Among them, the first inverter includes a first MOS transistor M1 and a second MOS transistor M2, and the second inverter includes a third MOS transistor M3 and a fourth MOS transistor M4.

[0058] In some embodiments of the present invention, the first MOS transistor M1 and the third MOS transistor M3 are NPD transistors, the second MOS transistor M2 and the fourth MOS transistor M4 are PPU transistors, and the first selection transistor and the second selection transistor M6 are NPG transistors.

[0059] Among them, the NPD transistor is an N-type pull-down transistor in the inverter, the PPU transistor is a P-type pull-up transistor in the inverter, and the NPG transistor is an N-type transmission transistor in the SRAM.

[0060] In a specific embodiment, the drain terminal of the first MOS transistor M1 is connected to the drain terminal of the first selection transistor, the source terminal of the first MOS transistor M1 is grounded, the gate terminal of the first MOS transistor M1 is connected to the gate terminal of the second MOS transistor M2, the source terminal of the second MOS transistor M2 is connected to the power supply terminal, the drain terminal of the second MOS transistor M2 is connected to the gate terminal of the third MOS transistor M3, the drain terminal of the third MOS transistor M3 is connected to the drain terminal of the second selection transistor M6, the source terminal of the third MOS transistor M3 is grounded, the gate terminal of the third MOS transistor M3 is further connected to the gate terminal of the fourth MOS transistor M4, the source terminal of the fourth MOS transistor M4 is connected to the power supply terminal, the drain terminal of the fourth MOS transistor M4 is connected to the gate terminal of the first MOS transistor M1, the gate terminal of the first selection transistor is connected to the word line WL, the source terminal of the first selection transistor is connected to the complementary bit line B̅L̅, the gate terminal of the second selection transistor M6 is connected to the word line WL, and the source terminal of the second selection transistor M6 is connected to the bit line BL.

[0061] In the circuit of the device under test in the embodiments of the present invention, during normal operation, the drain terminals of the MOS transistors whose drain terminals are electrically connected are electrically isolated. Specifically, the drain terminal of the second MOS transistor M2 is electrically isolated from the drain terminal of the first MOS transistor M1, and the drain terminal of the second MOS transistor M2 is electrically isolated from the drain terminal of the first selection transistor, avoiding the increase in the voltage of the drain terminal during the test from affecting the test result, thereby improving the accuracy of the test result.

[0062] In a specific embodiment, on the basis of Figure 1 combined with Figure 2 , taking the structural schematic diagram of the layout of the device under test in Figure 2 as an example, the structure of the layout of the device under test is described.

[0063] The layout of the device under test includes: a substrate; a well region located within the substrate; a semiconductor device layer located on the substrate, where the semiconductor device layer includes a plurality of gates and source / drain ends located on both sides of the gates; contact holes located on the semiconductor device layer; and a first metal layer located on the contact holes.

[0064] In the circuit of the device under test in the embodiments of the present invention, during normal operation, the drain ends of the MOS transistors electrically connected to the drain end are electrically isolated. Specifically, the first metal layer on the drain end of the second MOS transistor M2 is disconnected from the first metal layer on the drain end of the first MOS transistor M1 (as shown in the red frame in the figure) to achieve electrical isolation, and the first metal layer on the drain end of the second MOS transistor M2 is disconnected from the first metal layer on the drain end of the first selection transistor (as shown in the red frame in the figure) to achieve electrical isolation, avoiding the increase in the voltage of the drain end during the test from affecting the test result, thereby improving the accuracy of the test result.

[0065] In a specific embodiment, in combination with Figures 3 to 5 , to Figures 3 to 5 taking the layout structure schematic diagram of the mismatch test structure in

[0066] It should be noted that Figure 3 the device under test in

[0067] In some embodiments of the present invention, Figures 3 to 5 the layout of the mismatch test structure in

[0068] Please refer to Figures 3 to 5 , Figure 3 which is a top view schematic diagram of the mismatch test structure, Figure 4 and Figure 5 is Figure 3Schematic cross-sectional view along AA1 in the figure. The method for forming the mismatch test structure includes: providing a device under test, the device under test including a substrate 100 and a semiconductor device layer, an array including a number of repeated device units being formed in the semiconductor device layer, and each device unit containing a number of MOS transistors; selecting the same type of PPU transistors from adjacent device unit groups as the mismatch modules to be tested, the adjacent device unit groups including a number of adjacent device units in the device under test, and each PPU transistor in the mismatch modules to be tested having an adjacent PPU transistor whose source terminal is commonly connected to a contact hole 106 during normal device operation and an adjacent PPU transistor whose source terminal is not commonly connected to a contact hole 106 during normal device operation; providing a transfer pad for connecting the mismatch modules to be tested to a test system for mismatch testing.

[0069] In some embodiments of the present invention, Figure 4 shows the connection situation of the first metal layer and the second metal layer on the source terminal in the figure, Figure 5 shows the connection situation of the first metal layer and the second metal layer on the gate terminal in the figure.

[0070] In some embodiments of the present invention, the adjacent device unit groups are adjacent memory device units within a 4-bit region, and the mismatch modules to be tested include 4 PPU transistors.

[0071] Specifically, in combination with Figure 1 and Figure 2 , the 4 PPU transistors in the mismatch modules to be tested are all second MOS transistors, or the 4 PPU transistors in the mismatch modules to be tested are all fourth MOS transistors.

[0072] In some embodiments of the present invention, a first metal layer 107 is formed on the semiconductor device layer to respectively lead out the source terminal, drain terminal, and gate terminal of the PPU transistors in the mismatch modules to be tested; a second metal layer 110 is formed on the first metal layer 107 to respectively lead out the common source terminals S1 / S2, drain terminals D1-1 / D1-2 / D2-1 / D2-2 other than the common source terminals S1 / S2, and the gate terminal of the mismatch modules to be tested; a first metal layer 107 is formed on the contact hole 106 on the source terminal of the PPU transistors, the contact hole 106 on the drain terminal of the PPU transistors, and the gate terminal of the PPU transistors.

[0073] In some other embodiments of the present invention, the second metal layer 110 electrically connects the gate terminals of adjacent MOS transistors whose source terminals are commonly connected during normal device operation in the mismatch modules to be tested to form common gate terminals G1 / G2.

[0074] In a specific embodiment, the four PPU tubes in the mismatching module to be measured are divided into two pairs of PPU tubes, and the connection modes of each pair of PPU tubes are the same. Taking one pair of PPU tubes as an example, the method for forming the mismatching module to be measured will be described below.

[0075] The method for forming the mismatching module to be measured includes: providing a substrate 100; performing ion implantation on the substrate 100 to form a well region 101 on the surface of the substrate 100; depositing two gate layers 104 on the well region 101; using the gate layers 104 as a mask to perform ion implantation on the well region 101 to form a common source region 103 between the two gate layers 104 and drain regions 102 on both sides of the two gate layers 104; forming a first dielectric layer 105 on the substrate 100; etching the first dielectric layer 105 until the surfaces of the drain region 102, the common source region 103, and the two gate layers 104 are exposed to form a plurality of first trenches (not shown in the figure); filling the first trenches with a conductive material to form contact holes 106 on the surfaces of the drain region 102, the common source region 103, and the two gate layers 104; respectively forming a first metal layer 107 on the contact holes 106 on the surfaces of the drain region 102, the common source region 103, and the two gate layers 104, so as to respectively lead out the source end, drain end, and gate end of the PPU tube in the mismatching module to be measured; forming a second dielectric layer 108 on the substrate 100; etching the second dielectric layer 108 until the surface of the first metal layer 107 is exposed to form a plurality of second trenches (not shown in the figure); filling the second trenches with a conductive material to form connection holes 109 on the surface of the first metal layer 107; respectively forming a second metal layer 110 on the connection holes 109 on the common source end and the drain end, so as to respectively lead out the common source end S2 and the drain ends D2-1 / D2-2 of the PPU tube in the mismatching module to be measured; forming a second metal layer 110 on the first metal layer 107 on the surfaces of the two gate layers 104, so as to lead out the gate ends of the mismatching module to be measured simultaneously to form a common gate end G2; the second metal layer 110 is also electrically connected to the transfer pad.

[0076] Since the gate ends of each pair of PPU tubes are commonly connected and the source ends are commonly connected, that is, the number of the second metal layers 110 on each pair of PPU tubes is 4, and the number of the subsequent transfer pads connected to the second metal layer 110 is also 4; the mismatching module to be measured includes two pairs of PPU tubes with the same connection mode, that is, the number of the second metal layers 110 in the mismatching module to be measured is 8, and the number of the subsequent transfer pads connected to the second metal layer 110 is also 8.

[0077] Among them, the source ends of the PPU transistors in each pair of PPU transistors are commonly connected, and the source ends of the PPU transistors in each pair of PPU transistors are not commonly connected to the source ends of the PPU transistors in other pairs of PPU transistors.

[0078] In this embodiment, each PPU transistor in the to-be-tested mismatch module further has at least one adjacent PPU transistor with its commonly connected gate terminal, which can realize the common connection of the gate terminals of several PPU transistors, reduce the number of test pads and the interconnection traces of the gate terminals, thereby reducing the parasitic resistance value in the to-be-tested device, and further improving the accuracy of the test result.

[0079] In addition, in the circuit of the to-be-tested device in this embodiment, when it works normally, the drain ends of the PPU transistors whose drain ends are electrically connected are electrically isolated from the drain end of the NPG transistor, and the drain ends of the PPU transistors are electrically isolated from the drain end of the NPD transistor. Specifically, the first metal layer 107 on the drain end of the PPU transistor is disconnected from the first metal layer 107 on the drain end of the NPG transistor (as shown in the red frame part in the figure) to achieve electrical isolation, and the first metal layer 107 on the drain end of the PPU transistor is disconnected from the first metal layer 107 on the drain end of the NPD (as shown in the red frame part in the figure) to achieve electrical isolation, avoiding the increase of the drain end voltage during the test affecting the test result, and further improving the accuracy of the test result.

[0080] In other embodiments of the present invention, a second metal layer is respectively formed on the first metal layer on the drain region and on the first metal layer on the surface of the common source region, so as to respectively lead out the common source end, the drain end other than the common source end, and the gate end of the to-be-tested mismatch module.

[0081] In the above solution, since the source ends of each pair of PPU transistors are commonly connected, that is, the number of the second metal layers on each pair of PPU transistors is 5, and the number of the subsequent transfer pads connected to the second metal layer is also 5; there are two pairs of PPU transistors with the same connection method in the to-be-tested mismatch module, that is, the number of the second metal layers in the to-be-tested mismatch module is 10, and the number of the subsequent transfer pads connected to the second metal layer is also 10.

[0082] In this embodiment, the second metal layer 110 is used to be electrically connected to the transfer pad to test the mismatch situation in the to-be-tested mismatch module, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0083] In other embodiments, a third metal layer or a fourth metal layer is used to be electrically connected to the transfer pad to test the mismatch situation in the to-be-tested mismatch module, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0084] Among them, the third metal layer is located on the second metal layer 110, and the fourth metal layer is located on the third metal layer.

[0085] In the above solution, by selecting the same type of PPU tubes in adjacent device unit groups as the mismatched modules to be tested, the mismatching characteristics of several PPU tubes can be tested simultaneously, increasing the number of PPU tubes tested and improving the efficiency of identifying the mismatching characteristics of PPU tubes. Moreover, each PPU tube has adjacent PPU tubes with and without a common source terminal connected to it, enabling the simultaneous testing of the mismatching characteristics of the source terminal of each PPU tube in two states: with and without a common connection, which can accurately reflect the process fluctuations of the device under test, thereby improving the accuracy of the test results.

[0086] In a specific embodiment, in combination with Figures 6 to 8 , taking Figures 6 to 8 as an example of the layout structure schematic diagram of the mismatching test structure, the formation method of the mismatching test structure will be described.

[0087] It should be noted that Figure 6 the device under test in

[0088] In some embodiments of the present invention, Figures 6 to 8 the layout of the mismatching test structure in

[0089] Please refer to Figures 6 to 8 , Figure 6 which is a top view schematic diagram of the mismatching test structure, Figure 7 and Figure 8 is Figure 6 the cross-sectional schematic diagram along BB1 in

[0090] In some embodiments of the present invention, Figure 7shows the connection of the first metal layer and the second metal layer on the source end, Figure 8 shows the connection of the first metal layer and the second metal layer on the gate end.

[0091] In some embodiments of the present invention, the adjacent device unit groups are adjacent memory device units within a 4-bit region, and the module to be measured for mismatch includes 4 NPD transistors.

[0092] Specifically, in combination with Figure 1 and Figure 2 , the 4 NPD transistors in the module to be measured for mismatch are all second MOS transistors, or the 4 NPD transistors in the module to be measured for mismatch are all fourth MOS transistors.

[0093] In some embodiments of the present invention, a first metal layer 207 is formed on the semiconductor device layer to lead out the source end, drain end, and gate end of the NPD transistors in the module to be measured for mismatch respectively; a second metal layer 210 is formed on the first metal layer 207 to lead out the common source ends G1 / G2 of the module to be measured for mismatch, the drain ends D1-1 / D1-2 / D2-1 / D2-2 other than the common source ends G1 / G2, and the gate ends respectively; the first metal layer 207 is formed on the contact hole 206 on the source end of the NPD transistor, the contact hole 206 on the drain end of the NPD transistor, and the gate end of the NPD transistor.

[0094] In some other embodiments of the present invention, the second metal layer 210 electrically connects the gate ends of adjacent MOS transistors whose source ends are commonly connected during normal operation of the device in the module to be measured for mismatch to form a common gate end S1 / S2.

[0095] In a specific embodiment, the 4 NPD transistors in the module to be measured for mismatch are divided into two pairs of NPD transistors, and the connection manner of each pair of NPD transistors is the same. Taking one pair of NPD transistors as an example, the formation method of the module to be measured for mismatch will be described below.

[0096] The method for forming the mismatch module to be measured includes: providing a substrate 200; performing ion implantation on the substrate 200 to form a well region 201 on the surface of the substrate 200; depositing and forming two gate layers 204 on the well region 201; using the gate layers 204 as a mask to perform ion implantation on the well region 201 to form a common source region 203 between the two gate layers 204 and drain regions 202 on both sides of the two gate layers 204; forming a first dielectric layer 205 on the substrate 200; etching the first dielectric layer 205 until the surfaces of the drain region 202, the common source region 203, and the two gate layers 204 are exposed to form a plurality of first trenches (not shown in the figure); filling the first trenches with a conductive material to form contact holes 206 on the surfaces of the drain region 202, the common source region 203, and the two gate layers 204; respectively forming first metal layers 207 on the contact holes 206 on the surfaces of the drain region 202, the common source region 203, and the two gate layers 204 so as to respectively lead out the source end, drain end, and gate end of the NPD transistor in the mismatch module to be measured; forming a second dielectric layer 208 on the substrate 200; etching the second dielectric layer 208 until the surface of the first metal layer 207 is exposed to form a plurality of second trenches (not shown in the figure); filling the second trenches with a conductive material to form connection holes 209 on the surface of the first metal layer 207; respectively forming second metal layers 210 on the connection holes 209 on the common source terminal G2 and the drain terminals D2-1 / D2-2 so as to respectively lead out the common source terminal G2 and the drain terminals D1-1 / D1-2 / D2-1 / D2-2 of the NPD transistor in the mismatch module to be measured; forming a second metal layer 210 on the first metal layer 207 on the surfaces of the two gate layers 204 so as to simultaneously lead out the gate ends of the mismatch module to be measured to form a common gate terminal S1 / S2.

[0097] Since the gate ends of each pair of NPD transistors are commonly connected and the source ends are commonly connected, that is, the number of the second metal layers 210 on each pair of NPD transistors is 4, and the number of subsequent adapter pads connected to the second metal layer 210 is also 4; the mismatch module to be measured includes two pairs of NPD transistors with the same connection method, that is, the number of the second metal layers 210 in the mismatch module to be measured is 8, and the number of subsequent adapter pads connected to the second metal layer 210 is also 8.

[0098] Among them, the source ends of the NPD transistors in each pair of NPD transistors are commonly connected, and the source ends of the NPD transistors in each pair of NPD transistors and the NPD transistors in other pairs of NPD transistors are not commonly connected.

[0099] In this embodiment, each NPD transistor in the mismatched module to be tested further has at least one NPD transistor adjacent to its common gate terminal, which can realize the common connection of the gate terminals of several NPD transistors, reduce the number of test pads and the interconnection traces of the gate terminals, thereby reducing the parasitic resistance value in the device to be tested, and further improving the accuracy of the test results.

[0100] In addition, in the circuit of the device to be tested in this embodiment, when it is working normally, the drain terminals of the PPU transistors whose drain terminals are electrically connected are electrically isolated from the drain terminals of the NPG transistors, and the drain terminals of the PPU transistors are electrically isolated from the drain terminals of the NPD transistors. Specifically, the first metal layer 207 on the drain terminal of the PPU transistor is disconnected from the first metal layer 207 on the drain terminal of the NPG transistor (as shown in the red frame in the figure) to achieve electrical isolation, and the first metal layer 207 on the drain terminal of the PPU transistor is disconnected from the first metal layer 207 on the drain terminal of the NPD (as shown in the red frame in the figure) to achieve electrical isolation, so as to avoid the increase of the voltage at the drain terminal affecting the test results during the test, and further improve the accuracy of the test results.

[0101] In other embodiments of the present invention, a second metal layer is respectively formed on the first metal layer on the drain region and on the first metal layer on the surface of the common source region, so as to respectively lead out the common source terminal, the drain terminal other than the common source terminal, and the gate terminal of the mismatched module to be tested.

[0102] In the above solution, since the source terminals on each pair of NPD transistors are commonly connected, that is, the number of the second metal layers on each pair of NPD transistors is 5, and the number of the subsequent adapter pads connected to the second metal layers is also 5; there are two pairs of NPD transistors with the same connection method in the mismatched module to be tested, that is, the number of the second metal layers in the mismatched module to be tested is 10, and the number of the subsequent adapter pads connected to the second metal layers is also 10.

[0103] In this embodiment, the second metal layer 210 is used to be electrically connected to the adapter pad to test the mismatch situation in the mismatched module to be tested, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0104] In other embodiments, the third metal layer or the fourth metal layer is used to be electrically connected to the adapter pad to test the mismatch situation in the mismatched module to be tested, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0105] Among them, the third metal layer is located on the second metal layer 210, and the fourth metal layer is located on the third metal layer.

[0106] In the above solution, by selecting the same type of NPD tubes as the mismatched modules to be tested in adjacent device unit groups, the mismatched characteristics of several NPD tubes can be tested simultaneously, increasing the number of NPD tubes tested and improving the efficiency of identifying the mismatched characteristics of NPD tubes. Moreover, each NPD tube has adjacent NPD tubes with and without a common source terminal connected to its source terminal, enabling the simultaneous testing of the mismatched characteristics of the source terminal of each NPD tube in two states: with and without a common connection, which can accurately reflect the process fluctuations of the device under test, thereby improving the accuracy of the test results.

[0107] In a specific embodiment, in combination with Figures 9 to 11 , taking Figures 9 to 11 as an example of the layout structure schematic diagram of the mismatched test structure, the formation method of the mismatched test structure will be described.

[0108] It should be noted that Figure 9 the device under test is an SRAM, and the mismatched test structure is used to perform mismatched tests on NPG tubes in adjacent device unit groups.

[0109] In some embodiments of the present invention, Figures 9 to 11 the layout of the mismatched test structure is the test layout of the device under test. The device under test further includes an actual layout (not shown in the figure). The semiconductor device layer in the layout of the mismatched test structure is the same as the semiconductor device layer in the actual layout, and there are differences between the metal layer on the layout of the mismatched test structure and the metal layer on the actual layout.

[0110] Please refer to Figures 9 to 11 , Figure 9 which is a top view schematic diagram of the mismatched test structure, Figure 10 and Figure 11 is Figure 9 the cross-sectional schematic diagram along CC1 in . The formation method of the mismatched test structure includes: providing a device under test, which includes a substrate 300 and a semiconductor device layer. An array containing several repeated device units is formed in the semiconductor device layer, and each device unit contains several MOS transistors; selecting the same type of NPG tubes from adjacent device unit groups as the mismatched modules to be tested. The adjacent device unit groups include several adjacent device units in the device under test. Each NPG tube in the mismatched module to be tested has an adjacent NPG tube with a contact hole 306 commonly connected to its source terminal when the device is operating normally and an adjacent NPG tube with a source terminal not commonly connected to a contact hole 306 when the device is operating normally; providing a transfer pad for connecting the mismatched module to be tested to a test system for mismatched testing.

[0111] In some embodiments of the present invention, Figure 10 shows the connection situation of the first metal layer and the second metal layer on the source terminal, Figure 11The connection situation of the first metal layer and the second metal layer on the gate terminal is shown.

[0112] In some embodiments of the present invention, the adjacent device unit groups are adjacent memory device units within a 4-bit region, and the to-be-tested mismatch module includes 4 NPG transistors.

[0113] Specifically, in combination with Figure 1 and Figure 2 , the 4 NPG transistors in the to-be-tested mismatch module are all second MOS transistors, or the 4 NPG transistors in the to-be-tested mismatch module are all fourth MOS transistors.

[0114] In some embodiments of the present invention, a first metal layer 307 is formed on the semiconductor device layer to respectively lead out the source terminal, drain terminal, and gate terminal of the NPG transistor in the to-be-tested mismatch module; a second metal layer 310 is formed on the first metal layer 307 to respectively lead out the common source terminals S1 / S2 of the to-be-tested mismatch module, the drain terminals D1-1 / D1-2 / D2-1 / D2-2 other than the common source terminals S1 / S2, and the gate terminal; the first metal layer 307 is formed on the contact hole 306 on the source terminal of the NPG transistor, the contact hole 306 on the drain terminal of the NPG transistor, and the gate terminal of the NPG transistor.

[0115] In some other embodiments of the present invention, the second metal layer 310 electrically connects the gate terminals of adjacent MOS transistors whose source terminals are commonly connected during normal operation of the device in the to-be-tested mismatch module to form common gate terminals G1 / G2.

[0116] In a specific embodiment, the 4 NPG transistors in the to-be-tested mismatch module are divided into two pairs of NPG transistors, and the connection manner of each pair of NPG transistors is the same. Taking one pair of NPG transistors as an example, the formation method of the to-be-tested mismatch module will be described below.

[0117] The method for forming the mismatched module to be measured includes: providing a substrate 300; performing ion implantation on the substrate 300 to form a well region 301 on the surface of the substrate 300; depositing two gate layers 304 on the well region 301; using the gate layers 304 as a mask to perform ion implantation on the well region 301 to form a common source region 303 between the two gate layers 304 and drain regions 302 on both sides of the two gate layers 304; forming a first dielectric layer 305 on the substrate 300; etching the first dielectric layer 305 until the surfaces of the drain regions 302, the common source region 303, and the two gate layers 304 are exposed to form a plurality of first trenches (not shown in the figure); filling the first trenches with a conductive material to form contact holes 306 on the surfaces of the drain regions 302, the common source region 303, and the two gate layers 304; respectively forming first metal layers 307 on the contact holes 306 on the surfaces of the drain regions 302, the common source region 303, and the two gate layers 304 so as to lead out the source end, drain ends D1-1 / D1-2 / D2-1 / D2-2, and gate end of the NPG transistors in the mismatched module to be measured; forming a second dielectric layer 308 on the substrate 300; etching the second dielectric layer 308 until the surface of the first metal layer 307 is exposed to form a plurality of second trenches (not shown in the figure); filling the second trenches with a conductive material to form connection holes 309 on the surface of the first metal layer 307; respectively forming second metal layers 310 on the connection holes 309 on the surfaces of the drain regions 302 and the common source region 303 so as to lead out the common source end S2 and drain ends D2-1 / D2-2 of the NPG transistors in the mismatched module to be measured; forming a second metal layer 310 on the first metal layer 307 on the surfaces of the two gate layers 304 so as to lead out the gate ends of the mismatched module to be measured simultaneously to form a common gate end G2.

[0118] Since the gate ends of each pair of NPG transistors are commonly connected and the source ends are commonly connected, that is, the number of the second metal layers 310 on each pair of NPG transistors is 4, and the number of subsequent adapter pads connected to the second metal layers 310 is also 4; the mismatched module to be measured includes two pairs of NPG transistors with the same connection method, that is, the number of the second metal layers 310 in the mismatched module to be measured is 8, and the number of subsequent adapter pads connected to the second metal layers 310 is also 8.

[0119] Among them, the source ends of the NPG transistors in each pair of NPG transistors are commonly connected, and the source ends of the NPG transistors in each pair of NPG transistors and the NPG transistors in other pairs of NPG transistors are not commonly connected.

[0120] In this embodiment, each NPG transistor in the mismatched module to be measured further has at least one NPG transistor adjacent to it with a common gate terminal, which can achieve the common connection of the gate terminals of several NPG transistors, reduce the number of test pads and the interconnection traces of the gate terminals, thereby reducing the parasitic resistance value in the device to be measured, and further improving the accuracy of the test results.

[0121] In addition, in the circuit of the device to be measured in this embodiment, when it is working normally, the drain terminals of the PPU transistors whose drain terminals are electrically connected are electrically isolated from the drain terminals of the NPG transistors, and the drain terminals of the PPU transistors are electrically isolated from the drain terminals of the NPD transistors. Specifically, the first metal layer 307 on the drain terminal of the PPU transistor is disconnected from the first metal layer 307 on the drain terminal of the NPG transistor (as shown in the red frame in the figure) to achieve electrical isolation, and the first metal layer 307 on the drain terminal of the PPU transistor is disconnected from the first metal layer 307 on the drain terminal of the NPD (as shown in the red frame in the figure) to achieve electrical isolation, avoiding the increase in the voltage at the drain terminal during the test from affecting the test results, and further improving the accuracy of the test results.

[0122] In other embodiments of the present invention, a second metal layer is formed on the first metal layer on the drain region and on the first metal layer on the surface of the common source region respectively, so as to lead out the common source terminal, the drain terminal other than the common source terminal, and the gate terminal of the mismatched module to be measured respectively.

[0123] In this embodiment, since the source terminals on each pair of NPG transistors are commonly connected, that is, the number of the second metal layers on each pair of NPG transistors is 5, and the number of the subsequent adapter pads connected to the second metal layers is also 5; there are two pairs of NPG transistors with the same connection method in the mismatched module to be measured, that is, the number of the second metal layers in the mismatched module to be measured is 10, and the number of the subsequent adapter pads connected to the second metal layers is also 10.

[0124] In the above solution, the second metal layer is electrically connected to the adapter pad to test the mismatch situation in the mismatched module to be measured, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0125] In other embodiments, a third metal layer or a fourth metal layer is electrically connected to the adapter pad to test the mismatch situation in the mismatched module to be measured, which can reduce the metal wire resistance to an acceptable range and improve the measurement accuracy.

[0126] Among them, the third metal layer is located on the second metal layer 310, and the fourth metal layer is located on the third metal layer.

[0127] In the above solution, by selecting the same type of NPG transistors as the mismatched module to be tested in adjacent device unit groups, the mismatch characteristics of several NPG transistors can be tested simultaneously, increasing the number of NPG transistors tested and improving the efficiency of identifying the mismatch characteristics of NPG transistors. Moreover, each NPG transistor has adjacent NPG transistors with and without a common source terminal connected to its source terminal, enabling the simultaneous testing of the mismatch characteristics of the source terminal of each NPG transistor in two states: with and without a common connection, which can accurately reflect the process fluctuations of the device under test, thereby improving the accuracy of the test results.

[0128] Correspondingly, the technical solution of the present invention also provides a mismatch test structure, including: a mismatched module to be tested, which is a part of the device under test. The device under test includes a substrate and a semiconductor device layer, and an array containing several repeated device units is formed in the semiconductor device layer. Each device unit contains several MOS transistors; the mismatched module to be tested is the same type of MOS transistors in adjacent device unit groups. The adjacent device unit groups include several adjacent device units in the device under test. Each MOS transistor in the mismatched module to be tested has an adjacent MOS transistor with its source terminal commonly connected during normal device operation and an adjacent MOS transistor with its source terminal not commonly connected to its source terminal during normal device operation; a transfer pad for connecting the mismatched module to be tested to a test system for mismatch testing.

[0129] Among them, the common connection of the source terminal is characterized in that the source terminals of several MOS transistors are connected to the same transfer pad, and subsequently, the same test voltage is applied to the source terminals of several MOS transistors. Specifically, the common connection of the source terminal is that the source terminals of several MOS transistors are commonly connected to a contact hole.

[0130] Among them, the non - common connection of the source terminal is characterized in that the source terminals of several MOS transistors are respectively connected to different transfer pads, and subsequently, different test voltages are respectively applied to the source terminals of several MOS transistors. Specifically, the non - common connection of the source terminal is that the source terminals of several MOS transistors are not commonly connected to a contact hole.

[0131] In some embodiments of the invention, the mismatch test structure further includes: a first metal layer located on the semiconductor device layer to respectively lead out the source terminal, drain terminals D1 - 1 / D1 - 2 / D2 - 1 / D2 - 2, and gate terminal of the MOS transistors in the mismatched module to be tested; the first metal layer electrically connects the source terminals of the transistors in the mismatched module that share a contact hole at the source terminal during normal device operation to form a common source terminal S1 / S2.

[0132] In some embodiments of the invention, the mismatch test structure further includes: a second metal layer located on the first metal layer, so as to respectively lead out the common source terminals S1 / S2 of the mismatch module to be tested, the drain terminals D1-1 / D1-2 / D2-1 / D2-2 other than the common source terminals S1 / S2, and the gate terminals; the second metal layer electrically connects the common source terminals S1 / S2, the gate terminals, and the drain terminals D1-1 / D1-2 / D2-1 / D2-2 of the mismatch module to be tested to the transfer pads respectively, so as to test the mismatch of each MOS transistor in the mismatch module to be tested in two states of source terminal common connection and non-common connection.

[0133] In some embodiments of the invention, the second metal layer electrically connects the gate terminals of adjacent MOS transistors whose source terminals are commonly connected during normal operation of the device in the mismatch module to be tested, to form common gate terminals G1 / G2; the second metal layer electrically connects the common source terminals S1 / S2, the common gate terminals G1 / G2, and the drain terminals D1-1 / D1-2 / D2-1 / D2-2 of the mismatch module to be tested to the transfer pads respectively, so as to test the mismatch of each MOS transistor in the mismatch module to be tested in two states of source terminal common connection and non-common connection.

[0134] In some embodiments of the invention, in the mismatch module to be tested, the drain terminals D1-1 / D1-2 / D2-1 / D2-2 between MOS transistors whose drain terminals D1-1 / D1-2 / D2-1 / D2-2 are electrically connected during normal operation are electrically isolated.

[0135] In some embodiments of the invention, the MOS transistors of the same type refer to MOS transistors with the same function in each device unit; the types of the MOS transistors include NPD transistors, NPG transistors or PPU transistors; the number of MOS transistors in the mismatch module to be tested is greater than or equal to 4; the number of transfer pads is greater than or equal to 8.

[0136] In some embodiments of the invention, the device to be tested is a SRAM or a CMOS image sensor.

[0137] Correspondingly, please refer to Figure 12 , the technical solution of the present invention further provides a mismatch test method, including: performing a mismatch test step on at least one adjacent device unit group, including:

[0138] S1: Select a first mismatch module to be tested from the first adjacent device unit group, where each MOS transistor in the first mismatch module to be tested has an adjacent MOS transistor whose source terminal is commonly connected to it during normal operation of the device and an adjacent MOS transistor whose source terminal is not commonly connected to it during normal operation of the device;

[0139] S2: Provide transfer pads, and connect the first mismatch module to be tested to a test system to perform a first mismatch test;

[0140] S3: Repeat the above steps until the mismatch test for each type of MOS transistor in the first adjacent device unit group is completed.

[0141] Among them, the first adjacent device unit is a part of the device under test, the device under test includes an array of several repeated device units, the first adjacent device unit group includes several adjacent device units in the device under test, and the first mismatch module to be tested is the same type of MOS transistor in the adjacent device units.

[0142] Among them, the source - common connection is characterized in that the sources of several MOS transistors are connected to the same transfer pad, and subsequently the same test voltage is applied to the sources of several MOS transistors. Specifically, the source - common connection means that the sources of several MOS transistors are commonly connected to a contact hole.

[0143] Among them, the non - source - common connection is characterized in that the sources of several MOS transistors are respectively connected to different transfer pads, and subsequently different test voltages are respectively applied to the sources of several MOS transistors. Specifically, the non - source - common connection means that the sources of several MOS transistors are not commonly connected to a contact hole.

[0144] In some embodiments of the present invention, the mismatch test method further includes: selecting a second mismatch module to be tested from the first adjacent device unit group, and each MOS transistor in the second mismatch module to be tested has an adjacent MOS transistor whose source is commonly connected to a contact hole during normal device operation and an adjacent MOS transistor whose source is not commonly connected to a contact hole during normal device operation.

[0145] In some other embodiments of the present invention, the mismatch test method further includes: selecting a third mismatch module to be tested from the first adjacent device unit group, and each MOS transistor in the third mismatch module to be tested has an adjacent MOS transistor whose source is commonly connected to a contact hole during normal device operation and an adjacent MOS transistor whose source is not commonly connected to a contact hole during normal device operation.

[0146] In the above solutions, the MOS transistors in the first mismatch module to be tested are PPU transistors, the MOS transistors in the second mismatch module to be tested are NPD transistors, and the MOS transistors in the third mismatch module to be tested are NPG transistors.

[0147] Please refer to Figure 3When performing a mismatch test on the PPU transistors in the first device under test for mismatch, apply a test voltage to the adapter pads connected to the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the PPU transistors, so as to obtain the electrical parameters of the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the PPU transistors; measure the mismatch conditions of each PPU transistor in the first device under test for mismatch in two states: with the source terminals commonly connected and not commonly connected.

[0148] Please refer to Figure 6 When performing a mismatch test on the NPD transistors in the second device under test for mismatch, apply a test voltage to the adapter pads connected to the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the NPD transistors, so as to obtain the electrical parameters of the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the NPD transistors; measure the mismatch conditions of each NPD transistor in the second device under test for mismatch in two states: with the source terminals commonly connected and not commonly connected.

[0149] Please refer to Figure 9 When performing a mismatch test on the NPG transistors in the third device under test for mismatch, apply a test voltage to the adapter pads connected to the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the NPG transistors, so as to obtain the electrical parameters of the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the common source terminals S1 / S2, and the common gate terminals G1 / G2 of the NPG transistors; measure the mismatch conditions of each NPG transistor in the third device under test for mismatch in two states: with the source terminals commonly connected and not commonly connected.

[0150] In the mismatch test method according to the embodiments of the present invention, through the adapter pads, the drain terminals D1-1 / D1-2 / D2-1 / D2-2, the gate terminals, and the commonly connected source terminals of the same type of MOS transistors in the adjacent device units are tested, so as to simultaneously test the electrical parameters of several MOS transistors, improve the efficiency of identifying the mismatch characteristics of the MOS transistors, and there are two states of the source terminals being commonly connected and not commonly connected in each MOS transistor, thereby improving the accuracy of the test results. Moreover, through the mismatch test of each type of MOS transistor in the first adjacent device unit group, the mismatch test of each device unit in the adjacent device unit group can be realized, further improving the accuracy of the test results.

[0151] In some embodiments of the present invention, the performing of the first mismatch test includes: obtaining the electrical parameters of each MOS transistor in the mismatch test structure in two states: with the source terminals commonly connected and not commonly connected.

[0152] In some embodiments of the present invention, the electrical parameters include one or more of the following: threshold voltage, saturation drain current, cut-off drain current, on-resistance, gate current, transconductance, source-drain conductance, voltage amplification factor.

[0153] In some embodiments of the present invention, the mismatch test structures obtained from the device under test at least once are several device units located at the center of the array of the device under test.

[0154] In some embodiments of the present invention, it further includes the step of performing mismatch tests on other adjacent device unit groups within the device under test.

[0155] In a specific embodiment, the mismatch test method further includes: selecting a first device module to be tested for mismatch from the second adjacent device unit group, where each MOS transistor in the first device module to be tested for mismatch has an adjacent MOS transistor whose source terminal is commonly connected to a contact hole during normal operation of the device and an adjacent MOS transistor whose source terminal is not commonly connected to a contact hole during normal operation of the device;

[0156] Selecting a first device module to be tested for mismatch from the third adjacent device unit group, where each MOS transistor in the first device module to be tested for mismatch has an adjacent MOS transistor whose source terminal is commonly connected to a contact hole during normal operation of the device and an adjacent MOS transistor whose source terminal is not commonly connected to a contact hole during normal operation of the device.

[0157] In the above solutions, the second adjacent device unit group and the third adjacent device unit group are other adjacent device unit groups located at the center of the array of the device under test.

[0158] Correspondingly, the technical solution of the present invention also provides a modeling method, including: performing modeling using the results obtained by the above-mentioned mismatch test method.

[0159] In some embodiments of the present invention, the modeling method includes: selecting a modeling model based on the type of MOS transistor in the device module to be tested for mismatch in the device under test; obtaining the mismatch conditions of each MOS transistor in the device module to be tested for mismatch in two states where the source terminals are commonly connected and not commonly connected; establishing a mismatch model based on the mismatch conditions and the modeling model; verifying the device under test based on the mismatch model to obtain a verification result; and optimizing the mismatch model based on the verification result.

[0160] In some embodiments of the present invention, the modeling model is a transistor model, and the mismatch model is a SPICE model.

[0161] In the above solution, a mismatch model is established according to the mismatch conditions of several MOS transistors, which increases the number of parameters for model establishment, thereby enhancing the fitting ability of the mismatch model to electrical parameters and improving the performance of the mismatch model. In addition, by obtaining the mismatch conditions of each MOS transistor in two states: with the source terminals commonly connected and not commonly connected, the accuracy and stability of the established mismatch model are improved.

[0162] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a mismatch test structure, characterized in that, Comprising: Providing a device under test, the device under test includes a substrate and a semiconductor device layer, an array including a number of repeated device units is formed in the semiconductor device layer, and each device unit contains a number of MOS transistors; Selecting the same type of MOS transistors from adjacent device unit groups as the mismatch module under test, the adjacent device unit groups include a number of adjacent device units in the device under test, and each MOS transistor in the mismatch module under test has an adjacent MOS transistor whose source terminal is commonly connected to its source terminal during normal device operation and an adjacent MOS transistor whose source terminal is not commonly connected to its source terminal during normal device operation; Providing a transfer pad for connecting the mismatch module under test to a test system for mismatch testing.

2. The method for forming the mismatch test structure according to claim 1, characterized in that, Further comprising: Forming a first metal layer on the semiconductor device layer to respectively lead out the source terminal, drain terminal, and gate terminal of the MOS transistors in the mismatch module under test; The first metal layer electrically connects the source terminals of the MOS transistors in the mismatch module under test that share a contact hole at the source terminal during normal device operation to form a common source terminal.

3. The method for forming the mismatch test structure according to claim 2, wherein, Further comprising: Forming a second metal layer on the first metal layer to respectively lead out the common source terminal, drain terminals other than the common source terminal, and gate terminals of the mismatch module under test; The second metal layer electrically connects the common source terminal, gate terminal, and drain terminal of the mismatch module under test to the transfer pad respectively to test the mismatch conditions of each MOS transistor in the mismatch module under test in two states where the source terminals are commonly connected and not commonly connected.

4. The method for forming the mismatch test structure according to claim 3, wherein, Further comprising: The second metal layer electrically connects the gate terminals of the adjacent MOS transistors in the mismatch module under test that share a common source terminal during normal device operation to form a common gate terminal; The second metal layer electrically connects the common source terminal, common gate terminal, and drain terminal of the mismatch module under test to the transfer pad respectively to test the mismatch conditions of each MOS transistor in the mismatch module under test in two states where the source terminals are commonly connected and not commonly connected.

5. The method for forming the mismatch test structure according to claim 1, wherein In the mismatch module under test, the drain terminals between the MOS transistors whose drain terminals are electrically connected during normal operation are electrically isolated.

6. The method for forming the mismatch test structure according to claim 1, characterized in that, The number of the transfer pads is greater than or equal to 8.

7. The method for forming the mismatch test structure according to claim 1, characterized in that, The number of the MOS transistors in the mismatch module under test is greater than or equal to 4.

8. The method for forming the mismatch test structure according to claim 1, wherein, The same type of MOS transistors refers to the MOS transistors with the same function in each device unit.

9. The method for forming the mismatch test structure according to claim 1, wherein, The types of the MOS transistors include NPD transistors, NPG transistors, or PPU transistors.

10. The method for forming the mismatch test structure according to claim 1, wherein, The device under test is a SRAM or a CMOS image sensor.

11. A mismatch test structure, characterized in that, Comprising: A mismatch module under test, which is a part of the device under test, the device under test includes a substrate and a semiconductor device layer, an array including a number of repeated device units is formed in the semiconductor device layer, and each device unit contains a number of MOS transistors; the mismatch module under test is the same type of MOS transistors in adjacent device unit groups, the adjacent device unit groups include a number of adjacent device units in the device under test, and each MOS transistor in the mismatch module under test has an adjacent MOS transistor whose source terminal is commonly connected to its source terminal during normal device operation and an adjacent MOS transistor whose source terminal is not commonly connected to its source terminal during normal device operation; A transfer pad for connecting a mismatched module under test to a test system for mismatch testing.

12. The mismatch test structure according to claim 11, wherein, Further comprising: A first metal layer located on the semiconductor device layer to respectively lead out the source, drain, and gate of the MOS transistors in the mismatched module under test; The first metal layer electrically connects the sources of the transistors in the mismatched module under test whose sources are commonly connected to a contact hole during normal device operation to form a common source terminal.

13. The mismatch test structure according to claim 12, wherein Further comprising: A second metal layer located on the first metal layer to respectively lead out the common source terminal, the drain terminals other than the common source terminal, and the gate terminals of the mismatched module under test; The second metal layer electrically connects the common source terminal, the gate terminal, and the drain terminal of the mismatched module under test to the transfer pad respectively to test the mismatch conditions of each MOS transistor in the mismatched module under test in two states of source common connection and non - common connection.

14. The mismatch test structure according to claim 13, wherein Further comprising: The second metal layer electrically connects the gate terminals of adjacent MOS transistors in the mismatched module under test whose sources are commonly connected during normal device operation to form a common gate terminal; The second metal layer electrically connects the common source terminal, the common gate terminal, and the drain terminal of the mismatched module under test to the transfer pad respectively to test the mismatch conditions of each MOS transistor in the mismatched module under test in two states of source common connection and non - common connection.

15. The mismatch test structure according to claim 11, characterized in that, Further comprising: In the mismatched module under test, the drain terminals between the MOS transistors whose drains are electrically connected during normal operation are electrically isolated.

16. A mismatch testing method, characterized in that, Comprising: A step of performing mismatch testing on at least one adjacent device unit group, including: Selecting a first mismatched module under test from a first adjacent device unit group, the first adjacent device unit being a part of the device under test, the device under test comprising an array of several repeated device units, the first adjacent device unit group comprising several adjacent device units within the device under test, the first mismatched module under test being the same type of MOS transistors in the adjacent device units, and each MOS transistor in the first mismatched module under test having an adjacent MOS transistor whose source is commonly connected to it during normal device operation and an adjacent MOS transistor whose source is not commonly connected to it during normal device operation; Providing a transfer pad to connect the first mismatched module under test to a test system for a first mismatch test; Repeating the above steps until the mismatch tests for each type of MOS transistor within the first adjacent device unit group are completed.

17. The mismatch test method according to claim 16, wherein, Performing the first mismatch test includes: obtaining the electrical parameters of each MOS transistor in the mismatch test structure in two states of source common connection and non - common connection.

18. The mismatch test method according to claim 17, wherein The electrical parameters include one or several of: threshold voltage, saturation drain current, cut - off drain current, on - resistance, gate current, transconductance, source - drain conductance, voltage amplification factor.

19. The mismatch test method according to claim 16, wherein, The mismatch test structure obtained at least once from the device under test is several device units located at the center of the array of the device under test.

20. The mismatch testing method according to claim 16, characterized in that Further comprising a step of performing mismatch testing on other adjacent device unit groups within the device under test.

21. A modeling method, characterized in that, Comprising: Modeling using the results obtained by the mismatch test method according to any one of claims 16 to 20.

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