Test circuit and device to be tested
By setting a test circuit design of delay circuit and solder pad on the cutting path of the substrate, the problem of high probe testing costs and data bus collision is solved, and low-cost and efficient electronic component testing is achieved.
Patent Information
- Application Number
- CN202410195412.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-03
- Filing Date
- 2024-02-22
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, the probe testing of electronic components is expensive and collisions are prone to occur on the data bus.
The test circuit design is adopted to set a delay circuit and a solder pad on the cutting path of the substrate. The electronic components are tested in sequence through delay trigger signals to avoid collision of the test results on the same solder pad.
It reduces the testing cost and effectively avoids the collision of test results on the same welding pad, improving the testing efficiency.
Smart Images
Figure CN120254558A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a test circuit for testing a plurality of electronic components, and a device under test including the test circuit. Background Art
[0002] Generally, electronic components such as chips can be tested before or after packaging. For example, probe testing is performed on electronic components before packaging. However, the cost of probe testing is relatively high, and when the number of electronic components to be tested simultaneously is high, the output of the device under test on the data bus is prone to collision. Summary of the Invention
[0003] The present invention provides a test circuit and a device under test, which can reduce the test cost and avoid the collision of the output of the device under test on the data bus.
[0004] The test circuit of the present invention is used to test a plurality of electronic components. The test circuit includes a first pad and a plurality of delay circuits. The first pad is disposed on a scribe line of a substrate. The first pad is configured to receive a trigger signal to trigger the electronic components to perform test operations in sequence. The electronic components are disposed on the substrate. The delay circuits are disposed on the scribe line of the substrate. The delay circuits are electrically connected to the first pad. The delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding electronic components. The electronic components perform test operations in sequence according to the delayed trigger signal to respectively output test results.
[0005] The device under test of the present invention includes a plurality of electronic components and a test circuit. The electronic components are disposed on a substrate. The test circuit includes a first pad and a plurality of delay circuits. The first pad is disposed on a scribe line of the substrate. The first pad is configured to receive a trigger signal to trigger the electronic components to perform test operations in sequence. The electronic components are disposed on the substrate. The delay circuits are disposed on the scribe line of the substrate. The delay circuits are electrically connected to the first pad. The delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding electronic components. The electronic components perform test operations in sequence according to the delayed trigger signal to respectively output test results.
[0006] In an embodiment of the present invention, the test circuit further includes a plurality of second pads. The second pads are disposed on the scribe line of the substrate and are electrically connected to the electronic components. The second pads are configured to receive a frequency signal, a power supply signal, and a test instruction, and output the frequency signal, the power supply signal, and the test instruction to the electronic components. The electronic components perform test operations according to the frequency signal, the power supply signal, and the test instruction.
[0007] In an embodiment of the present invention, each electronic component further includes a logic circuit, a built-in self-test circuit, and a data bus. The logic circuit is electrically connected to the second pad. The logic circuit is configured to receive and output a frequency signal and a test instruction. The built-in self-test circuit is electrically connected to the logic circuit. The built-in self-test circuit is configured to perform a test operation according to the frequency signal and the test instruction. The data bus is electrically connected to the built-in self-test circuit. The data bus is configured to output a test result.
[0008] In an embodiment of the present invention, each electronic component includes an input pad. The input pad is electrically connected to a corresponding delay circuit. The input pad is configured to receive and output a delayed trigger signal.
[0009] In an embodiment of the present invention, each electronic component further includes a storage circuit. The storage circuit is electrically connected to the input pad. The storage circuit is configured to receive the delayed trigger signal and store the delay count value of the electronic component.
[0010] In an embodiment of the present invention, the data bus is further electrically connected to the storage circuit. The data bus is configured to output a test result according to the delay count value.
[0011] In an embodiment of the present invention, the delay count values of the electronic components may be different.
[0012] In an embodiment of the present invention, the logic circuit is further electrically connected to the input pad. The logic circuit is configured to receive and output a delayed trigger signal. The built-in self-test circuit is further configured to perform a test operation according to the delayed trigger signal to output a test result.
[0013] In an embodiment of the present invention, each electronic component is a memory chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 is a schematic block diagram of a test system drawn according to an embodiment of the present invention;
[0015] Figure 2 is according to the present invention Figure 1 a schematic diagram of a device under test drawn according to an embodiment;
[0016] Figure 3 is according to the present invention Figure 1 a schematic layout diagram of a device under test drawn according to an embodiment;
[0017] Figure 4 is a schematic diagram of an electronic component drawn according to the present invention;
[0018] Figure 5 is according to the present invention Figure 4 a schematic diagram of signal waveforms of an electronic component in a first operating mode drawn according to an embodiment;
[0019] Figure 6 is a schematic diagram of signal waveforms of an electronic component in a second operation mode drawn according to an embodiment of the present invention Figure 4 ;
[0020] Figure 7 is a flowchart of steps of a test method according to an embodiment of the present invention
[0021] Figure 8 is a schematic diagram of a general view of an electronic component according to an embodiment of the present invention
[0022] Figure 9 is according to the present invention Figure 8 a schematic diagram of signal waveforms of an electronic component in a second operation mode according to an embodiment
[0023] Figure 10 is a flowchart of steps of a test method according to another embodiment of the present invention Detailed Description of the Invention
[0024] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts
[0025] Figure 1 is a schematic block diagram of a test system according to an embodiment of the present invention Figure 2 is Figure 1 a schematic diagram of a general view of a device under test according to an embodiment. Please refer to Figure 1 and Figure 2 , in this embodiment, the test system 100 includes a test device 110 and a device under test 120. The device under test 120 is electrically connected to the test device 110. The device under test 120 includes a test circuit 200 and a plurality of electronic components 300_1, 300_2, 300_3, 300_4. The test circuit 200 is used to test the electronic components 300_1, 300_2, 300_3, 300_4. The electronic components 300_1, 300_2, 300_3, 300_4 are disposed on a substrate (such as a silicon wafer) 400. The test device 110 performs a test operation on the electronic components 300_1, 300_2, 300_3, 300_4 through the test circuit 200
[0026] In an embodiment, each of the electronic components 300_1, 300_2, 300_3, 300_4 is, for example, a memory chip serving as a device under test (DUT). In an embodiment, the electronic component may also be a digital logic chip or an emulation circuit chip. The testing device 110 uses probes to perform wafer probing on the electronic components 300_1, 300_2, 300_3, 300_4 through the testing circuit 200. However, the present invention does not limit the types of testing operations, the types, and the number of electronic components.
[0027] Figure 3 Is Figure 1 Schematic diagram of the layout of the device under test in the embodiment. Please refer to Figure 2 And Figure 3 , the testing circuit 200 includes a first pad 210, a plurality of delay circuits 230_1, 230_2, 230_3, 230_4, and a plurality of second pads 220.
[0028] The first pad 210 is disposed on the scribe line 410 of the substrate 400. The first pad 210 is configured to receive a trigger signal S1 to trigger the electronic components 300_1, 300_2, 300_3, 300_4 to perform testing operations in sequence. The trigger signal S1 is, for example, from the testing device 110.
[0029] The delay circuits 230_1, 230_2, 230_3, 230_4 are disposed on the scribe line 410 of the substrate 400. The delay circuits 230_1, 230_2, 230_3, 230_4 are electrically connected to the first pad 210. The delay circuits 230_1, 230_2, 230_3, 230_4 are configured to delay the trigger signal S1 and output the delayed trigger signals S1_1, S1_2, S1_3, S1_4 to the corresponding electronic components 300_1, 300_2, 300_3, 300_4. For example, the delay circuit 230_1 delays the trigger signal S1 and outputs the delayed trigger signal S1_1 to the electronic component 300_1 and the delay circuit 230_2. The delay circuit 230_2 delays the trigger signal S1_1 and outputs the delayed trigger signal S1_2 to the electronic component 300_2 and the delay circuit 230_3, and so on. The electronic components 300_1, 300_2, 300_3, 300_4 receive the delayed trigger signals S1_1, S1_2, S1_3, S1_4 through their respective input pads 340. Then, the electronic components 300_1, 300_2, 300_3, 300_4 perform testing operations in sequence according to the delayed trigger signals S1_1, S1_2, S1_3, S1_4 to respectively output test results S2. In this embodiment, the test result S2 is, for example, fromFigure 2 Output from the same pad 420 shown.
[0030] The second pad 220 is disposed on the scribe line 410 of the substrate 400. The second pad 220 is electrically connected to the electronic components 300_1, 300_2, 300_3, 300_4. The second pad is configured to receive a frequency signal CLK, a power signal PWR, and a test command CMD, and output the frequency signal CLK, the power signal PWR, and the test command CMD to the electronic components 300_1, 300_2, 300_3, 300_4. The electronic components 300_1, 300_2, 300_3, 300_4 receive the delayed trigger signals S1_1, S1_2, S1_3, S1_4 through their respective logic circuits 310. Then, the electronic components perform test operations according to the frequency signal CLK, the power signal PWR, and the test command CMD. In an embodiment of the present invention, depending on the operating mode, the test command CMD may be a write command CMD1 ( Figure 5 ) or a read command CMD2 ( Figure 6 , Figure 8 ).
[0031] Figure 4 Schematic diagram showing an overview of the electronic components according to an embodiment of the present invention. Please refer to Figure 4 , the electronic component 300A of this embodiment includes a logic circuit 310, a built-in self-test circuit 320, a data bus 330, an input pad 340, and a storage circuit 350. The electronic component 300A further includes a comparator 360, a compression circuit 370, and a memory circuit 380. The memory circuit 380 is the circuit to be tested. The electronic component 300A is an embodiment of the electronic components 300_1, 300_2, 300_3, 300_4.
[0032] The logic circuit 310 is electrically connected to the second pad 220. The logic circuit 310 is configured to receive and output the frequency signal CLK and the test command CMD. The logic circuit 310 can, for example, perform a decoding operation on the test command CMD. The built-in self-test (BIST) circuit 320 is electrically connected to the logic circuit 310. The built-in self-test circuit 320 is configured to perform test operations according to the frequency signal CLK and the test command CMD. The data bus 330 is electrically connected to the built-in self-test circuit 320 through the memory circuit 380. The data bus 330 is configured to output a test result S2_A.
[0033] On the other hand, the input pad 340 is electrically connected to the corresponding delay circuits 230_1, 230_2, 230_3 or 230_4. The input pad 340 is configured to receive and output a delayed trigger signal S1_A. The storage circuit 350 is electrically connected to the input pad 340. The storage circuit 350 is configured to receive the delayed trigger signal S1_A and store the latency counter value of the electronic component 300A. The storage circuit 350 can be a buffer, a volatile memory circuit or a non-volatile memory circuit. The data bus 330 is also electrically connected to the storage circuit 350. The data bus 330 is configured to output a test result S2_A according to the latency counter value stored in the storage circuit 350.
[0034] In addition, the comparator 360 is used to compare the test pattern provided by the built-in self-test circuit 320 and the data output by the memory circuit 380, and present the comparison result in the form of a flag 390. For example, a digital value 1 represents a pass of the test, and a digital value 0 represents a fail of the test. Then, the compression circuit 370 compresses the flag 390 and outputs it to the data bus 330 as the test result S2_A.
[0035] The electronic component 300A of this embodiment can operate in a first operation mode or a second operation mode. In the first operation mode, the latency counter value of the electronic component 300A is written into the storage circuit 350. In the second operation mode, the test result S2_A is read out from the electronic component 300A.
[0036] In addition, in this embodiment, the logic circuit 310, the built-in self-test circuit 320, the data bus 330, the storage circuit 350, the comparator 360 and the compression circuit 370 can be implemented by suitable digital circuits or simulation circuits in the technical field respectively, and the present invention is not limited thereto.
[0037] Figure 5 Yes Figure 4 Schematic diagram of the signal waveform of the electronic component in the first operation mode of the embodiment. Please refer to Figures 3 to 5 , the frequency signal CLK and the write command CMD1 are input from the second pad 220. The frequency signal CLK includes operation timings T0, T1, T2, T3, T4, T5, T6. The write command CMD1 instructs the electronic components 300_1, 300_2, 300_3, 300_4 to write the latency counter value into their respective storage circuits 350.
[0038] The trigger signal S1 is input from the first pad 210 and transmitted to the delay circuit 230_1. The delay circuit 230_1 delays the trigger signal S1 and outputs the delayed trigger signal S1_1 to the electronic component 300_1 and the delay circuit 230_2. Therefore, compared with the trigger signal S1, the trigger signal S1_1 is delayed by one time period and is marked as 1T in Figure 5 . Then, the delay circuit 230_2 delays the trigger signal S1_1 and outputs the delayed trigger signal S1_2 to the electronic component 300_2 and the delay circuit 230_3. Therefore, compared with the trigger signal S1, the trigger signal S1_2 is delayed by two time periods and is marked as 2T in Figure 5 . By analogy, compared with the trigger signal S1, the trigger signals S1_3 and S1_4 are delayed by three time periods and four time periods respectively and are marked as 3T and 4T in Figure 5 .
[0039] On the other hand, the write command CMD1 includes information on the reference count value. In this embodiment, the reference count value is preset to 4T for example. The delay count values stored in the storage circuits 350 of the electronic components 300_1, 300_2, 300_3, and 300_4 are 5T (i.e., 1T + 4T), 6T (i.e., 2T + 4T), 7T (i.e., 3T + 4T), and 8T (i.e., 4T + 4T) respectively. That is to say, through the delay circuits 230_1, 230_2, 230_3, and 230_4, the trigger signal S1 input from the first pad 210 can be transmitted to the input pads 340 of the electronic components 300_1, 300_2, 300_3, and 300_4 with different time differences. And, in coordination with the setting of the reference count value of the write command CMD1, the delay count values stored in the storage circuits 350 of the electronic components 300_1, 300_2, 300_3, and 300_4 can be sequentially defined as 5T, 6T, 7T, and 8T. That is to say, the delay count values of the electronic components 300_1, 300_2, 300_3, and 300_4 are different. The delay count values stored in the respective storage circuits 350 represent the order in which the test results S2_1, S2_2, S2_3, and S2_4 are read out from the electronic components 300_1, 300_2, 300_3, and 300_4 when the electronic components operate in the second operation mode.
[0040] Figure 6 is Figure 4 a schematic diagram of the signal waveforms of the electronic components of the embodiment in the second operation mode. Please refer to Figure 3 , Figure 4 and Figure 6, a frequency signal CLK and a readout instruction CMD2 are input from the second pad 220. The frequency signal CLK includes operation timings T0, T1, T2, T3, T4, T5, T6, T7, T8, T9. The readout instruction CMD2 instructs the electronic components 300_1, 300_2, 300_3, 300_4 to output their respective test results S2_1, S2_2, S2_3, S2_4. In Figure 6 , H represents the high level of the signal, L represents the low level of the signal, LC represents the delay count value, PASS represents a successful test, and FAIL represents a failed test.
[0041] In this embodiment, the delay count values LC of the electronic components 300_1, 300_2, 300_3, 300_4 are 5T, 6T, 7T, 8T respectively. Therefore, the electronic components 300_1, 300_2, 300_3, 300_4 output the test results S2_1, S2_2, S2_3, S2_4 at timings T5, T6, T7, T8, T9 respectively. And, the test result S2 is output by, for example, Figure 2 the same pad 420 shown, but the present invention is not limited thereto. In this embodiment, since the delay count values have been written into the electronic components in the first operation mode, therefore, in the second operation mode, the test results can be sequentially read out from the electronic components to avoid collisions of the test results at the same pad.
[0042] Figure 7 is a flowchart of the steps of the test method according to an embodiment of the present invention. Please refer to Figures 2 to 6 , the test method of this embodiment is applicable to at least Figure 3 , Figure 4 the electronic components 300_1, 300_2, 300_3, 300_4, but the present invention is not limited thereto. In step S100, the test circuit 200 receives and delays the trigger signal S1, and outputs the delayed trigger signals S1_1, S1_2, S1_3, S1_4 to the corresponding electronic components 300_1, 300_2, 300_3, 300_4 to trigger the electronic components 300_1, 300_2, 300_3, 300_4 to perform test operations. In step S110, the electronic components 300_1, 300_2, 300_3, 300_4 execute the first operation mode to write the delay count values into their respective storage circuits 350. In step S120, the electronic components 300_1, 300_2, 300_3, 300_4 execute the second operation mode to sequentially output the test results S2_1, S2_2, S2_3, S2_4, and the test result S2 is output by, for example, Figure 2 the same pad 420 shown.
[0043] In addition, the test method of the embodiment of the present invention can be performed byFigures 1 to 6 Adequate teachings, suggestions, and implementation instructions can be obtained from the description of the embodiments.
[0044] Figure 8 It is a schematic diagram of the outline of an electronic component according to an embodiment of the present invention. Please refer to Figure 8 , the electronic component 300B is another implementation of the electronic components 300_1, 300_2, 300_3, and 300_4. The electronic component 300B in this embodiment is similar to Figure 4 the electronic component 300A in the embodiment, but the main difference between the two is, for example, that the electronic component 300B does not include the storage circuit 350, and the electronic component 300B does not need to execute the first operation mode to write the delay count value. In Figure 8 , the logic circuit 310 is also electrically connected to the input pad 340. The logic circuit 310 is configured to receive and output the delayed trigger signal S1_B. The built-in self-test circuit 320 is also configured to perform a test operation according to the delayed trigger signal S1_B to output a test result.
[0045] Figure 9 is Figure 8 a schematic diagram of the signal waveforms of the electronic component in the second operation mode according to an embodiment. Please refer to Figure 3 , Figure 8 and Figure 9 , the frequency signal CLK and the read command CMD2 are input from the second pad 220 to the corresponding electronic components 300_1, 300_2, 300_3, and 300_4. The delayed trigger signals S1_1, S1_2, S1_3, and S1_4 are input from their respective input pads 340 to the corresponding electronic components 300_1, 300_2, 300_3, and 300_4 to trigger the electronic components 300_1, 300_2, 300_3, and 300_4 to perform test operations.
[0046] In this embodiment, the delay count values LC of the electronic components 300_1, 300_2, 300_3, and 300_4 are set to be the same, for example, 4T. Therefore, the electronic components 300_1, 300_2, 300_3, and 300_4 output the test results S2_1, S2_2, S2_3, and S2_4 at time sequences T5, T6, T7, T8, and T9, respectively. And, the test result S2 is output, for example, by Figure 2 the same pad 420 shown, but the present invention is not limited thereto.
[0047] As for the trigger signals S1_1, S1_2, S1_3, S1_4, the trigger signals S1_1, S1_2, S1_3, S1_4 are generated by delay circuits 230_1, 230_2, 230_3, 230_4. Since the trigger signals S1_1, S1_2, S1_3, S1_4 arrive at their respective input pads 340 at different times, the trigger signals S1_1, S1_2, S1_3, S1_4 received by the electronic components 300_1, 300_2, 300_3, 300_4 differ by one time period. Then, the built-in self-test circuits 320 of the electronic components 300_1, 300_2, 300_3, 300_4 are triggered to perform the test operation in sequence at the timings T1, T2, T3, T4.
[0048] As for the test results S2_1, S2_2, S2_3, and S2_4, by setting the delay count values LC of the electronic components 300_1, 300_2, 300_3, and 300_4 to be the same, for example, all set to 4T, the data buses 330 of the electronic components 300_1, 300_2, 300_3, and 300_4 can output the test results in sequence at timings T5, T6, T7, and T8.
[0049] Therefore, in this embodiment, it is not necessary to pre-write the delay count value into the electronic components 300_1, 300_2, 300_3, 300_4, but the delay count value LC of each electronic component 300_1, 300_2, 300_3, 300_4 is set to be the same. Therefore, in the second operation mode, the test results can be read out from the electronic components in sequence to avoid collision of the test results on the same pad.
[0050] Figure 10 This is a flow chart of the test method steps of another embodiment of the present invention. Please refer to Figure 2 , Figure 3 , Figure 8 , Figure 9 and Figure 10 The test method of this embodiment is at least applicable to Figure 3 , Figure 8Electronic components 300_1, 300_2, 300_3, 300_4, but the present invention is not limited thereto. In step S200, the test circuit 200 receives and delays the trigger signal S1, and outputs the delayed trigger signals S1_1, S1_2, S1_3, S1_4 to the corresponding electronic components 300_1, 300_2, 300_3, 300_4 to trigger the electronic components 300_1, 300_2, 300_3, 300_4 to perform test operations. In step S210, the test device 110 sets the delay count values of the electronic components 300_1, 300_2, 300_3, 300_4 to fixed values. In step S220, the electronic components 300_1, 300_2, 300_3, 300_4 execute the second operation mode to sequentially output test results S2_1, S2_2, S2_3, S2_4, and the test result S2 is output, for example, by Figure 2 the same pad 420 shown.
[0051] In addition, the test method of the embodiments of the present invention can be obtained from Figures 1 to 3 and Figure 8 the description of the embodiments to obtain sufficient teachings, suggestions and implementation instructions.
[0052] In summary, in the embodiments of the present invention, the electronic components are tested by the test circuit provided on the scribe line of the substrate. The test circuit includes a delay circuit so that the electronic components output test results at different times. In this way, the test cost can be reduced, and the collision of test results on the same pad can be avoided.
[0053] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A test circuit for testing a plurality of electronic components, the test circuit comprising: A first pad disposed on a scribe line of a substrate and configured to receive a trigger signal to trigger the plurality of electronic components to sequentially perform test operations, wherein the plurality of electronic components are disposed on the substrate; And A plurality of delay circuits disposed on the scribe line of the substrate and electrically connected to the first pad, wherein the plurality of delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding plurality of electronic components, and the plurality of electronic components sequentially perform the test operations according to the delayed trigger signal to respectively output test results.
2. The test circuit according to claim 1, wherein the test circuit further comprises: A plurality of second pads disposed on the scribe line of the substrate and electrically connected to the plurality of electronic components, wherein the plurality of second pads are configured to receive a frequency signal, a power signal, and a test instruction and output the frequency signal, the power signal, and the test instruction to the plurality of electronic components, Wherein the plurality of electronic components perform the test operations according to the frequency signal, the power signal, and the test instruction.
3. The test circuit according to claim 2, wherein each of the plurality of electronic components further comprises: A logic circuit electrically connected to the plurality of second pads and configured to receive and output the frequency signal and the test instruction; A built-in self-test circuit electrically connected to the logic circuit and configured to perform the test operation according to the frequency signal and the test instruction; And A data bus electrically connected to the built-in self-test circuit and configured to output the test result.
4. The test circuit according to claim 3, wherein each of the plurality of electronic components comprises: An input pad electrically connected to the corresponding delay circuit and configured to receive and output the delayed trigger signal.
5. The test circuit according to claim 4, wherein each of the plurality of electronic components further comprises: A storage circuit electrically connected to the input pad and configured to receive the delayed trigger signal and store a delay count value of the electronic component.
6. The test circuit according to claim 5, wherein the data bus is further electrically connected to the storage circuit and configured to output the test result according to the delay count value.
7. The test circuit according to claim 5, wherein the plurality of delay count values of the plurality of electronic components are different.
8. The test circuit according to claim 4, wherein the logic circuit is further electrically connected to the input pad and configured to receive and output the delayed trigger signal, and the built-in self-test circuit is further configured to perform the test operation according to the delayed trigger signal to output the test result.
9. The test circuit according to claim 5, wherein the plurality of delay count values of the plurality of electronic components are the same.
10. The test circuit according to claim 1, wherein each of the plurality of electronic components is a memory chip.
11. A device under test, comprising: a plurality of electronic components disposed on a substrate; and a test circuit, comprising: a first pad disposed on a scribe line of the substrate and configured to receive a trigger signal to trigger the plurality of electronic components to perform test operations in sequence, wherein the plurality of electronic components are disposed on the substrate; and a plurality of delay circuits disposed on the scribe line of the substrate and electrically connected to the first pad, wherein the plurality of delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding plurality of electronic components, wherein the plurality of electronic components perform the test operations in sequence according to the delayed trigger signal to respectively output test results.
12. The device under test according to claim 11, wherein each of the plurality of electronic components is a memory chip.