Standard resistance test method of interface resistance calibration circuit

Abstract

The invention provides a standard resistance test method of an interface resistance calibration circuit, the interface resistance calibration circuit comprises a current mirror circuit, two outputs of the current mirror circuit are respectively output to a standard resistance to generate a reference voltage and output to an interface resistance circuit to generate a calibration voltage, a plurality of parallel resistance branches are arranged in the interface resistance circuit, each resistance branch is provided with a first control switch and an mos circuit, and the logic circuit generates a grid selection signal to control the interface resistance circuit to be connected to the resistance branches before starting resistance calibration so as to enable the resistance value of the interface resistance circuit to be maximum; and meanwhile, the comparator compares the reference voltage and the calibration voltage at the moment, and judges that the standard resistor is not connected to the current mirror circuit when the output result of the comparator is high. According to the invention, the comparator carries out comparison operation before the system starts resistor calibration, and judges whether the standard resistor is connected according to the comparison result, so that the circuit has the advantage of simple structure; and the electrostatic discharge risk is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of resistance calibration, and particularly relates to a standard resistance test method for an interface resistance calibration circuit. Background Art

[0002] An interface resistance calibration circuit is an electronic system used to dynamically adjust or compensate the resistance value in an interface circuit, aiming to solve the problem of resistance mismatch caused by environmental changes, device aging, or process deviations, thereby ensuring signal integrity, improving measurement accuracy, or optimizing system performance.

[0003] In the existing interface resistance calibration circuit, it generally includes a comparator, a reference voltage, and a calibration voltage of a resistance circuit. By comparing the reference voltage with the calibration voltage through the comparator, when the ratio between the reference voltage and the calibration voltage meets the set value, the comparator will jump, indicating the end of the comparison process. At this time, the resistance value in the resistance circuit is the calibrated resistance value required.

[0004] Before starting the resistance calibration of the interface resistance circuit, it is necessary to determine whether the externally connected standard resistance is connected to the current mirror circuit. In the existing technology, an ESD module (electrostatic discharge protection module) and a resistance access detection circuit are externally connected to the current mirror branch of the standard resistance. However, the connected resistance detection circuit will occupy the circuit area, resulting in a large circuit area overhead. At the same time, the externally connected resistance detection circuit has the risk of electrostatic discharge. Summary of the Invention

[0005] The present invention provides a standard resistance test method for an interface resistance calibration circuit. Before the system starts resistance calibration, a comparator performs a comparison operation, and based on the comparison result, it is determined whether the standard resistance is connected. It has the advantage of a simple circuit structure, and the circuit does not need to be provided with an ESD module, reducing the risk of electrostatic discharge.

[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] To achieve one or part or all of the above objects or other objects, a standard resistance test method for an interface resistance calibration circuit provided by a technical solution of the present invention. The interface resistance calibration circuit includes a current mirror circuit. Two outputs of the current mirror circuit are respectively output to a standard resistance to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage. A plurality of parallel resistance branches are provided in the interface resistance circuit. Each resistance branch is provided with a first control switch and a MOS circuit. A logic circuit generates a gate selection signal to control the interface resistance circuit to access the resistance branch before starting resistance calibration to make the resistance value of the interface resistance circuit the largest. At the same time, a comparator compares the reference voltage and the calibration voltage at this time, and when the output result of the comparator is high, it is determined that the standard resistance is not connected to the current mirror circuit.

[0008] The resistance selection signal is a binary signal corresponding to each of the MOS circuits. The resistance selection signal and the control signal generated by the internal circuit are sent to the logic circuit for logical selection, and a gate selection signal is generated. The generated gate selection signal controls the interface resistance circuit to connect the first resistance branch of the interface resistance circuit before the system starts resistance calibration, so that the resistance value of the interface resistance circuit is the largest.

[0009] The logic circuit includes an OR gate circuit and a plurality of AND gate circuits. The OR gate circuit is connected in parallel with the plurality of AND gate circuits. The resistance selection signal is input bit by bit into the logic circuit, and the lowest bit of the resistance selection signal is input into the OR gate circuit. The control signal includes a first control signal and a second control signal. The second control signal is input into the OR gate circuit and is set high until the standard resistance test is completed, controlling the first resistor corresponding to the lowest bit of the resistance selection signal to always remain connected to the interface resistance circuit. The first control signal is respectively input into the AND gate circuits and is set low until the standard resistance test is completed, controlling the remaining resistance branches except the first resistor to remain disconnected.

[0010] The first control switch is controlled by an enable signal. When the standard resistance starts to be tested, the enable signal is pulled high to control the first control switch to close.

[0011] The enable signal is delayed by a time T1 to be the first control signal. The first control signal is set high after the standard resistance test is completed. After the first control signal is set high, all the AND gate circuits connected in parallel in the logic circuit except the OR gate circuit are controlled by the resistance selection signal input externally. The second control signal is the inverted signal of the first control signal delayed by a time T2. After the second control signal is set low, the OR gate circuit in the logic circuit is controlled by the resistance selection signal input externally.

[0012] It further includes a system working signal, which is the inverted signal of the second control signal delayed by a time T3. When the standard resistance test ends, the system working signal is set high, and the system performs the interface resistance calibration operation.

[0013] The first control signal, the second control signal, and the system working signal are generated by the signal control circuit. The signal control circuit includes a plurality of delay circuits and an inverter circuit. The enable signal is input into the signal control circuit and is output as the first control signal after being delayed by the first delay circuit. The first control signal is output as the second control signal after being processed by the second delay circuit and the first inverter circuit. The second control signal is output as the system working signal after being processed by the third delay circuit and the second inverter circuit.

[0014] After the comparison result output by the comparator is saved, it is retrieved by the system. After the system working signal is set high, the system reads the comparison result of the comparator to determine whether the standard resistor is connected to the current mirror circuit.

[0015] The comparison result output by the comparator is input to the D input terminal of the D flip-flop. The clock signal input terminal of the D flip-flop inputs the first control signal. After the first control signal is pulled high, the comparison result is read and latched.

[0016] The first control switch is a transmission tube.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present invention does not require an external ESD module and an external resistor detection circuit, which can greatly reduce the risk of electrostatic discharge. 2. Through the control of the logic circuit and the control signal, the present invention can adjust the resistance value of the interface resistance circuit respectively in the resistor detection stage and the resistor calibration stage, and then use a comparator to compare the reference resistor and the calibration circuit, and judge whether the resistor is connected to the current mirror circuit according to the comparison result. This method not only does not affect the normal calibration process of the resistor, but also has a simple circuit structure, accurate testing, and reduces the problem of large circuit area overhead caused by using an external resistor test circuit and an ESD module in the prior art.

[0018] To make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. Brief Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic diagram of the interface resistor calibration circuit of the present invention.

[0021] Figure 2 It is a schematic diagram of the logic circuit and the timing control diagram of the present invention.

[0022] Figure 3 It is a schematic diagram of the signal control circuit of the present invention. Detailed Embodiments

[0023] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or rear, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0024] Embodiment 1 Embodiment 1 provides a standard resistance test method for an interface resistance calibration circuit. The interface resistance calibration circuit includes a current mirror circuit. Two outputs of the current mirror circuit are respectively output to a standard resistance to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage. A plurality of parallel resistance branches are arranged in the interface resistance circuit, and each resistance branch is provided with a first control switch and a MOS circuit. The logic circuit generates a gate selection signal to control the interface resistance circuit to access the resistance branch before starting resistance calibration so that the resistance value of the interface resistance circuit is the largest; at the same time, the comparator compares the reference voltage and the calibration voltage at this time, and when the output result of the comparator is high, it is determined that the standard resistance is not connected to the current mirror circuit.

[0025] In Embodiment 1, refer to Figure 1 , the principle of determining whether the standard resistance is connected to the current mirror circuit through the comparison result of the comparator is: if the standard resistance is not connected, the external resistance is equivalent to infinity at this time, Figure 1 there is no current in the left current mirror branch in , so the current in the right current mirror branch after being mirrored n times is close to 0. At this time, although the maximum resistance value is connected to the interface resistance circuit on the right, the calibration voltage generated by this circuit is still very small and close to 0. The calibration voltage is connected to the negative terminal of the comparator. If the calibration voltage is close to 0, the comparison result of the comparator should be high at this time, indicating that the external resistance is not connected. Similarly, when the standard resistance is connected, the current in the left current mirror branch is: cb_vref / rext, which is mirrored to the right circuit through the current mirror circuit. The interface resistance circuit on the right is set to the maximum resistance. At this time, the calibration voltage on the right is much larger than the reference voltage on the left. At this time, the output result of the comparator should be low. After the above comparison result is output, it can be saved. When the system starts resistance calibration, the system reads and judges whether the standard resistance is connected to determine whether to start the resistance calibration operation.

[0026] The method of the present invention will be explained in detail below with reference to the accompanying drawings.

[0027] Refer to Figure 1, the interface resistance calibration circuit includes a current mirror circuit. The two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage compA, and output to an interface resistance circuit to generate a calibration voltage compB. The calibration voltage compB is input to the negative terminal of a comparator, and the reference voltage compA is input to the positive terminal of the comparator. The comparator outputs a comparison result comp_out.

[0028] The current mirror circuit realizes current mirroring of two branches. The interface resistance circuit includes multiple parallel resistor branches, and each resistor branch is provided with a resistor (S3, S6, S12, S24, S48,), a first control switch k1, and a MOS transistor (P0, P1, P2, P3, P4). The first switch k1 is a transmission tube controlled by an enable signal en. When the standard resistor starts to be tested, the enable signal is pulled high to control the first control switch to close. The on-state of the MOS transistor directly determines the number of resistor branches connected to the MOS circuit. Each time a resistor branch is connected to the interface resistance circuit in sequence, the total resistance value of the interface resistance circuit will change.

[0029] When calibrating the resistance value of the interface resistance circuit, since one resistor branch is connected, the total resistance of the parallel circuit will decrease. Therefore, it is possible to traverse from high to low total resistance (connecting resistor branches in sequence) or from low to high total resistance (canceling the connected resistor branches in sequence) until the comparator toggles. Since the total resistance does not change regularly after each resistor is connected to the parallel resistor circuit, the resistance value of each resistor branch can be designed so that the total resistance value of the interface resistance circuit changes regularly each time a resistor branch is connected or a connected resistor branch is canceled during the resistance value traversal.

[0030] The traversal of the resistors is controlled by a resistor selection signal. The resistor selection signal is a binary signal corresponding to each of the MOS circuits, in order to Figure 1 take the interface resistance circuit in Figure 1 as an example. When the resistor selection signal is 00001, the low-order signal "1" at this time corresponds to the first resistor of the interface resistance circuit (i.e.,

[0031] the rightmost resistor in Figure 2 . Figure 2 The signal that is set to "1" will control the MOS transistor of the corresponding branch of the resistor to be fully turned on, and only the resistor of this branch is connected to the interface resistance circuit. At this time, the resistance value of the interface resistance circuit is the largest. In the prior art, the resistor selection signal is directly input to the gate of each MOS transistor of the interface resistance circuit to control the connection and disconnection of each resistor branch. Figure 1For the interface resistance circuit in [the context], during actual setup, it can be set according to the specific interface resistance circuit. The logic circuit set in the present invention includes an OR gate circuit and several AND gate circuits, which are connected in parallel between the OR gate circuit and the multiple AND gate circuits. The logic gate circuits in this logic circuit correspond one-to-one with the resistance branches in the interface resistance circuit, and the OR gate circuit corresponds to the first resistance branch in the interface resistance circuit. The resistance selection signal and the control signal generated by the internal circuit are sent into the logic circuit for logical selection, and the gate selection signal sw_inside<4:0> is generated. The resistance selection signal is sequentially input bit by bit into the logic circuit. The control signal generated by the internal circuit includes a first control signal en1 and a second control signal enn. The first control signal en1 is respectively input into the AND gate circuits, and the second control signal enn is input into the OR gate circuit. When starting the test for whether the standard resistance is connected, by pulling up the second control signal enn and pulling down the first control signal en1 simultaneously, at this time, due to the input of the set-high second control signal enn, the OR gate circuit always outputs high, controlling the MOS transistor of the first resistance branch of the interface resistance circuit to remain conducting, that is, ensuring that the first resistance branch always remains connected to the interface resistance circuit. And the set-low first control signal en1 is input into the AND gate circuits in the logic circuit. At this time, the AND gate circuits always output low. At this time, the remaining resistance branches of the interface resistance circuit except the first resistance branch remain disconnected. At this time, no matter whether the resistance selection signal changes or not, it will not affect the connection situation of the resistance branches. And ensuring that the first resistance branch is connected to the interface resistance circuit can ensure that the total resistance value of the interface resistance circuit is the largest. At this time, the comparator is used to compare the reference voltage and the calibration voltage to output a comparison result for characterizing the connection situation of the standard resistance.

[0032] When starting the resistance calibration, the connection situation of the resistance branches needs to be controlled by the resistance selection signal. At this time, pull up the first control signal en1 and pull down the second control signal enn. At this time, the output of the logic circuit will be selected and output according to the input situation of the resistance selection signal (that is, during resistance calibration, the connection of the resistance branches of the interface resistance circuit is controlled by the resistance selection signal). Through the control of this logic circuit and the control signal, the present invention can realize the test control for whether the standard resistance is connected and the control of resistance calibration without adding additional circuits.

[0033] Among them, the enable signal becomes the first control signal en1 after being delayed by a time T1. The first control signal en1 is inverted after being delayed by a time T2 to obtain the second control signal enn. The second control signal enn is inverted after being delayed by a time T3 to obtain the system working signal enok. The system working signal enok is set high after the standard resistance test is completed, and the control system performs the interface resistance calibration operation. At the same time, after the system working signal is set high, the subsequent circuit will read the comparison result comp_out output by the comparator when it receives this signal, and determine whether the standard resistance is connected to the current mirror circuit based on this comparison result, and then decide whether the system starts the resistance calibration work.

[0034] For the convenience of generating the above signals, refer to Figure 3 the signal control circuit in. The signal control circuit includes a plurality of delay circuits and inversion circuits. After the enable signal en is input into the signal control circuit, it outputs the first control signal en1 after being delayed by the first delay circuit for a time T1; the first control signal en1 is inverted by the first inversion circuit after being delayed by the second delay circuit for a time T2 to output the second control signal enn; the second control signal enn is processed by the second inversion circuit after being delayed by the third delay circuit for a time T3 to output the system working signal enok. Different control signals are generated according to the set time sequence through the signal control circuit, realizing the automatic operation of the system.

[0035] Refer to Figure 2 the timing diagram in. At time t0, the enable signal is input and the system starts to work. At the same time, the first control signal en1 is pulled low and the second control signal enn is pulled high. At this time, the first resistor is connected to the interface resistance circuit, and the comparator makes a comparison based on the connected resistor branch and outputs the comparison result. At time t1, the first control signal en1 is pulled high. At this time, the logic circuit controls the remaining resistor branches except the first resistor branch by the resistor selection signal sw<4:1>. At time t2, the second control signal enn is pulled low. At this time, the logic circuit controls the first resistor branch by the resistor selection signal sw<0>. At time t3, the system working signal enok is pulled high. At this time, the system starts the resistance calibration work, reads the result of the standard resistance test, and determines whether the standard resistance is connected and whether to start the resistance calibration work.

[0036] While the present invention realizes the detection of whether the standard resistance is connected to the interface resistance calibration circuit, it also avoids the use of an external ESD module and the use of an external resistance detection circuit, reducing the circuit cost and the risk of electrostatic discharge. Different from the prior art, in order to test whether the rext resistor is connected, an external resistance detection circuit needs to be set on one side of the rext resistor. In order to reduce the risk of electrostatic discharge, an external ESD module (anti-electrostatic discharge module) must be connected. However, this will not only increase the circuit cost, but also there is still a risk of electrostatic discharge.

[0037] In order to facilitate the saving of the comparison result comp_out output by the comparator during the standard resistor detection stage for subsequent circuits to read, the present invention uses a D flip-flop to save the output result of the comparator. Specifically, the comparison result comp_out output by the comparator is saved to the D input terminal of the D flip-flop. The clock signal input terminal of the D flip-flop inputs a first control signal en1, and the comparison result is read at the rising edge of the first control signal en1. After the first control signal en1 is pulled high, the test stage of the standard resistor ends at this time. The comparison result of the comparator read at this time is the comparison result output during the standard resistor detection stage. The D flip-flop latches the comparison result for subsequent circuits to read.

[0038] The above has introduced in detail a method for testing a standard resistor of an interface resistor calibration circuit provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A standard resistance testing method for an interface resistance calibration circuit, the interface resistance calibration circuit comprising a current mirror circuit, two outputs of the current mirror circuit being respectively output to a standard resistor to generate a reference voltage and output to an interface resistance circuit to generate a calibration voltage, characterized in that, A plurality of parallel-connected resistor branches are provided inside the interface resistance circuit. Each resistor branch is provided with a first control switch and a MOS circuit. The logic circuit generates a gate selection signal to control the interface resistance circuit to access the resistor branch before starting the resistance calibration so that the resistance value of the interface resistance circuit is the largest; At the same time, the comparator compares the reference voltage and the calibration voltage at this time, and when the output result of the comparator is high, it is determined that the standard resistor is not connected to the current mirror circuit.

2. The standard resistance test method for an interface resistance calibration circuit according to claim 1, wherein The resistor selection signal is a binary signal corresponding to each MOS circuit one by one. The resistor selection signal and the control signal generated by the internal circuit are sent to the logic circuit for logical selection and generate a gate selection signal; The generated gate selection signal controls the interface resistance circuit to connect the first resistor branch of the interface resistance circuit before the system starts the resistance calibration, so that the resistance value of the interface resistance circuit is the largest.

3. The standard resistance test method for an interface resistance calibration circuit according to claim 2, characterized in that The logic circuit includes an OR gate circuit and a plurality of AND gate circuits. The OR gate circuit is connected in parallel with the plurality of AND gate circuits. The resistor selection signal is input bit by bit into the logic circuit, and the lowest bit of the resistor selection signal is input into the OR gate circuit; The control signal includes a first control signal and a second control signal; The second control signal is input into the OR gate circuit and is kept high until the standard resistor test is completed, controlling the first resistor corresponding to the lowest bit of the resistor selection signal to always remain connected to the interface resistance circuit; The first control signal is respectively input into the AND gate circuits and is kept low until the standard resistor test is completed, controlling the remaining resistor branches except the first resistor to remain disconnected; 4. The standard resistance testing method for an interface resistance calibration circuit according to claim 3, characterized in that, The first control switch is controlled by an enable signal. When the standard resistor starts to be tested, the enable signal is pulled high to control the first control switch to close.

5. The standard resistance test method for an interface resistance calibration circuit according to claim 4, characterized in that, The enable signal is delayed by a time T1 to be the first control signal. The first control signal is pulled high after the standard resistor test is completed. After the first control signal is pulled high, all the parallel AND gate circuits in the logic circuit except the OR gate circuit are controlled by the externally input resistor selection signal; The second control signal is the inverted signal of the first control signal delayed by a time T2. After the second control signal is pulled low, the OR gate circuit in the logic circuit is controlled by the externally input resistor selection signal.

6. The standard resistance testing method of an interface resistance calibration circuit according to claim 5, characterized in that, It further includes a system working signal. The system working signal is the inverted signal of the second control signal delayed by a time T3. When the standard resistor test ends, the system working signal is pulled high, and the system performs the interface resistance calibration operation.

7. The standard resistor testing method for an interface resistor calibration circuit according to claim 6, characterized in that, The first control signal, the second control signal, and the system working signal are generated by the signal control circuit; The signal control circuit includes a plurality of delay circuits and an inverter circuit; The enable signal is input into the signal control circuit and is output as the first control signal after being delayed by the first delay circuit; The first control signal is processed by the second delay circuit and the first inverter circuit to output the second control signal; The second control signal is processed by the third delay circuit and the second inverter circuit to output the system working signal.

8. The standard resistance testing method for an interface resistance calibration circuit according to claim 3, characterized in that The comparison result output by the comparator is saved and then retrieved by the system. After the system working signal is set high, the system reads the comparison result of the comparator to determine whether the standard resistor is connected to the current mirror circuit.

9. The standard resistance test method for an interface resistance calibration circuit according to claim 8, characterized in that The comparison result output by the comparator is input to the D input terminal of the D flip-flop. The clock signal input terminal of the D flip-flop inputs a first control signal. After the first control signal is pulled high, the comparison result is read and latched.

10. The standard resistance testing method for an interface resistance calibration circuit according to claim 1, characterized in that The first control switch is a transmission tube.

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