A standard resistance test method for interface resistance calibration circuit

Abstract

The present invention provides a standard resistor testing method for an interface resistor calibration circuit. The interface resistor calibration circuit includes a current mirror circuit, wherein two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage and to an interface resistor circuit to generate a calibration voltage. A plurality of parallel resistor branches are provided in the interface resistor circuit, each resistor branch is provided with a first control switch and a MOS circuit, and a logic circuit generates a gate selection signal to control the interface resistor circuit to be connected to the resistor branch before starting resistance calibration so as to maximize the resistance value of the interface resistor circuit; simultaneously, a comparator compares the reference voltage and the calibration voltage at this time, and when the comparator output result is high, determines that the standard resistor is not connected to the current mirror circuit. The present invention uses the comparator to perform a comparison operation before the system starts resistance calibration, and determines whether the standard resistor is connected based on the comparison result. The circuit structure is simple and the risk of electrostatic discharge is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of resistance calibration, and in particular relates to a standard resistance testing method for an interface resistance calibration circuit. Background Art

[0002] An interface resistor calibration circuit is an electronic system used to dynamically adjust or compensate the resistance value in an interface circuit. It aims to address resistance mismatch problems caused by environmental changes, device aging, or process deviations, thereby ensuring signal integrity, improving measurement accuracy, or optimizing system performance.

[0003] The interface resistance calibration circuit in the prior art generally includes a comparator, a reference voltage, and a calibration voltage for the resistance circuit. The comparator compares the reference voltage with the calibration voltage. When the reference voltage and the calibration voltage meet the set ratio, the comparator jumps, indicating that the comparison process is completed. At this time, the resistance value in the resistance circuit is the required calibrated resistance value.

[0004] Before starting resistance calibration, the interface resistor circuit needs to determine whether the external standard resistor is connected to the current mirror circuit. In the existing technology, an ESD module (anti-electrostatic discharge module) and a resistor detection circuit are connected to the current mirror branch connected to the standard resistor. However, the connected resistor detection circuit occupies circuit area, resulting in a large circuit area overhead. At the same time, the external resistor detection circuit has the risk of electrostatic discharge. Summary of the Invention

[0005] The present invention provides a standard resistance testing method for an interface resistance calibration circuit. A comparator is used to perform a comparison operation before the system starts resistance calibration, and whether a standard resistor is connected is determined based on the comparison result. The method has the advantages of a simple circuit structure, and the circuit does not need to be provided with an ESD module, thereby reducing the risk of electrostatic discharge.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] In order to achieve one or part or all of the above-mentioned purposes or other purposes, a technical solution of the present invention provides a standard resistance testing method of an interface resistance calibration circuit, wherein the interface resistance calibration circuit includes a current mirror circuit, and the two outputs of the current mirror circuit are respectively output to the standard resistor to generate a reference voltage, and output to the interface resistance circuit to generate a calibration voltage. A plurality of parallel resistance branches are arranged in the interface resistance circuit, and each resistance branch is provided with a first control switch and a MOS circuit. The logic circuit generates a gate selection signal to control the interface resistance circuit to connect to the resistance branch before starting the resistance calibration so that the resistance value of the interface resistance circuit is maximized; at the same time, the comparator compares the reference voltage and the calibration voltage at this time, and when the comparator output result is high, it is determined that the standard resistor is not connected to the current mirror circuit.

[0008] The resistance selection signal is a binary signal corresponding to each of the MOS circuits. The resistance selection signal and the control signal generated by the internal circuit are sent to the logic circuit for logical selection and generate a gate selection signal; the generated gate selection signal controls the interface resistance circuit to connect the first resistance branch of the interface resistance circuit before the system starts resistance calibration, so as to maximize the resistance value of the interface resistance circuit.

[0009] The logic circuit includes an OR gate circuit and multiple AND gate circuits, the OR gate circuit is connected in parallel with the multiple AND gate circuits, the resistance selection signal is input into the logic circuit bit by bit, and the lowest bit of the resistance selection signal is input into the OR gate circuit; the control signal includes a first control signal and a second control signal; the second control signal is input into the OR gate circuit and is always set high before the standard resistance test is completed, controlling the first resistor corresponding to the lowest bit of the resistance selection signal to always remain connected to the interface resistance circuit state; the first control signal is respectively input into the AND gate circuit and is always set low before the standard resistance test is completed, controlling the remaining resistance branches except the first resistor to remain disconnected.

[0010] The first control switch is controlled by an enable signal. When the standard resistor test starts, the enable signal is pulled high to control the first control switch to be closed.

[0011] The enable signal becomes the first control signal after being delayed by T1 time. The first control signal is set high after the standard resistance test is completed. After the first control signal is set high, all the parallel AND gate circuits in the logic circuit except the OR gate circuit are controlled by the externally input resistance selection signal; the second control signal is the inverse signal of the first control signal after being delayed by T2 time. After the second control signal is set low, the OR gate circuit in the logic circuit is controlled by the externally input resistance selection signal.

[0012] It also includes a system working signal, which is a reverse signal of the second control signal after the delay T3 time. When the standard resistance test is completed, the system working signal is set high, and the system performs an interface resistance calibration operation.

[0013] The first control signal, the second control signal and the system working signal are generated by the signal control circuit; the signal control circuit includes multiple delay circuits and inverting circuits; the enable signal is input into the signal control circuit, and after being delayed by the first delay circuit, the first control signal is output; the first control signal is processed by the second delay circuit and the first inverting circuit, the second control signal is output; the second control signal is processed by the third delay circuit and the second inverting circuit, and the system working signal is output.

[0014] The comparison result output by the comparator is stored and retrieved by the system. After the system working signal is set high, the system reads the comparison result of the comparator to determine whether the standard resistor is connected to the current mirror circuit.

[0015] The comparison result output by the comparator is input into the D input terminal of the D flip-flop, and the clock signal input terminal of the D flip-flop is input into the first control signal. After the first control signal is pulled high, the comparison result is read and latched.

[0016] The first control switch is a transmission tube.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present invention does not require an external ESD module and an external resistance detection circuit, which can greatly reduce the risk of electrostatic discharge;

[0018] 2. The present invention can adjust the resistance of the interface resistor circuit in the resistance detection stage and the resistance calibration stage respectively through the control of the logic circuit and the control signal, and then use a comparator to compare the reference resistor and the calibration circuit, and judge whether the resistor is connected to the current mirror circuit based on the comparison result. This method not only does not affect the normal calibration process of the resistor, but also has a simple circuit structure and accurate testing, reducing the problem of large circuit area overhead caused by the use of external resistor test circuits and ESD modules in the prior art.

[0019] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the interface resistance calibration circuit of the present invention.

[0022] Figure 2 It is a schematic diagram of the logic circuit and timing control of the present invention.

[0023] Figure 3 Schematic diagram of the signal control circuit of the present invention. DETAILED DESCRIPTION

[0024] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0025] Example 1

[0026] Embodiment 1 provides a standard resistance testing method for an interface resistance calibration circuit, wherein the interface resistance calibration circuit includes a current mirror circuit, wherein two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage, and output to an interface resistance circuit to generate a calibration voltage. A plurality of parallel resistance branches are provided in the interface resistance circuit, and each resistance branch is provided with a first control switch and a MOS circuit. A logic circuit generates a gate selection signal to control the interface resistance circuit to be connected to the resistance branch before starting resistance calibration so that the resistance value of the interface resistance circuit is maximized; at the same time, a comparator compares the reference voltage and the calibration voltage at this time, and when the comparator output result is high, it is determined that the standard resistor is not connected to the current mirror circuit.

[0027] In Example 1, see Figure 1 The principle of judging whether the standard resistor is connected to the current mirror circuit through the comparison result of the comparator is: if the standard resistor is not connected, the external resistance is equivalent to infinity. Figure 1 The left current mirror branch has no current, so after being mirrored n times, the current in the right current mirror branch is close to 0. At this time, although the interface resistor circuit on the right is connected to the maximum resistance value, the calibration voltage generated by this circuit is still very small and close to 0. The calibration voltage is connected to the negative terminal of the comparator. If the calibration voltage is close to 0, the comparison result of the comparator should be high, indicating that the external resistor is not connected. Similarly, when the standard resistor is connected, the current in the left current mirror branch is: cb_vref / rext, which is mirrored to the right circuit through the current mirror circuit. The interface resistor circuit on the right is set to the maximum resistance. At this time, the calibration voltage on the right is much greater than the reference voltage on the left. At this time, the output result of the comparator should be low. The above comparison result can be saved after output. When the system starts resistance calibration, it reads and determines whether the standard resistor is connected to decide whether to start the resistance calibration operation.

[0028] The method of the present invention is explained in detail below with reference to the accompanying drawings.

[0029] See also Figure 1The interface resistor calibration circuit includes a current mirror circuit. The two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage compA, and output to an interface resistor circuit to generate a calibration voltage compB. The calibration voltage compB is input to the negative terminal of the comparator, and the reference voltage compA is input to the positive terminal of the comparator. The comparator outputs a comparison result comp_out.

[0030] The current mirror circuit mirrors the currents of two branches. The interface resistor circuit includes multiple parallel resistor branches, each equipped with a resistor (S3, S6, S12, S24, S48), a first control switch K1, and a MOSFET (P0, P1, P2, P3, P4). The first switch K1 is a transmission transistor controlled by an enable signal, En. When the standard resistor test begins, the enable signal is pulled high to close the first control switch. The conduction state of the MOSFET directly determines the number of resistor branches connected to the MOSFET circuit. Each resistor branch connected to the interface resistor circuit changes the total resistance of the interface resistor circuit.

[0031] When calibrating the resistance value of the interface resistor circuit, since the total resistance of the parallel circuit decreases with each resistor branch connected, the total resistance can be traversed from high to low (connecting resistor branches sequentially) or from low to high (sequentially removing connected resistor branches) until the comparator trips. Since the total resistance of the parallel resistor circuit does not change regularly after each resistor is connected, the resistance value of each resistor branch can be designed so that the total resistance of the interface resistor circuit changes regularly after each resistor branch is connected or removed during resistance value traversal.

[0032] The traversal of the resistor is controlled by the resistor selection signal, which is a binary signal corresponding to each of the MOS circuits. Figure 1 Take the interface resistor circuit in the figure as an example, when the resistor selection signal is 00001, the low-order signal "1" corresponds to the first resistor of the interface resistor circuit (i.e. Figure 1 The rightmost resistor in the interface resistor circuit is shown in Figure 1. A signal set to "1" fully turns on the MOSFET in the branch corresponding to that resistor, connecting only that branch resistor to the interface resistor circuit. At this point, the interface resistor circuit has its maximum resistance. In the prior art, the resistor selection signal is directly input to the gate of each MOSFET in the interface resistor circuit to control the connection and disconnection of each resistor branch.

[0033] In order to facilitate the present invention to test whether the standard resistor is connected, the present invention also provides a logic circuit, specifically, see Figure 2 , Figure 2 The logic circuit in Figure 1The interface resistor circuit in the interface resistor circuit can be set according to the specific interface resistor circuit during actual setting. The logic circuit set in the present invention includes an OR gate circuit and several AND gate circuits, and the OR gate circuit and multiple AND gate circuits are set in parallel. The logic gate circuit in the logic circuit corresponds one-to-one to the resistor branch in the interface resistor circuit, and the OR gate circuit corresponds to the first resistor branch in the interface resistor circuit. The resistor selection signal and the control signal generated by the internal circuit are sent to the logic circuit for logical selection, and a gate selection signal sw_inside<4:0> is generated. The resistor selection signal is input into the logic circuit bit by bit in sequence, and the control signal generated by the internal circuit includes a first control signal en1 and a second control signal enn. The first control signal en1 is input into the AND gate circuit, and the second control signal enn is input into the OR gate circuit. When the system begins testing whether a standard resistor is connected, it pulls the second control signal enn high while simultaneously pulling the first control signal en1 low. Due to the input of the high second control signal enn, the OR gate circuit always outputs a high value, controlling the MOSFET of the first resistor branch of the interface resistor circuit to remain on, thus ensuring that the first resistor branch remains connected to the interface resistor circuit. The low first control signal en1 is then input into the AND gate circuit within the logic circuit, causing the AND gate circuit to always output a low value. At this point, the remaining resistor branches of the interface resistor circuit, except for the first resistor branch, remain disconnected. Changes to the resistor selection signal will not affect the connection of the resistor branches. Ensuring that the first resistor branch is connected to the interface resistor circuit ensures that the total resistance of the interface resistor circuit is maximized. A comparator then compares the reference voltage with the calibration voltage to output a comparison result that characterizes the connection of the standard resistor.

[0034] When resistance calibration begins, the connection of the resistance branch is controlled by a resistance selection signal. At this time, the first control signal en1 is pulled high, and the second control signal enn is pulled low. The output of the logic circuit is then selected based on the input of the resistance selection signal (that is, during resistance calibration, the connection of the resistance branch of the interface resistance circuit is controlled by the resistance selection signal). The present invention, through the control of this logic circuit and control signals, can achieve control of whether standard resistors are connected and control of resistance calibration without adding additional circuitry.

[0035] The enable signal, after a delay of T1, becomes the first control signal en1. The first control signal en1 is then inverted after a delay of T2 to become the second control signal enn. The second control signal enn is then inverted after a delay of T3 to become the system operating signal enok. After the standard resistor test is complete, the system operating signal enok goes high, and the control system performs interface resistor calibration. When the system operating signal goes high, subsequent circuits receiving this signal read the comparison result comp_out output by the comparator. Based on this comparison result, they determine whether the standard resistor is connected to the current mirror circuit, and thus decide whether the system should initiate resistance calibration.

[0036] To facilitate the generation of the above signals, see Figure 3 The signal control circuit includes multiple delay circuits and an inverting circuit. After the enable signal en enters the signal control circuit, it is delayed by a first delay circuit for a time period of T1 before outputting a first control signal en1. The first control signal en1 is delayed by a second delay circuit for a time period of T2 before being inverted by a first inverting circuit and outputting a second control signal enn. The second control signal enn is delayed by a third delay circuit for a time period of T3 before being processed by a second inverting circuit and outputting a system operating signal enok. The signal control circuit generates different control signals according to a set timing sequence, enabling automatic system operation.

[0037] See also Figure 2 In the timing diagram, at time t0, the enable signal is input and the system starts working. At the same time, the first control signal en1 is pulled low and the second control signal enn is pulled high. At this time, the interface resistor circuit is connected to the first resistor. The comparator compares based on the connected resistor branch and outputs the comparison result. At time t1, the first control signal en1 is pulled high. At this time, the control right of the logic circuit over the remaining resistor branches except the first resistor branch is controlled by the resistor selection signal sw<4:1>. At time t2, the second control signal enn is pulled low. At this time, the control right of the logic circuit over the first resistor branch is controlled by the resistor selection signal sw <0> At t3, the system working signal enok is pulled high, and the system starts resistance calibration, reads the results of the standard resistor test, and determines whether the standard resistor is connected and whether to start resistance calibration.

[0038] While the present invention detects whether the interface resistor calibration circuit is connected to a standard resistor, it also avoids the use of an external ESD module and an external resistance detection circuit, reducing circuit overhead and lowering the risk of electrostatic discharge. Unlike the prior art, which requires an external resistance detection circuit on the rext resistor side to test whether the rext resistor is connected, and requires an external ESD module (anti-electrostatic discharge module) to reduce the risk of electrostatic discharge, this not only increases circuit overhead but also still poses the risk of electrostatic discharge.

[0039] In order to conveniently save the comparison result comp_out output by the comparator in the standard resistance detection stage so as to facilitate reading by the subsequent circuit, the present invention adopts a D flip-flop to save the output result of the comparator. Specifically, the comparison result comp_out output by the comparator is saved to the D input end of the D flip-flop, the clock signal input end of the D flip-flop inputs the first control signal en1, and the comparison result is read at the rising edge of the first control signal en1. After the first control signal en1 is pulled high, the test stage of the standard resistance ends. At this time, the comparison result of the comparator read is the comparison result output in the standard resistance detection stage. The D flip-flop latches the comparison result to facilitate reading by the subsequent circuit.

[0040] The above describes in detail the standard resistance test method for an interface resistance calibration circuit provided by the present invention. Specific examples are used herein to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A method for testing a standard resistance of an interface resistance calibration circuit, wherein the interface resistance calibration circuit includes a current mirror circuit, wherein two outputs of the current mirror circuit are respectively output to a standard resistor to generate a reference voltage and to an interface resistance circuit to generate a calibration voltage, wherein: The interface resistance circuit is provided with multiple parallel resistance branches, each resistance branch is provided with a first control switch and a MOS circuit; When the standard resistor begins to be tested, the first control switch is closed, and the conduction state of the MOS circuit determines the number of resistance branches connected to the interface resistance calibration circuit; The logic circuit generates a gate selection signal to control the interface resistance circuit to be connected to the resistance branch before starting the resistance calibration so as to maximize the resistance value of the interface resistance circuit; At the same time, the comparator compares the reference voltage and the calibration voltage at this time, and when the comparator output result is high, it is determined that the standard resistor is not connected to the current mirror circuit.

2. The standard resistance testing method of an interface resistance calibration circuit according to claim 1, characterized in that: The resistor selection signal is a binary signal corresponding to each of the MOS circuits. The resistor selection signal and the control signal generated by the internal circuit are sent to the logic circuit for logic selection and generate a gate selection signal. The generated gate selection signal controls the interface resistance circuit to connect the first resistance branch of the interface resistance circuit before the system starts resistance calibration, so as to maximize the resistance value of the interface resistance circuit.

3. The standard resistance testing method of an interface resistance calibration circuit according to claim 2, characterized in that: The logic circuit includes an OR gate circuit and multiple AND gate circuits, the OR gate circuit is connected in parallel with the multiple AND gate circuits, the resistance selection signal is input into the logic circuit bit by bit, and the lowest bit of the resistance selection signal is input into the OR gate circuit; The control signal includes a first control signal and a second control signal; The second control signal is input to the OR gate circuit and is kept high until the standard resistance test is completed, so as to control the first resistor corresponding to the lowest bit of the resistance selection signal to always remain connected to the interface resistance circuit; The first control signals are respectively input into the AND gate circuits and are kept low until the standard resistance test is completed, so as to control the remaining resistance branches except the first resistor to remain in a disconnected state.

4. The standard resistance testing method of an interface resistance calibration circuit according to claim 3, characterized in that: The first control switch is controlled by an enable signal. When the standard resistor test starts, the enable signal is pulled high to control the first control switch to be closed.

5. The standard resistance testing method of an interface resistance calibration circuit according to claim 4, characterized in that: The enable signal becomes the first control signal after a delay of T1. The first control signal is set high after the standard resistance test is completed. After the first control signal is set high, all the parallel AND gate circuits in the logic circuit except the OR gate circuit are controlled by the externally input resistance selection signal. The second control signal is an inverted signal of the first control signal after being delayed by T2 time. After the second control signal is set low, the OR gate circuit in the logic circuit is controlled by the externally input resistance selection signal.

6. The standard resistance testing method of an interface resistance calibration circuit according to claim 5, characterized in that: It also includes a system working signal, which is a reverse signal of the second control signal after the delay T3 time. When the standard resistance test is completed, the system working signal is set high, and the system performs an interface resistance calibration operation.

7. The standard resistance testing method of an interface resistance calibration circuit according to claim 6, characterized in that: The first control signal, the second control signal and the system working signal are generated by a signal control circuit; The signal control circuit includes a plurality of delay circuits and an inverting circuit; The enable signal is input into the signal control circuit, and is delayed by the first delay circuit to output a first control signal; The first control signal is processed by the second delay circuit and the first inverting circuit to output a second control signal; The second control signal is processed by the third delay circuit and the second inverting circuit and then output as a system working signal.

8. The standard resistance testing method of an interface resistance calibration circuit according to claim 6, characterized in that: The comparison result output by the comparator is stored and retrieved by the system. After the system working signal is set high, the system reads the comparison result of the comparator to determine whether the standard resistor is connected to the current mirror circuit.

9. The standard resistance testing method of an interface resistance calibration circuit according to claim 8, characterized in that: The comparison result output by the comparator is input into the D input terminal of the D flip-flop, and the clock signal input terminal of the D flip-flop is input into the first control signal. After the first control signal is pulled high, the comparison result is read and latched.

10. The standard resistance testing method of an interface resistance calibration circuit according to claim 1, characterized in that: The first control switch is a transmission tube.

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