Array substrate, preparation method thereof and electronic paper display panel

Abstract

The invention discloses an array substrate and a preparation method thereof, and an electronic paper display panel, and relates to the technical field of display, the array substrate is used in the electronic paper display panel, a storage capacitor is formed between a common electrode block and a pixel electrode block, each pixel unit area is internally provided with the common electrode block and the pixel electrode block, and the common electrode block and the pixel electrode block form a storage capacitor. A first substrate channel and a second substrate channel are arranged on the substrate in each pixel unit region; the pixel main body part is connected with the pixel extension part, and the pixel extension part is at least partially located in the first substrate channel; the common electrode main body part is connected with the common electrode extension part, and the common electrode extension part is at least partially located in the second substrate channel; the projection between the pixel main body part and the common electrode main body part is overlapped to form a main storage capacitor, and the projection between the pixel extension part and the common electrode extension part is overlapped to form an auxiliary storage capacitor. Through the design, the color cast problem of the electronic paper display panel is avoided, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and an electronic paper display panel. Background Art

[0002] With the continuous development of technology, the frequency of replacement of electronic digital products is getting higher and higher, and various new products are continuously developed. The electronic paper display panel is a new type of display device, mainly used in devices such as electronic tags, billboards, and e-readers. The display effect of the electronic paper display panel is close to that of natural paper, which can reduce visual fatigue during reading.

[0003] When the storage capacitor in the array substrate is small, it will cause the electrophoresis particles to fail to move to the target position, resulting in abnormal display of the electronic paper display panel. Summary of the Invention

[0004] The purpose of the present application is to provide an array substrate, a preparation method thereof, and an electronic paper display panel, to avoid color deviation problems in the electronic paper display panel and improve the display effect of the display panel.

[0005] The present application discloses an array substrate, which is used in an electronic paper display panel. The array substrate further includes a substrate, a common electrode block, and a pixel electrode block. The common electrode block and the pixel electrode block are both disposed on the substrate. A storage capacitor is formed between the common electrode block and the pixel electrode block. The array substrate includes a pixel unit area, and the common electrode block and the pixel electrode block are both disposed in each pixel unit area; The array substrate further includes a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are both disposed on the substrate of each pixel unit area; The pixel electrode block includes a pixel main body portion and a pixel extension portion. The pixel main body portion is connected to the pixel extension portion, and at least part of the pixel extension portion is located in the first substrate channel; The common electrode block includes a common electrode main body portion and a common electrode extension portion. The common electrode main body portion is connected to the common electrode extension portion, and at least part of the common electrode extension portion is located in the second substrate channel; The pixel main body portion and the common electrode main body portion overlap in projection to form a main storage capacitor, and the pixel extension portion and the common electrode extension portion overlap in projection to form a sub-storage capacitor.

[0006] Optionally, the array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode layer, which are sequentially stacked on the substrate; the array substrate further includes a first insulating channel and a second insulating channel, and each pixel unit region is provided with the first insulating channel and the second insulating channel; the first insulating channel and the second insulating channel both penetrate through the first insulating layer and the second insulating layer; The pixel extension includes a first pixel extension and a second pixel extension. The first pixel extension is located in the first substrate channel, the second pixel extension is located in the first insulating channel, and the second pixel extension is connected to the first pixel extension and the pixel main body. The common electrode extension includes a first common electrode extension and a second common electrode extension. The first common electrode extension is located in the second substrate channel, the second common electrode extension is located in the second insulating channel, and the second common electrode extension is connected to the first common electrode extension and the common electrode main body.

[0007] Optionally, the distance between the first common electrode extension and the first pixel extension is greater than the distance between the second common electrode extension and the second pixel extension.

[0008] Optionally, an insulating isolation wall is provided between the first substrate channel and the second substrate channel. The material of the insulating isolation wall is the same as the materials of the first insulating layer and the second insulating layer, and the distance between the first common electrode extension and the first pixel extension is equal to the distance between the second common electrode extension and the second pixel extension.

[0009] Optionally, the pixel main body is only located in the pixel electrode layer, and the common electrode main body is located in the first metal layer or the second metal layer.

[0010] Optionally, the pixel main body further includes a first sub-main body and a second sub-main body. The first sub-main body is connected to the second sub-main body, and the first sub-main body is located in the pixel electrode layer; The second sub-main body is located in the second metal layer, and the common electrode main body is located in the first metal layer; or the second sub-main body is located in the first metal layer, and the common electrode main body is located in the second metal layer; The first sub-main body and the common electrode main body overlap in the orthographic projection, the second sub-main body and the common electrode main body overlap in the orthographic projection, and the pixel extension is connected to the first sub-main body.

[0011] The present application also discloses a method for manufacturing an array substrate for manufacturing the array substrate. The steps of the method for manufacturing the array substrate include: Forming a first substrate channel and a second substrate channel on the substrate; Forming a common electrode block and a pixel electrode block on the substrate; Wherein, the pixel electrode block includes a pixel main body portion and a pixel extension portion. The pixel main body portion is connected to the pixel extension portion, and the pixel extension portion is at least partially located in the first substrate channel; the common electrode block includes a common electrode main body portion and a common electrode extension portion. The common electrode main body portion is connected to the common electrode extension portion, and the common electrode extension portion is at least partially located in the second substrate channel; a main storage capacitor is formed by projection overlap between the pixel main body portion and the common electrode main body portion, and a sub-storage capacitor is formed by projection overlap between the pixel extension portion and the common electrode extension portion.

[0012] Optionally, the step of forming the common electrode block and the pixel electrode block on the substrate includes: Forming a first metal layer on the substrate, filling a conductive material in the first substrate channel to form a first pixel extension portion, filling a conductive material in the second substrate channel to form a first common electrode extension portion, and forming a common electrode main body portion; Forming a first insulating layer on the first metal layer; Forming a second metal layer on the first insulating layer; Forming a second insulating layer on the second metal layer, and providing a first insulating channel and a second insulating channel on the second insulating layer and the first insulating layer. Filling a conductive material in the first insulating channel to form a second pixel extension portion, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main body portion; filling a conductive material in the second insulating channel to form a second common electrode extension portion, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main body portion; Forming a passivation layer on the second insulating layer; Forming the pixel electrode layer on the passivation layer and forming the pixel main body portion.

[0013] Optionally, the step of forming the first substrate channel and the second substrate channel on the substrate includes: Forming a main channel on the substrate; Filling an insulating material in the main channel to form an insulating filling layer; Opening the first substrate channel and the second substrate channel on the insulating filling layer.

[0014] The present application also discloses an electronic paper display panel, which includes an electronic paper reflective layer and an array substrate. The electronic paper reflective layer is disposed on the array substrate, and the array substrate drives the electronic paper reflective layer to reflect light for displaying an image.

[0015] Compared with the existing array substrate solutions, in the present application, a first substrate channel and a second substrate channel are provided on the substrate, and then a pixel extension part is disposed in the first substrate channel, and a common electrode extension part is disposed in the second substrate channel. In this way, a main storage capacitor is formed between the pixel main part and the common electrode main part, and a secondary storage capacitor is formed by the projection overlap between the pixel extension part and the common electrode extension part, thereby increasing the size of the storage capacitor in each pixel unit area, avoiding the color deviation problem of the electronic paper display panel, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings included herein are used to provide a further understanding of the embodiments of the present application, and they constitute a part of the specification. They are used to illustrate the embodiments of the present application and, together with the written description, to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings: Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application; Figure 2 is a cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application; Figure 3 is a top view schematic diagram of an array substrate according to the first embodiment of the present application; Figure 4 is a cross-sectional schematic diagram of a first insulating channel and a second insulating channel according to the first embodiment of the present application; Figure 5 is a plan view schematic diagram of a first substrate channel according to the first type of the first embodiment of the present application; Figure 6 is a cross-sectional schematic diagram of a first substrate channel according to the first type of the first embodiment of the present application; Figure 7 is a schematic diagram of a first substrate channel according to the second type of the first embodiment of the present application; Figure 8 is a schematic diagram of a first substrate channel and a second substrate channel according to the first type of the first embodiment of the present application; Figure 9 is a top view schematic diagram of a first substrate channel and a second substrate channel according to the second type of the first embodiment of the present application; Figure 10It is a cross-sectional schematic diagram of the first substrate channel and the second substrate channel of the second first embodiment of the present application; Figure 11 It is a cross-sectional schematic diagram of an array substrate of the second embodiment of the present application; Figure 12 It is a cross-sectional schematic diagram of an array substrate of the third embodiment of the present application; Figure 13 It is a top view schematic diagram of a second metal layer of the third embodiment of the present application; Figure 14 It is a cross-sectional schematic diagram of an array substrate of the fourth embodiment of the present application; Figure 15 It is a top view schematic diagram of a first metal layer of the fourth embodiment of the present application; Figure 16 It is a cross-sectional schematic diagram of a third substrate channel of the fourth embodiment of the present application; Figure 17 It is a schematic diagram of a preparation method of an array substrate of an embodiment of the present application; Figure 18 It is a preparation schematic diagram of a first insulating channel and a second insulating channel of an embodiment of the present application; Figure 19 It is a preparation schematic diagram of a first substrate channel and a second substrate channel of an embodiment of the present application.

[0017] Among them, 10 is an electronic paper display panel; 20 is an electronic paper reflective layer; 21 are electrophoretic particles; 22 is a color resist layer; 23 is a color resist; 30 is an array substrate; 40 is a pixel unit area; 100 is a substrate; 110 is a first metal layer; 120 is a first insulating layer; 130 is a second metal layer; 140 is a second insulating layer; 150 is a passivation layer; 160 is a pixel electrode layer; 210 is a first substrate channel; 211 is a sub-substrate channel; 220 is a second substrate channel; 230 is a third substrate channel; 240 is an insulating filling layer; 241 is an insulating isolation wall; 250 is a main channel; 310 is a first insulating channel; 311 is a sub-insulating channel; 320 is a second insulating channel; 410 is a first avoidance notch; 420 is a second avoidance notch; 500 is a pixel electrode block; 510 is a pixel main body; 511 is a first sub-main body; 512 is a second sub-main body; 520 is a pixel extension; 521 is a first pixel extension; 522 is a second pixel extension; 530 is a pixel connection segment; 540 is a second main body extension; 600 is a common electrode block; 610 is a common electrode main body; 620 is a common electrode extension; 621 is a first common electrode extension; 622 is a second common electrode extension; 630 is a common electrode connection segment; 710 is a data line; 720 is a scan line; 730 is an active switch; 810 is a first via; 820 is a substrate through hole; 830 is a second via. Detailed implementation manners

[0018] It should be understood that the terms, the specific structures and functional details disclosed herein are only for the purpose of describing specific embodiments, which are representative, but the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments set forth herein.

[0019] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating relative importance or implicitly indicating the number of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any deformation thereof means non-exclusive inclusion, and there may be or be added one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0020] In addition, the terms indicating the orientation or positional relationship such as "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only for the purpose of facilitating the simplified description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application.

[0021] In addition, unless otherwise clearly defined and limited, the terms "install", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, or it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] The present application will be described in detail below with reference to the accompanying drawings and optional embodiments.

[0023] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application. As Figure 1 shown, the present application discloses an electronic paper display panel 10. The electronic paper display panel 10 includes an electronic paper reflective layer 20 and an array substrate 30. The electronic paper reflective layer 20 is disposed on the array substrate 30, and the array substrate 30 drives the electronic paper reflective layer 20 to reflect light for displaying an image.

[0024] Taking the electronic paper display panel 10 as a microcapsule type electronic paper display panel 10 as an example, the electronic paper reflective layer 20 includes microcapsules and a color resist layer 22. The microcapsules are filled with electrophoretic particles 21. The electrophoretic particles 21 include black particles and white particles. The color resist layer 22 includes a plurality of color resists 23. By applying different voltages on the pixel electrode block 500, particles of different colors are moved to target positions to reflect the incident light, thereby realizing the display of an image.

[0025] The present application also discloses an array substrate 30, which can be used in the above-mentioned electronic paper display panel 10. For the array substrate 30, the following design is provided in the present application and will be specifically introduced through several embodiments: Embodiment 1: Figure 2 is a cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application. Figure 3 is a top view schematic diagram of an array substrate according to the first embodiment of the present application. Combining Figures 1-3As shown, the present application discloses an array substrate 30, which is used in an electronic paper display panel 10. The array substrate 30 further includes a substrate 100, a common electrode block 600, and a pixel electrode block 500. The common electrode block 600 and the pixel electrode block 500 are both disposed on the substrate 100. A storage capacitor is formed between the common electrode block 600 and the pixel electrode block 500. The array substrate 30 includes a pixel unit area 40, and the common electrode block 600 and the pixel electrode block 500 are both disposed in each pixel unit area 40.

[0026] The array substrate 30 further includes a first substrate channel 210 and a second substrate channel 220. The first substrate channel 210 and the second substrate channel 220 are both disposed on the substrate 100 of each pixel unit area 40.

[0027] The pixel electrode block 500 includes a pixel main body 510 and a pixel extension 520. The pixel main body 510 is connected to the pixel extension 520, and at least a part of the pixel extension 520 is located in the first substrate channel 210.

[0028] The common electrode block 600 includes a common electrode main body 610 and a common electrode extension 620. The common electrode main body 610 is connected to the common electrode extension 620, and at least a part of the common electrode extension 620 is located in the second substrate channel 220.

[0029] A main storage capacitor is formed by the projection overlap between the pixel main body 510 and the common electrode main body 610, and a secondary storage capacitor is formed by the projection overlap between the pixel extension 520 and the common electrode extension 620.

[0030] When the electronic paper display panel 10 refreshes the screen, the movement speed of the electrophoretic particles 21 is slower than the charging speed of the pixel electrode block 500. For example, when refreshing the second row after refreshing the first row, the electrophoretic particles 21 on the pixel electrode block 500 of the first row have not yet moved to the target position. Therefore, a larger storage capacitor is required to maintain the movement of the electrophoretic particles 21 to the target position. Moreover, since the working voltage of the electronic paper display panel 10 is relatively large, for example, taking the maximum driving voltage of the data line 710 as plus or minus 15V as an example, then the voltage difference between the source and the drain of the active switch 730 will be relatively large, resulting in more leakage of the active switch 730. Therefore, the electronic paper display panel 10 needs to have a larger storage capacitor.

[0031] However, affected by the area of the pixel unit region 40, the overlapping area between the common electrode block 600 and the pixel electrode block 500 within each pixel unit region 40 is limited, resulting in a small storage capacitance formed between the common electrode block 600 and the pixel electrode block 500 within each pixel unit region 40. This can cause the electrophoretic particles 21 to be unable to move to the target position, leading to display anomalies such as color deviation problems.

[0032] Compared with the existing array substrate 30 solution, in this application, a first substrate channel 210 and a second substrate channel 220 are provided on the substrate 100. Then, the pixel extension 520 is disposed in the first substrate channel 210, and the common electrode extension 620 is disposed in the second substrate channel 220. In this way, a main storage capacitance is formed by the projection overlap between the pixel main body 510 and the common electrode main body 610, and a secondary storage capacitance is formed by the projection overlap between the pixel extension 520 and the common electrode extension 620, thereby increasing the size of the storage capacitance within each pixel unit region 40, avoiding color deviation problems in the electronic paper display panel 10, and improving the display effect of the display panel.

[0033] Among them, the array substrate 30 includes a first metal layer 110, a first insulating layer 120, a second metal layer 130, a second insulating layer 140, a passivation layer 150, and a pixel electrode layer 160. The first metal layer 110, the first insulating layer 120, the second metal layer 130, the second insulating layer 140, the passivation layer 150, and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0034] The array substrate 30 further includes a data line 710, a scan line 720, and an active switch 730. The active switch 730 can be a top-gate type active switch 730, that is, the gate of the active switch 730 is disposed on the second metal layer 130, the source and drain of the active switch 730 are disposed on the first metal layer 110, and the semiconductor layer of the active switch 730 is disposed between the substrate 100 and the first metal layer 110. The active switch 730 can also be a bottom-gate type active switch 730, that is, the gate of the active switch 730 is disposed on the first metal layer 110, the source and drain of the active switch 730 are disposed on the second metal layer 130, and the semiconductor layer of the active switch 730 is disposed between the first insulating layer 120 and the second metal layer 130. There is no limitation here.

[0035] The data line 710 is connected to the pixel electrode block 500 through an active switch 730. The scan line 720 is connected to the gate of the active switch 730. The data line 710 and the scan line 720 are arranged in a crisscross pattern and define the pixel unit region 40. When the data line 710 is in the first metal layer 110, the scan line 720 is in the second metal layer 130. When the data line 710 is in the second metal layer 130, the scan line 720 is in the first metal layer 110. In this application, an example is given where the data line 710 is in the second metal layer 130 and the scan line 720 is in the first metal layer 110.

[0036] Specifically, in this embodiment, the pixel main body 510 is only disposed in the pixel electrode layer 160, and the common electrode main body 610 is only disposed in the first metal layer 110. Specifically, the pixel main body 510 is only located in the pixel electrode layer 160, and the common electrode main body 610 is located in the first metal layer 110. The pixel main body 510 disposed in the pixel electrode layer 160 and the pixel extension 520 disposed in the first substrate channel 210 can be connected by a via hole penetrating through the first insulating layer 120 and the second insulating layer 140.

[0037] Figure 4 It is a cross-sectional schematic diagram of a first insulating channel and a second insulating channel according to the first embodiment of the present application. In combination with Figure 4 As shown, in order to further increase the size of the auxiliary storage capacitor, the present application further provides a first insulating channel 310 and a second insulating channel 320. The first pixel extension 521 of the pixel extension 520 is disposed in the first substrate channel 210, the second pixel extension 522 is disposed in the first insulating channel 310, and the first common electrode extension 621 of the common electrode extension 620 is disposed in the second substrate channel 220, and the second common electrode extension 622 is disposed in the second insulating channel 320.

[0038] In other words, by providing a first insulating channel 310 and a second insulating channel 320 on the first insulating layer 120 and the second insulating layer 140, and then filling conductive materials in the first insulating channel 310 and the second insulating channel 320 to form the second pixel extension 522 and the second common electrode extension 622 respectively.

[0039] Specifically, the array substrate 30 includes a first metal layer 110, a first insulating layer 120, a second metal layer 130, a second insulating layer 140, a passivation layer 150, and a pixel electrode layer 160. The first metal layer 110, the first insulating layer 120, the second metal layer 130, the second insulating layer 140, the passivation layer 150, and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0040] The array substrate 30 further includes a first insulating channel 310 and a second insulating channel 320, and each pixel unit region 40 is provided with the first insulating channel 310 and the second insulating channel 320; both the first insulating channel 310 and the second insulating channel 320 penetrate through the first insulating layer 120 and the second insulating layer 140.

[0041] The pixel extension 520 includes a first pixel extension 521 and a second pixel extension 522. The first pixel extension 521 is located in the first substrate channel 210, the second pixel extension 522 is located in the first insulating channel 310, and the second pixel extension 522 is connected to the first pixel extension 521 and the pixel main body 510; wherein, the second pixel extension 522 can be connected to the pixel main body 510 by providing a first via hole 810 in the passivation layer 150. Of course, a channel having the same shape as the second insulating channel 320 can also be provided on the passivation layer 150, and a conductive material is filled to connect the second pixel extension 522 to the pixel main body 510.

[0042] The common electrode extension 620 includes a first common electrode extension 621 and a second common electrode extension 622. The first common electrode extension 621 is located in the second substrate channel 220, the second common electrode extension 622 is located in the second insulating channel 320, and the second common electrode extension 622 is connected to the first common electrode extension 621 and the first common electrode extension 621.

[0043] Since the overlapping area of the second pixel extension 522 and the second common electrode extension 622 is increased, it is equivalent to increasing the size of the auxiliary storage capacitor, thereby further increasing the total storage capacitor size in each pixel unit region 40.

[0044] Figure 5 is a plan view of the first substrate channel of the first embodiment of the present application, Figure 6 is a cross-sectional view of the first substrate channel of the first embodiment of the present application, combined with Figures 5-6As shown, the substrate 100 is a glass substrate 100, the material of the glass substrate 100 is silicon dioxide, the materials of the first insulating layer 120 and the second insulating layer 140 are silicon nitride, the dielectric constant of the substrate 100 is less than that of the first insulating layer 120 and the second insulating layer 140, and since the operating voltage of the electronic paper display panel 10 is relatively large, at this time, if the first insulating channel 310 is located directly above the first substrate channel 210 and the second insulating channel 320 is located directly above the second substrate channel 220, it will result in the distance between the first common electrode extension 621 and the first pixel extension 521 being equal to the distance between the second common electrode extension 622 and the second pixel extension 522. Then, there is a risk of breakdown between the first pixel extension 521 and the first common electrode extension 621 on the first substrate channel 210.

[0045] Therefore, the present application also provides an insulating isolation wall 241 between the first substrate channel 210 and the second substrate channel 220. Specifically, an insulating isolation wall 241 is provided between the first substrate channel 210 and the second substrate channel 220. The material of the insulating isolation wall 241 is the same as that of the first insulating layer 120 and the second insulating layer 140. The distance between the first common electrode extension 621 and the first pixel extension 521 is equal to the distance between the second common electrode extension 622 and the second pixel extension 522.

[0046] Since the insulating isolation wall 241 has the same dielectric constant as the first insulating layer 120 and the second insulating layer 140, it can ensure that the distance between the second common electrode extension 622 and the second pixel extension 522 is as small as the distance between the first common electrode extension 621 and the first pixel extension 521. Thus, the size of the storage capacitor can be further increased, and the risk of breakdown between the first common electrode extension 621 and the first pixel extension 521 can be avoided.

[0047] Moreover, the distance between the first common electrode extension 621 and the first pixel extension 521 and the distance between the second common electrode extension 622 and the second pixel extension 522 within each pixel unit area 40 are equal, which is more convenient for calculating the size of the storage capacitor.

[0048] And since the distance between the first common electrode extension 621 and the first pixel extension 521 is equal to the distance between the second common electrode extension 622 and the second pixel extension 522, that is, the second insulating channel 320 is located directly above the second substrate channel 220, the number of mask plates can be reduced during fabrication, thereby reducing the fabrication cost.

[0049] Figure 7 It is a schematic diagram of the second first substrate channel of the first embodiment of the present application. As Figure 7 shown, of course, it is also possible to set the distance between the first common electrode extension 621 and the first pixel extension 521 to be greater than the distance between the second common electrode extension 622 and the second pixel extension 522. This can ensure that the distance between the second common electrode extension 622 and the second pixel extension 522 is small enough to increase the size of the storage capacitor. At the same time, when no insulating material is provided between the first substrate channel 210 and the second substrate channel 220, the risk of breakdown between the first common electrode extension 621 and the first pixel extension 521 can be avoided.

[0050] The orthographic projection of the first substrate channel 210 coincides with the orthographic projection of the first insulating channel 310, which is more convenient for connecting the first pixel extension 521 and the second pixel extension 522. And the orthographic projection of the common electrode main body 610 covers the orthographic projection of the second substrate channel 220, avoiding the problem of poor connection between the first common electrode extension 621 and the common electrode main body 610 and improving the reliability.

[0051] Exemplarily, the substrate 100 is made of glass material, and the dielectric strength of the substrate 100 is 400 KV / cm, which is 40 V / μm. The voltage of the pixel electrode block 500 of the electronic paper display panel 10 is ±15 V, and the voltage of the common electrode block is 1 V; the maximum voltage difference is 16 V, and the calculated breakdown thickness is 0.4 μm. Considering the fluctuation of the grooving process of ±1.2 μm, the distance between the first pixel extension 521 and the second pixel extension 522 is greater than 1.6 μm.

[0052] The first insulating layer 120 and the second insulating layer 140 are both insulating materials, and the dielectric strength of the insulating material is 350 KV / cm, which is 35 V / μm. The calculated breakdown thickness is 0.457 μm. Therefore, the distance between the second pixel extension 522 and the second common electrode extension 622 is greater than 0.457 μm.

[0053] Thus, on the basis of ensuring a sufficiently large storage capacitor, the problem of breakdown between the first pixel extension 521 and the first common electrode extension 621 on the first substrate channel 210 can be avoided.

[0054] Figure 8 It is a schematic diagram of the first first substrate channel and the second substrate channel of the first embodiment of the present application. As Figure 8As shown, in order to increase the overlapping area between the pixel electrode block 500 and the common electrode block 600 and increase the size of the storage capacitor, in this application, the first substrate channel 210 in each pixel unit area 40 is set as a strip-shaped channel of the substrate 100. The first substrate channel 210 is arranged on the outer side around the second substrate channel 220. The first insulating channel 310 is an insulating strip-shaped channel, and the orthographic projection of the first insulating channel 310 coincides with that of the first substrate channel 210. The second substrate channel 220 is an annular channel, and the second insulating channel 320 is an annular channel. The overlapping area between the first pixel extension 521 and the first common electrode extension 621 can be maximally increased, and the size of the storage capacitor can be increased.

[0055] Moreover, adjacent two strip-shaped channels of the substrate 100 are spaced apart to form a first avoidance notch 410, and adjacent two insulating strip-shaped channels are spaced apart to form a first avoidance notch 410. The array substrate 30 further includes a common electrode connection section 630. The common electrode connection section 630 is located in the first metal layer 110. Two ends of the common electrode connection section 630 are respectively connected to the common electrode main parts 610 in two laterally adjacent pixel unit areas 40, and the common electrode connection section 630 passes through the first avoidance notch 410, so that the common electrode blocks 600 in two adjacent pixel unit areas 40 are connected through the common electrode connection section 630.

[0056] Exemplarily, the first substrate channel 210 includes four sub-substrate channels 211, which are respectively defined as a first sub-substrate channel 211, a second sub-substrate channel 211, a third sub-substrate channel 211, and a fourth sub-substrate channel 211. A first avoidance notch 410 is formed between the first sub-substrate channel 211 and the second sub-substrate channel 211, a first avoidance notch 410 is formed between the second sub-substrate channel 211 and the third sub-substrate channel 211, a first avoidance notch 410 is formed between the third sub-substrate channel 211 and the fourth sub-substrate channel 211, and a first avoidance notch 410 is formed between the fourth sub-substrate channel 211 and the first sub-substrate channel 211. The four first avoidance notches 410 are respectively located around the common electrode main part 610.

[0057] The first insulating channel 310 includes four sub-insulating channels 311, which are respectively defined as a first sub-insulating channel 311, a second sub-insulating channel 311, a third sub-insulating channel 311, and a fourth sub-insulating channel 311. A first avoidance notch 410 is formed between the first sub-insulating channel 311 and the second sub-insulating channel 311, a first avoidance notch 410 is formed between the second sub-insulating channel 311 and the third sub-insulating channel 311, a first avoidance notch 410 is formed between the third sub-insulating channel 311 and the fourth sub-insulating channel 311, and a first avoidance notch 410 is formed between the fourth sub-insulating channel 311 and the first sub-insulating channel 311. The four first avoidance notches 410 are respectively located around the common electrode main body portion 610; the first sub-insulating channel 311 and the first sub-substrate channel 211 are coincident in the orthographic projection, the second sub-insulating channel 311 and the second sub-substrate channel 211 are coincident in the orthographic projection, the third sub-insulating channel 311 and the third sub-substrate channel 211 are coincident in the orthographic projection, and the fourth sub-insulating channel 311 and the fourth sub-substrate channel 211 are coincident in the orthographic projection.

[0058] When the scanning line 720 is located in the first metal layer 110 and the data line 710 is located in the second metal layer 130, the common electrode connection segment 630 connects two adjacent common electrode main body portions 610 in the same row parallel to the length direction of the scanning line 720; when the data line 710 is located in the first metal layer 110 and the scanning line 720 is located in the second metal layer 130, the common electrode connection segment 630 connects two adjacent common electrode main body portions 610 in the same column parallel to the length direction of the data line 710.

[0059] First avoidance notches 410 are reserved around the common electrode main body portion 610. In this way, according to the specific positions of the scanning line 720 and the data line 710, it can be determined whether the common electrode connection segment 630 is located on the upper and lower sides or the left and right sides of the common electrode main body portion 610, improving the adaptability.

[0060] The common electrode connection segment 630 is located at the middle position of the first avoidance notch 410, that is, the distances between the common electrode connection segment 630 and the sub-substrate channels 211 on both sides are equal. In this way, the distances between the second pixel extension portions 522 on both sides of the common electrode connection segment 630 are also equal. And when the common electrode connection segment 630 is located in the first metal layer 110, the distance between the common electrode connection segment 630 and the sub-substrate channel 211 is greater than 1.6 μm, which can avoid the risk of breakdown between the common electrode connection segment 630 and the first pixel extension portion 521 at the position of the common electrode connection segment 630.

[0061] Figure 9 It is a top view schematic diagram of the first substrate channel and the second substrate channel in the second embodiment of the first embodiment of the present application. Figure 10It is a schematic cross-sectional view of the first substrate channel and the second substrate channel of the first embodiment of the present application. As Figures 9-10 shown, different from the first type, the first substrate channel 210 is a circular channel of the substrate 100, the second substrate channel 220 is a circular channel of the substrate 100, the first substrate channel 210 is disposed around the outside of the second substrate channel 220, the first insulating channel 310 is an insulating circular channel, the second insulating channel 320 is an insulating circular channel, and the first insulating channel 310 is disposed around the outside of the second insulating channel 320.

[0062] The common electrode connection section 630 is located on the side of the substrate 100 away from the first metal layer 110. A substrate through hole 820 is provided on the substrate 100. The two ends of the common electrode connection section 630 are respectively connected to the common electrode main body portions 610 in two adjacent pixel unit regions 40 through the substrate through hole 820. In this way, since there is no need to provide the first avoidance notch 410, the overlapping area between the pixel electrode block 500 and the common electrode block 600 can be further increased, thereby increasing the size of the storage capacitor.

[0063] Embodiment 2: Figure 11 It is a schematic cross-sectional view of an array substrate of the second embodiment of the present application. As Figure 11 shown, different from the first embodiment, the common electrode main body portion 610 of this embodiment is located in the second metal layer 130.

[0064] Compared with the solution of the first embodiment, by disposing the common electrode main body portion 610 in the second metal layer 130, the distance between the common electrode main body portion 610 and the pixel main body portion 510 is reduced, and the size of the storage capacitor between the pixel electrode block 500 and the common electrode block 600 is increased.

[0065] Embodiment 3: Figure 12 It is a schematic cross-sectional view of an array substrate of the third embodiment of the present application. Figure 13 It is a top view schematic diagram of a second metal layer of the third embodiment of the present application. As Figures 12-13 shown, different from the first embodiment, in this embodiment, the pixel electrode blocks 500 are disposed both in the second metal layer 130 and in the pixel electrode layer 160, and the common electrode main body portion 610 is located in the first metal layer 110. Specifically: The pixel main body portion 510 further includes a first sub-main body portion 511 and a second sub-main body portion 512. The first sub-main body portion 511 is connected to the second sub-main body portion 512, and the first sub-main body portion 511 is located in the pixel electrode layer 160.

[0066] The second sub - main body portion 512 is located within the second metal layer 130, and the second insulating channel 320 surrounds the outer side of the second sub - main body portion 512. The second sub - main body portion 512 is connected to the pixel main body portion 510 through a second via 830. The common electrode main body portion 610 is located within the first metal layer 110. The orthographic projection between the first sub - main body portion 511 and the common electrode main body portion 610 overlaps, the orthographic projection between the second sub - main body portion 512 and the common electrode main body portion 610 overlaps, and the pixel extension portion 520 is connected to the first sub - main body portion 511. That is, the first sub - main body portion 511 is connected to the second sub - main body portion 512 through the pixel main body portion 510.

[0067] Compared with the solution of the first embodiment, in this embodiment, by providing the second sub - main body portion 512 within the second metal layer 130, the distance between the pixel electrode block 500 and the common electrode block 600 is reduced, thereby increasing the size of the storage capacitor.

[0068] Embodiment 4: Figure 14 It is a cross - sectional schematic diagram of an array substrate according to the fourth embodiment of the present application. As Figure 14 shown, different from the first embodiment, in this embodiment, a second sub - main body portion 512 is provided within the first metal layer 110, and the common electrode main body portion 610 is located within the second metal layer 130. Specifically: The pixel main body portion 510 further includes a first sub - main body portion 511 and a second sub - main body portion 512. The first sub - main body portion 511 is connected to the second sub - main body portion 512, and the first sub - main body portion 511 is located within the pixel electrode layer 160.

[0069] The second sub - main body portion 512 is located within the first metal layer 110, and the second insulating channel 320 surrounds the outer side of the second sub - main body portion 512. The common electrode main body portion 610 is located within the second metal layer 130.

[0070] The orthographic projection between the first sub - main body portion 511 and the common electrode main body portion 610 overlaps, the orthographic projection between the second sub - main body portion 512 and the common electrode main body portion 610 overlaps, and the pixel extension portion 520 is connected to the first sub - main body portion 511.

[0071] A main storage capacitor is formed between the first sub - main body portion 511 and the common electrode main body portion 610, and a main storage capacitor is formed between the second sub - main body portion 512 and the common electrode main body portion 610, thereby increasing the overlapping area between the pixel electrode block 500 and the common electrode block 600 and increasing the size of the storage capacitor.

[0072] Figure 15 is a top view schematic diagram of a first metal layer according to a fourth embodiment of the present application. As Figure 15 shown, the array substrate 30 further includes a pixel connection segment 530. The pixel connection segment 530 is located within the first metal layer 110. The second substrate channel 220 is a strip-shaped channel, and a second avoidance notch 420 is formed by arranging intervals between the head and the tail of the second substrate channel 220. The second insulating channel 320 is a strip-shaped channel, and a second avoidance notch 420 is formed by arranging intervals between the head and the tail of the second insulating channel 320. The second avoidance notch 420 formed by arranging intervals between the head and the tail of the second substrate channel 220 and the second avoidance notch 420 formed by arranging intervals between the head and the tail of the second insulating channel 320 are located in the same horizontal direction, so that both ends of the pixel connection segment 530 pass through the second avoidance notch 420 and are connected to the pixel extension portion 520 and the second sub-main body portion 512 respectively.

[0073] The pixel connection segment 530 is located at the middle of the second avoidance notch 420, that is, the distances between the pixel connection segment 530 and the head and the tail of the second insulating channel 320 are equal respectively, and the distances between the pixel connection segment 530 and the head and the tail of the second substrate channel 220 are equal respectively. The first sub-main body portion 511 and the second sub-main body portion 512 are connected through the pixel extension portion 520 and the pixel connection segment 530.

[0074] The common electrode connection segment 630 is located within the second metal layer 130. Both ends of the common electrode connection segment 630 are respectively connected to the common electrode main body portions 610 in two longitudinally adjacent pixel unit regions 40, and the common electrode connection segment 630 passes through the first avoidance notch 410, so that the common electrode blocks 600 in two adjacent pixel unit regions 40 are connected through the common electrode connection segment 630.

[0075] Figure 16 is a cross-sectional schematic diagram of a third substrate channel according to a fourth embodiment of the present application. As Figure 16As shown, the array substrate 30 further includes a third substrate channel 230. The third substrate channel 230 is provided on the substrate 100 of each pixel unit region 40, and the third substrate channel 230 is located on a side of the second substrate channel 220 away from the first substrate channel 210. The pixel electrode block 500 further includes a second main body extension 540. The second main body extension 540 is connected to the second sub-main body portion 512, and the second main body extension 540 is disposed in the third substrate channel 230. The third substrate channel 230 is an annular channel, and the second substrate channel 220 is disposed around the outside of the third substrate channel 230. A projection overlap is formed between the second main body extension 540 and the common electrode extension 620 to form another auxiliary storage capacitor.

[0076] By providing the third substrate channel 230 on the substrate 100 and disposing the second main body extension 540 in the third substrate channel 230, a projection overlap is formed between the second main body extension 540 and the common electrode extension 620 to form another auxiliary storage capacitor, thereby further increasing the storage capacitance between the pixel electrode block 500 and the common electrode block 600 in a single pixel region.

[0077] An insulating isolation wall 241 is provided between the third substrate channel 230 and the second substrate channel 220. The material of the insulating isolation wall 241 is the same as the materials of the first insulating layer 120 and the second insulating layer 140. The distances between the first common electrode extension 621 and the first pixel extension 521 and between the first common electrode extension 621 and the second main body extension 540 are equal, so as to avoid the risk of breakdown between the first common electrode extension 621 and the second main body extension 540.

[0078] Figure 17 It is a schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present application. As Figure 17 shown, the present application discloses a method for manufacturing an array substrate 30 for manufacturing the above-mentioned array substrate 30. The steps of the method for manufacturing the array substrate 30 include: S1: Form a first substrate channel and a second substrate channel on the substrate; S2: Form a common electrode block and a pixel electrode block on the substrate; Among them, the pixel electrode block 500 includes a pixel main body portion 510 and a pixel extension portion 520. The pixel main body portion 510 is connected to the pixel extension portion 520, and at least a part of the pixel extension portion 520 is located in the first substrate channel 210; the common electrode block 600 includes a common electrode main body portion 610 and a common electrode extension portion 620. The common electrode main body portion 610 is connected to the common electrode extension portion 620, and at least a part of the common electrode extension portion 620 is located in the second substrate channel 220; a main storage capacitor is formed by the projection overlap between the pixel main body portion 510 and the common electrode main body portion 610, and a secondary storage capacitor is formed by the projection overlap between the pixel extension portion 520 and the common electrode extension portion 620.

[0079] Compared with the existing solution of the array substrate 30, in this application, by providing the first substrate channel 210 and the second substrate channel 220 on the substrate 100, then setting the pixel extension portion 520 in the first substrate channel 210 and setting the common electrode extension portion 620 in the second substrate channel 220, in this way, the pixel main body portion 510 and the common electrode main body portion 610 form a main storage capacitor, and a secondary storage capacitor is formed by the projection overlap between the pixel extension portion 520 and the common electrode extension portion 620, thereby increasing the size of the storage capacitor in each pixel unit area 40, avoiding the color deviation problem of the electronic paper display panel 10, and improving the display effect of the display panel.

[0080] Figure 18 It is a schematic diagram of the preparation of a first insulating channel and a second insulating channel according to an embodiment of the present application, as Figure 18 shown, the step S2: The step of forming the common electrode block and the pixel electrode block on the substrate includes: S21: Form a first metal layer on the substrate, fill a conductive material in the first substrate channel to form a first pixel extension portion, fill a conductive material in the second substrate channel to form a first common electrode extension portion, and form a common electrode main body portion; S22: Form a first insulating layer on the first metal layer; S23: Form a second metal layer on the first insulating layer; S24: Form a second insulating layer on the second metal layer, and provide a first insulating channel and a second insulating channel on the second insulating layer and the first insulating layer. Fill a conductive material in the first insulating channel to form a second pixel extension portion, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main body portion; fill a conductive material in the second insulating channel to form a second common electrode extension portion, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main body portion; S25: Form a passivation layer on the second insulating layer; S26: Form the pixel electrode layer on the passivation layer and form the pixel main body.

[0081] By providing a first insulating channel 310 and a second insulating channel 320 on the first insulating layer 120 and the second insulating layer 140, and then filling the first insulating channel 310 and the second insulating channel 320 with a conductive material to form a second pixel extension 522 and a second common electrode extension 622 respectively. Since the overlapping portion of the second pixel extension 522 and the second common electrode extension 622 is increased, it is equivalent to increasing the size of the parasitic storage capacitor, thereby further increasing the total storage capacitor size within each pixel unit region 40.

[0082] Figure 19 It is a schematic diagram for preparing a first substrate channel and a second substrate channel according to an embodiment of the present application, as Figure 19 shown, S1: The steps of forming a first substrate channel and a second substrate channel on the substrate include: S11: Form a main channel on the substrate; S12: Fill the main channel with an insulating material to form an insulating filling layer; S13: Open a first substrate channel and a second substrate channel on the insulating filling layer.

[0083] By first providing a main channel 250 on the substrate 100, and then filling the main channel 250 with an insulating material to form an insulating filling layer 240, and then opening a first substrate channel 210 and a second substrate channel 220 on the insulating filling layer 240.

[0084] This can reduce the distance between the first substrate channel 210 and the second substrate channel 220, such that the distance between the first substrate channel 210 and the second substrate channel 220, the distance between the first insulating channel 310 and the second insulating channel 320 can be equal. Thus, the distance between the first pixel extension 521 and the first common electrode extension 621, the distance between the second pixel extension 522 and the second common electrode extension 622 can be equal, which is convenient for calculating the actual storage capacitor size. Moreover, since the spacing between the first common electrode extension 621 and the first pixel extension 521 is equal to the spacing between the second common electrode extension 622 and the second pixel extension 522, that is, the second insulating channel 320 is located directly above the second substrate channel 220, and the second insulating channel 320 is located directly above the second substrate channel 220, the number of mask plates can be reduced during fabrication, reducing the fabrication cost. And it can also avoid the problem of breakdown between the first common electrode extension 621 and the first pixel extension 521.

[0085] It should be noted that the limitations of each step involved in this solution do not, on the premise that the specific solution can be implemented, be regarded as limiting the order of the steps. The steps written in the front can be executed first, or can be executed later, or even can be executed simultaneously. As long as this solution can be implemented, it should be regarded as falling within the protection scope of this application.

[0086] It should be noted that the inventive concept of this application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of no conflict, the above-described embodiments or technical features can be combined arbitrarily to form new embodiments. After the combination of each embodiment or technical feature, the original technical effect will be enhanced.

[0087] The above content is a further detailed description of this application in combination with specific optional implementation manners, and it cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application pertains, without departing from the concept of this application, several simple deductions or substitutions can still be made, and all should be regarded as falling within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate is used in an electronic paper display panel. The array substrate further includes a substrate, a common electrode block, and a pixel electrode block. The common electrode block and the pixel electrode block are both disposed on the substrate. A storage capacitor is formed between the common electrode block and the pixel electrode block. The array substrate includes a pixel unit area, and the common electrode block and the pixel electrode block are both disposed in each pixel unit area; The array substrate further includes a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are both disposed on the substrate of each pixel unit area; The pixel electrode block includes a pixel main body portion and a pixel extension portion. The pixel main body portion is connected to the pixel extension portion, and at least a part of the pixel extension portion is located in the first substrate channel; The common electrode block includes a common electrode main body portion and a common electrode extension portion. The common electrode main body portion is connected to the common electrode extension portion, and at least a part of the common electrode extension portion is located in the second substrate channel; A main storage capacitor is formed by the projection overlap between the pixel main body portion and the common electrode main body portion, and a sub-storage capacitor is formed by the projection overlap between the pixel extension portion and the common electrode extension portion.

2. The array substrate according to claim 1, wherein The array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode layer. The first metal layer, the first insulating layer, the second metal layer, the second insulating layer, the passivation layer, and the pixel electrode layer are sequentially stacked on the substrate; The array substrate further includes a first insulating channel and a second insulating channel, and the first insulating channel and the second insulating channel are both disposed in each pixel unit area; The first insulating channel and the second insulating channel both penetrate through the first insulating layer and the second insulating layer; The pixel extension portion includes a first pixel extension portion and a second pixel extension portion. The first pixel extension portion is located in the first substrate channel, the second pixel extension portion is located in the first insulating channel, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main body portion; The common electrode extension portion includes a first common electrode extension portion and a second common electrode extension portion. The first common electrode extension portion is located in the second substrate channel, the second common electrode extension portion is located in the second insulating channel, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main body portion.

3. The array substrate according to claim 2, wherein The distance between the first common electrode extension portion and the first pixel extension portion is greater than the distance between the second common electrode extension portion and the second pixel extension portion.

4. The array substrate according to claim 2, wherein An insulating isolation wall is disposed between the first substrate channel and the second substrate channel. The material of the insulating isolation wall is the same as the materials of the first insulating layer and the second insulating layer. The distance between the first common electrode extension portion and the first pixel extension portion is equal to the distance between the second common electrode extension portion and the second pixel extension portion.

5. The array substrate according to any one of claims 3 and 4, characterized in that The pixel main body portion is only located in the pixel electrode layer, and the common electrode main body portion is located in the first metal layer or in the second metal layer.

6. The array substrate according to any one of claims 3 and 4, characterized in that, The pixel main body further includes a first sub-main body and a second sub-main body. The first sub-main body is connected to the second sub-main body, and the first sub-main body is located within the pixel electrode layer; The second sub-main body is located within the second metal layer, and the common electrode main body is located within the first metal layer; or the second sub-main body is located within the first metal layer, and the common electrode main body is located within the second metal layer; The first sub-main body and the common electrode main body overlap in the orthographic projection therebetween, the second sub-main body and the common electrode main body overlap in the orthographic projection therebetween, and the pixel extension is connected to the first sub-main body.

7. A method for preparing an array substrate, characterized in that, For preparing the array substrate according to any one of the above claims 1-6, the steps of the preparation method of the array substrate include: Forming a first substrate channel and a second substrate channel on the substrate; Forming a common electrode block and a pixel electrode block on the substrate; Wherein, the pixel electrode block includes a pixel main body and a pixel extension. The pixel main body is connected to the pixel extension, and at least a part of the pixel extension is located within the first substrate channel; the common electrode block includes a common electrode main body and a common electrode extension. The common electrode main body is connected to the common electrode extension, and at least a part of the common electrode extension is located within the second substrate channel; the pixel main body and the common electrode main body overlap in the projection therebetween to form a main storage capacitor, and the pixel extension and the common electrode extension overlap in the projection therebetween to form a sub-storage capacitor.

8. The method for manufacturing an array substrate according to claim 7, wherein The step of forming the common electrode block and the pixel electrode block on the substrate includes: Forming a first metal layer on the substrate, filling a conductive material in the first substrate channel to form a first pixel extension, filling a conductive material in the second substrate channel to form a first common electrode extension, and forming a common electrode main body; Forming a first insulating layer on the first metal layer; Forming a second metal layer on the first insulating layer; Forming a second insulating layer on the second metal layer, and providing a first insulating channel and a second insulating channel on the second insulating layer and the first insulating layer. Filling a conductive material in the first insulating channel to form a second pixel extension, and the second pixel extension is connected to the first pixel extension and the pixel main body; filling a conductive material in the second insulating channel to form a second common electrode extension, and the second common electrode extension is connected to the first common electrode extension and the common electrode main body; Forming a passivation layer on the second insulating layer; Forming a pixel electrode layer on the passivation layer, and forming the pixel main body.

9. The manufacturing method of the array substrate according to claim 7, characterized in that, The step of forming the first substrate channel and the second substrate channel on the substrate includes: Forming a main channel on the substrate; Filling an insulating material in the main channel to form an insulating filling layer; Opening a first substrate channel and a second substrate channel on the insulating filling layer.

10. An electronic paper display panel, characterized in that, The electronic paper display panel includes an electronic paper reflective layer and an array substrate as described in any one of claims 1-6. The electronic paper reflective layer is disposed on the array substrate, and the array substrate drives the electronic paper reflective layer to reflect light for displaying an image.

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