Power supply method and circuit for large-scale inter-chiplet high-speed parallel port interconnection

Abstract

The application discloses a power supply method for large-scale Chiplet high-speed parallel port interconnection, wherein in a Chiplet interconnection circuit, a plurality of drivers are connected to a TX end, each driver is connected to a transmission link, and a plurality of transmission links are formed; the number of transmission links sharing one LDO is calculated by using a preset algorithm, and the number and distribution positions of required LDOs are obtained according to the number and distance of the transmission links, so that each transmission link is timely supplemented with power charges. In a system in which a plurality of Chiplets work in parallel, the method can ensure that each Chiplet obtains accurate voltage, avoids performance degradation or failure caused by power fluctuations, and thus improves the overall reliability and stability of the system. The LDO in the method is small in size and simple in design, can effectively reduce required external components (such as inductors, capacitors and the like), and thus reduces the overall size and cost of the system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power supply, and particularly relates to a power supply method and circuit for large-scale Chiplet high-speed parallel port interconnection. BACKGROUND

[0002] There are a large number of parallel transceiving data links in the Chiplet interconnection port, and the transmitted data will affect the stability of the system power supply, and generate a ripple on the power supply. In high-speed data transmission, the quality of the transmitted data is closely related to the stability of the output voltage of a low-dropout regulator (LDO), and the speed of the change of the LDO load current also changes at a high speed, which will cause a large amount of charge to be extracted from the power supply, and the traditional LDO power supply method cannot achieve such a high bandwidth. If a relatively stable power supply voltage is required, a larger decoupling capacitor is needed, which will consume more chip area. SUMMARY

[0003] The application aims to provide a power supply method for large-scale Chiplet high-speed parallel port interconnection, which adopts a hybrid LDO power supply method, can not only supplement the power charge of each transmission link in time, but also reduce the size of the load capacitance of a single LDO, and make the layout design of the entire LDO more reasonable.

[0004] To solve the above problems, the technical scheme of the application is as follows:

[0005] A power supply method for large-scale Chiplet high-speed parallel port interconnection, which adopts a hybrid LDO power supply method to supply power to the Chiplet interconnection circuit, and includes the following steps:

[0006] In the Chiplet interconnection circuit, a plurality of drivers are connected to the TX end, each driver is connected to a transmission link, and a plurality of transmission links are formed.

[0007] The number of transmission links sharing one LDO is calculated by a preset algorithm, and the number and distribution position of the required LDO are obtained according to the number and distance of the transmission links, so that each transmission link can supplement the power charge in time.

[0008] The preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links through the charge conservation formula, so as to accurately control the number of LDO power supply links.

[0009] According to an embodiment of the application, a comparator is connected to the output end of the LDO, and a compensation tube is connected to the output end of the comparator.

[0010] The output voltage of the LDO is detected by a comparator, and when the output voltage exceeds a preset range, a compensation tube is triggered to quickly compensate or release charges in a data transmission period, so as to ensure the stability of the power supply voltage, and meanwhile, the value of the decoupling capacitor is reduced, and the chip area is saved.

[0011] According to an embodiment of the present application, two comparators are used to detect the output voltage of the LDO, and are respectively used to compare the output voltage with an upper limit voltage and a lower limit voltage, so as to realize the quick compensation or release of charges, ensure the stability of the LDO output voltage, and realize the on-chip LDO.

[0012] According to an embodiment of the present application, the voltage fluctuation of the LDO output node is inhibited by the cooperative work of the comparator and the compensation tube, the output data quality is ensured, and the BER value is optimized.

[0013] According to an embodiment of the present application, the cooperative work of the comparator and the compensation tube for inhibiting the voltage fluctuation of the LDO output node further comprises:

[0014] The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes in the process of data transmission; when the value of VDDQ is lower than a preset lower limit voltage, the comparator outputs a valid bit, a compensation tube is controlled to adjust a unit charging current, and the lost charges are compensated, so as to stabilize VDDQ in one clock cycle.

[0015] According to an embodiment of the present application, the output end of the LDO is connected to the input end of a first comparator, another input end of the first comparator is connected to a first reference voltage, the first reference voltage is used to indicate a lower limit voltage; the output end of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output end of the LDO.

[0016] The LDO outputs an initial voltage VDDQ, and the value of VDDQ changes in the process of data transmission; when the value of VDDQ is lower than a preset lower limit voltage, the comparator outputs a valid bit, a compensation tube is controlled to adjust a unit charging current, and the lost charges are compensated, so as to stabilize VDDQ in one clock cycle.

[0017] According to an embodiment of the present application, the output end of the LDO is connected to the input end of a second comparator, another input end of the second comparator is connected to a second reference voltage, the second reference voltage is used to indicate an upper limit voltage; the output end of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output end of the LDO.

[0018] The LDO outputs an initial voltage VDDQ, the value of VDDQ changes in the process of data transmission, when the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, and the second CTR module is controlled to adjust the unit charging current of the second Charge module to release the excessive charge and stabilize VDDQ in one clock cycle.

[0019] A power supply circuit for large-scale Chiplet high-speed parallel port interconnection, comprising:

[0020] A Chiplet interconnection circuit, the TX end of any Chiplet is connected to a plurality of drivers, each driver is connected to a transmission link, and a plurality of transmission links are formed;

[0021] A plurality of LDO modules, each LDO module is powered to a plurality of transmission links in a distributed position area calculated according to a preset algorithm, so that each transmission link is timely supplemented with power charge;

[0022] The output end of each LDO module is connected to a comparator, and the output end of the comparator is connected to a compensation tube;

[0023] The comparator is used for detecting the output voltage of the LDO, and when the output voltage exceeds a preset range, the compensation tube is triggered to quickly compensate or release the charge in the data transmission period, so as to ensure the stability of the power supply voltage, reduce the value of the decoupling capacitor, and save the chip area.

[0024] According to an embodiment of the present application, the output end of the LDO is connected to the input end of the first comparator, the other input end of the first comparator is connected to the first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output end of the first comparator is connected to the first CTR module, the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output end of the LDO;

[0025] The LDO outputs an initial voltage VDDQ, the value of VDDQ changes in the process of data transmission, when the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, and the first CTR module is controlled to adjust the unit charging current of the first Charge module to release the excessive charge and stabilize VDDQ in one clock cycle.

[0026] According to an embodiment of the present application, the output end of the LDO is connected to the input end of the second comparator, the other input end of the second comparator is connected to the second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output end of the second comparator is connected to the second CTR module, the second CTR module is connected to the second Charge module, and the output of the second Charge module is connected to the output end of the LDO;

[0027] The LDO outputs an initial voltage VDDQ, the value of VDDQ changes in the process of data transmission, and when the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit to control the second CTR module to adjust the unit charging current of the second Charge module to release the excess charge to stabilize VDDQ in one clock cycle.

[0028] Compared with the prior art, the present application has the following advantages and positive effects:

[0029] 1) The power supply method for large-scale Chiplet high-speed parallel port interconnection in an embodiment of the present application, in the Chiplet interconnection circuit, the TX end is connected to a plurality of drivers, each driver is connected to a transmission link, and a plurality of transmission links are formed; the number of transmission links sharing one LDO is calculated by a preset algorithm, and the number and distribution position of the required LDO are obtained according to the number and distance of the transmission links, so that each transmission link can be timely supplemented with power charge. In a system in which a plurality of Chiplets work in parallel, this method can ensure that each Chiplet obtains accurate voltage, avoids performance degradation or failure caused by power fluctuations, and thus improves the overall reliability and stability of the system. For high-performance computing, AI accelerators and other applications, the low-noise characteristics of the LDO are particularly important, which helps to maintain the purity of the signal and the response speed of the system. The LDO in this method is small in size and simple in design, which can effectively reduce the required external components (such as inductors, capacitors, etc.), thereby reducing the overall size and cost of the system. In Chiplet design, since a plurality of small chips are integrated in a system, the compactness of the LDO makes it an ideal choice to solve the space limitation.

[0030] 2) The power supply method for large-scale Chiplet high-speed parallel port interconnection in an embodiment of the present application, a comparator is connected to the output end of the LDO, and a compensation tube is connected to the output end of the comparator; the output voltage of the LDO is detected by the comparator, and when the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release the charge in the data transmission period, so as to ensure the stability of the power voltage and avoid the influence of ripple on the signal quality. Through fast charge compensation, the area and power consumption of the decoupling capacitor are reduced, and the chip power consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 The flow chart of the power supply method for large-scale Chiplet high-speed parallel port interconnection in an embodiment of the present application;

[0032] Figure 2 The schematic diagram of the large-scale Chiplet high-speed parallel port interconnection circuit in an embodiment of the present application;

[0033] Figure 3A schematic diagram of a distance splitting module shared by a plurality of transmission links in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of a fast charge compensation circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application provides a power supply method and circuit for large-scale Chiplet high-speed parallel interconnection, which will be further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be clearer according to the following description and claims.

[0036] Chiplet technology divides a chip into multiple small chip modules, each of which is independently designed and optimized according to functions, and can select appropriate process and power management strategies to reduce power consumption. Different Chiplet modules can independently switch and adjust voltage and frequency to avoid power consumption of unused parts and improve energy efficiency. High-speed parallel interconnection between Chiplets requires additional communication circuits such as transceivers and routing logic, which will increase power consumption. Power management strategies need to be designed for different Chiplet modules to coordinate power supply and power consumption optimization. Improper design may lead to unreasonable power distribution and power supply interference, thereby increasing power consumption.

[0037] There are a large number of parallel data transmission links in Chiplet interconnection, and the transmitted data will affect the stability of the system power supply and generate ripples on the power supply. In high-speed data transmission, the quality of transmitted data is closely related to the stability of the output voltage of the low-dropout regulator (LDO), and the speed of the LDO load current change will also change rapidly, which will cause a large amount of charge to be extracted from the power supply. The traditional LDO power supply method cannot achieve such high bandwidth. If a more stable power supply voltage is required, a larger decoupling capacitor is needed, which will consume more chip area.

[0038] In order to improve the stability of the power supply voltage and reduce the area of the decoupling capacitor, the present embodiment adopts a hybrid LDO power supply method, and adds a comparator and a compensation current tube to quickly compensate or release the charge. The LDO meets the requirements of low dropout and high precision voltage regulation, and switches to a switching regulator mode when the load is high, thereby reducing the overall power consumption of the system, improving the current efficiency, and optimizing the quality of the output data.

[0039] Specifically, please refer to Figure 1 The present embodiment provides a power supply method for large-scale Chiplet high-speed parallel interconnection, which adopts a hybrid LDO power supply method to supply power to Chiplet interconnection circuit, including the following steps:

[0040] In the Chiplet interconnection circuit, the TX end is connected with a plurality of drivers, each driver is connected with a transmission link, and a plurality of transmission links are formed;

[0041] The number of transmission links sharing one LDO is calculated by a preset algorithm, and the number and distribution position of the required LDO are obtained according to the number and distance of the transmission links, so that each transmission link can be timely supplemented with power supply charge.

[0042] Through the method, the LDO is reasonably arranged, a plurality of transmission links share one LDO, the distance splitting module is split according to the distance, the LDO is close to the load, the transmission distance and voltage drop are reduced, the power supply efficiency and stability are improved, and the layout compactness is improved.

[0043] The LDO is split to a plurality of positions to avoid heat concentration, reduce the chip temperature, and improve the thermal performance and reliability. Or the LDO is reasonably arranged to be close to the heat dissipation structure or region, so as to enhance the heat dissipation effect and ensure stable operation of the chip under high power consumption.

[0044] A plurality of LDOs can be customized to meet the power consumption and voltage requirements of different Chiplets, support a plurality of power supply specifications, and improve the design flexibility. The number and layout of the LDOs are adjusted according to the requirements to meet the requirements of different application scenarios, and the chip design upgrade and expansion are facilitated.

[0045] The preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links by the charge conservation formula to accurately control the number of LDO power supply links. For example, the average current extracted by the data change of a single link is , the size of the capacitor connected to the LDO is C, the change of the LDO output voltage is , and the total amount of charge that the LDO can compensate within a specified time t is Q. According to the charge conservation formula, the following results are obtained:

[0046]

[0047] Since the average current extracted by each link is determined after the design is completed, the number of LDO power supply links can be accurately controlled according to the compensation performance of the designed LDO.

[0048] For example: when the average current extracted by a single link is 1mA and the continuous extraction time is 100ps, the amount of charge lost is , and the amount of charge that the LDO can compensate within 1UI time is (unit is the same as above), so one LDO can carry 5-6 links.

[0049] For details, please refer to Figure 2, the performance of high-speed Chiplet interconnection circuit is not only related to the circuit design itself, but also greatly related to the stability of the power supply. Since the output at the TX end is a driver, the output current of the driver is large, and the current will change synchronously at high speed with the data stream, which needs to continuously extract current from the power supply. If the LDO cannot supplement the charge of the output node in time, it will cause the power supply voltage at the driver end to drop, and the power supply voltage at the driving end will affect the quality of the output signal at the TX end. The current of each transmission line will produce a transient peak current when the data jumps. Since the interconnection circuit is located at the edge of the Chiplet, and multiple transmission links need to be integrated in each Chiplet, the area requirement of the Chiplet interconnection circuit is very high. When designing the power supply of the Chiplet interconnection circuit, multiple transmission links can share an LDO, and the LDO can be optimized and designed to save the area of the decoupling capacitor needed, such as Figure 2 As shown, 20 transmission links share one LDO for power supply. When the number of shared links is too large, the distance between the transmission links is too far, and the changed charge cannot be supplemented to the transmission links far from the LDO in time, so the module can be split, for example, 5 transmission links share one LDO, and the like, Figure 3 As shown. By selecting the appropriate number of LDO transmission links shared, not only can each transmission link supplement the power supply charge in time, but also the size of the load capacitor of a single LDO can be reduced, making the layout design of the entire LDO more reasonable.

[0050] Further, a comparator is connected to the output end of the LDO, and the output end of the comparator is connected to a compensation tube; the output voltage of the LDO is detected by the comparator, and when the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release the charge in the data transmission period, to ensure the stability of the power supply voltage, and to reduce the value of the decoupling capacitor and save the chip area.

[0051] Preferably, a double comparator is used to detect the output voltage of the LDO, which is used to compare the size of the output voltage and the upper limit voltage and the lower limit voltage, respectively, to realize the rapid compensation or release of the charge and ensure the stability of the LDO output voltage, and realize the on-chip LDO.

[0052] Specifically, at the output node of the LDO, due to the change of the load current, the voltage at the output node of the LDO will also change, and in order to suppress the overshoot and voltage drop, two comparators are added in this case, which are used to detect the upper limit voltage and the lower limit voltage respectively, and when the LDO output voltage is higher than the upper limit preset threshold voltage VH or lower than the lower limit preset threshold voltage VL, the output voltage of the comparator will change. Then the output of the comparator is applied to the gate of a compensation tube. Since the charge extraction changes at the data rate, the result of each comparison only needs to supplement or release the charge within a period, so as to ensure the stability of the power supply voltage and the small influence on the output data. This way can greatly reduce the value of the required decoupling capacitor and save chip area.

[0053] The voltage fluctuation of the output node of the LDO is suppressed by the cooperation of the comparator and the compensation tube to ensure the quality of the output data and optimize the BER value. Please refer to Figure 4 , the output end of the LDO is connected to the input end of the first comparator (CMP1), and the other input end of the first comparator is connected to the first reference voltage (VREF1), which is used to indicate the lower limit voltage; the output end of the first comparator is connected to the first CTR module, and the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output end of the LDO.

[0054] The output end of the LDO is connected to the input end of the second comparator (CMP2), and the other input end of the second comparator is connected to the second reference voltage (VREF2), which is used to indicate the upper limit voltage; the output end of the second comparator is connected to the second CTR module, and the second CTR module is connected to the second Charge module, and the output of the second Charge module is connected to the output end of the LDO.

[0055] In the figure, VDDQ is the required stable output end power supply.

[0056] The target of the power supply compensation is to ensure that when the data 0-1 jumps, the lost charge can be compensated within one clock cycle, so as to not affect the transmission of the next 0-1 data.

[0057] The cooperative compensation mechanism is as follows: first, the LDO provides an initial value for VDDQ, and the data transmission causes the voltage of VDDQ to change, when VDDQ is lower than the voltage value VREF1, the comparator will output an effective bit, so as to control the subsequent Charge module and CTR module. The CTR module is a module used to adjust the unit charge current size of the Charge module. The CTR module is a adjustable module designed for testing.

[0058] That is, the LDO outputs an initial voltage VDDQ, the value of VDDQ changes during data transmission, when the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, and controls the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charge, so as to stabilize VDDQ in one clock cycle.

[0059] Or the LDO outputs an initial voltage VDDQ, the value of VDDQ changes during data transmission, when the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, and controls the second CTR module to adjust the unit charging current of the second Charge module to release excess charge, so as to stabilize VDDQ in one clock cycle.

[0060] By quickly compensating for the lost charge, the voltage can be quickly stabilized back to the normal VDDQ in one clock cycle, so as not to affect the transmission of the next 0-1 jump data. The output data quality is closely related to the power voltage of the Driver, which will directly affect the eye height of the output data eye diagram, and will also have a certain influence on the data rising and falling edges. As long as the voltage is stabilized back in one cycle, the eye diagram and data quality can be optimized, and the BER value is also optimized.

[0061] If the compensation tube is not added, the rate of the LDO cannot compensate for the lost charge in one clock cycle, and it needs to go through a certain period of time to compensate for the charge, so it will affect the eye diagram quality of the output data, and thus worsen the BER.

[0062] The embodiment adds a comparator and a compensation current tube in the LDO, which can quickly detect the output voltage fluctuation and compensate or release the charge to maintain the stability of the power supply and avoid the influence of the ripple on the signal quality. Through fast charge compensation, the decoupling capacitor area and power consumption are reduced, and the chip power consumption is reduced. A stable voltage is provided for each Chiplet to prevent power fluctuations from causing performance degradation or failure and improve system reliability. Reduce power ripple and noise, improve system anti-interference ability, and ensure stable operation. Ensure the stability of the TX driver power supply, reduce the influence of current fluctuation on the output signal, and improve signal integrity. Through fast charge compensation, reduce the interference of power voltage fluctuation on signal transmission, reduce the bit error rate (BER), and improve the data transmission reliability.

[0063] In summary, the power supply method for large-scale Chiplet high-speed parallel port interconnection can flexibly provide stable voltage for different Chiplets, support various power supply specifications and low-voltage design requirements. Compared with the traditional LDO scheme, this method can more accurately meet the power supply requirements of each Chiplet, thereby improving the power efficiency and performance of the entire system. The design has strong flexibility and can be customized according to different application requirements; manufacturers can design LDOs of different specifications according to different Chiplet application scenarios, further expanding the product line to meet the needs of different industries and customers. This customization capability has great market appeal in the chip industry and can help enterprises occupy a larger market share. With the continuous advancement of semiconductor technology, chip design is gradually moving towards miniaturization and high integration, and the high-precision power control characteristics of LDO are compatible with small-scale design. Using this method to power Chiplet not only adapts to the needs of advanced process technology, but also enables the control module to be faster, and by optimizing the design and manufacturing process, the cost of manufacturing can be reduced, enhancing the market competitiveness of the product.

[0064] Based on the same concept, the application also provides a power supply circuit for large-scale Chiplet high-speed parallel port interconnection, please refer to Figures 2-4 The circuit comprises:

[0065] Chiplet interconnection circuit, the TX end of any Chiplet is connected to a plurality of drivers, each driver is connected to a transmission link, forming a plurality of transmission links;

[0066] A plurality of LDO modules, each LDO module is powered by a plurality of transmission links in the distribution position area calculated by a preset algorithm, so that each transmission link can supplement power charge in time;

[0067] The output end of each LDO module is connected to a comparator, and the output end of the comparator is connected to a compensation tube; the comparator is used for detecting the output voltage of the LDO, and when the output voltage exceeds the preset range, the compensation tube is triggered to quickly compensate or release the charge in the data transmission period, so as to ensure the stability of the power supply voltage, and at the same time, the value of the decoupling capacitor is reduced, saving the chip area.

[0068] Among them, the output end of the LDO is connected to the input end of the first comparator, the other input end of the first comparator is connected to the first reference voltage, and the first reference voltage is used to indicate the lower limit voltage; the output end of the first comparator is connected to the first CTR module, the first CTR module is connected to the first Charge module, and the output of the first Charge module is connected to the output end of the LDO;

[0069] The LDO outputs an initial voltage VDDQ, the value of VDDQ changes in the process of data transmission, when the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, and the first CTR module adjusts the unit charging current of the first Charge module to compensate for the lost charge, so as to stabilize VDDQ in one clock cycle.

[0070] The output end of the LDO is connected to the input end of the second comparator, the other input end of the second comparator is connected to the second reference voltage, and the second reference voltage is used to indicate the upper limit voltage; the output end of the second comparator is connected to the second CTR module, the second CTR module is connected to the second Charge module, and the output end of the second Charge module is connected to the output end of the LDO;

[0071] The LDO outputs an initial voltage VDDQ, the value of VDDQ changes in the process of data transmission, when the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, and the second CTR module adjusts the unit charging current of the second Charge module to release the excess charge, so as to stabilize VDDQ in one clock cycle.

[0072] The circuit can realize the power supply method of the large-scale Chiplet high-speed parallel port interconnection described above, and provide stable voltage for different Chiplets.

[0073] The embodiments of the application are described in detail above with reference to the drawings, but the application is not limited to the above-described embodiments. Even if various changes are made to the application, as long as the changes fall within the scope of the claims of the application and equivalent technologies thereof, they still fall within the protection scope of the application.

Claims

1. A power supply method for high-speed parallel port interconnection between large-scale chiplets, characterized in that, Powering the chiplet interconnect circuit using a hybrid LDO power supply method includes the following steps: In a Chiplet interconnect circuit, the TX terminal is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links; The number of transmission links sharing a single LDO is calculated using a preset algorithm. Based on the number of transmission links and their distances, the required number and distribution locations of LDOs are obtained, ensuring that each transmission link is replenished with power charge in a timely manner. The preset algorithm calculates the relationship between the LDO's compensation performance and the number of links using the charge conservation formula, so as to precisely control the number of LDO power supply links.

2. The power supply method for high-speed parallel port interconnection between large-scale Chiplet interfaces according to claim 1, characterized in that, A comparator is connected to the output of the LDO, and a compensation transistor is connected to the output of the comparator. The LDO's output voltage is detected by a comparator. When the output voltage exceeds the preset range, the compensation transistor is triggered to quickly compensate or release the charge during the data transmission cycle, ensuring the power supply voltage is stable. At the same time, the value of the decoupling capacitor is reduced, saving chip area.

3. The power supply method for high-speed parallel port interconnection between large-scale Chiplet according to claim 2, characterized in that, The output voltage of the LDO is detected by dual comparators, which are used to compare the output voltage with the upper and lower limit voltages respectively, thereby realizing rapid charge compensation or release, ensuring the stability of the LDO output voltage, and realizing an on-chip LDO.

4. The power supply method for high-speed parallel port interconnection between large-scale Chiplet according to claim 2, characterized in that, By using the comparator and compensation transistor in tandem, voltage fluctuations at the LDO output node are suppressed, ensuring output data quality and optimizing the BER value.

5. The power supply method for high-speed parallel port interconnection between large-scale Chiplet according to claim 4, characterized in that, Suppressing voltage fluctuations at the LDO output node through the coordinated operation of comparators and compensation transistors further includes: The LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is lower than the preset lower limit voltage, the comparator outputs a valid bit to control the compensation transistor to adjust the unit charging current and compensate for the lost charge, so as to stabilize VDDQ within one clock cycle.

6. The power supply method for high-speed parallel port interconnection between large-scale Chiplet according to claim 3, characterized in that, The output of the LDO is connected to the input of a first comparator, and the other input of the first comparator is connected to a first reference voltage, which is used to indicate the lower limit voltage. The output of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output of the LDO. The LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, controlling the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charge, so as to stabilize VDDQ within one clock cycle.

7. The power supply method for high-speed parallel port interconnection between large-scale Chiplet according to claim 3, characterized in that, The output of the LDO is connected to the input of a second comparator, and the other input of the second comparator is connected to a second reference voltage, which is used to indicate the upper limit voltage. The output of the second comparator is connected to a second CTR module, the second CTR module is connected to a second Charge module, and the output of the second Charge module is connected to the output of the LDO. The LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, controlling the second CTR module to adjust the unit charging current of the second Charge module to release excess charge and stabilize VDDQ within one clock cycle.

8. A power supply circuit for high-speed parallel port interconnection between large-scale chiplets, characterized in that, include: Chiplet interconnect circuits: the TX terminal of any chipplet is connected to multiple drivers, and each driver is connected to a transmission link, forming multiple transmission links; Multiple LDO modules, each distributed according to a preset algorithm, supply power to multiple transmission links within the distribution area, ensuring timely replenishment of power charge for each transmission link; wherein, the preset algorithm calculates the relationship between the compensation performance of the LDO and the number of links using the charge conservation formula, so as to precisely control the number of LDO power supply links; The output of each LDO module is connected to a comparator, and the output of the comparator is connected to a compensation transistor. The comparator is used to detect the output voltage of the LDO. When the output voltage exceeds the preset range, it triggers the compensation transistor to quickly compensate or release the charge during the data transmission cycle, ensuring the stability of the power supply voltage and reducing the value of the decoupling capacitor to save chip area.

9. The power supply circuit for high-speed parallel port interconnection between large-scale Chiplet ports according to claim 8, characterized in that, The output of the LDO is connected to the input of the first comparator, and the other input of the first comparator is connected to a first reference voltage, which is used to indicate the lower limit voltage. The output of the first comparator is connected to a first CTR module, the first CTR module is connected to a first Charge module, and the output of the first Charge module is connected to the output of the LDO. The LDO outputs an initial voltage VDDQ. The value of VDDQ changes during data transmission. When the value of VDDQ is lower than the first reference voltage, the first comparator outputs a valid bit, controlling the first CTR module to adjust the unit charging current of the first Charge module to compensate for the lost charge, so as to stabilize VDDQ within one clock cycle.

10. The power supply circuit for high-speed parallel port interconnection between large-scale Chiplet ports according to claim 8, characterized in that, The output of the LDO is connected to the input of a second comparator, the other input of which is connected to a second reference voltage, which indicates the upper limit voltage. The output of the second comparator is connected to a second CTR module, which is connected to a second Charge module. The output of the second Charge module is connected to the output of the LDO. The LDO outputs an initial voltage VDDQ, the value of which changes during data transmission. When the value of VDDQ is higher than the second reference voltage, the second comparator outputs a valid bit, controlling the second CTR module to adjust the unit charging current of the second Charge module to release excess charge and stabilize VDDQ within one clock cycle.

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