Optimization circuit and communication equipment for digital truncation error

Abstract

The present invention provides a digital truncation error optimization circuit and communication device, wherein the digital truncation error optimization circuit includes: a first adder, wherein a first input end of the first adder is connected to a signal input end; a truncation circuit, wherein an input end of the truncation circuit is connected to an output end of the first adder, and an output end of the truncation circuit is connected to a signal output end, the truncation circuit being used to truncate the signal output by the first adder to obtain a truncation signal; and a truncation error processing circuit, wherein a first input end of the truncation error processing circuit is connected to an output end of the truncation circuit, a second input end of the truncation error processing circuit is connected to an output end of a frequency factor generating circuit, a third input end of the truncation error processing circuit is connected to an output end of the first adder, and an output end of the truncation error processing circuit is connected to a second input end of the first adder. Through the present invention, the effect of improving the signal-to-noise ratio within the signal band is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular to a digital truncation error optimization circuit and a communication device. Background Art

[0002] Digital signal processing circuits require fixed-point processing of signal bit widths. Multiplication and addition often result in bit-width expansion of the calculation results. For example, the multiplication of an N-bit unsigned number by an M-bit unsigned number produces an N+M-bit result. Without any processing of this result, the bit width of the subsequent link will continue to expand, resulting in an extremely high link implementation cost. To reduce this link implementation cost, the N+M-bit calculation result is typically truncated to ensure that the resource overhead of the subsequent link is controllable. However, truncation of the calculation result is effectively equivalent to a requantization process in the digital domain, which discards the precision of the input data and introduces truncation errors. In related technologies, circuits that optimize truncation errors often incur significant power consumption overhead, resulting in a reduced signal-to-noise ratio.

[0003] It can be seen from this that the related art has the problem of low signal-to-noise ratio of the optimized truncation error circuit.

[0004] Currently, no effective solution has been proposed to the above-mentioned problems existing in the related technologies. Summary of the Invention

[0005] Embodiments of the present invention provide a digital truncation error optimization circuit and a communication device to at least solve the problem of low signal-to-noise ratio of the truncation error optimization circuit in the related art.

[0006] According to one embodiment of the present invention, a digital truncation error optimization circuit is provided, comprising: a first adder, wherein a first input terminal of the first adder is connected to a signal input terminal; a truncation circuit, wherein an input terminal of the truncation circuit is connected to an output terminal of the first adder, and an output terminal of the truncation circuit is connected to a signal output terminal, the truncation circuit being configured to truncate a signal output by the first adder to obtain a truncation signal, and output the truncation signal to the signal output terminal; a frequency factor generation circuit being configured to generate a frequency modulation factor based on carrier frequency information of an input signal sent by the signal input terminal; and a truncation error processing circuit, wherein a first input terminal of the truncation error processing circuit is connected to an output terminal of the truncation circuit, a second input terminal of the truncation error processing circuit is connected to an output terminal of the frequency factor generation circuit, a third input terminal of the truncation error processing circuit is connected to an output terminal of the first adder, and an output terminal of the truncation error processing circuit is connected to a second input terminal of the first adder, the truncation error processing circuit being configured to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder, and the truncation signal, and send the error adjustment signal to the first adder.

[0007] In an exemplary embodiment, the truncation circuit includes a low-bit truncation circuit.

[0008] In an exemplary embodiment, the truncation error processing circuit includes: a bit filling circuit, the input end of the bit filling circuit is connected to the output end of the truncation circuit, and is used to perform a bit filling operation on the truncated signal to obtain a bit filling signal, wherein the bit width of the bit filling signal is the same as the bit width of the input signal; a second adder, the first input end of the second adder is connected to the output end of the bit filling circuit, and the second input end of the second adder is connected to the output end of the first adder, and is used to subtract the signal output by the first adder from the bit filling signal to obtain an error signal; a first multiplier, the first input end of the first multiplier is connected to the output end of the second adder, the second input end of the first multiplier is connected to the output end of the frequency factor generation circuit, and the output end of the first multiplier is connected to the second input end of the first adder, and is used to multiply the error signal by the frequency modulation factor to obtain a product signal, and input the product signal into the first adder.

[0009] In an exemplary embodiment, the truncation error processing circuit further includes: a first delay circuit, and the output end of the second adder is connected to the first multiplier through the first delay circuit.

[0010] In an exemplary embodiment, the digital truncation error optimization circuit also includes: a judgment circuit, the input end of the judgment circuit is connected to the signal input end, for receiving the input signal and judging whether two adjacent signals in the time domain included in the input signal are the same; if they are the same, the truncation error processing circuit is controlled to be turned off; if they are not the same, the truncation error processing circuit is controlled to be enabled.

[0011] In an exemplary embodiment, the judgment circuit includes: a second delay circuit, the input end of the second delay circuit is connected to the signal input end, and is used to delay the input signal; a judgment sub-circuit, the first input end of the judgment sub-circuit is connected to the signal input end, and the second input end of the judgment sub-circuit is connected to the output end of the second delay circuit, and is used to judge whether the signal sent by the signal input end is the same as the signal output by the output end of the second delay circuit.

[0012] In an exemplary embodiment, the frequency factor generating circuit generates a frequency modulation factor based on the carrier frequency information of the input signal sent from the signal input terminal in the following manner: determining the ratio of the carrier frequency information to the sampling frequency of the input signal; and determining the frequency modulation factor based on the ratio.

[0013] In an exemplary embodiment, the frequency factor generation circuit determines the frequency modulation factor based on the ratio in the following manner: determining a first product of the ratio and an imaginary unit; and determining an exponential function with a natural constant as the base and the first product as the exponent as the frequency modulation factor.

[0014] In an exemplary embodiment, the z-transform truncation error optimization transfer function of the digital truncation error optimization circuit is as follows: ; Wherein, X(z) represents the input signal, E(z) represents the truncation error, and Y(z) represents the output signal of the digital truncation error optimization circuit.

[0015] According to another embodiment of the present invention, a method for optimizing digital truncation error is provided, which is applied to the digital truncation error optimization circuit in any of the above embodiments, including: receiving a first signal sent by the signal input end; generating the frequency modulation factor based on the carrier frequency information of the first signal; truncation processing the first signal to obtain the truncation signal; generating the error adjustment signal based on the frequency modulation factor, the truncation signal and a second signal, wherein the second signal is a signal sent by the signal input end after sending the first signal; adjusting a third signal based on the error adjustment signal, wherein the third signal is a signal sent by the signal input end after sending the second signal, and the input signal includes the first signal, the second signal and the third signal.

[0016] In an exemplary embodiment, generating the frequency modulation factor based on the carrier frequency information of the first signal includes: determining a ratio of the carrier frequency information to a sampling frequency for sampling the input signal; and determining the frequency modulation factor based on the ratio.

[0017] In an exemplary embodiment, determining the frequency modulation factor based on the ratio includes: determining a first product of the ratio and an imaginary unit; and determining an exponential function having a natural constant as a base and the first product as an exponent as the frequency modulation factor.

[0018] In an exemplary embodiment, generating the error adjustment signal based on the frequency modulation factor, the truncated signal and the second signal includes: padding the truncated signal to obtain a padding signal, wherein the bit width of the padding signal is the same as the bit width of the input signal; determining a difference between the second signal and the padding signal; after a first predetermined time delay, determining a second product of the difference and the frequency modulation factor; and determining the second product as the error adjustment signal.

[0019] In an exemplary embodiment, adjusting the third signal based on the error adjustment signal includes: performing a sum operation on the third signal and the error adjustment signal to adjust the third signal.

[0020] In an exemplary embodiment, before generating the error adjustment signal based on the frequency modulation factor, the truncation signal and the second signal, the method further includes: obtaining a fourth signal, wherein the fourth signal is a signal sent by the signal input terminal before sending the first signal, and the input signal includes the fourth signal; when the first signal is different from the fourth signal, generating the error adjustment signal based on the frequency modulation factor, the truncation signal and the second signal.

[0021] According to another embodiment of the present invention, a cascaded digital signal processing circuit is provided, comprising: a plurality of digital signal processing circuits, a frequency information configuration circuit, and a plurality of digital truncation error optimization circuits as described in any one of the above embodiments; the frequency information configuration circuits are respectively connected to the frequency factor generation circuits of the plurality of digital truncation error optimization circuits, for providing carrier frequency information to the frequency factor generation circuits; the output end of each of the digital signal processing circuits is connected to one of the digital truncation error optimization circuits to obtain a plurality of connection circuits, and different digital signal processing circuits are connected to different digital truncation error optimization circuits; the plurality of connection circuits are connected in series to form a multi-stage digital signal processing circuit.

[0022] According to another embodiment of the present invention, a radio frequency transmitting device is also provided, comprising a first baseband module, a digital-to-analog conversion module, and a cascaded digital signal processing circuit as in the above embodiment, wherein the output end of the first baseband module is connected to the input end of the digital-to-analog conversion module through the cascaded digital signal processing circuit.

[0023] According to another embodiment of the present invention, a radio frequency receiving device is also provided, including a second baseband module, an analog-to-digital conversion module and a cascaded digital signal processing circuit as in the above embodiment, wherein the output end of the analog-to-digital conversion module is connected to the input end of the second baseband module through the cascaded digital signal processing circuit.

[0024] According to another embodiment of the present invention, a radio frequency digital-to-analog converter is also provided, comprising: a filtering circuit, the filtering circuit comprising a sampling rate converter and a digital truncation error optimization circuit as in any of the above embodiments, the output end of the sampling rate converter being connected to the signal input end of the digital truncation error optimization circuit; a digital frequency shifting circuit, the digital frequency shifting circuit comprising a second multiplier, a digitally controlled oscillator and the digital truncation error optimization circuit, the first input end of the second multiplier being connected to the output end of the filtering circuit, the second input end of the second multiplier being connected to the digitally controlled oscillator, and the output end of the second multiplier being connected to the input end of the digital truncation error optimization circuit; a digital-to-analog converter, the input end of the digital-to-analog converter being connected to the output end of the digital frequency shifting circuit; a frequency controller, the frequency controller being connected to the frequency factor generation circuit of each of the digital truncation error optimization circuits, for providing carrier frequency information to the frequency factor generation circuit.

[0025] In an exemplary embodiment, there are multiple filtering circuits and multiple digital frequency shifting circuits, and the multiple digital frequency shifting circuits are arranged at intervals. The input end of each digital frequency shifting circuit is connected to the output end of one filtering circuit, and the output end of the digital frequency shifting circuit is connected to the input end of other filtering circuits.

[0026] According to another embodiment of the present invention, a communication device is also provided, including the digital truncation error optimization circuit as described in any of the above embodiments, or, including the cascaded digital signal processing circuit as described in the above embodiments, or, including the radio frequency transmitting device as described in the above embodiments, or including the radio frequency receiving device as described in the above embodiments, or, including the radio frequency digital-to-analog converter as described in any of the above embodiments.

[0027] In an exemplary embodiment, the communication device includes one of the following: a base station set in a satellite, a base station set on the ground, and a terminal device.

[0028] In an exemplary embodiment, the terminal device includes: a mobile phone, a car, and a ship.

[0029] Through the present invention, since the frequency factor generation circuit can generate a frequency modulation factor based on the carrier frequency information of the input signal, the truncation error processing circuit can generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder and the truncation signal, the first adder can add the error adjustment signal to the input signal and input the added signal to the truncation circuit, and the truncation circuit can perform truncation processing on the added signal and output it, thereby adjusting the error shaping frequency domain response curve according to the actual frequency point of the carrier, thereby improving the signal-to-noise ratio within the signal band. Therefore, the problem of low signal-to-noise ratio of the optimized truncation error circuit existing in the related art can be solved, and the effect of improving the signal-to-noise ratio within the signal band can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a structural diagram of a circuit for optimizing digital truncation error according to an embodiment of the present invention;

[0031] Figure 2 1 is a specific structural diagram of a circuit for optimizing digital truncation error according to an embodiment of the present invention;

[0032] Figure 3 3. This is a diagram showing the optimization effect of the total integrated energy of the truncation error noise within different bandwidths away from the center frequency of the signal according to an embodiment of the present invention;

[0033] Figure 4 2. It is a schematic diagram of the application effect in a single-stage module according to an embodiment of the present invention;

[0034] Figure 5is a structural block diagram of a cascaded digital signal processing circuit according to an embodiment of the present invention;

[0035] Figure 6 is a structural block diagram of a radio frequency transmitting device according to an embodiment of the present invention;

[0036] Figure 7 is a schematic diagram of a specific structure of a radio frequency transmitting device according to an embodiment of the present invention;

[0037] Figure 8 is a structural block diagram of a radio frequency receiving device according to an embodiment of the present invention;

[0038] Figure 9 is a schematic diagram of a specific structure of a radio frequency receiving device according to an embodiment of the present invention;

[0039] Figure 10 is a structural block diagram of a radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0040] Figure 11 is a schematic diagram of a specific structure of a radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0041] Figure 12 is a schematic diagram of a spectrum of an input test signal input to a radio frequency digital-to-analog converter according to an embodiment of the present invention;

[0042] Figure 13 FIG. 4 is a schematic diagram of a digital signal spectrum at a DAC input according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0044] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] In this embodiment, a circuit for optimizing digital truncation error is provided. Figure 1 FIG. 1 is a structural diagram of a circuit for optimizing digital truncation error according to an embodiment of the present invention. Figure 1 As shown, the optimization circuit for the digital truncation error includes:

[0046] A first adder 12, wherein a first input terminal of the first adder is connected to the signal input terminal;

[0047] a truncation circuit 14, wherein an input end of the truncation circuit is connected to the output end of the first adder, and an output end of the truncation circuit is connected to the signal output end, the truncation circuit is configured to truncate the signal output by the first adder to obtain a truncation signal, and output the truncation signal to the signal output end;

[0048] A frequency factor generating circuit 16, configured to generate a frequency modulation factor based on the carrier frequency information of the input signal sent by the signal input terminal;

[0049] A truncation error processing circuit 18, wherein the first input terminal of the truncation error processing circuit is connected to the output terminal of the truncation circuit, the second input terminal of the truncation error processing circuit is connected to the output terminal of the frequency factor generating circuit, the third input terminal of the truncation error processing circuit is connected to the output terminal of the first adder, and the output terminal of the truncation error processing circuit is connected to the second input terminal of the first adder. The truncation error processing circuit is used to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder and the truncation signal, and send the error adjustment signal to the first adder.

[0050] In the above embodiment, the truncation error may be an error caused by truncation of the signal bit width in the digital signal processing circuit. Typically, the low-order bits of the data are independent of the envelope information and are random. The truncation error can be approximately equivalent to Gaussian noise, exhibiting a uniform distribution in the frequency domain. The truncation error power calculation formula can be expressed as:

[0051] Pn = 10*log10((1 / 2^(b-1)) / 12) (1)

[0052] Where b is the data width after truncation, in dBfs. If the truncation error power spectrum density is considered, the calculation formula is:

[0053] Pn_Hz = 10*log10((1 / 2^(b-1)) / 12)-10*log10(fs)(2)

[0054] Where fs is the digital sampling rate, and the error power spectral density is expressed in dBfs / Hz. Equation (2) shows that when the sampling rate is high and the signal has a large oversampling ratio, the truncation error is evenly distributed across the entire sampling frequency band, reducing its impact on the effective signal-to-noise ratio (SNR).

[0055] In the above embodiment, the first adder can be a digital logic circuit configured to perform an addition operation on two or more signals. A first input terminal of the first adder can be connected to a signal input terminal. The signal input terminal inputs an input signal to the first adder. The input signal can be a discrete digital signal in the time domain. Alternatively, it can be a high-bitwidth signal processed by a preceding digital module. A truncation circuit can be used to truncate the bit width of the high-bitwidth signal to ensure that downstream link resource overhead is controllable.

[0056] In the above embodiment, the truncation circuit may be a circuit for rounding off the signal or a circuit for directly truncate the signal. When the truncation circuit is a direct truncation circuit, the truncation circuit may truncate the bit width of the received signal according to a fixed length, wherein the fixed length may be a pre-configured length.

[0057] In the above embodiment, the frequency factor generation circuit can generate a frequency modulation factor according to the carrier frequency information of the input signal sent by the signal input terminal. The carrier frequency information can be configured in advance in the frequency factor generation circuit. The frequency modulation factor can be expressed as exp(jω c / ω s ), where ω c is the carrier frequency information of the input signal, that is, the carrier frequency information configured by the user, ω s is the signal sampling rate at the node position. The frequency factor generation circuit can be implemented by digital signal processing (DSP / FPGA) to output the frequency modulation factor exp(jω c / ω s ).

[0058] In the above embodiment, the truncation error processing circuit can pad the truncated signal, subtract the padded signal from the high-precision signal before truncation to obtain an error signal, and then process the error signal and inversely pad it to the input signal. This digital truncation error optimization circuit can reduce the truncation error energy within the signal's effective bandwidth and adjust the circuit's frequency domain response based on the signal's frequency, thereby improving the signal-to-noise ratio within the signal band. This circuit also features automatic protection in special scenarios to prevent performance degradation.

[0059] In the above embodiment, truncation is a common data compression method in digital signal processing, but it can introduce errors. Adjusting this error through a frequency modulation factor effectively reduces truncation errors and improves signal processing accuracy. For example, in radio frequency communication systems, carrier frequency information is a key parameter. The frequency modulation factor generated using this information can accurately compensate for frequency response changes caused by truncation, ensuring signal integrity. Furthermore, this technical solution is applicable not only to radio frequency communications but also to any system requiring digital signal processing, including but not limited to audio processing and image processing.

[0060] Through the present invention, since the frequency factor generation circuit can generate a frequency modulation factor based on the carrier frequency information of the input signal, the truncation error processing circuit can generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder and the truncation signal, the first adder can add the error adjustment signal to the input signal and input the added signal to the truncation circuit, and the truncation circuit can perform truncation processing on the added signal and output it, thereby adjusting the error shaping frequency domain response curve according to the actual frequency point of the carrier, thereby improving the signal-to-noise ratio within the signal band. Therefore, the problem of low signal-to-noise ratio of the optimized truncation error circuit existing in the related art can be solved, and the effect of improving the signal-to-noise ratio within the signal band can be achieved.

[0061] In an exemplary embodiment, the truncation circuit includes a low-bit truncation circuit. In this embodiment, the low-bit truncation circuit can truncate the signal output by the first adder starting from the low bit, truncating N bits to obtain a truncated signal, where N can be a natural number such as 1, 2, 3, or 5. N can be specifically designed according to the application scenario, and the present invention does not limit the specific value of N.

[0062] In an exemplary embodiment, the truncation error processing circuit includes: a bit-filling circuit, the input end of the bit-filling circuit is connected to the output end of the truncation circuit, and is used to perform a bit-filling operation on the truncation signal to obtain a bit-filling signal, wherein the bit width of the bit-filling signal is the same as the bit width of the input signal; a second adder, the first input end of the second adder is connected to the output end of the bit-filling circuit, and the second input end of the second adder is connected to the output end of the first adder, and is used to subtract the signal output by the first adder from the bit-filling signal to obtain an error signal; a first multiplier, the first input end of the first multiplier is connected to the output end of the second adder, the second input end of the first multiplier is connected to the output end of the frequency factor generation circuit, and the output end of the first multiplier is connected to the second input end of the first adder, and is used to multiply the error signal with the frequency modulation factor to obtain a product signal, and input the product signal into the first adder. In this embodiment, the specific structure diagram of the digital truncation error optimization circuit can be found in the attached figure. Figure 2 ,like Figure 2 As shown, the optimization circuit for digital truncation error includes a first adder 12, a truncation circuit (ie Figure 2 The truncation bit Nbit in the circuit) 14, the frequency factor generation circuit (i.e. Figure 2 Frequency factor generation in) 16, truncation error processing circuit 18. The truncation error processing circuit 18 may include a filling circuit (ie Figure 2 The low-order bit padding (N bits) 1802, a second adder 1804, and a first multiplier 1806 are connected. The padding circuit can be a low-order zero padding circuit that pads the low-order bits of the truncated signal with zeros to generate a padding signal. The second adder can subtract the padding signal from the input signal to obtain an error signal, multiply the error signal by the frequency modulation factor to obtain a product signal, and input the product signal to the first adder. The error signal can be multiplied by the frequency modulation factor directly or after a delay.

[0063] In the above embodiment, the padding operation is used to restore the bit width of the truncated signal to match that of the original signal, facilitating subsequent error calculation. The combination of the second adder and the first multiplier can accurately calculate the truncation error based on the frequency modulation factor and compensate it through a feedback mechanism, thereby significantly improving the accuracy and stability of signal processing. For example, in wireless communication systems, this error compensation mechanism can effectively reduce signal distortion and improve communication quality. The introduction of this technical feature solves the problem of error accumulation in traditional truncation operations and is applicable not only to radio frequency communications, but also to any scenario requiring digital signal processing, including but not limited to satellite communications and fiber optic communications.

[0064] In an exemplary embodiment, the truncation error processing circuit further includes: a first delay circuit, and the output end of the second adder is connected to the first multiplier through the first delay circuit. Figure 2 The truncation error processing circuit may further include a first delay circuit 1808 for delaying the error signal output by the second adder, and multiplying the delayed error signal by the frequency generation factor.

[0065] In the above-described embodiment, the delay circuit is introduced to ensure that the error signal and the frequency modulation factor are aligned in time, thereby avoiding inaccurate error compensation caused by asynchronous signal processing timing. For example, in high-speed digital signal processing, the timing of the signal has a significant impact on the processing results. The first delay circuit can ensure that the error adjustment signal and the original signal are precisely matched in time, thereby improving the accuracy of error compensation. The use of this technical feature solves the problem of timing synchronization in signal processing and is applicable not only to radio frequency communications, but also to any digital signal processing system requiring precise timing control, including but not limited to real-time audio processing and video encoding.

[0066] In an exemplary embodiment, the digital truncation error optimization circuit further includes: a judgment circuit, wherein the input end of the judgment circuit is connected to the signal input end, and is used to receive the input signal and judge whether two adjacent signals in the time domain included in the input signal are the same. If they are the same, the truncation error processing circuit is controlled to be turned off; if they are not the same, the truncation error processing circuit is controlled to be enabled. In this embodiment, continue to refer to the attached Figure 2 , the optimization circuit of digital truncation error also includes a judgment circuit ( Figure 2 Input signal determination 1810 determines whether the two input signals are identical. If so, the truncation error processing circuit is disabled; otherwise, the truncation error processing circuit is enabled. The determination circuit determines whether the input signals of two adjacent time-domain sampling points are identical. If so, the truncation error processing circuit is disabled. This is because when the input signal exhibits DC input characteristics, the truncation error distribution does not conform to the random characteristics of white noise. The truncation optimization circuit may generate periodic time-domain errors, resulting in spurious output signals. Therefore, a determination module is required as a maintenance protection.

[0067] In the above-mentioned embodiment, the judgment circuit is introduced to intelligently control error processing, avoiding unnecessary error compensation when signal changes are not significant, thereby saving power resources and improving device energy efficiency. The use of this technical feature solves the problem of energy waste in traditional signal processing and is applicable not only to radio frequency communications but also to any digital signal processing device that requires energy-saving optimization, including but not limited to mobile phones and portable audio players.

[0068] In an exemplary embodiment, the judgment circuit includes: a second delay circuit, the input end of the second delay circuit is connected to the signal input end, and is used to delay the input signal; a judgment sub-circuit, the first input end of the judgment sub-circuit is connected to the signal input end, and the second input end of the judgment sub-circuit is connected to the output end of the second delay circuit, and is used to judge whether the signal sent by the signal input end is the same as the signal output by the output end of the second delay circuit. In this embodiment, continue to refer to the attached Figure 2 The judgment circuit 1810 may further include a second delay circuit 1812, which may delay the input signal so that the judgment circuit may determine whether two adjacent signals in the time domain are identical.

[0069] In the above embodiment, the judgment circuit can accurately identify the change of the signal through delay and comparison, and intelligently control the switch of the truncation error processing circuit, thereby saving power resources when the signal change is not significant.

[0070] In the above embodiment, the truncation error optimization transfer function (Z-transform expression) of the digital truncation error optimization circuit can be: , where X(z) is the input signal, E(z) is the intercept error, and Y(z) is the output signal. c Represents the center frequency of the carrier normalized to the range of -π~π. In the general case where the carrier is located at baseband frequency 0, that is, ω c =0 for analysis; when |1-z -1 When |<1, the corresponding frequency band range is -π / 3~π / 3; that is, within the range of -π / 3~π / 3 from the carrier center, the optimized truncation error power spectrum density is smaller than the normal truncation. Considering the full frequency band range of -π~π, That is, from the perspective of the entire frequency band, this truncation optimization method does not reduce the total power of the truncation error, but optimizes the truncation error spectral density in a specific frequency band to achieve a shaping effect. The optimization effect diagram of the total integrated energy of the truncation error noise in different bandwidths away from the signal center frequency can be found in the attached figure. Figure 3 ,like Figure 3 As shown in the figure, the integral bandwidth is normalized to 0~π. It can be inferred that in the oversampling scenario (the sampling rate is much larger than the carrier bandwidth scenario), the optimization circuit benefits of digital truncation error are particularly obvious.

[0071] In the above embodiment, the optimization circuit for digital truncation error can be applied to a single-stage module. The schematic diagram of the application effect in the single-stage module can be found in the attached FIG. Figure 4 ,like Figure 4As shown in the figure, two sine waves are input, separated by 10 MHz, with a center frequency of 25 MHz and a sampling rate of 245.76 MHz. The first curve shows the 16-bit input signal; the second curve shows the output signal directly truncated to 12 bits using the nearest bit error; and the third curve shows the output signal truncated to 12 bits using a circuit optimized for digital truncation error. A significant reduction in the noise floor within and near the effective signal band can be observed.

[0072] In an exemplary embodiment, the frequency factor generation circuit generates a frequency modulation factor based on the carrier frequency information of the input signal sent by the signal input terminal in the following manner: determining a ratio of the carrier frequency information to a sampling frequency for sampling the input signal; and determining the frequency modulation factor based on the ratio. In this embodiment, the frequency factor generation circuit can generate a frequency modulation factor based on the carrier frequency information of the input signal. For example, when the carrier frequency information is When the sampling frequency is w s , according to / w s Determine the frequency modulation factor. Generating the frequency modulation factor based on the carrier frequency information and the sampling frequency ensures that the frequency modulation factor can be dynamically adjusted according to the frequency characteristics of the signal, improving the adaptability of error compensation.

[0073] In an exemplary embodiment, the frequency factor generation circuit determines the frequency modulation factor based on the ratio by: determining a first product of the ratio and an imaginary unit; and determining an exponential function with a natural constant as the base and the first product as the exponent as the frequency modulation factor. In this embodiment, the frequency modulation factor can be expressed as exp(jw c / w s ), where j is the imaginary unit. The frequency modulation factor is generated through mathematical operations, ensuring a precise match with the signal's frequency characteristics. For example, by calculating the ratio of the signal frequency to the sampling frequency and multiplying it by the imaginary unit, and then applying the exponential function of the natural constant e, a modulation factor closely related to the signal's frequency characteristics can be obtained, thereby improving the accuracy and effectiveness of error compensation.

[0074] In an exemplary embodiment, the z-transform truncation error optimization transfer function of the digital truncation error optimization circuit is as follows: Wherein, X(z) represents the input signal, E(z) represents the truncation error, and Y(z) represents the output signal of the digital truncation error optimization circuit. In this embodiment, w c It can be represented as the carrier center frequency normalized to the range of -π to π. By using the z-transform transfer function, we can analyze the performance of the circuit at different frequencies and guide the optimization of circuit parameters, thereby achieving better signal processing results in practical applications.

[0075] In this embodiment, a method for optimizing digital truncation error is provided, which can be applied to the digital truncation error optimization circuit in any of the above embodiments. The method includes:

[0076] receiving a first signal sent by the signal input terminal;

[0077] generating the frequency modulation factor based on the carrier frequency information of the first signal;

[0078] performing truncation processing on the first signal to obtain the truncation signal;

[0079] generating the error adjustment signal based on the frequency modulation factor, the truncation signal, and a second signal, wherein the second signal is a signal sent by the signal input terminal after sending the first signal;

[0080] A third signal is adjusted based on the error adjustment signal, wherein the third signal is a signal sent by the signal input terminal after sending the second signal, and the input signal includes the first signal, the second signal, and the third signal.

[0081] In this embodiment, the input signal can be a digital signal or a discrete signal, and the signal input terminal can transmit a digital signal. When the first signal is input, a frequency modulation factor can be generated based on the carrier frequency information of the first signal. When other signals have been input to the signal input terminal before the first signal, a first error adjustment signal can be generated based on the other signals. The first signal passes through a first adder and is added to the first error adjustment signal to obtain an added signal, which is then input to a truncation circuit. The truncation circuit performs truncation processing on the added signal. When no other signals have been input to the signal input terminal before the first signal, there is no first error adjustment signal. The first signal passes through the first adder and is input to the truncation circuit. The truncation circuit performs truncation processing on the first signal to obtain a truncation signal. Therefore, the truncation signal can be a signal obtained by directly truncation of the first signal or a signal obtained by truncation of the added signal.

[0082] In this embodiment, an error adjustment signal may be generated according to the frequency modulation factor, the truncation signal and the second signal, and the third signal may be adjusted according to the obtained error adjustment signal. After the third signal is adjusted, the adjusted third signal may be truncation processed and then output.

[0083] In this embodiment, the above method may be a cyclic execution method, which realizes effective compensation for truncation errors through a dynamic adjustment mechanism, thereby improving the accuracy and stability of signal processing.

[0084] Through the present invention, since a frequency modulation factor can be generated according to the carrier frequency information of the input signal, an error adjustment signal can be generated according to the frequency modulation factor, the second signal and the truncation signal, and the third signal is truncation-processed and then output by the error adjustment signal, it is possible to adjust the error shaping frequency domain response curve according to the actual frequency point of the carrier, thereby improving the signal-to-noise ratio within the signal band. Therefore, the problem of low signal-to-noise ratio of the optimized truncation error circuit existing in the related art can be solved, and the effect of improving the signal-to-noise ratio within the signal band can be achieved.

[0085] In an exemplary embodiment, generating the frequency modulation factor based on the carrier frequency information of the first signal includes: determining a ratio of the carrier frequency information to a sampling frequency for sampling the input signal; and determining the frequency modulation factor based on the ratio. In this embodiment, the frequency factor generation circuit can generate the frequency modulation factor based on the carrier frequency information of the input signal. For example, when the carrier frequency information is When the sampling frequency is w s , according to / w s Determine the frequency modulation factor. Generating the frequency modulation factor based on the carrier frequency information and the sampling frequency ensures that the frequency modulation factor can be dynamically adjusted according to the frequency characteristics of the signal, improving the adaptability of error compensation.

[0086] In an exemplary embodiment, determining the frequency modulation factor based on the ratio includes: determining a first product of the ratio and an imaginary unit; and determining an exponential function with a natural constant as the base and the first product as the exponent as the frequency modulation factor. In this embodiment, the frequency modulation factor can be expressed as exp(jw c / w s ), where j is the imaginary unit. The frequency modulation factor is generated through mathematical operations, ensuring a precise match with the signal's frequency characteristics. For example, by calculating the ratio of the signal frequency to the sampling frequency and multiplying it by the imaginary unit, and then applying the exponential function of the natural constant e, a modulation factor closely related to the signal's frequency characteristics can be obtained, thereby improving the accuracy and effectiveness of error compensation.

[0087] In an exemplary embodiment, generating the error adjustment signal based on the frequency modulation factor, the truncated signal and the second signal includes: padding the truncated signal to obtain a padding signal, wherein the bit width of the padding signal is the same as the bit width of the input signal; determining a difference between the second signal and the padding signal; after a first predetermined time delay, determining a second product of the difference and the frequency modulation factor; and determining the second product as the error adjustment signal.

[0088] In one exemplary embodiment, adjusting the third signal based on the error adjustment signal includes summing the third signal with the error adjustment signal to adjust the third signal. In this embodiment, the third signal and the error adjustment signal can be summed to obtain an adjusted signal, and the adjusted signal can be truncated and output. This achieves signal error compensation through simple mathematical operations, improving signal processing efficiency and accuracy.

[0089] In an exemplary embodiment, before generating the error adjustment signal based on the frequency modulation factor, the truncation signal, and the second signal, the method further includes: obtaining a fourth signal, wherein the fourth signal is a signal sent by the signal input terminal before sending the first signal, and the input signal includes the fourth signal; and if the first signal and the fourth signal differ, generating the error adjustment signal based on the frequency modulation factor, the truncation signal, and the second signal. In this embodiment, before adjusting the signal, it is possible to determine whether two adjacent samples included in the input signal, namely, the first signal and the fourth signal, are identical. If they are identical, no signal adjustment is required, i.e., no error adjustment signal is generated. This is because when the input signal exhibits DC input characteristics, the truncation error distribution does not conform to the random characteristics of white noise. When the two differ, an error adjustment signal is generated to adjust the signal. This conditional judgment enables accurate detection of signal changes, providing a basis for intelligent activation and deactivation of error compensation. For example, in signal processing, by detecting the difference between the current signal and the previous signal, it is possible to accurately determine whether to activate the error processing mechanism, avoiding unnecessary calculations and improving the system's response speed and stability.

[0090] Figure 5 is a structural block diagram of a cascade digital signal processing circuit according to an embodiment of the present invention. Figure 5 As shown, the device includes:

[0091] A plurality of digital signal processing circuits 52, a frequency information configuration circuit 54, and a plurality of digital truncation error optimization circuits as in any of the above embodiments;

[0092] The frequency point information configuration circuit is respectively connected to the frequency factor generation circuits of the plurality of digital truncation error optimization circuits, and is used to provide carrier frequency point information to the frequency factor generation circuits;

[0093] The output end of each digital signal processing circuit is connected to one of the digital truncation error optimization circuits to obtain a plurality of connection circuits, and different digital signal processing circuits are connected to different digital truncation error optimization circuits;

[0094] A plurality of the connection circuits are connected in series to form a multi-stage digital signal processing circuit.

[0095] In the above embodiment, a digital truncation error optimization circuit can be connected to each digital signal processing circuit to optimize the error of the signal output by the digital signal processing circuit. Multiple digital truncation error optimization circuits can be configured with a frequency information configuration circuit, which can provide carrier frequency information for the frequency factor generation circuits in the multiple digital truncation error optimization circuits.

[0096] In the above embodiment, the frequency information configuration circuit can calculate parameters based on the carrier center frequency corresponding to each node in the link. In the cascaded digital signal processing circuit, by optimizing the truncation of each digital module stage, the SNR within the effective signal band is improved. The introduction of a cascaded structure can handle complex signal processing chains and effectively reduce error accumulation in multi-stage processing.

[0097] Figure 6 is a structural block diagram of a radio frequency transmitting device according to an embodiment of the present invention. Figure 6 As shown, the apparatus includes: a first baseband module 62, a digital-to-analog conversion module 64, and a cascaded digital signal processing circuit as in the above-described embodiment, wherein the output of the first baseband module is connected to the input of the digital-to-analog conversion module via the cascaded digital signal processing circuit. In this embodiment, the RF transmitting device may be an RF transmitting device, such as an antenna, in an RF direct acquisition architecture signal transceiver (RF transceiver).

[0098] In the above embodiment, the specific structural diagram of the radio frequency transmitting device can be found in the attached Figure 7 ,like Figure 7 As shown, the first baseband module outputs signal data to the cascaded digital signal processing circuit, which then sends the output signal to the digital-to-analog conversion module. Modules 1 and 2 are digital signal processing circuits, truncation error optimization 1 and truncation error optimization 2 are digital truncation error optimization circuits. Baseband refers to the first baseband module, digital-to-analog conversion refers to the digital-to-analog conversion module, and module-level frequency information configuration refers to the frequency information configuration circuit.

[0099] In RF transmitters, baseband signals undergo multiple stages of processing before being converted into analog signals. The introduction of cascaded digital signal processing circuits can effectively reduce truncation errors during signal processing, ensuring high-quality transmitted signals. For example, in 5G communication systems, high-speed baseband signal processing requires extremely high precision. Cascaded optimization circuits can significantly improve the accuracy and stability of signal processing, reducing distortion in transmitted signals. This technical solution addresses the issue of signal processing accuracy in RF transmitters and is applicable not only to 5G communications but also to any scenario requiring high-quality signal transmission, including but not limited to satellite communications and radar systems.

[0100] Figure 8 is a structural block diagram of a radio frequency receiving device according to an embodiment of the present invention. Figure 8 As shown, the RF receiving device includes a second baseband module 82, an analog-to-digital conversion module 84, and a cascaded digital signal processing circuit as described in the above embodiment. The output of the analog-to-digital conversion module is connected to the input of the second baseband module via the cascaded digital signal processing circuit. In this embodiment, the RF receiving device can be an RF receiving device in an RF direct acquisition architecture signal transceiver (RF transceiver), such as an antenna.

[0101] In the above embodiment, the specific structural diagram of the radio frequency receiving device can be found in the attached Figure 9 ,like Figure 9 As shown, the signal output by the analog-to-digital conversion module is input to the cascaded digital signal processing circuit, which then sends the output signal to the second baseband module. Modules 1 and 2 are digital signal processing circuits, truncation error optimization 1 and truncation error optimization 2 are digital truncation error optimization circuits. The baseband module is the second baseband module, the analog-to-digital conversion module is the analog-to-digital conversion module, and the module-level frequency information configuration is the frequency information configuration circuit.

[0102] In radio frequency receiving equipment, after analog signals are converted to baseband signals, they undergo multiple stages of digital signal processing. Cascaded digital signal processing circuits can effectively reduce truncation errors during this processing and improve the accuracy of received signals. For example, at the receiving end of wireless communications, the received signal may degrade due to interference during transmission. Cascaded optimization circuits can restore the original signal quality through precise error compensation. This technical solution addresses the issue of signal processing accuracy in radio frequency receiving equipment and is applicable not only to wireless communications but also to any scenario requiring high-quality signal reception, including but not limited to cable television signal reception and sonar signal processing.

[0103] Figure 10 is a structural block diagram of a radio frequency digital-to-analog converter according to an embodiment of the present invention. Figure 10 As shown, the RF digital-to-analog converter includes:

[0104] A filtering circuit 1002, the filtering circuit comprising a sampling rate converter and a digital truncation error optimization circuit as in any of the above embodiments, wherein an output of the sampling rate converter is connected to a signal input of the digital truncation error optimization circuit;

[0105] a digital frequency shift circuit 1004, the digital frequency shift circuit comprising a second multiplier, a digitally controlled oscillator, and the digital truncation error optimization circuit, wherein a first input of the second multiplier is connected to the output of the filter circuit, a second input of the second multiplier is connected to the digitally controlled oscillator, and an output of the second multiplier is connected to an input of the digital truncation error optimization circuit;

[0106] A digital-to-analog converter 1006, wherein the input terminal of the digital-to-analog converter is connected to the output terminal of the digital frequency shift circuit;

[0107] The frequency controller 1008 is connected to the frequency factor generation circuit of each digital truncation error optimization circuit, and is used to provide carrier frequency information to the frequency factor generation circuit.

[0108] In the above embodiment, the input of the sampling rate converter serves as the input of the filter circuit, the output of the sampling rate converter is connected to the output of the digital truncation error optimization circuit, and the output of the filter circuit serves as the output of the filter circuit. The first input of the second multiplier serves as the first input of the digital frequency shift circuit, the second input of the second multiplier serves as the second input of the digital frequency shift circuit, and the output of the digitally controlled oscillator, connected to the output of the second multiplier circuit, serves as the output of the digital frequency shift circuit.

[0109] In the above embodiment, there may be one or more filter circuits, and there may be one or more digital frequency shift circuits.

[0110] Among them, the sampling rate converter SRC (Sample rate converter) is used to convert the baseband signal sampling rate into the digital-to-analog converter (DAC) sampling rate, and the digitally controlled oscillator can be an NCO (numerically controlled oscillator) for converting the signal frequency from the baseband frequency band to the radio frequency band.

[0111] In an exemplary embodiment, there are multiple filter circuits, multiple digital frequency shift circuits, and the multiple digital frequency shift circuits are arranged at intervals. The input end of each digital frequency shift circuit is connected to the output end of one filter circuit, and the output end of the digital frequency shift circuit is connected to the input end of the other filter circuits. In this embodiment, when there are multiple filter circuits, the multiple filter circuits can be connected in series to obtain a serial link, and the output end of the serial link is connected to the input end of the digital frequency shift circuit. In the above embodiment, the specific structural diagram of the RF digital-to-analog converter can be found in the attached Figure 11 ,like Figure 11 As shown, the RF digital-to-analog converter includes a 4-stage interpolation filter module, i.e., a sampling rate converter. Each interpolation filter performs 2x upsampling. The frequency control module is used to generate the frequency modulation information required by each truncation optimization circuit. The input signal is a high-precision 16-bit signal, and the output of each subsequent digital processing module truncates the data bit width to 12 bits. The spectrum diagram of the input test signal to the RF digital-to-analog converter can be found in the attached figure. Figure 12 , after 4 levels of interpolation filtering, each level output is truncated to 12 bits; the final output is frequency-shifted to the 1.84GHz center frequency by a digital NCO. Comparing the truncation method of the optimized circuit with normal truncation and digital truncation error, the final digital signal spectrum diagram at the DAC input can be seen in the attached figure. Figure 13 ,like Figure 13 As shown, the fourth curve shows the signal spectrum after optimization using the digital truncation error optimization circuit; the fifth curve shows the spectrum using the conventional truncation method. Focusing on the in-band noise floor within the 200 MHz range between two single-tone signals, the digital truncation error optimization circuit shows a decreasing in-band noise floor and an increasing out-of-band noise floor. This out-of-band noise degradation can be filtered out by the subsequent analog filter and does not impact system performance. The digital truncation error optimization circuit improves the average in-band SNR by approximately 10 dB. The truncation error optimization circuit is applied to each interpolation filter and digital frequency shift module to optimize the total digital noise within the effective signal band. By observing the final digital node of the DAC or the DAC output analog pin, inputting a single-tone signal at a specific frequency, and adjusting the frequency configuration to observe the noise distribution, noise optimization demonstrates frequency tracking.

[0112] In the above embodiment, the RF digital-to-analog converter may include multiple filter circuits and multiple digital frequency shift circuits. When the number of filter circuits and digital frequency shift circuits is the same, the filter circuits and the digital frequency shift circuits may be arranged at intervals, with the output of one filter circuit connected to the input of one digital frequency shift circuit, and the output of the digital frequency shift circuit connected to the input of another filter circuit. For example, if the number of filter circuits A and the number of digital frequency shift circuits B is the same, the connection relationship may be ABABAB... When the number of filter circuits is greater than the number of digital frequency shift circuits, multiple filter circuits may be connected in series and then connected to one digital frequency shift circuit. For example, if the number of filter circuits A and the number of digital frequency shift circuits B is greater than the number of B, the connection relationship may be AAABABAB...

[0113] In the aforementioned embodiment, the digital truncation error optimization circuit allows the user to configure the signal frequency information for each link location of each truncation optimization circuit. This interface is visible and can be determined in the product user manual. The digital truncation error optimization circuit can be used to optimize overall truncation noise in a digital cascade architecture and features free frequency adjustment, adjusting the error shaping frequency domain response curve based on the actual carrier frequency. It also features low cost and low power consumption.

[0114] An embodiment of the present invention further provides a communications device, which may include one or more of a digital truncation error optimization circuit, a cascaded digital signal processing circuit, a radio frequency transmitter, a radio frequency receiver, and a radio frequency digital-to-analog converter. In this embodiment, the communications device may be, for example, an RF direct acquisition architecture signal transceiver (RF transceiver).

[0115] In one exemplary embodiment, the communication device includes one of the following: a base station located in a satellite, a base station located on the ground, or a terminal device. In this embodiment, the communication device can be a satellite device, such as a base station located in a satellite. It can also be a ground device, such as a base station located on the ground. It can also be a terminal device, such as a mobile phone, an automobile (electric vehicle, gasoline vehicle), a ship, an aircraft, etc. In the aforementioned embodiment, by shaping the truncation errors of each stage of the digital link processing module, the overall in-band signal-to-noise ratio (SNR) of the cascaded modules is improved. The error shaping process can flexibly adapt to the signal frequency, achieving performance improvements with minimal circuit cost.

[0116] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A digital truncation error optimization circuit, characterized in that: include: a first adder, wherein a first input terminal of the first adder is connected to the signal input terminal; a truncation circuit, wherein an input end of the truncation circuit is connected to the output end of the first adder, an output end of the truncation circuit is connected to the signal output end, the truncation circuit is configured to truncate the signal output by the first adder to obtain a truncation signal, and output the truncation signal to the signal output end; A frequency factor generating circuit, configured to generate a frequency modulation factor based on carrier frequency information of the input signal sent by the signal input terminal; a truncation error processing circuit, wherein a first input terminal of the truncation error processing circuit is connected to the output terminal of the truncation circuit, a second input terminal of the truncation error processing circuit is connected to the output terminal of the frequency factor generation circuit, a third input terminal of the truncation error processing circuit is connected to the output terminal of the first adder, and the output terminal of the truncation error processing circuit is connected to the second input terminal of the first adder, the truncation error processing circuit is configured to generate an error adjustment signal based on the frequency modulation factor, the signal output by the first adder, and the truncation signal, and send the error adjustment signal to the first adder; The error adjustment signal is determined by: padding the truncated signal to obtain a padding signal, wherein the bit width of the padding signal is the same as the bit width of the input signal; determining a difference between a second signal and the padding signal, wherein the second signal is a signal sent by the signal input terminal after sending the first signal; after a first predetermined time delay, determining a second product of the difference and the frequency modulation factor; and determining the second product as the error adjustment signal; The digital truncation error optimization circuit is also used to adjust a third signal based on the error adjustment signal, wherein the third signal is a signal sent by the signal input end after sending the second signal, and the input signal includes the first signal, the second signal and the third signal.

2. The digital truncation error optimization circuit according to claim 1, characterized in that: The truncation circuit includes a low-bit truncation circuit.

3. The digital truncation error optimization circuit according to claim 1, characterized in that: The truncation error processing circuit includes: a padding circuit, the input end of the padding circuit being connected to the output end of the truncation circuit, and configured to perform a padding operation on the truncation signal to obtain a padding signal, wherein the bit width of the padding signal is the same as the bit width of the input signal; a second adder, wherein a first input terminal of the second adder is connected to the output terminal of the bit-filling circuit, and a second input terminal of the second adder is connected to the output terminal of the first adder, and is configured to subtract the signal output by the first adder from the bit-filling signal to obtain an error signal; A first multiplier, wherein the first input end of the first multiplier is connected to the output end of the second adder, the second input end of the first multiplier is connected to the output end of the frequency factor generating circuit, and the output end of the first multiplier is connected to the second input end of the first adder, and is used to multiply the error signal by the frequency modulation factor to obtain the error adjustment signal, and input the error adjustment signal into the first adder.

4. The digital truncation error optimization circuit according to claim 3, characterized in that: The truncation error processing circuit further includes: A first delay circuit, wherein the output end of the second adder is connected to the first multiplier through the first delay circuit.

5. The digital truncation error optimization circuit according to claim 1, characterized in that: The digital truncation error optimization circuit further includes: A judgment circuit, wherein the input end of the judgment circuit is connected to the signal input end, is used to receive the input signal and judge whether two adjacent signals in the time domain included in the input signal are the same. If they are the same, the truncation error processing circuit is controlled to be turned off; if they are not the same, the truncation error processing circuit is controlled to be enabled.

6. The digital truncation error optimization circuit according to claim 5, characterized in that: The judgment circuit includes: a second delay circuit, wherein an input end of the second delay circuit is connected to the signal input end, and is used to delay the input signal; A judgment subcircuit, wherein the first input end of the judgment subcircuit is connected to the signal input end, and the second input end of the judgment subcircuit is connected to the output end of the second delay circuit, and is used to judge whether the signal sent by the signal input end is the same as the signal output by the output end of the second delay circuit.

7. The digital truncation error optimization circuit according to claim 1, characterized in that: The frequency factor generation circuit generates a frequency modulation factor based on the carrier frequency information of the input signal sent by the signal input terminal by: determining a ratio of the carrier frequency information to a sampling frequency for sampling the input signal; The frequency modulation factor is determined based on the ratio.

8. The digital truncation error optimization circuit according to claim 7, characterized in that: The frequency factor generating circuit determines the frequency modulation factor based on the ratio in the following manner: determining a first product of the ratio and an imaginary unit; and determining an exponential function having a natural constant as a base and the first product as an exponent as the frequency modulation factor.

9. The digital truncation error optimization circuit according to claim 1, characterized in that: The z-transform truncation error optimization transfer function of the digital truncation error optimization circuit is as follows: ； Wherein, X(z) represents the input signal, E(z) represents the truncation error, Y(z) represents the output signal of the digital truncation error optimization circuit, and w c Indicates the carrier frequency information, j is an imaginary unit.

10. A method for optimizing digital truncation error, characterized in that: The circuit for optimizing digital truncation error according to any one of claims 1 to 9 comprises: receiving a first signal sent by the signal input terminal; generating the frequency modulation factor based on the carrier frequency information of the first signal; performing truncation processing on the first signal to obtain the truncation signal; generating the error adjustment signal based on the frequency modulation factor, the truncation signal, and a second signal, wherein the second signal is a signal sent by the signal input terminal after sending the first signal; A third signal is adjusted based on the error adjustment signal, wherein the third signal is a signal sent by the signal input terminal after sending the second signal, and the input signal includes the first signal, the second signal, and the third signal.

11. The method for optimizing digital truncation error according to claim 10, wherein: Generating the frequency modulation factor based on the carrier frequency information of the first signal includes: Determine a ratio of the carrier frequency information to a sampling frequency for sampling the input signal; and determine the frequency modulation factor based on the ratio.

12. The method for optimizing digital truncation error according to claim 11, wherein: Determining the frequency modulation factor based on the ratio includes: determining a first product of the ratio and an imaginary unit; An exponential function having a natural constant as a base and the first product as an exponent is determined as the frequency modulation factor.

13. The method for optimizing digital truncation error according to claim 10, wherein: Generating the error adjustment signal based on the frequency modulation factor, the truncation signal, and the second signal includes: padding the truncated signal to obtain a padding signal, wherein a bit width of the padding signal is the same as a bit width of the input signal; determining a difference between the second signal and the padding signal; After a first predetermined time delay, determining a second product of the difference and the frequency modulation factor; The second product is determined as the error adjustment signal.

14. The method for optimizing digital truncation error according to claim 10, wherein: Adjusting the third signal based on the error adjustment signal includes: A sum operation is performed on the third signal and the error adjustment signal to adjust the third signal.

15. The method for optimizing digital truncation error according to claim 10, wherein: Before generating the error adjustment signal based on the frequency modulation factor, the truncated signal, and the second signal, the method further includes: Acquire a fourth signal, wherein the fourth signal is a signal sent by the signal input terminal before sending the first signal, and the input signal includes the fourth signal; In a case where the first signal and the fourth signal are different, the error adjustment signal is generated based on the frequency modulation factor, the truncation signal, and the second signal.

16. A cascade digital signal processing circuit, characterized in that: include: A plurality of digital signal processing circuits, a frequency information configuration circuit, and a plurality of digital truncation error optimization circuits according to any one of claims 1 to 9; The frequency point information configuration circuit is respectively connected to the frequency factor generation circuits of the plurality of digital truncation error optimization circuits, and is used to provide carrier frequency point information to the frequency factor generation circuits; The output end of each digital signal processing circuit is connected to one of the digital truncation error optimization circuits to obtain a plurality of connection circuits, and different digital signal processing circuits are connected to different digital truncation error optimization circuits; A plurality of the connection circuits are connected in series to form a multi-stage digital signal processing circuit.

17. A radio frequency transmitting device, characterized in that: include: A first baseband module, a digital-to-analog conversion module, and the cascaded digital signal processing circuit according to claim 16, wherein the output end of the first baseband module is connected to the input end of the digital-to-analog conversion module through the cascaded digital signal processing circuit.

18. A radio frequency receiving device, characterized in that: It includes a second baseband module, an analog-to-digital conversion module and the cascaded digital signal processing circuit according to claim 16, wherein the output end of the analog-to-digital conversion module is connected to the input end of the second baseband module through the cascaded digital signal processing circuit.

19. A radio frequency digital-to-analog converter, characterized in that: include: a filtering circuit, the filtering circuit comprising a sampling rate converter and the digital truncation error optimization circuit according to any one of claims 1 to 9, wherein an output terminal of the sampling rate converter is connected to a signal input terminal of the digital truncation error optimization circuit; a digital frequency shift circuit, the digital frequency shift circuit comprising a second multiplier, a digitally controlled oscillator, and the digital truncation error optimization circuit, wherein a first input of the second multiplier is connected to an output of the filter circuit, a second input of the second multiplier is connected to the digitally controlled oscillator, and an output of the second multiplier is connected to an input of the digital truncation error optimization circuit; a digital-to-analog converter, wherein an input terminal of the digital-to-analog converter is connected to an output terminal of the digital frequency shift circuit; A frequency controller is connected to the frequency factor generation circuit of each digital truncation error optimization circuit, and is used to provide carrier frequency point information to the frequency factor generation circuit.

20. The radio frequency digital-to-analog converter according to claim 19, wherein: There are multiple filtering circuits and multiple digital frequency shifting circuits, which are arranged at intervals. The input end of each digital frequency shifting circuit is connected to the output end of one filtering circuit, and the output end of the digital frequency shifting circuit is connected to the input end of the other filtering circuits.

21. A communication device, characterized in that: The circuit comprises the digital truncation error optimization circuit according to any one of claims 1 to 9.

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