Power-on multi-clock redundancy switching method and system
By using the error comparison method of the backup clock counter in the on-chip clock system, the switching between the main clock and the backup clock is dynamically managed, which solves the problem of unreliability of the single clock source of the on-chip clock system, and the balance of stability and flexibility is achieved.
Patent Information
- Application Number
- CN202510326969.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-07-04
AI Technical Summary
In on-chip clock systems, the unreliability problem of a single clock source cannot be effectively solved through the three-mode redundancy reinforcement method, especially in semiconductor integrated circuits such as power management and motor control, the design of on-chip redundant clock structures faces challenges in system cost, PCB layout density and convenience.
Use the backup clock as the reference and count within the preset time. By comparing the error between the main clock and the backup clock counter, we can determine whether there is a fault in the main clock, and use the main clock frequency division within the preset range. Otherwise, switch to the backup clock frequency division to ensure the stability of the clock signal.
Dynamic management and switching of clock sources are realized, system complexity and hardware resource utilization are reduced, stability and flexibility of chip logic drivers are ensured, and performance and power consumption are balanced.
Smart Images
Figure CN120256209A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of clock redundancy switching, and relates to a power-on multi-clock redundancy switching method and system. Background Art
[0002] In the fields of power electronics systems and aerospace, the reliability and accuracy of system clocks are crucial. As the "heartbeat" of the system, the clock signal controls the coordinated operation of each module and component. Once the clock signal fails, the functions of the entire system may instantly fail, resulting in serious consequences. The traditional single clock source design has obvious failure risks. Since the clock source may be affected by various factors, such as hardware aging, external environmental interference, electromagnetic radiation, etc., once the clock source fails, the system will not be able to continue operating normally.
[0003] The core idea of redundant clock design is to improve the fault tolerance of the system clock network by introducing multiple clock sources and redundant configurations. When the main system clock source fails, it can automatically switch to other backup clock sources, thus ensuring the continuity and accuracy of system clock synchronization. This design method not only improves the reliability of the system, but also enhances the maintainability and scalability of the system.
[0004] Currently, off-chip redundant clock solutions have been widely used in single-board systems. These solutions usually use clock voting circuits, clock synchronization circuits, comparators, etc. to form a clock system, and ensure the continuity of the system clock through clock on / off control and automatic switching mechanisms. When the main clock source fails, the system can quickly identify and switch to the backup clock source, thus ensuring the normal operation of the system.
[0005] However, in the design of on-chip clock systems, higher requirements are placed on clock reliability. For radiation-hardened circuits, considering the space radiation environment, when radiation particles such as plasma, trapped particles, solar particles, and cosmic rays enter the chip, they may cause single-event effects inside the chip, including errors such as single-event upsets and single-event transient pulses. In order to suppress these errors, the triple modular redundancy (TMR) reinforcement method is widely used in the design of on-chip clock systems.
[0006] The triple modular redundancy (TMR) reinforcement method copies the key parts of the clock system and forms three independent modules, and then votes on the outputs of each module to determine the final output by majority. This method can effectively suppress the SEU errors of the flip-flops themselves, and at the same time suppress the SEU errors caused by combinational logic SET, thereby improving the reliability of the system clock.
[0007] However, for normal circuits, the triple modular redundancy reinforcement method is not applicable and cannot solve the problem of the unreliability of a single on-chip clock source. Especially for semiconductor integrated circuits for power management, motor control, etc., considering factors such as system cost, PCB layout density, and ease of use, an on-chip clock system is more inclined to be adopted. Therefore, it is particularly important to improve the reliability of the clock system through an on-chip redundant clock structure. Summary of the Invention
[0008] Aiming at the deficiencies of the prior art, the present invention aims to provide a power-on multi-clock redundant switching method and system. First, the stability of the main clock is judged. After the main clock can continuously and stably output a clock signal for a waiting time, a specific time is selected to judge whether the main clock has a fault. If the main clock fails, it is switched to the backup clock, and the switched backup clock is output through frequency division control to drive interface modules inside the chip that operate at different frequencies.
[0009] To achieve the above object, the present invention adopts the following technical solutions: The present invention provides a power-on multi-clock redundant switching method, including the following steps: taking the backup clock as a reference, within a preset time, a backup clock counter counts; the flag_start flag bit of the backup clock counter becomes valid after the preset time, and the main clock counter starts to count; when the main clock counter counts within a specific time, the backup clock counter also counts until flag_end is 1; calculate the error between the time values corresponding to the main clock counter and the backup clock counter within the specific time to judge whether the main clock has a fault; if the error is within the preset range, use the main clock for frequency division, otherwise use the backup clock for frequency division.
[0010] Further, the preset time is the waiting time for the main clock to stably output a clock signal.
[0011] Further, when the backup clock counter counts, within the preset time, the flag_start flag bit and the flag_end flag bit detected by the backup clock counter are both invalid; after the preset time, the flag_start flag bit of the backup clock counter becomes valid and the flag_end flag bit is invalid; the backup clock counter continues to increment and count, and after a specific time, the flag_end flag bit becomes valid.
[0012] Further, the main clock counter starts to count when the flag_start of the backup clock counter is valid and the flag_end flag bit is invalid, until the flag_end flag bit becomes valid.
[0013] Further, the specific time is the cumulative deviation time of the cycle jitter of the master clock; the error between the time values corresponding to the master clock counter and the backup clock counter is within ±2 of the cumulative deviation of the cycle jitter of the master clock.
[0014] Further, the clock selection signal clk_sel for dividing the frequency of the master clock is 0, and the clock selection signal clk_sel for dividing the frequency of the backup clock is 1.
[0015] Further, the master clock and the backup clock are frequency-divided and output through frequency division control; the frequency division control includes a variable vDiv4, variables vDiv8_s1, vDiv8_s2, and a signal clkDiv[2:0].
[0016] Further, the variables vDiv4, vDiv8_s1, and vDiv8_s2 are used to meet the requirement that the master / backup clock frequency division control logic takes effect immediately within each clock cycle.
[0017] Further, the signal clkDiv[2:0] includes a divided-by-two clock signal clkdiv[0], a divided-by-four clock signal clkDiv[1], and a divided-by-eight clock signal clkDiv[2]; the divided-by-two clock signal clkdiv[0] is obtained by inverting each period of the selected clock; the variable vDiv4 is obtained by inverting the exclusive OR of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s1 is the result of the OR logic of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s2 is obtained by inverting the exclusive OR of the variable vDiv8_s1 and the divided-by-eight clock signal clkDiv[2].
[0018] The present invention also provides a power-on multi-clock redundant switching system, including: a first counting module: used to count the backup clock counter based on the backup clock within a preset time; a second counting module: used to make the flag_start flag bit of the backup clock counter valid after the preset time, and the master clock counter starts to count; when the master clock counter counts within a specific time, the backup clock counter also counts until flag_end is 1; a judgment module: used to calculate the error between the time values corresponding to the master clock counter and the backup clock counter within a specific time, and judge whether the master clock has a fault; a frequency division module: used to perform frequency division using the master clock if the error is within the preset range, otherwise use the backup clock for frequency division.
[0019] Compared with the prior art, the present invention has the following beneficial technical effects: A power-on multi-clock redundant switching method of the present invention does not rely on a specific type of on-chip clock source. Whether it is a voltage-controlled oscillator or a clock source of other types of oscillators, as long as it can provide a stable clock signal, it can be used as the main clock or the backup clock. The main clock may have cumulative deviation of cycle jitter, resulting in the instability of the clock signal output by it. While the backup clock is relatively stable. By comparing the error of the time values corresponding to the main clock counter and the backup clock counter within a specific time, if the error is within the preset range, the main clock is used for frequency division, otherwise the backup clock is used for frequency division, so as to avoid affecting the clock signal after frequency division due to the instability of the main clock. In addition, when the main clock fails, the backup clock can be smoothly and automatically switched, so as to ensure the normal operation of the chip logic drive.
[0020] A power-on multi-clock redundant switching method of the present invention can realize the dynamic management and switching of the clock source through simple counting and error comparison operations, avoiding complex clock synchronization and compensation algorithms, thereby reducing the complexity of the system, reducing the occupation of hardware resources and power consumption.
[0021] A power-on multi-clock redundant switching method of the present invention can realize the output of the same phase at multiple frequencies by setting different frequency division control variables and signals, meet the working frequencies and timing requirements of different modules in the system, dynamically adjust the frequency of the clock signal according to the working state and requirements of the system, use a high frequency when high performance is required, and reduce the frequency in the low-power mode, so as to balance performance and power consumption. Brief Description of the Drawings
[0022] Figure 1 is a flowchart of a power-on multi-clock redundant switching method of the present invention; Figure 2 is a schematic diagram of a power-on multi-clock redundant switching method of the present invention; Figure 3 is the output timing of the same-phase different-frequency clocks in the embodiment of the present invention. Detailed Embodiments
[0023] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.
[0024] Embodiment 1 The present invention provides a method for redundant switching of multiple clocks during power-on. The master clock may have a cumulative deviation in cycle jitter, resulting in an unstable clock signal output. While the backup clock is relatively stable. By comparing the error between the time values corresponding to the master clock counter and the backup clock counter within a specific time, if the error is within the preset range, the master clock is used for frequency division, otherwise the backup clock is used for frequency division, thus avoiding the influence of the instability of the master clock on the frequency-divided clock signal.
[0025] In this embodiment, the specific time is 1 us, where us is the abbreviation of microsecond. The setting of the specific time enables the system to immediately detect the abnormality of the master clock, so as to quickly switch to the backup clock and avoid the influence of the unstable clock signal for a long time on the system.
[0026] As Figure 1 described above, it includes: taking the backup clock as a reference, within a preset time, the backup clock counter performs counting; the flag_start flag bit of the backup clock counter becomes valid after the preset time, and the master clock counter starts counting; when the master clock counter performs counting within the specific time, the backup clock counter also performs counting until flag_end is 1; calculating the error between the time values corresponding to the master clock counter and the backup clock counter within the specific time, and judging whether there is a fault in the master clock; if the error is within the preset range, the master clock is used for frequency division, otherwise the backup clock is used for frequency division.
[0027] Specifically: Wait for the system reset to be revoked. Taking the backup clock as a reference, after the chip is powered on and the reset is revoked, start the backup clock counter cnt_backupclk and perform cumulative counting within the preset time. The preset time needs to consider the waiting time for the master clock to stably output the clock. Different complementary metal oxide semiconductor (CMOS) processes have different designs, so the preset time can be adjusted according to the actual situation and there are differences.
[0028] When the backup clock counter cnt_backupclk accumulates to the preset time interval, the time marking signal flag_start is pulled high. The validity of this time mark indicates that the master clock can start the master clock counter cnt_mainclk. At this time, the backup clock counter cnt_backupclk continues to accumulate and count. Set a new time interval, that is, the specific time, according to the cumulative deviation of the cycle jitter of the master clock. When the specific time arrives, the backup clock counter cnt_backupclk stops counting and maintains the count value unchanged. At the same time, another time marking signal flag_end is pulled high. The validity of this time mark indicates that the master clock counter cnt_mainclk stops counting.
[0029] The time when the master clock starts the master clock counter cnt_mainclk is that after sampling the time mark signal flag_start is set to 1, the counting starts to accumulate; after sampling the time mark signal flag_end is set to 1, the master clock counter cnt_mainclk stops counting and maintains the count value unchanged. According to the cycle count value accumulated by the master clock counter cnt_mainclk during the time interval from the validity of flag_start to the validity of flag_end, and comparing it with the time value corresponding to the cycle count value accumulated by the backup clock counter cnt_backupclk during this time interval, to determine whether there is a fault in the master clock. If the count value of cnt_mainclk is within the expected range, and the predicted range is within ±2 of the cumulative deviation of the cycle jitter of the master clock, then the clock switching signal clk_sel remains 0, and the master clock is default selected to work; if the count value of the master clock counter cnt_mainclk is not within the expected range, then the clock switching signal clk_sel is set to 1, and the backup clock is automatically selected to work.
[0030] Embodiment 2 After determining the master clock or the backup clock, the selected clock is frequency-divided and output by the frequency division control. In order to ensure the synchronous design requirements of the chip, the divided-by-two, divided-by-four, and divided-by-eight frequencies based on the selected clock are output in the same phase to drive the interface modules operating at different frequencies inside the chip, and at the same time it is more conducive to achieving timing convergence. The frequency division control in the present invention includes 3 variables and the signal clkDiv[2:0]. The 3 variables are respectively the variable vDiv4, the variable vDiv8_s1, and the variable vDiv8_s2, which are used to meet the requirement that the clock divided-by-four and divided-by-eight frequency control logics take effect immediately within each clock cycle. The signal clkDiv[2:0] includes the divided-by-two clock signal clkdiv[0], the divided-by-four clock signal clkDiv[1], and the divided-by-eight clock signal clkDiv[2].
[0031] The divided-by-two clock signal clkdiv[0], the divided-by-four clock signal clkDiv[1], and the divided-by-eight clock signal clkDiv[2] are the divided-by-two, divided-by-four, and divided-by-eight clocks in the same phase generated based on the selected system clock.
[0032] Among them, the divided-by-two clock signal clkdiv[0] is obtained by inverting each cycle of the selected clock; the variable vDiv4 is obtained by inverting the exclusive OR of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s1 is the result of the OR logic of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s2 is obtained by inverting the exclusive OR of the variable vDiv8_s1 and the divided-by-eight clock signal clkDiv[2].
[0033] In summary, by setting different frequency division control variables vDiv4, variable vDiv8_s1, variable vDiv8_s2, and signal clkDiv[2:0], clock outputs with the same phase at multiple frequencies can be achieved to meet the requirements of different system modules. For example, variable vDiv4 can be used to achieve a 4-fold frequency division, variables vDiv8_s1 and vDiv8_s2 can be used to achieve different stages or modes of an 8-fold frequency division, and clkDiv[2:0] is a 3-bit clock signal, with each bit representing a clock output at a different frequency.
[0034] Embodiment 3 As Figure 2 shown, it is a schematic diagram of the power-on multi-clock redundant switching method, where clk_main is the main clock, clk_backup is the backup clock, cnt_mainclk is the main clock counter, and cnt_backupclk is the backup clock counter.
[0035] The backup clock counter counts. Within a preset time, when the statuses of the flag_start flag bit and the flag_end flag bit detected by the backup clock counter are both invalid, the counting start time of the main clock counter starts from when the flag_start signal of the backup clock counter is valid and the flag_end flag bit is invalid, until the flag_end flag bit becomes valid. After the preset time, the flag_start flag bit of the backup clock counter becomes valid and the flag_end flag bit is invalid; the backup clock counter continues to increment and count, and after a specific time, the flag_end flag bit becomes valid Specifically, when the signal flag_start is set to 1, the main clock counter cnt_mainclk starts counting, and when the signal flag_end is set to 1, the counting of the main clock counter cnt_mainclk ends. The main clock fault determination is based on the cycle jitter deviation of the main clock within a certain time. When the deviation exceeds a certain range, the Clk_sel signal is set to 1, and it automatically switches to the backup clock for system use; when the deviation is within an acceptable range, the Clk_sel signal is set to 0, and it is considered that the main clock is stable and reliable. It should be noted that the main clock frequency is higher than the backup clock frequency, and when the main clock of the chip fails, it can automatically switch to the backup clock and use it at a reduced frequency.
[0036] Specifically, first, taking the backup clock as a reference, after the chip is powered on, the system reset is revoked, the backup clock counter cnt_backupclk is started, and it waits for a preset time, which is the waiting time for the main clock to stably output a clock signal. At this time, the time mark flag_start is set to be valid, the backup clock counter continuously accumulates and counts, and it waits for a certain time interval again. This time interval is a specific time, and the selection of this specific time is related to the jitter characteristics within the fixed time period of the main clock. After the specific time, the time mark flag_end is set to be valid.
[0037] When the flag_start flag bit is sampled as valid while the flag_end flag bit is invalid, the main clock counter cnt_mainclk is started. The main clock counter accumulates and counts until the flag_end becomes valid, and then stops counting, keeping the count value of the main clock counter cnt_mainclk unchanged.
[0038] Taking the backup clock clk_backup and the backup clock counter cnt_backupclk within a specific time as a reference, the time value corresponding to this count value is compared with the count value of the main clock counter cnt_mainclk after stopping counting. If it is within ±2 of the cumulative deviation of the cycle jitter of the main clock, the main clock selection signal clk_sel is set to 0, and the chip system clock selects the main clock; if it is not within ±2 of the cumulative deviation of the cycle jitter of the main clock, the main clock selection signal clk_sel is set to 1, and the chip system clock selects the backup clock.
[0039] For example: The main clock is 100Mhz, and the corresponding period is 10ns; the backup clock is 50Mhz, and the corresponding period is 20ns. The specific time is 1us, the backup clock counter is 50, then the theoretical value of the main clock counter should be 100, the actual value of the main clock counter is 95, and the error between the time values corresponding to the main clock counter and the backup clock counter within the specific time is 5, exceeding the cumulative deviation of the cycle jitter of the main clock. Then the main clock is in a faulty state, and the backup clock needs to be used for frequency division.
[0040] It should be noted that in order to ensure the stability and reliability during the switching between the main clock and the backup clock, it is recommended to select a clock MUX library unit to ensure smooth switching.
[0041] MUX is a multiplexer. Using a clock MUX can improve system reliability, support seamless switching, reduce maintenance costs, and improve system flexibility.
[0042] The clock selection signal clk_sel for frequency division of the main clock is 0, and the clock selection signal clk_sel for frequency division of the backup clock is 1.
[0043] After determining the main clock or backup clock, the selected clock is divided by frequency through frequency division control. To ensure the synchronous design requirements of the chip, the divided-by-two, divided-by-four, and divided-by-eight frequencies based on the selected clock are output in the same phase to drive the interface modules operating at different frequencies inside the chip. In the present invention, the frequency division control includes 3 variables and the signal clkDiv[2:0]. The 3 variables are respectively the variable vDiv4, the variable vDiv8_s1, and the variable vDiv8_s2, which are used to meet the requirement that the clock divided-by-four and divided-by-eight frequency control logics take effect immediately within each clock cycle. The signal clkDiv[2:0] includes the divided-by-two clock signal clkdiv[0], the divided-by-four clock signal clkDiv[1], and the divided-by-eight clock signal clkDiv[2].
[0044] By setting different frequency division control variables and signals, the same-phase output of multiple frequencies can be achieved, meeting the working frequency requirements of different modules within the system, dynamically adjusting the frequency of the clock signal according to the working state and requirements of the system, using a high frequency when high performance is needed, and reducing the frequency in the low-power mode, thereby balancing performance and power consumption.
[0045] The divided-by-two clock signal clkdiv[0], the divided-by-four clock signal clkDiv[1], and the divided-by-eight clock signal clkDiv[2] are the divided-by-two, divided-by-four, and divided-by-eight clocks in the same phase generated based on the selected system clock.
[0046] As Figure 3 shown, among them, the divided-by-two clock signal clkdiv[0] is obtained by inverting each cycle of the selected clock; the variable vDiv4 is obtained by inverting the result of the exclusive OR of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s1 is the result of the OR logic of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; the variable vDiv8_s2 is obtained by inverting the result of the exclusive OR of the variable vDiv8_s1 and the divided-by-eight clock signal clkDiv[2]. The variables vDiv4, vDiv8_s1, and vDiv8_s2 are used to meet the requirement that the main / backup clock divided-by-four and divided-by-eight frequency control logics take effect immediately within each clock cycle.
[0047] The divided-by-two clock signal clkdiv[0] is the divided-by-two output based on the sys_clk clock, and clkDiv[1] and clkDiv[2] are respectively the register output results of vDiv4 and vDiv8_s2. This structure ensures the same-phase output of the divided-by-two, divided-by-four, and divided-by-eight clocks of sys_clk, meeting the requirements of the circuit synchronous design.
[0048] In summary, the backup clock counter is counted within a preset time, the master clock counter and the backup clock counter are counted within a specific time, the error between the time values corresponding to the master clock counter and the backup clock counter within the specific time is calculated based on the cumulative deviation of the cycle jitter of the master clock, and if the error is within the preset range, the master clock is used for frequency division; if the error is not within the preset range, the backup clock is used for frequency division.
[0049] Embodiment 4 A power-on multi-clock redundant switching system of the present invention includes a first counting module, a second counting module, a judgment module, and a frequency division module.
[0050] The first counting module: is used to count the backup clock counter within a preset time based on the backup clock; the second counting module: is used to make the flag_start flag bit of the backup clock counter valid after the preset time, and the master clock counter starts to count; when the master clock counter counts within a specific time, the backup clock counter also counts until flag_end is 1; the judgment module: is used to calculate the error between the time values corresponding to the master clock counter and the backup clock counter within the specific time and judge whether there is a fault in the master clock; the frequency division module: is used to use the master clock for frequency division if the error is within the preset range, otherwise use the backup clock for frequency division.
[0051] The power-on multi-clock redundant switching system provided by the present invention can implement method steps consistent with the above method embodiments, so details are not described herein again.
[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications or equivalent replacements can still be made to the specific embodiments of the present invention, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered by the protection scope of the claims of the present invention.
Claims
1. A method for redundant switching of multiple clocks during power-on, characterized in that It includes the following steps: Based on the backup clock as a reference, within a preset time, the backup clock counter counts; The flag_start flag bit of the backup clock counter becomes valid after the preset time, and the main clock counter starts to count; when the main clock counter counts within a specific time, the backup clock counter also counts until flag_end is 1; Calculate the error between the time values corresponding to the main clock counter and the backup clock counter within a specific time, and determine whether there is a fault in the main clock; If the error is within the preset range, use the main clock for frequency division, otherwise use the backup clock for frequency division.
2. The power-on multi-clock redundant switching method according to claim 1, characterized in that The preset time is the waiting time for the main clock to stably output a clock signal.
3. The power-on multi-clock redundant switching method according to claim 1, characterized in that: The backup clock counter counts, and within the preset time, the backup clock counter detects that the states of the flag_start flag bit and the flag_end flag bit are both invalid; after the preset time, the flag_start flag bit of the backup clock counter becomes valid and the flag_end flag bit is invalid; the backup clock counter continues to accumulate and count, and after a specific time, the flag_end flag bit becomes valid.
4. The power-on multi-clock redundant switching method according to claim 1, characterized in that: The main clock counter starts to count when the flag_start of the backup clock counter is valid and the flag_end flag bit is invalid, until the flag_end flag bit becomes valid.
5. The power-on multi-clock redundant switching method according to claim 4, characterized in that: The specific time is the cumulative deviation time of the cycle jitter of the main clock; The error between the time values corresponding to the main clock counter and the backup clock counter is within ±2 of the cumulative deviation of the cycle jitter of the main clock.
6. The power-on multi-clock redundant switching method according to claim 3, characterized in that: The clock selection signal clk_sel for frequency division of the main clock is 0, and the clock selection signal clk_sel for frequency division of the backup clock is 1.
7. The power-on multi-clock redundant switching method according to claim 1, characterized in that: The main clock and the backup clock are frequency-divided and output through frequency-division control; The frequency-division control includes variable vDiv4, variable vDiv8_s1, variable vDiv8_s2, and signal clkDiv[2:0].
8. The power-on multi-clock redundant switching method according to claim 7, characterized in that: The variables vDiv4, vDiv8_s1, and vDiv8_s2 are used to meet the requirement that the main / backup clock quarter-frequency and octal-frequency control logics take effect immediately within each clock cycle.
9. The power-on multi-clock redundant switching method according to claim 8, characterized in that: The signal clkDiv[2:0] includes a divided-by-two clock signal clkdiv[0], a divided-by-four clock signal clkDiv[1], and a divided-by-eight clock signal clkDiv[2]; The divided-by-two clock signal clkdiv[0] is obtained by inverting each cycle of the selected clock; The variable vDiv4 is obtained by inverting the result of the exclusive OR of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; The variable vDiv8_s1 is the result of the OR logic of the divided-by-two clock signal clkdiv[0] and the divided-by-four clock signal clkDiv[1]; The variable vDiv8_s2 is obtained by inverting the result of the exclusive OR of the variable vDiv8_s1 and the divided-by-eight clock signal clkDiv[2].
10. A power-on multi-clock redundant switching system, comprising: A first counting module: configured to count a backup clock counter within a preset time based on a backup clock; A second counting module: configured to make the flag_start flag bit of the backup clock counter valid after a preset time, and a main clock counter starts to count; when the main clock counter counts within a specific time, the backup clock counter also counts until flag_end is 1; A judgment module: configured to calculate the error between the time values corresponding to the main clock counter and the backup clock counter within a specific time, and judge whether the main clock has a fault; A frequency division module: configured to perform frequency division using the main clock if the error is within a preset range, otherwise perform frequency division using the backup clock.