Processing method and device and electronic equipment

Abstract

The invention discloses a processing method and device and electronic equipment, and the processing method comprises the steps: generating an initial test vector supported by test equipment according to the test equipment and a test case for a to-be-tested chip; based on the initial test vector, performing simulation verification on the to-be-tested chip, and based on a simulation verification result, adjusting the initial test vector until the simulation verification is passed, and forming a target test vector; and generating a test program of the test equipment based on the target test vector.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a processing method, apparatus, and electronic device. Background Art

[0002] In the chip automated test development process, the development of test programs for automatic test equipment (ATE) is a key link to ensure the verification of chip functions and performance. However, in actual operation, the development process of test programs faces challenges of low efficiency. This current situation not only prolongs the chip R & D cycle but also increases the test cost, becoming a bottleneck restricting the further development of chip automated test technology. Summary of the Invention

[0003] The technical solutions provided by this application are as follows:

[0004] A first aspect of this application provides a processing method, including:

[0005] Generating an initial test vector supported by the test equipment according to the test equipment and test cases for the chip under test;

[0006] Based on the initial test vector, performing simulation verification on the chip under test, and adjusting the initial test vector based on the simulation verification result until the simulation verification passes, to form a target test vector;

[0007] Generating a test program for the test equipment based on the target test vector.

[0008] Generating an initial test vector supported by the test equipment according to the test equipment and test cases for the chip under test includes:

[0009] Obtaining waveform state parameters, where the waveform state parameters are used to describe test signals supported by the test equipment;

[0010] Generating an initial test vector supported by the test equipment based on the waveform state parameters and test cases for the chip under test.

[0011] The waveform state parameters include at least one of the following:

[0012] A first state parameter, used to describe the allocation relationship between the input and output ports of the chip under test and the test channels available in the test equipment; the allocation relationship matches the total test channels of the test equipment;

[0013] A second state parameter, used to describe the voltage required for the test signals available for the chip under test; the voltage is within the voltage range that the test equipment can provide;

[0014] A third state parameter, which is used to describe the timing of the test signals available for the device under test; the timing matches the timing control accuracy of the device under test.

[0015] Based on the waveform state parameter and the test cases for the chip under test, generate an initial test vector supported by the test device, including:

[0016] Based on the test cases for the chip under test, form a test sub-operation sequence composed of multiple test sub-operations in a preset timing, where the sub-operations correspond to individual basic test operations within the test cases;

[0017] Based on the waveform state parameter and each test sub-operation in the test sub-operation sequence, respectively obtain the sub-test vectors supported by the test device corresponding to each test sub-operation;

[0018] Integrate each of the sub-test vectors in a preset timing to form an initial test vector.

[0019] Before performing simulation verification on the chip under test based on the initial test vector, it further includes:

[0020] Screen out the test elements to be adjusted in the initial test vector that do not meet the design specifications of the chip under test;

[0021] Corresponding to the test elements to be adjusted, obtain target test sub-operations; the target test sub-operations conform to the design specifications of the chip under test;

[0022] Based on the waveform state parameter and the target test sub-operation, compile to obtain the sub-test vector corresponding to the target test sub-operation;

[0023] Based on the sub-test vector corresponding to the target test sub-operation, adjust the initial test vector.

[0024] The step of respectively obtaining the sub-test vectors supported by the test device corresponding to each test sub-operation includes:

[0025] Respectively call from the template library the sub-test vectors supported by the test device that match each test sub-operation; the template library contains multiple test sub-vectors compiled and backed up according to the waveform state parameter and different test cases of the chip under test.

[0026] The initial test vector includes: an initial input test vector and an initial output test vector;

[0027] The step of performing simulation verification on the chip under test based on the initial test vector and adjusting the initial test vector based on the simulation verification result includes:

[0028] Process the initial input test vector based on the simulation model to obtain a simulation output vector;

[0029] Compare the simulation output vector and the initial output test vector to obtain a simulation verification result;

[0030] If the simulation verification result indicates that the simulation output vector and the initial output test vector are inconsistent, calibrate the initial output test vector based on the simulation output vector.

[0031] On the other hand, this application provides a processing device, including:

[0032] A test vector generation module, configured to generate an initial test vector supported by the test device according to the test device and test cases for the chip under test;

[0033] A simulation and data processing module, configured to perform simulation verification on the chip under test based on the initial test vector, and adjust the initial test vector based on the simulation verification result until the simulation verification passes, to form a target test vector;

[0034] A test program development module, configured to generate a test program for the test device based on the target test vector.

[0035] The test vector generation module includes:

[0036] A waveform description module, configured to obtain waveform state parameters, where the waveform state parameters are used to describe test signals supported by the test device;

[0037] A test case sequence writing module, configured to form a test sub-operation sequence composed of multiple test sub-operations in a preset time sequence based on test cases for the chip under test, where the sub-operations correspond to individual basic test operations within the test cases;

[0038] A test vector compilation module, configured to respectively obtain sub-test vectors supported by the test device corresponding to each test sub-operation based on the waveform state parameters and each test sub-operation in the test sub-operation sequence; and integrate the respective sub-test vectors in a preset time sequence to form an initial test vector.

[0039] On the third aspect, this application provides an electronic device, including:

[0040] A memory, configured to store at least one set of instruction sets;

[0041] The processor is configured to call and execute the instruction sets in the memory, and execute the processing method as described in any one of the above by executing the instruction sets. Description of the Drawings

[0042] In conjunction with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and that the original elements and elements are not necessarily drawn to scale.

[0043] Figure 1 It is a schematic flowchart of a processing method provided in Embodiment 1 of the present application;

[0044] Figure 2 It is a schematic flowchart of a processing method provided in Embodiment 2 of the present application;

[0045] Figure 3 It is a schematic flowchart of a processing method provided in Embodiment 4 of the present application;

[0046] Figure 4 It is a schematic diagram of a test sub-operation sequence provided by the present application;

[0047] Figure 5 It is a schematic diagram of a sub-test vector provided by the present application;

[0048] Figure 6 It is a schematic diagram of an initial test vector provided by the present application;

[0049] Figure 7 It is a schematic flowchart of a processing method provided in Embodiment 5 of the present application;

[0050] Figure 8 It is a schematic structural diagram of a processing device provided by the present application;

[0051] Figure 9 It is another schematic structural diagram of a processing device provided by the present application. Specific Embodiments

[0052] The following describes the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application.

[0053] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0054] In the description of this application and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device comprising a series of units does not have to be limited to those units, but may include other units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0055] In the traditional ATE test program development process, the acquisition of test vectors and the development of test programs show a strict serial dependency relationship. The specific process is as follows: First, test stimuli (i.e., input signal patterns used to stimulate specific functions of the chip) are generated according to test case design. Subsequently, compilation and simulation are performed through EDA tools (i.e., simulating the chip behavior through a digital model to verify the effectiveness of the test stimuli and the chip response). After the simulation is completed, the system outputs a simulation waveform representing the expected behavior of the chip, and then it is converted into a test vector recognizable by ATE through a waveform conversion tool. The development of the test program must wait until the above-mentioned simulation waveform generation and vector conversion are completed before it can be started. Developers need to write codes such as ATE device control logic, channel configuration, and timing control based on the final test vectors.

[0056] However, this serial process has the following defects:

[0057] (1) Only the chip function verification is concerned in the simulation stage, and the actual physical constraints of the ATE machine are not incorporated, resulting in the generated test vectors may contain signal parameters beyond the support range of the ATE hardware (such as unsupported voltage levels or clock frequencies). Eventually, multiple manual adjustments or even re-simulation are required to adapt to the device.

[0058] (2) Since the development of the test program completely depends on the test vectors generated by the simulation, developers cannot carry out any substantial development work (such as device initialization code, test process framework construction) in advance before the simulation is completed. If vector incompatibility issues (such as signal timing conflicts or resource overrun) are found during the subsequent ATE test, it is necessary to trace back to the simulation stage to regenerate the waveform and convert the vector, resulting in the full process being repeated, and the development cycle is significantly extended.

[0059] (3) The iteration cost is high: Each round of test vector correction requires the complete execution of the "compilation - simulation - waveform conversion" process, and the simulation link usually takes several hours to several days, seriously affecting the development efficiency.

[0060] Therefore, this application provides a processing method to shorten the development cycle and improve the development efficiency.

[0061] To make the above objects, features, and advantages of the present application more apparent and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] Referring to Figure 1 , which is a schematic flowchart of a processing method provided for Embodiment 1 of the present application. As Figure 1 shown, the method may include but is not limited to the following steps:

[0063] Step 101: Generate an initial test vector supported by the test device according to the test device and the test case for the chip under test.

[0064] The test case for the chip under test can be used to describe the test objective, input excitation conditions, and expected output response (e.g., the signal behavior (such as output level, timing delay) or data response (such as the data value returned for an I2C register read operation) that the chip under test should generate under the input excitation conditions), etc.

[0065] The test objective may include but is not limited to at least one of the elements of testing the function, performance, and reliability of the chip under test.

[0066] The input excitation conditions may include but are not limited to at least one of the electrical signal characteristics (such as voltage, frequency, waveform) applied to the pins or interfaces of the chip under test and the protocol instruction sequence (such as I2C register read and write operations).

[0067] The expected output response may include but is not limited to the expected logical value and the signal parameters (such as timing) corresponding to the expected logical value that the chip under test should generate under the input excitation conditions.

[0068] The initial test vector supported by the test device can be used to generate an input test signal that conforms to the hardware performance of the test device and to verify the response of the chip under test to the input test signal.

[0069] After the initial test vector is generated, the development of the test program framework can be started, e.g., developing signal channel allocation, test step arrangement, etc.

[0070] Step 102: Based on the initial test vector, perform simulation verification on the chip under test, and adjust the initial test vector based on the simulation verification result until the simulation verification passes to form a target test vector.

[0071] Step S102 may include but is not limited to:

[0072] Step S11: Based on the initial test vector, perform simulation verification on the chip under test to obtain a simulation verification result.

[0073] Step S12: If the simulation verification result fails, adjust the initial test vector based on the simulation verification result to obtain a new initial test vector, and continue to execute Step S11.

[0074] In this embodiment, the initial test vector may include the expected logical values in the above-mentioned expected output response. Since the expected logical values are directly related to the functional correctness of the chip under test and need to be consistent with the test cases, the expected logical values in the initial test vector can be kept unchanged based on the simulation verification result. However, the elements other than the expected logical values can be adjusted. For example, optimize the signal parameters corresponding to the expected logical values in the initial test vector and / or adjust the initial input test vector used to simulate the input test signal.

[0075] Step S13: If the simulation verification result passes, use the initial test vector that passes the simulation verification as the target test vector.

[0076] Compared with the initial test vector, the target test vector can be used to more accurately simulate the input test signal that conforms to the hardware performance of the test device and obtain the expected output signal corresponding to the input test signal.

[0077] Step 103: Generate a test program for the test device based on the target test vector.

[0078] Since the simulation verification based on the initial test vector can be executed in parallel with the development of the test program framework (such as signal channel allocation and test step arrangement), when generating the test program, there is no need to repeat the development of the above test program framework. Instead, the target test vector is structurally integrated with the previously developed test program framework to finally generate a test program that can be directly deployed to the test device.

[0079] In the test phase, the test device can execute the test program, generate an input test signal based on the target input test vector in the target test vector, input the input test signal into the chip under test, and collect the output signal of the chip under test. Convert the output signal of the chip under test into an output vector, and verify the output vector of the chip under test according to the target output test vector in the target test vector. If the verification passes, it is determined that the chip under test passes the test; if the verification fails, the chip under test fails the test.

[0080] In this embodiment, generating the initial test vector supported by the test device according to the test device and the test cases for the chip under test can ensure that the initial test vector does not exceed the hardware support range of the test device and reduce the later iterations caused by hardware performance conflicts.

[0081] Moreover, after the initial test vector is generated, while developing the test program framework (such as signal channel allocation, test step arrangement, etc.), reliable target test vectors are obtained through simulation verification based on the initial test vectors. This parallel execution method can shorten the development cycle and improve the efficiency of test program development. In addition, the target test vectors are determined through simulation verification, enabling the target test vectors to accurately reflect the actual working requirements of the chip under test. Furthermore, based on the target test vectors, test programs for the test equipment are generated, which can ensure the reliability of testing the chip under test using the test programs.

[0082] As another optional embodiment of the present application, referring to Figure 2 , which is a schematic flowchart of a processing method provided in Embodiment 2 of the present application. This embodiment is mainly an implementation manner of the above step S101. As Figure 2 shown, step S101 may include but is not limited to:

[0083] Step S1011: Obtain waveform state parameters, where the waveform state parameters are used to describe the test signals supported by the test equipment.

[0084] In this embodiment, the waveform state parameters can be defined based on the hardware resources of the test equipment and the program operation rules.

[0085] The hardware resources of the test equipment may include but are not limited to: the physical configuration of the test equipment (such as timing accuracy, channel resources, storage and computing resources, etc.) and board characteristics (such as signal support types, electrical characteristics, etc.).

[0086] The program operation rules can be used to constrain the execution logic of the test program on the test equipment. The program operation rules may include but are not limited to: signal generation rules, channel allocation rules, timing control logic, etc.

[0087] Step S1012: Generate initial test vectors supported by the test equipment based on the waveform state parameters and test cases for the chip under test.

[0088] Test cases may contain elements beyond the hardware support scope of the test equipment. Through the waveform state parameters, elements beyond the hardware support scope of the test equipment can be filtered out from the test cases or the content beyond the hardware support scope of the test equipment can be converted into elements within the hardware support scope of the test equipment.

[0089] In this embodiment, the hardware limitations of the test equipment can be quantified through the waveform state parameters. Furthermore, based on the waveform state parameters, the test cases for the chip under test can be automatically adjusted, reducing the generation of test vectors that the test equipment cannot support, thereby reducing subsequent iterations caused by hardware performance conflicts and improving the efficiency of test program development.

[0090] As another optional embodiment of the present application, a processing method provided for Embodiment 3 of the present application. This embodiment is mainly an implementation manner of the above waveform state parameters. The waveform state parameters may include at least one of the following:

[0091] The first state parameter, which can be used to describe the allocation relationship between the input / output ports of the chip under test and the test channels available in the test device.

[0092] The input / output ports of the chip under test may include a first type of port (which can be denoted as an IO port) for input / output of digital signals (such as data signals, control signals, clock signal lights) and a second type of port (which can be denoted as a Power port) for supplying power to the chip under test.

[0093] The test channels available in the test device may include but are not limited to at least one of the following: digital channels for driving or capturing digital signals; power channels for supplying power to the chip under test.

[0094] The allocation relationship may match the total test channels of the test device. The total test channels of the test device can be understood as: the sum of all available physical test channels of the test device (such as, ATE, automatic test equipment).

[0095] The second state parameter, which is used to describe the voltage required for the test signals available for the chip under test.

[0096] The voltage required for the test signals available for the chip under test may include but are not limited to: high and low level voltages, clamping voltages, and power supply voltages.

[0097] The voltage required for the test signals available for the chip under test may be included within the voltage range that the test device can provide.

[0098] The third state parameter, which is used to describe the timing of the test signals available for the device under test. The timing matches the timing control accuracy of the device under test.

[0099] The timing of the test signals available for the device under test may include but are not limited to: waveform template library (wavetable), timing set (timingset), and period.

[0100] The waveform template library may include multiple preset waveform states (waveform). Among them, the multiple preset waveform states may include a reference waveform state predefined by the system and a waveform state defined by the user according to special requirements.

[0101] The timing set may include specific timing parameters (such as delay time, hold time) for each level transition edge (such as rising edge, falling edge) in the waveform.

[0102] The period can be understood as the period length of the complete repetition of the waveform.

[0103] The waveform template library (wavetable), the timing set, and the period can jointly define the timing of the test signal, that is, the number of edges in the test signal, the level state (high / low) of each edge, and the exact time point at which it occurs.

[0104] In this embodiment, through the first state parameter, the mapping relationship between the input / output ports of the chip under test and the channels of the test device (digital channel, power supply channel) can be clarified, ensuring that the physical channel allocation matches the total channel capacity of the test device, and avoiding problems such as the inability to load the test program or execute the terminal caused by channel overrun.

[0105] Through the second state parameter, the voltage of the test signal (such as high and low levels, clamping voltage) can be restricted within the voltage range supported by the test device, preventing the distortion of the test signal caused by voltage overrun.

[0106] Through the third state parameter, it can be ensured that the timing of the test signal available for the device under test matches the timing control accuracy of the device under test, avoiding the failure of the test program execution caused by timing deviation.

[0107] As another optional embodiment of the present application, refer to Figure 3 , which is a schematic flowchart of a processing method provided in Embodiment 4 of the present application. This embodiment is mainly an implementation manner of the above step S1012. As Figure 3 shown, step S1012 may include but is not limited to:

[0108] Step S10121: Based on the test case of the chip under test, form a test sub-operation sequence composed of multiple test sub-operations in a preset timing.

[0109] The test case may include multiple basic test operations, and each basic test operation may correspond to a specific test target, and this specific test target cannot be further decomposed into smaller test targets. For example, the basic test operation may include: setting the value of a certain register or sending a signal, etc.

[0110] The test sub-operation may correspond to a single basic test operation in the test case, which means that the test sub-operation may correspond to a specific test target. The test sub-operation can be understood as: a single test action applied to the chip under test, and its execution process cannot be further decomposed into smaller test steps.

[0111] The test sub-operations may include, but are not limited to, at least one of the following elements: the order of occurrence (i.e., the execution order of the test sub-operations), the object of occurrence (i.e., the object on which the test sub-operation acts, such as a register or a signal line), the default state (i.e., the state of the object before the test sub-operation starts), the initial state (i.e., the state of the object when the test sub-operation starts to execute), the termination state (i.e., the state that the object should reach after the test sub-operation is completed), and the time of occurrence and duration (i.e., the specific time when the test sub-operation starts and ends, and the duration of the test sub-operation).

[0112] For example, if the multiple test objectives of a test case may include: verifying the effectiveness of the clock source clk1 configuration, the synchronization of signal forcing, the reliability of writing to each register, and the reliability of reading from each register, etc. This test case can be decomposed into multiple test sub-operations, and the multiple test sub-operations may include: a clock configuration sub-operation, a forcing sub-operation on the signal line, a writing sub-operation to the register, a reading sub-operation from the register, and a status verification sub-operation on the signal line. The multiple test sub-operations can form a test sub-operation sequence according to a preset timing. For example, as Figure 4 shown, in the test sub-operation sequence, the serial number can represent the order of the test sub-operation in the test sub-operations.

[0113] Each serial number can be arranged according to a preset timing to ensure that the test sub-operations can be executed sequentially in a predetermined order. clk.config(clk1, wave1, time0) can represent the clock configuration sub-operation, that is, at time point time0, change the waveform of the clock source clk1 (i.e., an implementation manner of the object) of the test device from the default state to the wave1 state defined by the wavetable (i.e., an implementation manner in the termination state).

[0114] #100ns (i.e., an implementation manner of the duration) can represent that after the clock configuration sub-operation is completed, wait for 100ns to start the next test sub-operation, that is, sig.force(sig1, value1, time1).

[0115] sig.force(sig1, value1, time1) can represent that at time point time1 (i.e., an implementation manner of the time of occurrence), force the signal line sig1 (i.e., an implementation manner of the object) between the test device and the chip under test to the level value1 (i.e., an implementation manner of the initial state).

[0116] reg.write(addr0, data0) can represent writing data data0 (i.e., an implementation of the termination state) to the register of the chip under test according to the register address addr0 (i.e., an implementation of the object); the explanations of other reg.write can refer to the understanding of reg.write(addr0, data0), which will not be elaborated here.

[0117] sig.force(sig1, value1, time2) can represent forcing the signal line sig1 between the test device and the chip under test to the level value1 at the time point time2.

[0118] #500ns can represent waiting for 500ns to start the next test sub-operation, i.e., reg.write(addr6, data6), after forcing the signal line sig1 to the level value1.

[0119] reg.read(addr0, data0) can represent reading data data0 (i.e., an implementation of the initial state) from the corresponding register of the chip under test according to the register address addr0 (i.e., an implementation of the object); the explanations of other reg.read can refer to the understanding of reg.read(addr0, data0), which will not be elaborated here.

[0120] sig.receive(sig2, value2, time3) can represent capturing the data or level of the signal line sig2 between the test device and the chip under test at the time point time3 and comparing it with the expected value value2.

[0121] By combining these test sub-operations according to the preset timing sequence, an ordered test sub-operation sequence can be formed. The test sub-operation sequence can achieve each test target in the test case according to the preset timing sequence, and systematically verify the various functions of the chip under test.

[0122] Step S10122, based on the waveform state parameters and each test sub-operation in the test sub-operation sequence, respectively obtain the sub-test vectors supported by the test device corresponding to each test sub-operation.

[0123] Corresponding to each test sub-operation corresponding to a specific test target, the sub-test vectors supported by the test device corresponding to the test sub-operation can be used to verify the specific test target.

[0124] The sub-test vectors supported by the test device corresponding to the test sub-operation can include: input-type sub-test vectors or output-type sub-test vectors.

[0125] The sub-test vectors of the input type can contain logical values for representing the test sub-operations of the input type, and the test sub-operations of the input type can be used to perform input operations on the chip under test.

[0126] The sub-test vectors of the input type can include logical values such as 0, 1, Z, etc., and the logical values such as 0, 1, Z, etc. can correspond to the corresponding waveform states defined in the wavetable.

[0127] The logical value 0 can represent inputting a low-level signal that conforms to the digital logic standard to the chip under test or forcing the voltage on the signal line of the chip under test to be maintained at the low-level state.

[0128] The logical value 1 can represent inputting a high-level signal that conforms to the digital logic standard to the chip under test or forcing the voltage on the signal line of the chip under test to be maintained at the high-level state.

[0129] The logical value Z can represent that the test device enters the high-impedance state, configuring the chip under test as the output mode.

[0130] For example, as Figure 5 shown, the sub-test vectors of the input type can include: clk.config, sig.force, reg.write, and reg.read.

[0131] clk.config can contain logical values in different cycles (i.e., Cycle). As Figure 5 shown, the logical values (i.e., the logical values within the red box) in different cycles of the sub-test vector corresponding to the test sub-operation clk.config(clk, 1) can all represent configuring the clock source clk1 in different cycles.

[0132] sig.force can contain logical values corresponding to IO4 (i.e., an implementation of the signal line of the chip under test) in different cycles. The logical values in different cycles of this sub-test vector can represent forcing the voltage on the IO4 of the chip under test to be maintained at the high-level state or the low-level state in different cycles. As Figure 5 shown, the logical values (i.e., the logical values within the red box) in different cycles of the sub-test vector corresponding to the test sub-operation sig.force(IO4, 0) can all represent forcing the voltage on the IO4 of the chip under test to be maintained at the low-level state.

[0133] reg.write can contain logical values corresponding to IO1 (i.e., an implementation of the input / output port of the register of the chip under test) in different cycles. These logical values can include the logical values corresponding to the register address and the logical values corresponding to the data to be written. As Figure 5As shown, the logical values in the sub-test vectors corresponding to the reg.write(addr0) test sub-operation (i.e., 11…10 within the red box) can represent low-level or high-level signals input to the chip under test corresponding to the register address in different cycles. The logical values in the sub-test vectors corresponding to the reg.write(data0) test sub-operation (i.e., 01…11 within the red box) can represent low-level or high-level signals input to the chip under test corresponding to the data to be written in different cycles.

[0134] reg.read can include logical values corresponding to IO1 (i.e., one implementation of the input / output port of the register of the chip under test) and IO2 (i.e., another implementation of the input / output port of the register of the chip under test) in different cycles. These logical values can include the logical value corresponding to the register address and the logical value corresponding to the read command. As Figure 5 shown, the logical values in the sub-test vector corresponding to the test sub-operation reg.read(addr0) (i.e., 10…11 within the red box) can represent low-level or high-level signals input to the IO1 of the chip under test corresponding to the register address in different cycles. The logical values in the sub-test vector corresponding to the test sub-operation reg.read(data0) (i.e., 10…11 within the red box) can represent low-level or high-level signals input to the IO2 of the chip under test corresponding to the read command in different cycles.

[0135] The sub-test vectors of the output type can be used to verify the response of the chip under test after a specific operation. The sub-test vectors of the output type can include logical values such as 0, 1, M, X, etc. The logical values 0, 1, M, X, etc. can correspond to the corresponding waveform states defined in the wavetable. Among them, the logical value 0 can be used to represent that the expected output response is low level, the logical value 1 can be used to represent that the expected output response is high level, the logical value M can represent that the expected output response is a custom state, and the logical value X can represent that the expected output response is any state.

[0136] The expected output response can be compared with the actual output of the chip under test after a specific operation to verify the function of the chip under test.

[0137] As Figure 5 shown, the sub-test vectors of the output type can include: sig.receive. sig.receive can include logical values corresponding to IO3 (one implementation of the input / output port or signal line of the chip under test) in different cycles. As Figure 5 shown, the logical value (i.e., 1 within the red box) in the sub-test vector corresponding to the test sub-operation sig.receive(IO3,1) can represent that the expected output response at Cycle = 2 is 1.

[0138] It should be noted that Figure 5 The ones shown are only several examples of test sub-vectors, and they do not represent all forms or scopes of the test sub-vectors. These examples are only used to illustrate and show the possible forms and contents of the test sub-vectors, and do not impose any restrictions on the specific design, composition or application of the test sub-vectors.

[0139] In this embodiment, it is possible but not limited to compile each of the test sub-operations based on the waveform state parameter and each test sub-operation in the test sub-operation sequence to obtain the sub-test vectors supported by the corresponding test device. Although, in this embodiment, the sub-test vectors supported by the test device corresponding to each test sub-operation can be obtained through compilation, the manner of obtaining the sub-test vectors is not limited thereto, and other suitable obtaining manners can also be adopted according to actual requirements.

[0140] Compiling the sub-test vectors supported by the corresponding test device for each of the test sub-operations based on the waveform state parameter and each test sub-operation in the test sub-operation sequence can make the sub-test vectors not depend on each other, and each test sub-vector can be modified and optimized independently without affecting other sub-test vectors.

[0141] This independence between the sub-test vectors can enable each sub-test vector to be independently backed up to the template library, which is convenient for subsequently calling and combining different sub-test vectors as needed to form the initial test vector. When backing up, the sub-test vector can be associated and stored with the label of the test sub-operation. The label of the test sub-operation can be used to identify the test sub-operation.

[0142] Step S10123: Integrate each of the sub-test vectors in a preset time sequence to form an initial test vector.

[0143] In this embodiment, by integrating each of the sub-test vectors in a preset time sequence to form an initial test vector, the test cycles in the initial test vector can be matched with the test process of the test case. Within the test cycle, the logical values of different test sub-vectors can be included, and the combination of the logical values within the test cycle can be used to constitute the test conditions for the chip under test in this test cycle.

[0144] It should be noted that there are differences between the test cycles in the initial test vector and the cycles in the sub-test vectors. The cycles in the sub-test vectors are used to describe the internal timing behavior of the test sub-operations, while the test cycles are used to describe the global timing behavior of the test process of the test case. For example, as Figure 6As shown, the logical value corresponding to reg.write(addr0) (an implementation of the test sub-operation), i.e., 11…10 within the red box, has a test period from Cycle = 7 to Cycle = 38 in the initial test vector. The logical value corresponding to reg.write(addr0) (i.e., 11…10 within the red box) in the sub-test vector can be referred to Figure 5 , that is, the period in the sub-test vector is Cycle = 2 to Cycle = 33.

[0145] Based on the test cases of the chip under test, a test sub-operation sequence composed of multiple test sub-operations in a preset time sequence is formed. Subsequently, sub-test vectors are obtained based on the waveform state parameters and the test sub-operation sequence, and these sub-test vectors are integrated into an initial test vector. The beneficial effects can be deduced from the following aspects:

[0146] In this embodiment, based on the test cases of the chip under test, forming a test sub-operation sequence composed of multiple test sub-operations in a preset time sequence can achieve modular and structured design of the test process. In this way, when a certain test operation needs to be modified or updated, only the corresponding test sub-operation needs to be modified, without reconstructing the entire test case. On this basis, based on the waveform state parameters and each test sub-operation in the test sub-operation sequence, the sub-test vectors supported by the test device corresponding to each test sub-operation are obtained respectively, which can make the sub-test vectors correspond to the hardware performance and test objectives of the test device.

[0147] Moreover, the sub-test vectors do not depend on each other, and each test sub-vector can be modified and optimized independently without affecting other sub-test vectors.

[0148] In addition, integrating each sub-test vector into an initial test vector according to a preset time sequence can ensure the generation of an accurate test program based on the initial test vector. And during the execution stage of the test program, the initial test vector can be used to generate accurate input test signals and expected output responses, ensuring the reliability of the test.

[0149] As another optional embodiment of the present application, referring to Figure 7 , it is a schematic flowchart of a processing method provided in Embodiment 5 of the present application. As Figure 7 shown, the method may include but is not limited to the following steps:

[0150] Step S201: Obtain waveform state parameters, where the waveform state parameters are used to describe the test signals supported by the test device.

[0151] For the detailed process of step S201, reference can be made to the relevant introduction of step S1011 above, and details will not be elaborated here.

[0152] Step S202: Based on the test cases of the chip under test, form a test sub-operation sequence composed of multiple test sub-operations in a preset time sequence, where the sub-operations correspond to individual basic test operations within the test cases.

[0153] Step S203: Based on the waveform state parameters and each test sub-operation in the test sub-operation sequence, respectively obtain the sub-test vectors supported by the test equipment corresponding to each test sub-operation.

[0154] Step S204: Integrate each sub-test vector in a preset time sequence to form an initial test vector.

[0155] For the detailed processes of steps S202 - S204, reference can be made to the relevant introductions in steps S10121 - S10123 above, which will not be elaborated here.

[0156] Step S205: Screen out the test elements to be adjusted that do not meet the design specifications of the chip under test from the initial test vector.

[0157] In this embodiment, at least one of the test elements of the input type and the output type that do not meet the design specifications of the chip under test can be screened out from the initial test vector as the test elements to be adjusted.

[0158] The test elements of the input type can be used to generate the input test signals required by the chip under test, and the input test signals meet the hardware performance of the test equipment.

[0159] The test elements of the output type can be used to verify the response of the chip under test to the input test signals.

[0160] Step S206: Corresponding to the test elements to be adjusted, obtain the target test sub-operations; the target test sub-operations conform to the design specifications of the chip under test.

[0161] In the case where there is no corresponding test sub-operation for the test element to be adjusted in the test sub-operation sequence, according to the design specifications of the chip under test, construct a new test sub-operation corresponding to the test element to be adjusted as the target test sub-operation.

[0162] In the case where there is a corresponding test sub-operation for the test element to be adjusted in the test sub-operation sequence, the test sub-operation can be adjusted according to the design style of the chip under test, and the adjusted test sub-operation is used as the target test sub-operation.

[0163] Step S207: Based on the waveform state parameters and the target test sub-operations, compile to obtain the sub-test vectors corresponding to the target test sub-operations.

[0164] In this embodiment, the compilation process may include but is not limited to: generating a waveform description supported by the test device based on the waveform state parameter and the target test sub-operation, and converting the waveform description into a sub-test vector supported by the test device.

[0165] In this embodiment, although the sub-test vector corresponding to the target test sub-operation can be obtained through compilation, the method for obtaining the sub-test vector corresponding to the target test sub-operation is not limited thereto, and other suitable obtaining methods can also be adopted according to actual requirements. For example, a sub-test vector matching the target test sub-operation can also be called from the template library. The template library contains multiple test sub-vectors compiled and backed up according to different test cases of the waveform state parameter and the chip under test.

[0166] Step S208: Adjust the initial test vector based on the sub-test vector corresponding to the target test sub-operation.

[0167] In this embodiment, it is possible but not limited to replace the test element corresponding to the test element to be adjusted in the sub-test vector corresponding to the target test sub-operation with the test element to be adjusted in the initial test vector according to a preset timing sequence.

[0168] Step S209: Perform simulation verification on the chip under test based on the adjusted initial test vector, and adjust the adjusted initial test vector based on the simulation verification result until the simulation verification passes to form a target test vector.

[0169] Step S209 is an implementation manner of step S102 in Embodiment 1.

[0170] Step S210: Generate a test program for the test device based on the target test vector.

[0171] For the detailed process of step S210, reference can be made to the relevant introduction of step S103 in Embodiment 1, which will not be elaborated here.

[0172] In this embodiment, by screening out the test elements to be adjusted in the initial test vector that do not meet the design specifications of the chip under test, obtaining the target test sub-operation corresponding to the test element to be adjusted, compiling the sub-test vector corresponding to the target test sub-operation based on the waveform state parameter and the target test sub-operation, and adjusting the initial test vector based on the sub-test vector corresponding to the target test sub-operation, the errors or inconsistencies in the initial test vector can be corrected, making the initial test vector more in line with the design specifications of the chip under test, so as to provide a more practical initial test vector as the starting point for simulation verification, which helps to accelerate the simulation verification process.

[0173] On this basis, further adjust the initial test vector based on the simulation verification results, which can ensure that the initial test vector after the readjustment can accurately reflect the actual working requirements of the chip under test and improve the reliability of the test for the chip under test.

[0174] In this embodiment, the two adjustments of the initial test vector complement each other and jointly improve the quality and efficiency of the test.

[0175] As another optional embodiment of the present application, a processing method provided in Embodiment 6 of the present application. This embodiment is mainly an implementation manner of the above step S10122. Step S10122 may include but is not limited to:

[0176] Step S21: Call the sub-test vectors supported by the test equipment that match each of the test sub-operations from the template library; the template library contains multiple test sub-vectors compiled and backed up according to the waveform state parameters and different test cases of the chip under test.

[0177] Corresponding to the implementation manner in which the sub-test vectors and the labels of the test sub-operations are associated and stored in the template library, the sub-test vectors associated with the labels of each of the test sub-operations can be called from the template library.

[0178] For the detailed process of compiling and backing up according to the waveform state parameters and different test cases of the chip under test, reference can be made to the relevant introduction in the above step S10122, which will not be elaborated here.

[0179] In this embodiment, by calling the sub-test vectors that have been compiled and backed up from the template library, the time for test preparation can be saved. Compared with recompiling the sub-test vectors every time a test is performed, this calling method can improve the efficiency of the test.

[0180] As another optional embodiment of the present application, a schematic flowchart of a processing method provided in Embodiment 7 of the present application. This embodiment is mainly an implementation manner of the above step S102. In this embodiment, the initial test vector may include: an initial input test vector and an initial output test vector. Step S102 may include but is not limited to the following steps:

[0181] Step S1021: Process the initial input test vector based on the simulation model to obtain a simulation output vector.

[0182] In this embodiment, based on the initial input test vector, a simulation input signal can be obtained, the simulation input signal is input into the simulation model, and a simulation output signal determined by the simulation model is obtained. The simulation output signal is converted into a simulation output vector.

[0183] The simulation model can be used to simulate the behavior of the chip under test in a real working environment and verify the functions of the chip under test.

[0184] The simulation output vector can be used to represent the actual output response of the simulation model to the initial input test vector.

[0185] Step S1022: Compare the simulation output vector and the initial output test vector to obtain a simulation verification result.

[0186] In this embodiment, the simulation output vector and the initial output test vector can be compared to obtain a simulation verification result when the simulation output vector is consistent with the expected output response in the test case.

[0187] If the simulation verification result indicates that the simulation output vector is inconsistent with the initial output test vector, it can be regarded as a failed simulation verification; if the simulation verification result indicates that the simulation output vector is consistent with the initial output test vector, it can be regarded as a passed simulation verification.

[0188] Step S1023: If the simulation verification result indicates that the simulation output vector is inconsistent with the initial output test vector, calibrate the initial output test vector based on the simulation output vector.

[0189] In this embodiment, the calibration method can include but is not limited to: replacing the initial output test vector as a whole with the simulation output vector; or, locating the incorrect test elements in the initial output test vector that are inconsistent with the simulation output vector, and extracting the corresponding parts in the simulation output vector to replace the incorrect test elements in the initial output test vector.

[0190] In this embodiment, the initial input test vector is processed based on the simulation model to obtain a simulation output vector. When the simulation output vector is consistent with the expected output response in the test case, the accuracy of the initial input test vector is verified.

[0191] On the basis that the accuracy of the initial input test vector is verified and no adjustment is required, the simulation output vector and the initial output test vector are compared to obtain a simulation verification result. If the simulation verification result indicates that the simulation output vector is inconsistent with the initial output test vector, calibrating the initial output test vector based on the simulation output vector can ensure that the initial output test vector (i.e., the target test vector) passing the simulation verification can more accurately reflect the expected response of the chip under test in actual work, thereby improving the quality of the test.

[0192] Next, the processing device provided by the present application will be introduced. The processing device introduced below can be correspondingly referred to the processing method introduced above.

[0193] Referring to Figure 8 , the processing device includes: a test vector generation module 100, a simulation and data processing module 200, and a test program development module 300.

[0194] The test vector generation module 100 can be connected to the simulation and data processing module 200, and the test program development module 300 can be respectively connected to the test vector generation module 100 and the simulation and data processing module 200.

[0195] The test vector generation module 100 is configured to generate an initial test vector supported by the test device according to the test device and test cases for the chip under test.

[0196] The test vector generation module 100 can transmit the initial test vector supported by the test device to the simulation and data processing module 200 and the test program development module 300.

[0197] The simulation and data processing module 200 is configured to perform simulation verification on the chip under test based on the initial test vector, and adjust the initial test vector based on the simulation verification result until the simulation verification passes, forming a target test vector.

[0198] The program test development module 300 can start the development of the test program framework based on the initial test vector.

[0199] The test program development module 300 is configured to generate a test program for the test device based on the target test vector.

[0200] The test program can be deployed to the test device, and the test device can test the chip under test based on the test program.

[0201] In this embodiment, as Figure 9 shown, the test vector generation module 100 may include:

[0202] A waveform description module 1001, a test case sequence writing module 1002, and a test vector compilation module 1003 respectively connected to the waveform description module 1001 and the test case sequence writing module 1002.

[0203] The waveform description module 1001 is configured to obtain waveform state parameters, and the waveform state parameters are used to describe test signals supported by the test device.

[0204] The waveform description module 1001 can transmit the waveform state parameters to the test vector compilation module 1003.

[0205] The test case sequence writing module 1002 is configured to form a test sub-operation sequence composed of a plurality of test sub-operations in a preset time sequence based on the test cases of the chip under test, and the sub-operations correspond to individual basic test operations within the test cases.

[0206] The test case sequence writing module 1002 can transmit the test sub-operation sequence to the test vector compilation module 1003.

[0207] The test vector compilation module 1003 is configured to respectively obtain sub-test vectors supported by the test device corresponding to each test sub-operation based on the waveform state parameters and the test sub-operations in the test sub-operation sequence; and integrate the sub-test vectors in a preset time sequence to form an initial test vector.

[0208] In another embodiment of the present application, an electronic device is provided, which may include: a memory for storing at least a set of instruction sets.

[0209] The processor is configured to call and execute the instruction sets in the memory, and execute the processing method introduced in any of the above embodiments by executing the instruction sets.

[0210] In addition, it should be noted that the device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the device embodiments provided in the present application, the connection relationship between the modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines.

[0211] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions accomplished by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be diverse, such as analog circuits, digital circuits or dedicated circuits, etc. However, for the present application, in more cases, software program implementation is a better embodiment. Based on such understanding, the technical solution of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disc of a computer, etc., and includes several instructions for causing a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0212] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0213] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, training device or data center to another website, computer, training device or data center in a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A processing method, comprising: Generating an initial test vector supported by the test device according to the test device and test cases for the chip under test; Based on the initial test vector, performing simulation verification on the chip under test, and adjusting the initial test vector based on the simulation verification result until the simulation verification passes, to form a target test vector; Generating a test program for the test device based on the target test vector.

2. The processing method according to claim 1, wherein the generating an initial test vector supported by the test device according to the test device and test cases for the chip under test comprises: Obtaining waveform state parameters, where the waveform state parameters are used to describe test signals supported by the test device; Generating an initial test vector supported by the test device based on the waveform state parameters and test cases for the chip under test.

3. The processing method according to claim 2, wherein the waveform state parameters include at least one of the following: A first state parameter, used to describe the allocation relationship between the input / output ports of the chip under test and the test channels available in the test device; the allocation relationship matches the total test channels of the test device; A second state parameter, used to describe the voltage required for the test signals available for the chip under test; the voltage is within the voltage range that the test device can provide; A third state parameter, used to describe the timing of the test signals available for the device under test; The timing matches the timing control accuracy of the device under test.

4. The processing method according to claim 2, wherein the generating an initial test vector supported by the test device based on the waveform state parameters and test cases for the chip under test comprises: Based on the test cases for the chip under test, forming a test sub-operation sequence composed of multiple test sub-operations in a preset timing, where the sub-operations correspond to individual basic test operations within the test cases; Based on the waveform state parameters and each test sub-operation in the test sub-operation sequence, respectively obtaining sub-test vectors supported by the test device corresponding to each test sub-operation; Integrating the sub-test vectors according to a preset timing to form an initial test vector.

5. The processing method according to claim 4, before performing simulation verification on the chip under test based on the initial test vector, further comprising: Screening out test elements to be adjusted in the initial test vector that do not conform to the design specifications of the chip under test; Corresponding to the test elements to be adjusted, obtaining target test sub-operations; The target test sub-operations conform to the design specifications of the chip under test; Compiling to obtain a sub-test vector corresponding to the target test sub-operation based on the waveform state parameters and the target test sub-operation; Adjusting the initial test vector based on the sub-test vector corresponding to the target test sub-operation.

6. The processing method according to claim 4, wherein the respectively obtaining sub-test vectors supported by the test device corresponding to each test sub-operation comprises: Respectively calling sub-test vectors supported by the test device that match each test sub-operation from a template library; The template library contains a plurality of test sub-vectors compiled and backed up according to the waveform state parameters and different test cases of the chip under test.

7. The processing method according to claim 1, wherein the initial test vector includes: An initial input test vector and an initial output test vector; Based on the initial test vector, performing simulation verification on the chip under test, and adjusting the initial test vector based on the simulation verification result, including: Processing the initial input test vector based on a simulation model to obtain a simulation output vector; Comparing the simulation output vector and the initial output test vector to obtain a simulation verification result; If the simulation verification result indicates that the simulation output vector and the initial output test vector are inconsistent, calibrating the initial output test vector based on the simulation output vector.

8. A processing device, comprising: A test vector generation module, configured to generate an initial test vector supported by the test device according to a test device and test cases for a chip under test; A simulation and data processing module, configured to perform simulation verification on the chip under test based on the initial test vector, and adjust the initial test vector based on the simulation verification result until the simulation verification passes, to form a target test vector; A test program development module, configured to generate a test program for the test device based on the target test vector.

9. The processing device according to claim 8, wherein the test vector generation module comprises: A waveform description module, configured to obtain waveform state parameters for describing test signals supported by the test device; A test case sequence writing module, configured to form a test sub-operation sequence composed of a plurality of test sub-operations in a preset time sequence based on test cases of the chip under test, where the sub-operations correspond to individual basic test operations in the test cases; A test vector compilation module, configured to respectively obtain sub-test vectors supported by the test device corresponding to each test sub-operation based on the waveform state parameters and the test sub-operations in the test sub-operation sequence; and integrate the sub-test vectors in a preset time sequence to form an initial test vector.

10. An electronic device, comprising: A memory, configured to store at least one set of instruction sets; The processor is configured to call and execute the instruction sets in the memory, and execute the processing method according to any one of claims 1-7 by executing the instruction sets.

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