Data reading control method and device and related equipment

Abstract

The invention discloses a data reading control method and device and related equipment, and the method comprises the steps: obtaining the total income brought by starting a memory advanced reading mechanism of a slave control module according to a preset time period; and according to the total revenue, opening or closing a memory advanced reading mechanism of the slave control module in a corresponding time period, so that the slave control module reads corresponding message data from a memory in advance or not in advance when receiving a preset reading request sent by the master control module. The embodiment of the invention is beneficial to improving the utilization rate of the memory bandwidth, correspondingly reducing the delay time of memory access and improving the system performance.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of computer information processing, and in particular, to a data reading control method, apparatus and related equipment. Background Art

[0002] Generally, the data received by the central processing unit (CPU) through the input / output (I / O) device is stored in the memory, and whether the data exists in the cache depends on whether the application reads the data.

[0003] For some computer systems, the memory prefetch mechanism of the slave control module in the data weaving module is used to prefetch and store the requested data from the memory in advance to minimize possible latency.

[0004] However, the use of the memory prefetch mechanism of the slave control module will cause excessive occupation of the memory bandwidth, which is not conducive to the improvement of the memory bandwidth utilization rate and system performance. Summary of the Invention

[0005] In view of this, the embodiments of the present invention provide a data reading control method, apparatus and related equipment, which can improve the utilization rate of the memory bandwidth and improve the system performance.

[0006] To achieve the above object, the embodiments of the present invention provide a data reading control method, including:

[0007] Obtaining the total benefit brought by enabling the memory prefetch mechanism of the slave control module according to a preset time period;

[0008] According to the total benefit, enabling or disabling the memory prefetch mechanism of the slave control module within the corresponding time period, so that the slave control module reads the corresponding message data from the memory in advance or not in advance when receiving a read request sent by a preset master control module.

[0009] Optionally, the enabling or disabling the memory prefetch mechanism of the slave control module according to the total benefit includes:

[0010] If the total benefit is greater than zero, enabling the memory prefetch mechanism of the slave control module within the corresponding time period;

[0011] If the total benefit is less than or equal to zero, disabling the memory prefetch mechanism of the slave control module within the corresponding time period.

[0012] Optionally, the total benefit brought by enabling the memory prefetch mechanism of the slave control module satisfies:

[0013] M*A+(L-M)*C-M*B;

[0014] Wherein, L represents the length of the message data received by the memory within the corresponding time period, M represents the length of the message data accessed by the processor within the corresponding time period, A represents the positive benefit value brought by enabling the memory prefetch mechanism of the slave module for each unit length of the M-length message data when the processor accesses the M-length message data within the corresponding time period, B represents the negative benefit value brought by enabling the memory prefetch mechanism of the slave module for each unit length of the M-length message data when the processor forwards the L-length message data within the corresponding time period, and C represents the positive benefit value brought by enabling the memory prefetch mechanism of the slave module for each unit length of the (L - M)-length message data not accessed by the processor when the processor forwards the L-length message data within the corresponding time period;

[0015] Enabling or disabling the memory prefetch mechanism of the slave module within the corresponding time period according to the total benefit includes: if M * A + (L - M) * C - M * B > 0, then enable the memory prefetch mechanism of the slave module within the corresponding time period; if M * A + (L - M) * C - M * B ≤ 0, then disable the memory prefetch mechanism of the slave module within the corresponding time period.

[0016] Optionally, when the values of A, B, and C are determined:

[0017] If M * A + (L - M) * C - M * B > 0, then enabling the memory prefetch mechanism of the slave module within the corresponding time period includes: if or or and it is detected that within the previous time period then enable the memory prefetch mechanism of the slave module within the corresponding time period;

[0018] If M * A + (L - M) * C - M * B ≤ 0, then disabling the memory prefetch mechanism of the slave module within the corresponding time period includes: if and it is detected that within the previous time period then disable the memory prefetch mechanism of the slave module within the corresponding time period.

[0019] Optionally, when the values of A, B, and C are uncertain:

[0020] If M * A + (L - M) * C - M * B > 0, then enabling the memory prefetch mechanism of the slave module within the corresponding time period includes: if it is detected through testing that or and Then, within the corresponding time period, enable the memory prefetch mechanism of the slave module;

[0021] If M*A+(L-M)*C-M*B≤0, then within the corresponding time period, disable the memory prefetch mechanism of the slave module, including: if it is detected through testing that and then within the corresponding time period, disable the memory prefetch mechanism of the slave module.

[0022] Optionally, if it is detected through testing that or and then within the corresponding time period, enable the memory prefetch mechanism of the slave module, including: if by respectively testing the system performance of enabling and disabling the memory prefetch mechanism of the slave module in the cases of and it is obtained that the system performance of enabling the memory prefetch mechanism of the slave module in the cases of and is better than the system performance of disabling the memory prefetch mechanism of the slave module, indicating that or then within the corresponding time period, enable the memory prefetch mechanism of the slave module; in other cases, if by sampling and testing the value of it is obtained that is less than a sampling value, and the system performance of enabling the memory prefetch mechanism of the slave module is better than the system performance of disabling the memory prefetch mechanism of the slave module, indicating that and then within the corresponding time period, enable the memory prefetch mechanism of the slave module;

[0023] If it is detected through testing that and then within the corresponding time period, disable the memory prefetch mechanism of the slave module, including: in other cases, if by sampling and testing the value of it is obtained that is greater than or equal to the sampling value, and the system performance of disabling the memory prefetch mechanism of the slave module is better than or equal to the system performance of enabling the memory prefetch mechanism of the slave module, indicating that and then within the corresponding time period, disable the memory prefetch mechanism of the slave module.

[0024] Optionally, the slave module includes a cache coherence slave interface, and the preset master module includes a cache coherence master interface and an input / output master interface.

[0025] Accordingly, an embodiment of the present invention further provides a data reading control module, including:

[0026] An acquisition unit, configured to acquire the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period;

[0027] A control unit, configured to enable or disable the memory pre-reading mechanism of the slave control module within a corresponding time period according to the total benefit, so that when the slave control module receives a preset reading request sent by the master control module, it reads or does not read the corresponding message data from the memory in advance.

[0028] Accordingly, an embodiment of the present invention further provides an acceleration library, where the acceleration library includes a data reading control module, and the data reading control module is configured to execute the data reading control method described in any one of the above.

[0029] Accordingly, an embodiment of the present invention further provides a computer system, including the acceleration library described above.

[0030] Optionally, the acceleration library includes any one of DPDK and SPDK.

[0031] Accordingly, an embodiment of the present invention further provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they are used to implement the data reading control method described in any one of the above.

[0032] Accordingly, an embodiment of the present invention further provides a computer device, including: at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the data reading control method described in any one of the above.

[0033] Accordingly, an embodiment of the present invention further provides a storage medium, where the storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are used to execute the data reading control method described in any one of the above.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0035] The embodiment of the present invention provides a data reading control method, device and related equipment. The method includes: acquiring the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period; enabling or disabling the memory pre-reading mechanism of the slave control module within a corresponding time period according to the total benefit, so that when the slave control module receives a preset reading request sent by the master control module, it reads or does not read the corresponding message data from the memory in advance.

[0036] The data reading control method provided by the embodiments of the present invention enables, according to the total benefit brought by enabling the memory pre-reading mechanism of the slave control module, to enable or disable the memory pre-reading mechanism of the slave control module within the corresponding time period, which can avoid the memory pre-reading operation of the slave control module from excessively occupying the memory bandwidth, thereby being conducive to improving the utilization rate of the memory bandwidth, correspondingly conducive to reducing the latency of memory access, and improving the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0038] Figure 1 It is a schematic diagram of an optional structure of a computer system in the embodiments of the present invention;

[0039] Figure 2 It is a schematic diagram of an optional process of a data reading control method in the embodiments of the present invention;

[0040] Figure 3 It is a schematic block diagram of an optional data reading control module in the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0042] As described in the background art, the memory pre-reading mechanism of the slave control module will cause excessive occupation of the memory bandwidth, which is not conducive to the utilization rate of the memory bandwidth and the improvement of the system performance.

[0043] With reference to Figure 1 , a computer system includes at least one CPU group (CPU Complex, CCX) 100, a data weaving module 200, a memory controller 300, and a memory 400. Among them, at least one CPU group 100, the data weaving module 200, the memory controller 300, and the memory 400 are sequentially coupled.

[0044] Among them, each of the at least one CPU group 100 respectively includes a plurality of application programs 00, an acceleration library 01, and a plurality of CPU cores 110. The data weaving module 200 includes a first master control module 210, a slave control module 220, and a second master control module 230.

[0045] The plurality of application programs 00 and the acceleration library 01 can be stored in a storage module (not shown) within the CPU group 100, such as in a flash memory. The acceleration library 01 is disposed between the plurality of application programs 00 and the plurality of CPU cores 110, and is used for forwarding and processing data between the application programs 00 and the CPU cores 110.

[0046] The plurality of CPU cores 110 are respectively coupled to corresponding first master control modules 210 in the data weaving module 200. The second master control module 230 is used for coupling to an external I / O device. The slave control module 220 is respectively coupled to the first master control module 210 and the second master control module 230.

[0047] As an example, the first master control module 210 is a Cache-Coherent Master (CCM) interface, the slave control module 220 is a Coherent Slave (CS) interface, and the second master control module 230 is an Input / Output Master (IOM) interface. It can be understood that the first master control module, the second master control module, and the slave control module can also be other modules with similar functions, which are not limited herein.

[0048] In the data weaving module 200, when receiving a data read request sent by the first master control module 210 or the second master control module 230, before the slave control module 220 determines whether the requested data exists in the CPU cache (not shown) by looking up the cache coherence table, it will send a corresponding read command to the memory controller 300, obtain the requested data from the memory 400 and store it. In this application, this mechanism is called the memory prefetching mechanism of the slave control module.

[0049] However, if the data requested by the data read request already exists in the CPU cache, the slave control module 220 can directly request the corresponding data from the CPU cache by looking up the coherence cache table. At this time, using the memory prefetching mechanism of the slave control module 220 to obtain the corresponding data from the memory 400 will be a redundant operation, which thus causes excessive occupation of the memory bandwidth, reduces the utilization rate of the occupied memory bandwidth, and exacerbates the memory access latency.

[0050] Based on this, the embodiments of the present invention provide a data reading control method, apparatus and related devices. The method includes: obtaining the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period; and enabling or disabling the memory pre-reading mechanism of the slave control module within the corresponding time period according to the total benefit, so that the slave control module reads the corresponding message data from the memory in advance or not in advance when receiving a reading request sent by a preset master control module.

[0051] The data reading control method provided by the embodiments of the present invention enables or disables the memory pre-reading mechanism of the slave control module within the corresponding time period according to the total benefit brought by enabling the memory pre-reading mechanism of the slave control module, which can avoid the memory pre-reading operation of the slave control module from occupying the memory bandwidth too much, thereby facilitating the improvement of the utilization rate of the memory bandwidth, correspondingly facilitating the reduction of the latency time of memory access, and improving the system performance.

[0052] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0053] In an optional embodiment of the present invention, refer to Figure 2 the optional flowchart of a data reading control method shown in Figure 2 As shown, the data reading control method includes:

[0054] Step S210: Obtain the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period;

[0055] Step S220: Enable or disable the memory pre-reading mechanism of the slave control module within the corresponding time period according to the total benefit, so that the slave control module reads the corresponding message data from the memory in advance or not in advance when receiving a reading request sent by a preset master control module.

[0056] Please continue to refer to Figure 1 and execute step S210 to obtain the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period.

[0057] Obtaining the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period provides a basis for enabling or disabling the memory pre-reading mechanism of the slave control module within the corresponding time period according to the total benefit, so that the slave control module reads the corresponding message data from the memory in advance or not in advance when receiving a reading request sent by a preset master control module.

[0058] If within a preset time period, the length of the message data received by the memory within the corresponding time period is L, and the length of the message data accessed by the processor (such as a CPU) is M. Since the message data of length M is stored in the memory in the form of Direct Memory Access (DMA) rather than in the processor cache, that is, the information of the message data of length M is not maintained in the cache coherence table, thus enabling the memory prefetch mechanism of the slave control module can reduce the latency caused by searching the cache coherence table, which will bring positive benefits to the processor accessing the message data of length M.

[0059] Correspondingly, denote the positive benefit value brought by enabling the memory prefetch mechanism of the slave control module to the message data of unit length in the message data of length M accessed by the processor as A, then the total benefit value brought by enabling the memory prefetch mechanism of the slave control module to the message data of length M accessed by the processor can be correspondingly denoted as M * A.

[0060] After accessing the message data of length M, the processor forwards the message data of length L within the time period.

[0061] Among the message data of length L, the message data of length M has been stored in the processor cache because it was previously accessed by the processor. Enabling the memory prefetch mechanism of the slave control module makes it a repeated operation for the slave control module to obtain the message data of length M from the memory. Therefore, enabling the memory prefetch mechanism of the slave control module brings negative benefits to the message data of length M accessed by the processor.

[0062] Correspondingly, when the processor forwards the message data of length L within the corresponding time period, denote the negative benefit value brought by enabling the memory prefetch mechanism of the slave control module to the message data of unit length in the message data of length M accessed by the processor as B. Then, when the processor forwards the message data of length L within the corresponding time period, the total benefit brought by enabling the memory prefetch mechanism of the slave control module to the message data of length M accessed by the processor can be correspondingly denoted as -M * B.

[0063] In addition, among the message data of length L, the message data of length (L - M) has always been in the memory because it was not previously accessed by the processor. Enabling the memory prefetch mechanism to obtain the message data of length (L - M) from the memory will bring positive benefits.

[0064] Accordingly, when the processor forwards packet data of length L within a corresponding time period, the memory prefetch mechanism of the slave module is enabled, and the positive benefit value brought by the packet data of unit length in the (L - M)-length packet data not accessed by the processor is denoted as C. Then, when the processor forwards packet data of length L within a corresponding time period, the total benefit brought by the memory prefetch mechanism of the slave module for the (L - M)-length packet data not accessed by the processor can be correspondingly denoted as (L - M)*C.

[0065] It can be seen therefrom that within a corresponding time period, the total benefit brought by enabling the memory prefetch mechanism of the slave module can be expressed as:

[0066] M*A+(L - M)*C - M*B(1)

[0067] As can be seen from the above formula (1), within each time period, the total benefit brought by enabling the memory prefetch mechanism of the slave module is related to the values of M, L, A, B, and C.

[0068] Please continue to refer to Figure 1 and execute step S120. According to the total benefit, enable or disable the memory prefetch mechanism of the slave module within a corresponding time period, so that the slave module reads or does not read the corresponding packet data from the memory in advance when receiving a preset read request sent by the master module.

[0069] Enabling or disabling the memory prefetch mechanism of the slave module within a corresponding time period according to the total benefit, so that the slave module reads or does not read the corresponding packet data from the memory in advance when receiving a preset read request sent by the master module, can avoid the redundant memory prefetch of the slave module from occupying the memory bandwidth, which is correspondingly beneficial to improving the utilization rate of the memory bandwidth, thereby helping to reduce the latency of memory access and improve the system performance.

[0070] In an exemplary embodiment, the step of enabling or disabling the memory prefetch mechanism of the slave module within a corresponding time period according to the total benefit includes: if the total benefit is greater than zero, enable the memory prefetch mechanism of the slave module within the corresponding time period; if the total benefit is less than or equal to zero, disable the memory prefetch mechanism of the slave module within the corresponding time period.

[0071] When the total revenue is greater than zero, enabling the memory prefetch mechanism of the slave control module will have a positive effect on system performance improvement. Therefore, the memory prefetch mechanism of the slave control module is enabled within the corresponding time period. Conversely, when the total revenue is less than or equal to zero, it indicates that enabling the memory prefetch mechanism of the slave control module will have a negative effect on system performance improvement. Thus, the memory prefetch mechanism of the slave control module is disabled within the corresponding time period.

[0072] Combined with formula (1), it can be seen that if the total revenue brought by enabling the memory prefetch mechanism of the slave control module is to be greater than zero within the corresponding time period, that is, to satisfy:

[0073] M*A+(L-M)*C-M*B>0 (2)

[0074] Conversely, if the total revenue brought by enabling the memory prefetch mechanism of the slave control module is to be less than or equal to zero within the corresponding time period, that is, to satisfy:

[0075] M*A+(L-M)*C-M*B≤0 (3)

[0076] Correspondingly, in an exemplary embodiment, when the values of A, B, and C are determined, if M*A+(L-M)*C-M*B>0, the steps of enabling the memory prefetch mechanism of the slave control module within the corresponding time period include: if or or and it is detected that within the previous time period then the memory prefetch mechanism of the slave control module is enabled within the corresponding time period.

[0077] Combined with reference formula (2), to satisfy that the total revenue of enabling the memory prefetch mechanism of the slave control module is greater than zero within the corresponding time period, when B+C-A>0, formula (2) is transformed as follows:

[0078]

[0079] When B+C-A<0, formula (2) is transformed as follows:

[0080]

[0081] Meanwhile, within the corresponding time period, the packet length M accessed by the processor is less than or equal to the packet length L received by the memory. Therefore, the ratio between the packet length M accessed by the processor and the packet length L received by the memory satisfies:

[0082]

[0083] Combining the above formulas (4) and (6), it can be seen that when the values of A, B, and C are determined and in the case of, it can be directly and unambiguously determined that and the numerical relationship between them satisfies formula (4), that is, the total benefit brought by enabling the memory prefetch mechanism of the slave control module within the corresponding time period is greater than zero. Therefore, the memory prefetch mechanism of the slave control module is enabled within the corresponding time period.

[0084] Similarly, combining the above formulas (5) and (6), it can be seen that when the values of A, B, and C are determined and in the case of, it can be directly and unambiguously determined that and the numerical relationship between them satisfies formula (5), that is, the total benefit brought by enabling the memory prefetch mechanism of the slave control module within the corresponding time period is greater than zero. Therefore, the memory prefetch mechanism of the slave control module is enabled within the corresponding time period.

[0085] And combining the above formulas (4) and (6), it can be seen that when the values of A, B, and C are determined and in the case of, because and are both values greater than or equal to zero and less than or equal to 1, therefore, within the corresponding time period, and the magnitude relationship between them cannot be determined, that is, there may be a situation where the value of is greater than the value of , or there may be a situation where the value of is less than or equal to the value of .

[0086] At this time, according to the correlation between the packet data transmitted over the network in adjacent time periods, the magnitude relationship between and within the current time period can be estimated. Specifically, the magnitude relationship between and in the previous time period can be used as the magnitude relationship between and within the current time period.

[0087] Correspondingly, when the values of A, B, and C are determined and in the case of, if the value of in the previous time period is less than the value of , then according to the correlation between the packet data transmitted over the network in adjacent time periods, it can be estimated that within the current time period The value of is also less than the value of

[0088] In an exemplary embodiment, when the values of A, B, and C are determined, if M*A+(L-M)*C-M*B≤0, then the step of closing the memory prefetch mechanism of the slave control module in the corresponding time period includes: if and it is detected that in the previous time period then the memory prefetch mechanism of the slave control module is closed in the corresponding time period.

[0089] Combined with the above formula (3), to satisfy that the total benefit of enabling the memory prefetch mechanism of the slave control module in the corresponding time period is less than or equal to zero, then when B+C-A>0, that is, when the above formula (3) is transformed to obtain:

[0090]

[0091] Combined with the above formulas (6) and (7), it can be seen that when the values of A, B, and C are determined and since and are both values greater than or equal to 0 and less than or equal to 1, therefore, in the corresponding time period, and the magnitude relationship between the values cannot be determined.

[0092] Similarly, according to the correlation between the packet data transmitted over the network in adjacent time periods, when the values of A, B, and C are determined and if the value of in the previous time period is greater than or equal to the value of then it is estimated that the value of in the current time period is also greater than or equal to the value of At this time, the total benefit brought by enabling the memory prefetch mechanism of the slave control module in the current time period is less than or equal to zero, so the memory prefetch mechanism of the slave control module is closed in the current time period.

[0093] It should be noted that when the values of A, B, and C are determined and if the current time period is the first time period, there is no previous time period, and correspondingly, it is also impossible to use the magnitude relationship between and in the previous time period as The numerical size relationship with At this time, within the first time period, those skilled in the art can choose to turn on or off the memory pre-reading mechanism of the slave control module according to actual needs, which is not limited herein.

[0094] It can be understood that in addition to the situation where the numerical values of A, B, and C can be determined, there may also be a situation where the numerical values of A, B, and C cannot be determined.

[0095] In an exemplary embodiment, when the numerical values of A, B, and C are uncertain, if M*A+(L-M)*C-M*B>0, then the steps of turning on the memory pre-reading mechanism of the slave control module in the corresponding time period include: if it is detected through testing that or and then turn on the memory pre-reading mechanism of the slave control module in the corresponding time period.

[0096] Correspondingly, when the numerical values of A 、 B 、 C are uncertain, if M*A+(L-M)*C-M*B≤0, then the steps of turning off the memory pre-reading mechanism of the slave control module in the corresponding time period include: if it is detected through testing that and then turn off the memory pre-reading mechanism of the slave control module in the corresponding time period.

[0097] Combined with the above formula (3), it can be seen that when the numerical values of A, B, and C cannot be determined, then the numerical value of correspondingly cannot be determined, so that the numerical size relationship between and

[0098] in each time period cannot be determined, and further the total benefit brought by turning on the memory pre-reading mechanism of the slave control module in the corresponding time period cannot be determined. For this reason, in an exemplary embodiment, a reverse test verification method is adopted to obtain the numerical size relationship with

[0099] Specifically, if it is detected through testing that or and then the steps of turning on the memory pre-reading mechanism of the slave control module in the corresponding time period include: if by and the system performance of turning on and off the memory pre-reading mechanism of the slave control module is tested respectively under the conditions of and In the case where the memory prefetch mechanism of the slave control module is enabled, the system performance is better than that when the memory prefetch mechanism of the slave control module is disabled, indicating that or then the memory prefetch mechanism of the slave control module is enabled within the corresponding time period; in other cases, if by sampling and testing the value of and obtaining a value less than a sampling value, the system performance when the memory prefetch mechanism of the slave control module is enabled is better than that when the memory prefetch mechanism of the slave control module is disabled, indicating that and then the memory prefetch mechanism of the slave control module is enabled within the corresponding time period.

[0100] Correspondingly, if it is detected through testing that and then the step of disabling the memory prefetch mechanism of the slave control module within the corresponding time period includes: in other cases, if by sampling and testing the value of and obtaining a value greater than or equal to the sampling value, the system performance when the memory prefetch mechanism of the slave control module is disabled is better than or equal to that when the memory prefetch mechanism of the slave control module is enabled, indicating that and then the memory prefetch mechanism of the slave control module is disabled within the corresponding time period.

[0101] The values that satisfy satisfy the above formula (6). Correspondingly, in cases, the system performance when the memory prefetch mechanism of the slave control module is enabled and disabled is obtained through testing respectively, and in cases, the system performance when the memory prefetch mechanism of the slave control module is enabled and disabled is obtained through testing respectively.

[0102] If in and cases, the system performance when the memory prefetch mechanism of the slave control module is enabled is better than that when the memory prefetch mechanism of the slave control module is disabled, indicating that in is any value in [0,1], the total benefit of enabling the memory prefetch mechanism of the slave control module is greater than zero, then combining the foregoing description, it can be known that or That is, the total benefit brought by enabling the memory prefetch mechanism of the slave control module is greater than zero, so the memory prefetch mechanism of the slave control module is enabled within the corresponding time period.

[0103] If neither of the above two situations is satisfied, it correspondingly indicates that At this time, it is possible to perform a sampling test on the value of to obtain the system performance with the memory prefetch mechanism of the slave control module enabled and the system performance with the memory prefetch mechanism of the slave control module disabled, so as to approximate the value of by continuously adjusting the value of

[0104] Specifically, make the value of be different sampling values in [0, 1], and detect and obtain the system performance with the memory prefetch mechanism of the slave control module enabled and the system performance with the memory prefetch mechanism of the slave control module disabled when is different sampling values.

[0105] If, when is a value less than the sampling value, it is detected that the system performance with the memory prefetch mechanism of the slave control module enabled is better than the system performance with the memory prefetch mechanism of the slave control module disabled, and when is a value greater than or equal to the sampling value, it is detected that the system performance with the memory prefetch mechanism of the slave control module disabled is better than or equal to the system performance with the memory prefetch mechanism of the slave control module enabled, then it can be determined that has the same value as the sampling value.

[0106] Correspondingly, when is less than the sampling value, it is detected that the system performance with the memory prefetch mechanism of the slave control module enabled is better than the system performance with the memory prefetch mechanism of the slave control module disabled, indicating that and then the total benefit brought by enabling the memory prefetch mechanism of the slave control module within the corresponding time period is greater than zero, so the memory prefetch mechanism of the slave control module is enabled within the corresponding time period; when is greater than or equal to the sampling value, it is detected that the system performance with the memory prefetch mechanism of the slave control module disabled is better than or equal to the system performance with the memory prefetch mechanism of the slave control module enabled, indicating that and then the total benefit brought by enabling the memory prefetch mechanism of the slave control module within the corresponding time period is less than or equal to zero, so the memory prefetch mechanism of the slave control module is disabled within the corresponding time period.

[0107] As an example, during the process of approximating the value of by continuously adjusting the value of any value X in [0, 1], such as 0.5, can be used as the initial value, with a step size of d, such as 0.1, by continuously increasing or decreasing the value of to obtain different values of

[0108] as the sampling values. Among them, the step size d can be set according to the precision requirement of

[0109] It can be understood that the smaller the value of the step size d, the higher the precision of the obtained value, which correspondingly helps to improve the control accuracy of the memory pre-reading mechanism of the slave control module. In other embodiments, according to the requirement for the numerical precision of the preliminary value of

[0110] In an exemplary embodiment, the system performance of enabling and disabling the memory pre-reading mechanism of the slave control module is characterized by system throughput. In other embodiments, the system performance of enabling and disabling the memory pre-reading mechanism of the slave control module can also be characterized by other system performance parameters, which are not limited in this application.

[0111] The duration T of the time period can be set according to actual needs. Specifically, the time period T can be determined by those skilled in the art according to prior experience or testing.

[0112] It should be noted that the duration T of the time period should not be too short or too long. If the duration T of the time period is too short, it will cause the memory pre-reading mechanism of the slave control module to be frequently enabled and disabled, which is not conducive to the improvement of system performance; if the duration T of the time period is too long, the correlation between the values obtained by sampling in adjacent time periods decreases, which is not conducive to accurately controlling the memory pre-reading mechanism of the slave control module. Therefore, those skilled in the art can set the duration T of the time period in combination with the requirements for system performance improvement and the correlation requirements between the values obtained by sampling in adjacent time periods.

[0113] In an exemplary embodiment, according to the total revenue, by sending corresponding control signals to the slave control module to enable or disable the memory pre-reading mechanism of the slave control module within the corresponding time period.

[0114] For example, if the total benefit brought by enabling the memory pre-reading mechanism of the slave control module within the corresponding time period is greater than zero, a control signal with a first logic level (such as a high level) is sent to the slave control module, so that the slave control module enables its own memory pre-reading mechanism within the corresponding time period according to the control signal with the first logic level; if the total benefit brought by enabling the memory pre-reading mechanism of the slave control module within the corresponding time period is less than or equal to zero, a control signal with a second logic level (such as a low level) is sent to the slave control module, so that the slave control module closes its own memory pre-reading mechanism within the corresponding time period according to the control signal with the second logic level.

[0115] In an exemplary embodiment, the control signals with the first logic level and the second logic level are sent to the slave control module by writing the corresponding control signals into the preset register in the slave control module.

[0116] Correspondingly, an embodiment of the present invention further provides a data reading control module.

[0117] Figure 3 The frame structure diagram of an embodiment of the data reading control module provided by the embodiment of the present invention is shown. As Figure 3 shown, the data reading control module 30 may include: an obtaining unit 301, configured to obtain the total benefit brought by enabling the memory pre-reading mechanism of the slave control module according to a preset time period; a control unit 302, configured to enable or disable the memory pre-reading mechanism of the slave control module within the corresponding time period according to the total benefit, so that the slave control module reads the corresponding message data from the memory in advance or not in advance when receiving a read request sent by a preset master control module.

[0118] The data reading control module in the embodiment of the present invention can be used to execute the foregoing data reading control method, or can also be used to execute the data reading control method in the embodiment of the present invention by using other functional modules. For the data reading control method provided by the embodiment of the present invention, please refer to the detailed description in the foregoing part, and details are not described herein again.

[0119] Correspondingly, an embodiment of the present invention further provides an acceleration library, and the acceleration library includes a data reading control module, and the data reading control module is configured to execute the data reading control method provided by the embodiment of the present invention. Among them, for the data reading control method provided by the embodiment of the present invention, please refer to the description in the foregoing part, and details are not described herein again.

[0120] In an exemplary embodiment, the acceleration library is a Data Plane Development Kit (DPDK). In other embodiments, the acceleration library can also be other types of acceleration libraries such as a Storage Performance Development Kit (SPDK) or a peripheral driver with similar functions, which are not limited herein.

[0121] The embodiments of the present invention also provide a computer system, and the structure of the computer system can be combined with Figure 1 as shown. The computer system includes the acceleration library provided by the embodiments of the present invention. For the acceleration library provided by the embodiments of the present invention, please refer to the description in the foregoing part and will not be elaborated herein.

[0122] The embodiments of the present application also provide a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, they are used to implement the data reading control method provided by the embodiments of the present application. For the data reading control method provided by the embodiments of the present application, please refer to the content in the foregoing part and will not be elaborated herein.

[0123] The embodiments of the present invention also provide a computer device, which may include: at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the data reading control method provided by the embodiments of the present invention. For the data reading control method provided by the embodiments of the present invention, please refer to the description in the foregoing part and will not be elaborated herein.

[0124] The embodiments of the present invention provide a storage medium, which stores one or more computer-executable instructions, and the one or more computer-executable instructions are used to execute the data reading control method provided by the embodiments of the present invention. For the data reading control method provided by the embodiments of the present invention, please refer to the description in the foregoing part and will not be elaborated herein.

[0125] The above describes multiple embodiment solutions provided by the embodiments of the present invention. The optional ways introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend a variety of possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0126] Although the embodiments of the present invention are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A data reading control method, characterized in that, Including: Obtain the total benefit brought by enabling the memory pre - reading mechanism of the slave control module according to a preset time period; According to the total benefit, enable or disable the memory pre - reading mechanism of the slave control module within the corresponding time period, so that when the slave control module receives a reading request sent by a preset master control module, it reads the corresponding message data from the memory in advance or not in advance.

2. The data reading control method according to claim 1, wherein The step of "According to the total benefit, enable or disable the memory pre - reading mechanism of the slave control module within the corresponding time period" includes: If the total benefit is greater than zero, enable the memory pre - reading mechanism of the slave control module within the corresponding time period; If the total benefit is less than or equal to zero, disable the memory pre - reading mechanism of the slave control module within the corresponding time period.

3. The data reading control method according to claim 2, wherein The total benefit brought by enabling the memory pre - reading mechanism of the slave control module satisfies: M * A+(L - M) * C - M * B; Wherein, L represents the length of the message data received by the memory within the corresponding time period, M represents the length of the message data accessed by the processor within the corresponding time period, A represents the positive benefit value brought by enabling the memory pre - reading mechanism of the slave control module for each unit - length message data in the M - length message data when the processor accesses the M - length message data within the corresponding time period, B represents the negative benefit value brought by enabling the memory pre - reading mechanism of the slave control module for each unit - length message data in the M - length message data when the processor forwards the L - length message data within the corresponding time period, and C represents the positive benefit value brought by enabling the memory pre - reading mechanism of the slave control module for each unit - length message data in the (L - M) - length message data not accessed by the processor when the processor forwards the L - length message data within the corresponding time period; According to the total benefit, enable or disable the memory pre - reading mechanism of the slave control module within the corresponding time period, including: if M * A+(L - M) * C - M * B>0, enable the memory pre - reading mechanism of the slave control module within the corresponding time period; if M * A+(L - M) * C - M * B≤0, disable the memory pre - reading mechanism of the slave control module within the corresponding time period.

4. The data reading control method according to claim 3, wherein When the values of A, B, and C are determined: If M*A+(L-M)*C-M*B>0, then the memory prefetch mechanism of the slave module is enabled during the corresponding time period, including: if or or and it is detected that during the previous time period then the memory prefetch mechanism of the slave module is enabled during the corresponding time period; If M*A+(L-M)*C-M*B≤0, then the memory prefetch mechanism of the slave module is turned off during the corresponding time period, including: if and it is detected that during the previous time period then the memory prefetch mechanism of the slave module is turned off during the corresponding time period.

5. The data reading control method according to claim 3, wherein When the values of A, B, and C are not determined: If M*A+(L-M)*C-M*B>0, then the memory prefetch mechanism of the slave module is enabled during the corresponding time period, including: if it is detected through testing that or and then the memory prefetch mechanism of the slave module is enabled during the corresponding time period; If M*A+(L-M)*C-M*B ≤ 0, then the memory prefetch mechanism of the slave module is turned off during the corresponding time period, including: if it is detected through testing that and then the memory prefetch mechanism of the slave module is turned off during the corresponding time period.

6. The data reading control method according to claim 5, wherein If detected through testing or and then the memory pre - reading mechanism of the slave control module is enabled within the corresponding time period, including: if by performing tests on the system performance of enabling and disabling the memory pre - reading mechanism of the slave control module respectively in the cases of and and obtaining that the system performance of enabling the memory pre - reading mechanism of the slave control module in the cases of and is better than that of disabling the memory pre - reading mechanism of the slave control module, indicating or then the memory pre - reading mechanism of the slave control module is enabled within the corresponding time period; in other cases, if by performing a sampling test on the value of and obtaining that is less than a sampling value, and the system performance of enabling the memory pre - reading mechanism of the slave control module is better than that of disabling the memory pre - reading mechanism of the slave control module, indicating and then the memory pre - reading mechanism of the slave control module is enabled within the corresponding time period; If detected through testing and then during the corresponding time period, the memory pre-reading mechanism of the slave control module is turned off, including: in other cases, if by sampling and testing the value of when it is greater than or equal to the sampling value, the system performance of turning off the memory pre-reading mechanism of the slave control module is better than or equal to the system performance of turning on the memory pre-reading mechanism of the slave control module, indicating and then during the corresponding time period, the memory pre-reading mechanism of the slave control module is turned off.

7. The data reading control method according to claim 1, characterized in that The slave control module includes a cache - coherent slave interface, and the preset master control module includes a cache - coherent master interface and an input / output master interface.

8. A data reading control module, characterized in that Including: An obtaining unit, configured to obtain the total benefit brought by enabling the memory pre - reading mechanism of the slave control module according to a preset time period; A control unit, configured to enable or disable the memory pre - reading mechanism of the slave control module within the corresponding time period according to the total benefit, so that when the slave control module receives a reading request sent by a preset master control module, it reads the corresponding message data from the memory in advance or not in advance.

9. An acceleration library, characterized in that, The acceleration library includes a data reading control module, and the data reading control module is used to execute the data reading control method according to any one of claims 1 to 7.

10. A computer system, characterized in that, Including the acceleration library according to claim 9.

11. The computer system according to claim 10, wherein The acceleration library includes any one of DPDK and SPDK.

12. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, they are used to implement the data reading control method according to any one of claims 1 to 7.

13. A computer device, characterized in that, Comprising: At least one memory and at least one processor; The memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the data reading control method according to any one of claims 1 to 7.

14. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, and the one or more computer-executable instructions are used to execute the data reading control method according to any one of claims 1 to 7.

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