Data communication method and device and related equipment

Abstract

The invention relates to a data communication method, a data communication device and related equipment, which are used for avoiding data transmission errors when two pieces of equipment on an I2C bus path simultaneously have a clock stretching function at the same moment in server data communication. Comprising the following steps: a server sends target data to a CPLD (Complex Programmable Logic Device) through first I2C equipment when a level signal of an SCL of the first I2C equipment drops; the server sends the target data to the second I2C device through the CPLD when the level signal of the SCL of the first I2C device rises; the server receives the target data through the second I2C device when the level signal of the SCL of the first I2C device is increased again, when the SCL signal of the second I2C device is a high level signal, the SCL signal of the first I2C device is a low level signal, and when the SCL signal of the second I2C device is a low level signal, the SCL signal of the first I2C device is a high level signal.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a data communication method, apparatus, and related devices. Background Art

[0002] On the motherboard of a server, many I2C (Inter-Integrated Circuit) buses are required to obtain the operating data of the server and information related to the environment, and the operating status of the server needs to be monitored in real time. The BMC (Baseboard Management Controller) in the server is a dedicated controller for monitoring and managing the server. The number of I2C bus interfaces on it is limited, and I2C buses need to be used for expansion to mount numerous I2C devices, including I2C master devices and I2C slave devices.

[0003] Currently, during the data communication process of the I2C bus expansion module implemented using a CPLD (Complex Programmable Logic Device), only the clock stretching function of a single device (I2C master device or I2C slave device) on the I2C bus path is supported at the same time, and the situation where the I2C master device and the I2C slave device on the I2C bus path stretch the clock simultaneously to generate Stretch cannot be supported. If two devices on the I2C bus path use the clock stretching function at the same time, data transmission errors will occur. Therefore, a new data communication method for the I2C bus is urgently needed. Summary of the Invention

[0004] The present invention provides a data communication method, which, when implementing server data communication, realizes the situation of avoiding data transmission errors when two devices on the I2C bus path use the clock stretching function at the same time, and improves the accuracy of data communication.

[0005] In a first aspect, the present application provides a data communication method applied to a server. The server includes an integrated circuit bus I2C bus, a complex programmable logic device CPLD, and an I2C expansion bus. The I2C bus and the I2C expansion bus are respectively mounted with I2C devices. The method includes:

[0006] When the level signal of the serial clock line SCL of the first I2C device decreases, the server sends target data to the CPLD through the first I2C device;

[0007] When the level signal of the SCL of the first I2C device rises, the server sends the target data to the second I2C device through the CPLD; wherein, the first I2C device and the second I2C device are devices of different types;

[0008] When the level signal of the SCL of the first I2C device rises again, the server receives the target data through the second I2C device. When the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

[0009] In the above method, during the period when the SCL signal at the I2C bus end is high, the SCL signal at the I2C extended bus end is low. And during the period when the SCL signal at the I2C extended bus end is high, the SCL signal at the I2C bus end is low. That is, during the data communication process, only one of the SCL signals at the I2C bus end and the I2C extended bus end is high at the same moment. Therefore, the problem of data transmission errors caused by the first I2C device and the second I2C device simultaneously stretching the clock and causing Stretch on the bus during the data communication process is solved, and the accuracy of data communication is improved.

[0010] In a possible implementation manner, the method further includes:

[0011] After the first I2C device sends the target data of a specified size, the CPLD sets the SCL signal of the first I2C device to a low-level signal until the first I2C device receives the acknowledgment reception signal sent by the second I2C device and the level signal of the SCL of the second I2C device decreases, and then the SCL signal of the first I2C device is restored.

[0012] In the above method, after the first I2C device sends the target data of a specified size, the CPLD sets the SCL signal of the first I2C device to a low-level signal. This ensures that subsequent data can be communicated normally.

[0013] In a possible implementation manner, the method further includes:

[0014] When the second I2C device receives the target data of a specified size and the level signal of the SCL of the second I2C device decreases, the second I2C device sends an acknowledgment reception signal to the CPLD;

[0015] When the level signal of the second I2C device rises through the CPLD, latch the acknowledgment reception signal and send the acknowledgment reception signal onto the serial data line SDA of the first I2C device; wherein, before the first I2C device receives the acknowledgment reception signal after sending target data of a specified size, the SCL signal of the first I2C device is a low-level signal;

[0016] When the level signal of the SCL of the second I2C device drops through the CPLD, restore the SCL signal of the first I2C device;

[0017] When the level signal of the SCL of the first I2C device rises through the first I2C device, receive the acknowledgment reception signal from the SDA.

[0018] In the above method, the second I2C device receives target data of a specified size, and when the level signal of the SCL of the second I2C device drops, the second I2C device sends an acknowledgment reception signal to the CPLD. When the level signal of the SCL of the second I2C device rises through the CPLD, latch the acknowledgment reception signal and send the acknowledgment reception signal onto the SDA of the first I2C device. When the level signal of the SCL of the second I2C device drops through the CPLD, restore the SCL signal of the first I2C device; and when the level signal of the SCL of the first I2C device rises through the first I2C device, receive the acknowledgment reception signal from the SDA, ensuring that the next data communication can proceed normally and improving the efficiency of data communication.

[0019] In a possible implementation, the method further includes:

[0020] If the SCL signal of the second I2C device is a low-level signal throughout one cycle, set the SCL signal of the first I2C device to a low-level signal through the CPLD;

[0021] When the level signal of the SCL of the second I2C device drops, restore the SCL signal of the first I2C device through the CPLD.

[0022] In the above method, if the SCL signal of the second I2C device is a low-level signal throughout one cycle, set the SCL signal of the first I2C device to a low-level signal through the CPLD, and when the level signal of the SCL of the second I2C device drops, restore the SCL signal of the first I2C device through the CPLD. This ensures that data can be transmitted normally.

[0023] In a possible implementation, the method further includes:

[0024] If the SCL signals of the first I2C device are all low-level signals within one cycle, the SCL signal of the second I2C device is set to a low-level signal through the CPLD;

[0025] When the level signal of the SCL of the first I2C device decreases, the SCL signal of the second I2C device is restored through the CPLD.

[0026] For the above method, if the SCL signals of the first I2C device are all low-level signals within one cycle, the SCL signal of the second I2C device is set to a low-level signal through the CPLD; when the level signal of the SCL of the first I2C device decreases, the SCL signal of the second I2C device is restored through the CPLD. This ensures the normal transmission of data.

[0027] In a possible implementation manner, the first I2C device is mounted on the I2C bus or the I2C extended bus, the second I2C device is mounted on the I2C bus or the I2C extended bus, and the first I2C device and the second I2C device are mounted on different buses.

[0028] For the above method, the I2C extended bus can mount both the second I2C device and the first I2C device, improving the expandability of the I2C extended bus.

[0029] In a possible implementation manner, when the first I2C device is an I2C master device, the second I2C device is an I2C slave device; or when the first I2C device is an I2C slave device, the second I2C device is an I2C master device.

[0030] In the embodiment of the present application, when the first I2C device is an I2C master device, the second I2C device is an I2C slave device; and when the first I2C device is an I2C slave device, the second I2C device is an I2C master device. This improves the expandability.

[0031] In a second aspect, the present application provides a data communication device, which is applied to a server. The server includes an integrated circuit bus I2C bus, a complex programmable logic device CPLD, and an I2C extended bus. The I2C bus and the I2C extended bus are respectively mounted with I2C devices. The device includes:

[0032] A first sending module, configured to send target data to the CPLD when the level signal of the serial clock line SCL of the first I2C device of the server decreases;

[0033] A second sending module, configured to enable the server to send the target data to a second I2C device when the level signal of the SCL of the first I2C device rises through the CPLD; wherein, the first I2C device and the second I2C device are devices of different types;

[0034] A receiving module, configured to enable the server to receive the target data through the second I2C device when the level signal of the SCL of the first I2C device rises again; wherein, when the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

[0035] In a possible implementation manner, the apparatus further includes:

[0036] A setting module, configured to, after the first I2C device sends target data of a specified size, set the SCL signal of the first I2C device to a low-level signal through the CPLD until the first I2C device receives an acknowledgment reception signal sent by the second I2C device, and when the level signal of the SCL of the second I2C device drops, restore the SCL signal of the first I2C device.

[0037] In a possible implementation manner, the apparatus further includes:

[0038] A signal sending module, configured to, when the second I2C device receives target data of a specified size and the level signal of the SCL of the second I2C device drops, send an acknowledgment reception signal to the CPLD through the second I2C device;

[0039] A forwarding module, configured to latch the acknowledgment reception signal through the CPLD when the level signal of the SCL of the second I2C device rises, and send the acknowledgment reception signal to the serial data line SDA of the first I2C device; wherein, before the first I2C device sends target data of a specified size and has not received the acknowledgment reception signal, the SCL signal of the first I2C device is a low-level signal;

[0040] A restoration module restores the SCL signal of the first I2C device through the CPLD when the level signal of the SCL of the second I2C device drops;

[0041] Receive the acknowledgment reception signal from the SDA through the first I2C device when the level signal of the SCL of the first I2C device rises.

[0042] In a possible implementation, the setting module is further configured to:

[0043] If the SCL signal of the second I2C device is a low-level signal within one cycle, set the SCL signal of the first I2C device to a low-level signal through the CPLD;

[0044] The recovery module is configured to, when the level signal of the SCL of the second I2C device decreases, recover the SCL signal of the first I2C device through the CPLD.

[0045] In a possible implementation, the setting module is further configured to:

[0046] If the SCL signal of the first I2C device is a low-level signal within one cycle, set the SCL signal of the second I2C device to a low-level signal through the CPLD;

[0047] The recovery module is further configured to, when the level signal of the SCL of the first I2C device decreases, recover the SCL signal of the second I2C device through the CPLD.

[0048] In a possible implementation, the first I2C device is mounted on the I2C bus or the I2C extended bus, the second I2C device is mounted on the I2C bus or the I2C extended bus, and the first I2C device and the second I2C device are mounted on different buses.

[0049] In a possible implementation, when the first I2C device is an I2C host device, the second I2C device is an I2C slave device; or when the first I2C device is an I2C slave device, the second I2C device is an I2C host device.

[0050] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps in the above data communication method are implemented.

[0051] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps in the above data communication method of the present application are implemented.

[0052] Fifth aspect, an embodiment of the present application provides a computer program product, including a computer program stored in a computer-readable storage medium; when a processor of a memory access device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the memory access device executes the steps in the data communication method described above in the present application.

[0053] For the various aspects in the second to fifth aspects above and the possible technical effects that each aspect may achieve, please refer to the description of the possible technical effects that can be achieved by the various possible solutions in the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0055] Figure 1 It is a schematic structural diagram between the I2C bus and the I2C extended bus provided by the embodiment of the present application;

[0056] Figure 2 It is one of the flow diagrams of a data communication method provided by the embodiment of the present application;

[0057] Figure 3 It is one of the schematic diagrams of data communication provided by the embodiment of the present application;

[0058] Figure 4 It is the second schematic diagram of data communication provided by the embodiment of the present application;

[0059] Figure 5 It is the third schematic diagram of data communication provided by the embodiment of the present application;

[0060] Figure 6 It is the fourth schematic diagram of data communication provided by the embodiment of the present application;

[0061] Figure 7 It is the second flow diagram of the data communication method provided by the embodiment of the present application;

[0062] Figure 8 It is a schematic diagram of a data communication device provided by the embodiment of the present application;

[0063] Figure 9 It is a schematic diagram of an electronic device provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0064] To make the objectives, technical solutions and advantages of this application clearer, the following will further describe this application in detail with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the apparatus embodiments or system embodiments.

[0065] In the description of this application, "a plurality of" is understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The connection between A and B can represent: A is directly connected to B and A is connected to B through C. In addition, in the description of this application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0066] In the prior art, during the data communication process of the I2C bus expansion module implemented using a CPLD (Complex Programmable Logic Device), only the clock stretching function of a single device (I2C master device or I2C slave device) on the I2C bus path is supported at the same time, and it is impossible to support the situation where the I2C master device and the I2C slave device on the I2C bus path stretch the clock simultaneously to generate Stretch at the same time. If two devices on the I2C bus path use the clock stretching function at the same time, data transmission errors will occur. Therefore, there is an urgent need for a new data communication method for the I2C bus.

[0067] In response to this, the embodiments of this application provide a data communication method. During the period when the SCL signal at the I2C bus end is high, the SCL signal at the I2C expansion bus end is low. And during the period when the SCL signal at the I2C expansion bus end is high, the SCL signal at the I2C bus end is low. That is, during the data communication process, only one of the SCL signals at the I2C bus end and the I2C expansion bus end is high at the same time. Therefore, the problem of data transmission errors caused by the first I2C device and the second I2C device stretching the clock simultaneously to generate Stretch on the bus during the data communication process is solved, and the accuracy of data communication is improved.

[0068] Before introducing the data communication method in this application, the structure of the server in the embodiments of this application will be described first. As Figure 1 shown, it is a schematic structural diagram between the I2C bus and the I2C expansion bus. From Figure 1It can be seen that the BMC writes data through the I2C bus. Then, the data is sent to the I2C expansion bus through the CPLD. The BMC can also send data through the I2C bus to control the opening and closing of the channels of the I2C expansion bus. Among them, the channel control includes clock control and data control.

[0069] The following further describes the present application in detail with reference to the accompanying drawings. Refer to Figure 2 As shown, it is a schematic flowchart of a data communication method provided by an embodiment of the present application. The specific implementation process of this method is as follows:

[0070] Step 201: When the level signal of the serial clock line SCL of the first I2C device decreases, the server sends target data to the CPLD through the first I2C device;

[0071] It should be noted that: In the embodiment of the present application, step 201 can be executed every specified duration, and the specified duration in the embodiment of the present application can be set according to specific actual situations. The embodiment of the present application does not limit the specific value of the specified duration here.

[0072] In the embodiment of the present application, the size of the target data is 1 byte. However, the embodiment of the present application does not limit the size of the target data, and the specific size of the target data can be set according to specific actual situations.

[0073] In the embodiment of the present application, the decrease in the level signal of SCL generates a falling edge of SCL.

[0074] Step 202: When the level signal of SCL of the first I2C device rises, the server sends the target data to the second I2C device through the CPLD; where the first I2C device and the second I2C device are different types of devices;

[0075] In the embodiment of the present application, the rise in the level signal of SCL generates a rising edge of SCL.

[0076] In a possible implementation manner, when the first I2C device is an I2C master device, the second I2C device is an I2C slave device; or when the first I2C device is an I2C slave device, the second I2C device is an I2C master device.

[0077] Step 203: When the level of the SCL of the first I2C device rises again, the server receives the target data through the second I2C device. When the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

[0078] In a possible implementation manner, after the first I2C device sends target data of a specified size, the CPLD sets the SCL signal of the first I2C device to a low-level signal until the first I2C device receives the acknowledgment reception signal sent by the second I2C device, and when the level signal of the SCL of the second I2C device decreases, the SCL signal of the first I2C device is restored.

[0079] It should be noted that: in the embodiments of the present application, the specified size is 1 byte, but the embodiments of the present application do not limit the specific value of the specified size here. The specific value of the specified size in the embodiments of the present application can be set according to specific actual situations.

[0080] Next, a method for the second I2C device to send an acknowledgment reception signal in the embodiments of the present application will be introduced.

[0081] In a possible implementation manner, when the second I2C device receives target data of a specified size and the level signal of the SCL of the second I2C device decreases, the second I2C device sends an acknowledgment reception signal to the CPLD; when the level signal of the SCL of the second I2C device rises, the CPLD latches the acknowledgment reception signal and sends the acknowledgment reception signal to the serial data line SDA of the first I2C device; where, before the first I2C device receives the acknowledgment reception signal after sending target data of a specified size, the SCL signal of the first I2C device is a low-level signal; when the level signal of the SCL of the second I2C device decreases, the CPLD restores the SCL signal of the first I2C device.

[0082] In a possible implementation manner, the first I2C device is mounted on the I2C bus or the I2C extended bus, the second I2C device is mounted on the I2C bus or the I2C extended bus, and the first I2C device and the second I2C device are mounted on different buses.

[0083] Next, the data communication method in the embodiments of the present application will be described in combination with different situations. The data communication method in the embodiments of the present application includes writing data and reading data. The following Figure 3and Figure 4 In it, the elevation of the level signal of SCL is uniformly called the rising edge, and the decline of the level signal of SCL is uniformly called the falling edge.

[0084] As Figure 3 shown, it is a schematic diagram of data communication where the first I2C device is mounted on the I2C bus and the second I2C device is mounted on the I2C extended bus. Figure 3 In it, the first I2C device is taken as the host device and the second I2C device is taken as the slave device for illustration. (Writing data)

[0085] Figure 3 In 302, after the first I2C device sends the target data of a specified size, it is ready to receive the acknowledgment signal (ACK / NACK signal). The low horizontal line after the falling edge (the level signal decreases) in 302 represents that the first I2C device is in the low level signal.

[0086] After the second I2C device sends the target data of a specified size, it is ready to send the acknowledgment signal. Figure 3 In the falling edge of the first clock cycle in 301, the second I2C device sends the acknowledgment signal. In the rising edge (the level signal increases) of the second clock cycle in 301, the CPLD latches the acknowledgment signal sent by the second I2C device and sends the latched acknowledgment signal to the SDA signal line of the first I2C device. After the falling edge of the second clock cycle in 301 appears, the SCL signal line of the first I2C device is released. In Figure 3 In 302, the first I2C device receives the acknowledgment signal sent by the second I2C device at the SCL rising edge, and completes the data transfer of the acknowledgment signal for writing data.

[0087] Figure 4 It is a schematic diagram of data communication where the first I2C device is mounted on the I2C extended bus and the second I2C device is mounted on the I2C bus. Figure 4 In it, the first I2C device is taken as the slave device and the second I2C device is taken as the host device for illustration. (Reading data)

[0088] After the first I2C device sends a byte of data, it is ready to receive the acknowledgment signal. During the two consecutive clock cycles in Figure 4 401, the second I2C device that is ready to receive the acknowledgment signal is always at the low level, as Figure 4 shown in 402.

[0089] Figure 4At the falling edge of the first clock cycle in 401, the second I2C device sends an acknowledgment reception signal. At the rising edge of the second clock cycle in 401, the CPLD latches the acknowledgment reception signal sent by the second I2C device and sends the latched acknowledgment reception signal to the SDA signal line of the first I2C device. Figure 4 After the falling edge of the second clock cycle in 401 appears, the SCL signal line of the first I2C device is released. In Figure 4 In 402, the first I2C device receives the acknowledgment reception signal sent by the second I2C device at the rising edge of SCL, and completes the data transfer of the acknowledgment reception signal for reading data.

[0090] To ensure normal data transmission, in a possible implementation, if the SCL signal of the second I2C device is a low-level signal within one cycle, the CPLD sets the SCL signal of the first I2C device to a low-level signal; when the level signal of the SCL of the second I2C device decreases, the CPLD restores the SCL signal of the first I2C device.

[0091] For example, as Figure 3 In Stretch-1, during the process of the second I2C device receiving data, it needs to pause data reception but does not want to give up the subsequent data reception. Therefore, it will temporarily lower the level of the SCL signal at the second I2C device end to notify the CPLD to pause the data transmission of the first I2C device, that is, the CPLD sets the SCL signal of the first I2C device to a low-level signal, that is Figure 3 Stretch-2 in

[0092] To ensure normal data transmission, in a possible implementation, if the SCL signal of the first I2C device is a low-level signal within one cycle, the CPLD sets the SCL signal of the second I2C device to a low-level signal; when the level signal of the SCL of the first I2C device decreases, the CPLD restores the SCL signal of the second I2C device.

[0093] For example, Figure 3 In Stretch-3, during the process of the first I2C device sending data, the data to be sent is not ready, but it does not want to give up this data transmission. Therefore, it will temporarily lower the SCL signal of the first I2C device to notify the CPLD to pause the data reception of the second I2C device. Figure 3 In Stretch-4, during the process of the second I2C device receiving data, when the CPLD detects that the SCL signal of the first I2C device is always low, it will continue to lower the SCL signal of the second I2C device and wait for the data transmission of the first I2C device to complete.

[0094] As shown Figure 5 in Figure 5 Figure 1, it is a write data timing diagram of the I2C extended bus mounting the first I2C device (host device) and the I2C bus mounting the second I2C device (slave device). In the following Figure 5 and Figure 6 Figures, the rising of the SCL level signal is uniformly referred to as the rising edge, and the falling of the SCL level signal is uniformly referred to as the falling edge.

[0095] As can be seen Figure 5 from Figure 1, during the period when the SCL signal at the I2C extended bus end is high, the SCL signal at the I2C bus end is low. Similarly, during the period when the SCL signal at the I2C bus end is high, the SCL signal at the I2C extended bus end is low. That is, during the data communication process, at the same moment, only one of the SCL signals at the I2C bus end and the I2C extended bus end is high. This processing method solves the situation where the host device and the slave device on the I2C bus stretch the clock simultaneously and cause data transmission errors due to Stretch.

[0096] Figure 5 In Figure 2, 501 is that after the second I2C device (slave device) at the I2C bus end receives a byte of data, it sends an acknowledgment reception signal. The second rising edge of the SCL signal at the I2C bus end appears, and the CPLD latches the acknowledgment reception signal and sends the latched acknowledgment reception signal to the SDA signal line of the first I2C device (host device) at the I2C extended bus end. Figure 5 In Figure 3, 502 is that after the first I2C device (host device) at the I2C extended bus end sends a byte of data, the rising edge of the SCL signal at the I2C extended bus end appears, and it receives the ACK / NACK signal sent by the second I2C device (slave device) at the I2 bus end.

[0097] Figure 5 501 and 502 in Figures 2 and 3 realize the transfer of the acknowledgment reception signal in the write data communication process of the I2C extended bus mounting the host device and the I2C bus mounting the slave device.

[0098] Figure 5 Stretch-1 in Figure 4 is generated when the first I2C device (host device) at the I2C extended bus end pulls down the clock during the process of receiving the acknowledgment reception signal. It notifies the CPLD to pause the reception of the acknowledgment reception signal of the second I2C device (slave device) at the I2C bus end. Figure 5During the data reception process of the second I2C device (slave device) at the I2C bus terminal, if the CPLD detects that the SCL signal of the first I2C device (master device) at the I2C extended bus terminal remains low, it will continue to pull down the SCL signal at the bus terminal and wait for the first I2C device (master device) at the I2C extended bus terminal to receive the acknowledgment reception signal.

[0099] Figure 6 It is the read data timing diagram when the first I2C device (master device) is mounted at the I2C extended bus terminal and the second I2C device (slave device) is mounted at the I2C bus terminal.

[0100] Figure 6 In [reference], 601 is that after the second I2C device (slave device) at the I2C bus terminal receives a byte address data, after sending an acknowledgment reception signal at the first falling edge of the SCL signal, it pulls down the clock to generate Stretch, that is Figure 6 Stretch-1 in [reference]. It notifies the CPLD to continue pulling down the SCL signal of the first I2C device (master device) at the I2C extended bus terminal and pauses the reception of the acknowledgment reception signal of the first I2C device (master device) at the I2C extended bus terminal.

[0101] Figure 6 In [reference], 602 is that after the first I2C device (master device) at the I2C extended bus terminal sends the target data of the specified size, if the CPLD detects that the SCL signal of the second I2C device (slave device) at the I2C bus terminal remains low, it will continue to pull down the SCL signal at the I2C extended bus terminal to generate Stretch, that is Figure 6 Stretch-2 in [reference]. Wait for the rising edge of the SCL signal at the I2C bus terminal. The CPLD latches the acknowledgment reception signal sent by the second I2C device (slave device) at the I2C bus terminal and sends the latched acknowledgment reception signal to the SDA signal line of the first I2C device (master device) at the I2C extended bus terminal.

[0102] Figure 6 In [reference], 601 and 602 realize the transfer of the acknowledgment reception signal in the read data communication process where the master device is mounted at the I2C extended bus terminal and the slave device is mounted at the I2C bus terminal.

[0103] Next, in combination with Figure 7 The data communication method in the embodiments of the present application will be described, which may specifically include the following steps:

[0104] Step 701: When the level signal of the serial clock line SCL of the first I2C device decreases, the server sends target data to the CPLD through the first I2C device;

[0105] Step 702: After the first I2C device sends target data of a specified size, the CPLD sets the SCL signal of the first I2C device to a low-level signal;

[0106] Step 703: When the level signal of the SCL of the first I2C device rises, the server sends the target data to the second I2C device through the CPLD;

[0107] Step 704: The server receives the target data through the second I2C device when the level signal of the SCL of the first I2C device rises again. When the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal;

[0108] Step 705: When the second I2C device receives target data of a specified size and the level signal of the SCL of the second I2C device drops, the second I2C device sends an acknowledgment reception signal to the CPLD;

[0109] Step 706: When the level signal of the SCL of the second I2C device rises, the CPLD latches the acknowledgment reception signal and sends the acknowledgment reception signal to the SDA signal line of the first I2C device; Before the first I2C device sends target data of a specified size and has not received the acknowledgment reception signal, the SCL signal of the first I2C device is a low-level signal;

[0110] Step 707: When the level signal of the SCL of the second I2C device drops, the CPLD restores the SCL signal of the first I2C device.

[0111] Based on the same inventive concept, the present application also provides a data communication device, which is applied to a server. The server includes an integrated circuit bus I2C bus, a complex programmable logic device CPLD, and an I2C expansion bus. The I2C bus and the I2C expansion bus are respectively mounted with I2C devices. See Figure 8 The device 800 includes:

[0112] A first sending module 801, configured to send target data to the CPLD by the server through a first I2C device when the level signal of the serial clock line SCL of the first I2C device drops;

[0113] A second sending module 802, configured to enable the server to send the target data to a second I2C device when a level signal of the SCL of the first I2C device rises through the CPLD; wherein, the first I2C device and the second I2C device are devices of different types;

[0114] A receiving module 803, configured to enable the server to receive the target data through the second I2C device when the level signal of the SCL of the first I2C device rises again; wherein, when the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

[0115] In a possible implementation manner, the apparatus further includes:

[0116] A setting module 804, configured to, after the first I2C device sends target data of a specified size, set the SCL signal of the first I2C device to a low-level signal through the CPLD until the first I2C device receives an acknowledgment reception signal sent by the second I2C device, and when the level signal of the SCL of the second I2C device drops, restore the SCL signal of the first I2C device.

[0117] In a possible implementation manner, the apparatus further includes:

[0118] A signal sending module 805, configured to, when the second I2C device receives target data of a specified size and the level signal of the SCL of the second I2C device drops, send an acknowledgment reception signal to the CPLD through the second I2C device;

[0119] A forwarding module 806, configured to latch the acknowledgment reception signal through the CPLD when the level signal of the SCL of the second I2C device rises, and send the acknowledgment reception signal to the serial data line SDA of the first I2C device; wherein, before the first I2C device receives the acknowledgment reception signal after sending target data of a specified size, the SCL signal of the first I2C device is a low-level signal;

[0120] A restoration module 807, configured to restore the SCL signal of the first I2C device through the CPLD when the level signal of the SCL of the second I2C device drops;

[0121] An acknowledgment signal receiving module 808, configured to receive the acknowledgment reception signal from the SDA through the first I2C device when the level signal of the SCL of the first I2C device rises.

[0122] In a possible implementation, the setting module 804 is further configured to:

[0123] If the SCL signals of the second I2C device are all low-level signals within one cycle, set the SCL signal of the first I2C device to a low-level signal through the CPLD;

[0124] The recovery module 807 is configured to, when the level signal of the SCL of the second I2C device decreases, recover the SCL signal of the first I2C device through the CPLD.

[0125] In a possible implementation, the setting module 804 is further configured to:

[0126] If the SCL signals of the first I2C device are all low-level signals within one cycle, set the SCL signal of the second I2C device to a low-level signal through the CPLD;

[0127] The recovery module 807 is further configured to, when the level signal of the first I2C device decreases, recover the SCL signal of the second I2C device through the CPLD.

[0128] In a possible implementation, the first I2C device is mounted on the I2C bus or the I2C extended bus, the second I2C device is mounted on the I2C bus or the I2C extended bus, and the first I2C device and the second I2C device are mounted on different buses.

[0129] In a possible implementation, when the first I2C device is an I2C master device, the second I2C device is an I2C slave device; or when the first I2C device is an I2C slave device, the second I2C device is an I2C master device.

[0130] Based on the same inventive concept, an electronic device is further provided in an embodiment of the present application. The electronic device can implement the functions of the foregoing data communication device. Refer to Figure 9 , the electronic device includes:

[0131] At least one processor 901 and a memory 902 connected to at least one processor 901. In the embodiment of the present application, the specific connection medium between the processor 901 and the memory 902 is not limited. Figure 9 Here, it is taken as an example that the processor 901 and the memory 902 are connected through a bus 900. The bus 900 is in Figure 9The connection in the figure is represented by a thick line. The connection methods between other components are only for illustrative purposes and are not limited thereto. The bus 900 can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 9 only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. Alternatively, the processor 901 can also be referred to as a controller, and there is no limitation on the name.

[0132] In the embodiment of the present application, the memory 902 stores instructions that can be executed by at least one processor 901. By executing the instructions stored in the memory 902, at least one processor 901 can execute the data communication method described above. The processor 901 can implement Figure 8 the functions of each module in the device shown.

[0133] Among them, the processor 901 is the control center of the device. It can use various interfaces and lines to connect all parts of the entire control device. By running or executing the instructions stored in the memory 902 and calling the data stored in the memory 902, various functions of the device and process data, so as to monitor the device as a whole.

[0134] In a possible design, the processor 901 may include one or more processing units. The processor 901 may integrate an application processor and a modem processor. Among them, the application processor mainly processes the operating system, user interface, application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above modem processor may not be integrated into the processor 901. In some embodiments, the processor 901 and the memory 902 can be implemented on the same chip. In some embodiments, they can also be implemented separately on independent chips.

[0135] The processor 901 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the data communication method disclosed in combination with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0136] The memory 902 serves as a non-volatile computer-readable storage medium and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The memory 902 may include at least one type of storage medium. For example, it may include flash memory, hard disks, multimedia cards, card-type memories, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memories, magnetic disks, optical disks, and so on. The memory 902 is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 902 in the embodiments of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and / or data.

[0137] By designing and programming the processor 901, the code corresponding to the data communication method described in the foregoing embodiments can be solidified into the chip, so that the chip can execute Figure 2 the steps of the data communication method of the embodiments shown. How to design and program the processor 901 is a well-known technology to those skilled in the art and will not be elaborated here.

[0138] The embodiments of the present application also provide a computer-readable storage medium storing computer-executable instructions required to be executed by the foregoing processor, which includes a program for executing the operations required to be executed by the foregoing processor.

[0139] In some possible implementation manners, various aspects of the data communication method provided in the present application may also be implemented in the form of a program product, which includes program code. When the program product runs on an electronic device, the program code causes the electronic device to execute the steps in the data communication method according to various exemplary embodiments described in this specification.

[0140] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, apparatus, or computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0141] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0142] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0143] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0144] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0145] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

Claims

1. A data communication method, characterized in that, Applied to a server, the server includes an integrated circuit bus I2C bus, a complex programmable logic device CPLD, and an I2C extended bus. The I2C bus and the I2C extended bus are respectively mounted with I2C devices. The method includes: When the level signal of the serial clock line SCL of the first I2C device decreases, the server sends target data to the CPLD through the first I2C device; When the level signal of the SCL of the first I2C device increases, the server sends the target data to the second I2C device through the CPLD; wherein, the first I2C device and the second I2C device are different types of devices; When the level signal of the SCL of the first I2C device increases again, the server receives the target data through the second I2C device. When the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

2. The method according to claim 1, wherein The method further includes: After the first I2C device sends target data of a specified size, the CPLD sets the SCL signal of the first I2C device to a low-level signal until the first I2C device receives the acknowledgment reception signal sent by the second I2C device, and when the level signal of the SCL of the second I2C device decreases, the SCL signal of the first I2C device is restored.

3. The method according to claim 1 or 2, characterized in that, The method further includes: When the second I2C device receives target data of a specified size and the level signal of the SCL of the second I2C device decreases, the second I2C device sends an acknowledgment reception signal to the CPLD; When the level signal of the SCL of the second I2C device increases, the CPLD latches the acknowledgment reception signal and sends the acknowledgment reception signal to the serial data line SDA of the first I2C device; wherein, before the first I2C device sends target data of a specified size and has not received the acknowledgment reception signal, the SCL signal of the first I2C device is a low-level signal; When the level signal of the SCL of the second I2C device decreases, the CPLD restores the SCL signal of the first I2C device; When the level signal of the SCL of the first I2C device increases, the first I2C device receives the acknowledgment reception signal from the SDA.

4. The method according to claim 1, wherein The method further includes: If the SCL signal of the second I2C device is a low-level signal throughout a cycle, the CPLD sets the SCL signal of the first I2C device to a low-level signal; When the level signal of the SCL of the second I2C device decreases, the CPLD restores the SCL signal of the first I2C device.

5. The method according to claim 1, wherein The method further includes: If the SCL signals of the first I2C device are all low-level signals within one cycle, the SCL signal of the second I2C device is set to a low-level signal through the CPLD; When the level signal of the SCL of the first I2C device decreases, the SCL signal of the second I2C device is restored through the CPLD.

6. According to the method described in any one of claims 1, 2, 4 to 5, characterized in that, The first I2C device is mounted on the I2C bus or the I2C extended bus, the second I2C device is mounted on the I2C bus or the I2C extended bus, and the first I2C device and the second I2C device are mounted on different buses.

7. The method according to claim 1, characterized in that When the first I2C device is an I2C master device, the second I2C device is an I2C slave device; or when the first I2C device is an I2C slave device, the second I2C device is an I2C master device.

8. A data communication device, characterized in that, Applied to a server, the server includes an integrated circuit bus I2C bus, a complex programmable logic device CPLD, and an I2C extended bus. The I2C bus and the I2C extended bus are respectively mounted with I2C devices. The device includes: A first sending module, configured to send target data to the CPLD when the level signal of the serial clock line SCL of the first I2C device decreases through the first I2C device of the server; A second sending module, configured to send the target data to the second I2C device through the CPLD when the level signal of the SCL of the first I2C device increases; wherein, the first I2C device and the second I2C device are devices of different types; A receiving module, configured to receive the target data when the level signal of the SCL of the first I2C device increases again through the second I2C device of the server; wherein, when the SCL signal of the second I2C device is a high-level signal, the SCL signal of the first I2C device is a low-level signal, and when the SCL signal of the second I2C device is a low-level signal, the SCL signal of the first I2C device is a high-level signal.

9. An electronic device, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the method according to any one of claims 1-7 when executing the computer program stored on the memory.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the method according to any one of claims 1-7 is implemented.

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