A comprehensive information system for domestic optical measurement equipment

Abstract

The present invention relates to a domestically produced optical measurement equipment information integration system, belonging to the field of data processing technology. It addresses existing issues such as unstable connectors, limited chip resources, and non-domestic equipment in current information integration systems. The system comprises a core control module, peripheral function modules, and a hardware interface module. The core control module is composed of a GD32F450 microcontroller and a PG2L100H FPGA. These modules utilize high-speed SPI data transmission to process real-time data exchange between various optical measurement equipment systems, implementing data communication, fiber optic communication, data monitoring, and time synchronization terminal functions. By integrating the functions of various units into the GD32F450 microcontroller and PG2L100H FPGA, the present invention reduces the workload of debuggers. By utilizing the domestically produced GD32F450 microcontroller and PG2L100H FPGA, the system meets the requirement for domestically produced chips in the equipment and achieves enhanced system stability.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a domestic optical measurement equipment information integration system. Background Art

[0002] During operation, the various systems of optical measurement equipment exchange data in real time to achieve fully or semi-automatic tracking. The information integration system processes the data exchanged between these systems in real time, including receiving operational control commands and performing photoelectric data conversion and restoration.

[0003] The current information integration system used for real-time data exchange with photoelectric theodolites relies on an outdated ARM9 series chip for data communication, with limited memory and an official announcement of discontinuation. The MSP430 chip used in the time-based terminal system also suffers from limited storage capacity and development resources. Furthermore, the chips used in each subsystem are not domestically produced, which contradicts current military equipment requirements. Therefore, replacing each chip in the information integration system is imperative. Furthermore, the current information integration board utilizes two boards, a top and bottom board, connected by QTE connectors. This connector method has been found to be unstable during project commissioning and use, necessitating a replacement for the connection method. Summary of the Invention

[0004] In response to the problems of unstable connectors, limited chip resources, and non-domestic equipment in current information integration systems, the present invention provides a domestic optical measurement equipment information integration system, which is a multi-channel high-speed information integration system based on domestic FPGA+ARM. The system has high integration, uses multiple optical fibers and multiple serial ports for data interaction, and can process real-time data exchanged between optical measurement equipment systems.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A domestic optical measurement equipment information integration system, the system comprising:

[0007] Core control module: Consists of a GD32F450 microcontroller and a PG2L100H FPGA. Their corresponding pins (SCK, MISO, MOSI, and NSS) are connected, enabling high-speed data transmission via SPI to process real-time data exchange between various systems in the optical measurement equipment. The GD32F450 microcontroller serves as the SPI master, and the PG2L100H FPGA serves as the SPI slave. The core control module has data communication, fiber optic communication, data monitoring, and timing terminal functions. It can process high-speed image data, real-time encoder data, dimming and focusing data, and trigger signals from the optical measurement equipment, including photoelectric conversion, electro-optical conversion, and data segmentation and reassembly. It also uses multiple optical fibers and serial communication connections.

[0008] Peripheral function modules: including:

[0009] Power supply voltage regulator module: composed of GM1203 linear voltage regulator and BL8034 converter, it provides stable voltage output and integrates overvoltage protection, overcurrent protection and short-circuit protection functions;

[0010] Clock management module: uses the BT0507 temperature-compensated crystal oscillator to provide accurate external clock signals for the PG2L100H FPGA;

[0011] AC acquisition module: Based on the MS5182N chip, it realizes digital conversion of input analog signals for processing by the core control module;

[0012] Signal conversion module: Based on the SIT3490 chip, it converts the 422 standard communication signal and the TTL level signal, and based on the SIT3232 chip, it converts the 232 standard communication signal and the TTL level signal;

[0013] Network communication module: The SR8201F chip and the YT8521SH-CA chip jointly provide network connection and data transmission capabilities to achieve efficient data exchange, and realize unicast and multicast functions based on UDP;

[0014] Timing module: integrated AC codec, automatic amplifier gain adjustment, DC codec, GPS / BD decoding and PTP timing functions;

[0015] Hardware interface module: including:

[0016] Signal strobe plug: controls the on and off of the signal path through circuit and software design;

[0017] Analog quantity acquisition interface: converts the input external continuously changing physical quantity into a digital signal;

[0018] Switching quantity acquisition interface: collects digital signals with only two states, used to monitor the operating status of optical measurement equipment and the switching status of various systems;

[0019] Dip switch interface: Set different binary codes by toggling the switch position to quickly configure the system signal gating function;

[0020] SFP optical module interface: realizes the transmission and reception function of optical signals and supports high-speed data transmission;

[0021] Data communication indicator: displays the status of data communication through different colors, flashing frequencies, or a combination of colors and flashing frequencies.

[0022] The beneficial effects of the present invention are as follows: compared with the existing technical solutions, the domestic optical measurement equipment information integration system proposed by the present invention replaces the chips used on the board, improves the storage capacity, and solves the problem of limited chip resources. The functions that require five chips on the original board are realized by integrating the functions of each unit into two chips, namely, the GD32F450 microcontroller and the PG2L100H FPGA, thereby reducing the workload of the debugging personnel. By utilizing the domestically produced GD32F450 microcontroller and PG2L100H FPGA, the requirements for domestically produced chips in the equipment are met. The original QTE connector, which would have unstable connection when not operated and used in accordance with regulations, has also been replaced by a data interaction method of multiple optical fibers and multiple serial ports, thereby enhancing the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a functional block diagram of a domestic optical measurement equipment information integration system according to an embodiment of the present invention;

[0024] Figure 2 This is a hardware design block diagram of a domestic optical measurement equipment information integration system described in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0026] The present invention provides a domestic optical measurement equipment information integration system, which mainly includes a core control module, peripheral function modules and hardware interface modules. The hardware design principle of the system is as follows:

[0027] The system can be divided into a data communication unit, a time terminal unit, a fiber optic communication unit and a data monitoring unit. The devices in each unit meet the requirements for the localization of military equipment. Figure 1The following is a block diagram of the system. The data communication unit is implemented using GigaDevice's GD32F450 microcontroller, based on the ARM Cortex-M4 core. This microcontroller features low power consumption, high integration, high reliability, and ease of use. It integrates extensive on-chip resources and peripheral interfaces, including eight USARTs, six SPIs, three fast I2Cs, two I2Ss, two CAN 2.0Bs, one SDIO interface, and a 10 / 100M Ethernet controller. The time synchronization terminal unit, fiber optic communication unit, and data monitoring unit are implemented using Unigroup Tongchuang's PG2L100H FPGA. The PG2L100H FPGA provides 100K LUT4 logic resources, supports eight channels of 6.6Gbps high-speed SerDes interfaces, and boasts abundant I / O and on-chip clock resources.

[0028] 1. Core control module.

[0029] In the domestic optical measurement equipment information integration system, the GD32F450 microcontroller and PG2L100H FPGA are the core control chips. High-speed data transmission is achieved between the two chips via SPI, connecting the corresponding pins SCK, MISO, MOSI, and NSS. The GD32F450 microcontroller acts as the SPI master, and the PG2L100H FPGA acts as the SPI slave.

[0030] SPI (Serial Peripheral Interface) is a synchronous serial communication interface featuring high-speed, full-duplex communication. In this system, the GD32F450 microcontroller configures its SPI registers to enable the SPI clock, set the appropriate baud rate, and data length to ensure accurate and efficient data transmission. When the GD32F450 microcontroller sends data to the PG2L100H FPGA, the master loads the data into a shift register and then, under the control of the clock signal SCK, transmits the data bit by bit to the slave via the MOSI pin. After receiving the clock signal, the PG2L100H FPGA synchronously reads the data and stores it in its internal receive buffer. Conversely, when the PG2L100H FPGA sends data to the GD32F450 microcontroller, the data is transmitted back to the master via the MISO pin, and the GD32F450 microcontroller also receives the data in synchronization with the clock signal.

[0031] The NSS pin is used as a chip select signal. When the GD32F450 microcontroller wishes to communicate with the PG2L100H FPGA, it pulls the NSS pin low, selecting the slave device, the PG2L100H FPGA, and initiating data transmission. During transmission, SPI enables continuous data transmission, improving data throughput. Furthermore, by appropriately configuring the baud rate, it can adapt to different application scenarios and data transmission requirements. For example, in applications with high real-time requirements, a higher baud rate can be selected to speed up data transmission; in noise-sensitive environments, a lower baud rate can be appropriately used to improve data stability. Furthermore, to ensure the reliability of SPI transmission, error detection and correction mechanisms have been implemented in the software. Transmitted data is verified using methods such as checksums and cyclic redundancy checks (CRCs), and any errors are promptly reported.

[0032] The PG2L100H FPGA, acting as an SPI slave, quickly responds and transmits data after receiving instructions from the master. It can provide required data or perform specific operations based on the master's instructions. This master-slave SPI communication architecture enables efficient data exchange and meets the system's data transmission requirements.

[0033] The GD32F450 microcontroller is a high-performance microcontroller. With a maximum clock speed of 200MHz, it can quickly handle a variety of complex tasks and algorithms. It integrates a wealth of peripheral resources, such as multiple SPI, I2C, and UART communication interfaces, facilitating data transmission and communication with other devices. It also features a large number of GPIO pins to connect to a variety of external devices. Its Flash memory capacity ranges from 256KB to 3072KB, suitable for program and data storage. Its SRAM capacity ranges from 256KB to 512KB, providing ample memory for program execution. The PG2L100H FPGA is a field-programmable gate array (FPGA). As a mid-to-high-end FPGA in Unigroup Tongchuang's Logos2 series, it offers high flexibility and programmability, along with high performance and stability. The PG2L100H FPGA uses the GD25Q flash chip, which features flexible programming and erasing capabilities. The memory is divided into multiple sectors and blocks, which can be independently erased and programmed, improving efficiency and facilitating data updates and modifications. It is suitable for applications that require frequent updates of certain data. The chip has fast programming and erasing speeds, which can reduce data writing time and quickly clear old data to write new data. In devices with frequent firmware updates, this can ensure timely firmware updates.

[0034] The GD32F450 microcontroller and PG2L100H FPGA jointly implement the system's core control module, providing data communication, fiber optic communication, data monitoring, and time synchronization terminal functions. Data and fiber optic communication primarily process high-speed image data from the optical measurement system, real-time encoder data, dimming and focusing data, and trigger signals. This includes photoelectric and electro-optical conversion, as well as data segmentation and reassembly. The PG2L100H FPGA uses GTX high-speed SerDes to perform photoelectric and electro-optical data conversion. Synchronous code control and data flow control during the conversion process are both implemented using proprietary protocols.

[0035] 2. Peripheral functional modules.

[0036] Power supply voltage regulator module: The power supply voltage regulator module primarily consists of the GM1203 and BL8034 chips. The GM1203, as a linear voltage regulator, offers high precision and stability. Its compact size facilitates miniaturization, enabling stable power supply to other components on the board. The BL8034, on the other hand, converts higher input voltages into lower output voltages with high efficiency, reducing energy loss and improving power efficiency. The power supply voltage regulator module effectively suppresses and regulates voltage fluctuations input from the power supply module, delivering a stable output voltage that meets the voltage accuracy and stability requirements of various components within the system. It also provides overvoltage, overcurrent, and short-circuit protection to prevent damage to the system caused by abnormal voltage and current conditions, ensuring stable operation and efficient performance.

[0037] Clock Management Module: The clock management module uses a temperature-compensated crystal oscillator, such as the BT0507, which measures 7.00 x 5.00 mm and has a height of 1.90 mm. The BT0507 offers high frequency stability, maintaining stable performance even in harsh environments. It provides a precise external clock signal for the PG2L100H FPGA, which in turn synchronizes the system's processors, memory, and other synchronous logic circuits. By dividing, multiplying, and adjusting the clock signal's phase, it can meet the clock requirements of different components. Managing multiple clock sources, enabling clock switching and selection, improves system reliability and flexibility.

[0038] Serial port transceiver module: provides the system with a physical connection channel that complies with serial communication electrical standards (such as RS-422 / RS-485 / TTL) to realize serial data transmission with external devices.

[0039] AC Acquisition Module: The AC acquisition module utilizes the MS5182N chip, which accurately acquires AC signals with 16-bit resolution and no missing codes. It precisely digitizes input analog signals for processing by the core control module. The MS5182N chip boasts high sampling accuracy and speed, enabling rapid and accurate acquisition of AC signal characteristic parameters such as voltage amplitude, frequency, and phase. When receiving AC codes from B codes, this chip samples and records the incoming AC codes for subsequent time code decoding.

[0040] Switching quantity acquisition module: The switching quantity acquisition module is responsible for collecting digital signals with only two states (such as on / off, high / low), and passing the collected digital signals to the core control module for the core control module to monitor the operating status of the optical measurement equipment, the switching status of each system, etc.

[0041] Digital-to-Analog Conversion Module: This module is implemented using the GD32F450 microcontroller. The ADC clock and corresponding GPIO clock are enabled, and the ADC input pins are configured for analog input mode. The operating mode is set to independent, with a resolution of 12 bits and data right-aligned. The ADC conversion channels and sampling time are configured. Next, the ADC is enabled and calibrated. The ADC conversion is triggered by software, and the conversion completion flag is set, indicating the end of the conversion. The conversion result is read to obtain the corresponding analog signal value.

[0042] Signal Conversion Module: This module utilizes two chips, the SIT3490 and the SIT3232, for signal conversion. The SIT3490, a 422-to-TTL converter, converts 422 standard communication signals to TTL-level signals, while the SIT3232, a 232-to-TTL converter, primarily converts 232 standard communication signals to TTL-level signals, ensuring communication with other digital devices on the board. The signal conversion module boasts excellent signal conversion performance and compatibility, ensuring accurate signal transmission between different standards.

[0043] Network Communication Module: The SR8201F and YT8521SH-CA chips serve as the core chips for the network communication module. The SR8201F supports multiple interfaces, offering strong compatibility and automatically adapting to different network connection methods. The YT8521SH-CA chip complies with multiple Ethernet standards and utilizes advanced DSP technology and an analog front end. Its diverse functional technologies ensure stable and accurate data transmission. Featuring a rich and flexible interface, it operates over a wide temperature range and utilizes a QFN48 package to ensure reliability and stability. Together, these two chips provide the network communication module with efficient, stable, and reliable network connectivity and data transmission capabilities. The network communication module leverages its fast data transmission capabilities to achieve efficient data exchange. It can quickly send small data packets and implement unicast and multicast capabilities based on UDP, allowing data to be sent simultaneously to multiple recipients, improving information dissemination efficiency. Furthermore, it can perform simple encapsulation and decapsulation of UDP packets, process packet header information, and extract key data content.

[0044] Timing module: The timing module performs several important functions. It includes an AC codec module, which encodes AC signals into a digital format suitable for system transmission and processing, and decodes received encoded AC signals to restore the original AC signal. When decoding the received AC code, the MS324 and MS8923 chips are used to amplify the weak AC signal to an appropriate amplitude for subsequent processing and analysis. The timing module also includes an automatic gain module, which monitors changes in input signal strength in real time and automatically adjusts the amplifier gain to maintain the output signal within a certain amplitude range to avoid distortion and misinterpretation caused by excessively strong or weak signals. When transmitting AC code, the MS5620 chip performs D / A conversion. This chip converts digital signals into analog signals with high accuracy and resolution, accurately converting digital signals into corresponding analog voltage or current signals. The timing module also includes a DC codec module, which encodes DC signals for digital transmission and processing, and decodes digitized DC signals to restore the original DC signal. The timing module also includes a GPS / BD decoding module. This module receives navigation signals from the GPS and BeiDou satellite systems through the GPS / BD data receiving module. After demodulation and decoding, it extracts location, time, and other information to provide data support for positioning and timing applications. Furthermore, the timing module also includes a PTP timing module. This module uses a network interface to access PTP time and transmit it to other systems, enabling the system to also support SNMP network management.

[0045] SFP optical communication module: used to transmit servo fiber data, serial port fiber data, two-way high-speed image fiber data, and PTP optical port data to the core control module to realize the system's fiber optic communication.

[0046] 3. Hardware interface module (external electrical interface).

[0047] Signal selection plug: Through circuit design and software design, it can selectively conduct or block different signal paths to achieve precise control of signal flow, making it convenient to directly observe the observation signal during debugging.

[0048] Analog quantity acquisition interface: used to convert external continuously changing physical quantities such as voltage, current, temperature, pressure and other analog signals into digital signals after entering the core control chip so that the system can process, analyze and store them.

[0049] Switching quantity acquisition interface: mainly used to collect digital signals with only two states (such as on / off, high / low), used to monitor the operating status of the equipment, the switching status of each system, etc.

[0050] Dip switch interface: Set different binary codes by toggling the switch position, thereby realizing quick configuration of the system signal gating function.

[0051] SFP optical module interface: realizes the transmission and reception functions of optical signals, supports high-speed data transmission, has the advantages of small size and hot plugging, and is commonly used in fiber-optic communication networks.

[0052] Data communication indicator light: Through different colors, flashing frequencies or combinations, it intuitively displays the status of data communication, such as whether it is transmitting, the transmission speed, whether there is a fault, etc.

[0053] Fiber optic communication indicator light: uses different colors, flashing frequencies or combinations to intuitively display the status of fiber optic communication, such as whether it is transmitting, the transmission speed, whether there is a fault, etc.

[0054] PTP network data interface, used to read PTP time data from the outside.

[0055] PTP network configuration interface, used to manage, monitor, and configure the system's PTP functions.

[0056] PTP control interface, used to transmit the PTP time data of the system timing to other systems.

[0057] The network communication interface is used to provide the core control module with network connection and fast data transmission capabilities to achieve efficient data exchange.

[0058] B code transceiver interface, used to receive the AC code of the B code.

[0059] The GPS / BD data interface board is used to transmit navigation signals from the GPS and BeiDou satellite systems to the core control module.

[0060] High-precision temperature-compensated crystal oscillator is used to provide accurate clock signals for the core control module.

[0061] Power input plug: used to transmit power from an external power supply to the system, providing all electronic components in the system with the voltage and current required for operation.

[0062] The power module is used to provide power to the entire system.

[0063] Compared with existing technical solutions, the domestic optical measurement equipment information integration system proposed by the present invention replaces the chips used on the board, thereby increasing storage capacity and solving the problem of limited chip resources. The functions that originally required five chips on the board are realized by integrating the functions of each unit into two chips, namely the GD32F450 microcontroller and the PG2L100H FPGA, reducing the workload of debugging personnel. The use of the domestically produced GD32F450 microcontroller and PG2L100H FPGA meets the requirements for domestically produced chips in the equipment. The original QTE connector, which would cause unstable connection when not operated and used in accordance with regulations, has been replaced by a data exchange method of multiple optical fibers and multiple serial ports, enhancing the stability of the system.

[0064] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A domestic optical measurement equipment information integrated system, characterized in that: Including core control module, peripheral function module and hardware interface module; Core control module: Consists of a GD32F450 microcontroller and a PG2L100H FPGA. Their corresponding pins (SCK, MISO, MOSI, and NSS) are connected, enabling high-speed data transmission via SPI to process real-time data exchange between various systems in the optical measurement equipment. The GD32F450 microcontroller serves as the SPI master, and the PG2L100H FPGA serves as the SPI slave. The core control module has data communication, fiber optic communication, data monitoring, and timing terminal functions. It can process high-speed image data, real-time encoder data, dimming and focusing data, and trigger signals from the optical measurement equipment, including photoelectric conversion, electro-optical conversion, and data segmentation and reassembly. It also uses multiple optical fibers and serial communication connections. Peripheral function modules: including: Power supply voltage regulator module: composed of GM1203 linear voltage regulator and BL8034 converter, it provides stable voltage output and integrates overvoltage protection, overcurrent protection and short-circuit protection functions; Clock management module: uses the BT0507 temperature-compensated crystal oscillator to provide accurate external clock signals for the PG2L100H FPGA; AC acquisition module: Based on the MS5182N chip, it realizes digital conversion of input analog signals for processing by the core control module; Switching quantity acquisition module: responsible for collecting digital signals with only two states and transmitting the collected digital signals to the core control module; Digital-to-analog conversion module: implemented using the GD32F450 microcontroller, triggering ADC conversion through software to obtain the corresponding value of the analog signal; Signal conversion module: Based on the SIT3490 chip, it converts the 422 standard communication signal and the TTL level signal, and based on the SIT3232 chip, it converts the 232 standard communication signal and the TTL level signal; Network communication module: The SR8201F chip and the YT8521SH-CA chip jointly provide network connection and data transmission capabilities to achieve efficient data exchange, and realize unicast and multicast functions based on UDP; Timing module: Integrates AC encoding and decoding, automatic amplifier gain adjustment, DC encoding and decoding, GPS / BD decoding, and PTP timing functions; the timing module includes a GPS / BD decoding module, which receives navigation signals from the GPS and Beidou satellite systems, demodulates and decodes them, and extracts position and time information to provide data support for positioning and timing applications; Hardware interface module: including: Signal strobe plug: controls the on and off of the signal path through circuit and software design; Analog quantity acquisition interface: converts the input external continuously changing physical quantity into a digital signal; Switching quantity acquisition interface: collects digital signals with only two states, used to monitor the operating status of optical measurement equipment and the switching status of various systems; Dip switch interface: Set different binary codes by toggling the switch position to quickly configure the system signal gating function; SFP optical module interface: realizes the transmission and reception function of optical signals and supports high-speed data transmission; Data communication indicator: displays the status of data communication through different colors, flashing frequencies, or a combination of colors and flashing frequencies.

2. A domestic optical measurement equipment information integrated system according to claim 1, characterized in that: When the GD32F450 microcontroller sends data to the PG2L100H FPGA, the master loads the data into the shift register and then, under the control of the clock signal SCK, sends the data bit by bit to the slave through the MOSI pin. After receiving the clock signal, the PG2L100H FPGA synchronously reads the data and stores it in the internal receive buffer. When the PG2L100H FPGA sends data to the GD32F450 microcontroller, the data is transmitted back to the master through the MISO pin, and the GD32F450 microcontroller receives the data in synchronization with the clock signal.

3. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The PG2L100H FPGA uses GTX high-speed SerDes to achieve optical-to-electrical and electro-optical conversion of data. The synchronization code control and data flow control during the conversion process are completed using proprietary protocols.

4. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The network communication module simply encapsulates and decapsulates UDP data packets, processes the header information of the data packets, and extracts key data content.

5. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The timing module includes an AC codec module, which encodes the AC signal to convert it into a digital format suitable for system transmission and processing, and can decode the received encoded AC signal to restore the original AC signal.

6. A domestic optical measurement equipment information integrated system according to claim 5, characterized in that: The AC codec module uses the MS324 chip and the MS8923 chip to amplify the AC signal when receiving AC code decoding, and uses the MS5620 chip to perform DA conversion when sending AC code encoding.

7. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The timing module includes a DC encoding and decoding module, which encodes the DC signal to achieve digital transmission and processing and decodes the digitized DC signal to restore the original DC signal.

8. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The external continuously changing physical quantity is any one of a voltage analog signal, a current analog signal, a temperature analog signal, and a pressure analog signal.

9. A domestic optical measurement equipment information integrated system according to claim 1 or 2, characterized in that: The data communication status can be any one of whether data is being transmitted, whether the transmission speed is fast or slow, or whether there is a fault.

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