PCB power supply integrity analysis method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of power supply detection, and provides a PCB power supply integrity analysis method and device, electronic equipment and a storage medium. The method comprises the following steps: performing frequency domain target impedance calculation on a design data set to obtain an impedance spectrum demand curve, performing multi-order resonance point matching in combination with a decoupling capacitor library in the design data set to obtain a decoupling network configuration table, and performing analysis in combination with a laminated structure in the design data set to obtain a current density distribution diagram. Thermal and electric coupling analysis is carried out by combining hole data in the design data set to obtain a local temperature rise hot spot list, and then calculation of a ground bomb noise transfer function is carried out by combining a packaging model in the design data set to obtain a noise coupling coefficient matrix; and finally, performing frequency domain impedance superposition verification on the noise coupling coefficient matrix and the impedance spectrum demand curve to generate a power supply integrity compliance report. According to the method, multi-order resonance point matching, eddy current field simulation, current density distribution and thermal and electric coupling analysis are integrated, so that the power supply ground integrity is comprehensively and accurately analyzed.

Description

Technical Field

[0001] The present application relates to the technical field of power supply detection, and in particular, to a PCB power integrity analysis method, device, electronic device, and storage medium. Background Art

[0002] With the increasing requirements for high frequency and high performance of electronic devices, the printed circuit board (PCB), as the core component of electronic products, carries a complex power supply system. Therefore, how to ensure power integrity has become an indispensable key issue in PCB design. Power integrity (PI) involves factors such as the stability of the power supply network, noise management, thermal performance, and current distribution, which directly affect the performance and reliability of the PCB board.

[0003] Existing PCB power integrity analysis usually combines impedance calculation and matching, decoupling capacitor configuration optimization, or current density analysis with the data of power supply design and simulation tools to provide designers with a detailed power integrity assessment.

[0004] However, existing PCB power integrity analysis often isolates and uses a single method to perform IP analysis of conventional factors on the PCB power supply. This scattered analysis method only analyzes single-level problems and only analyzes conventional factors, resulting in certain limitations in the analysis results, making the measures based on the analysis results unable to achieve the best power optimization effect. Summary of the Invention

[0005] In view of this, the present application provides a PCB power integrity analysis method, device, electronic device, and storage medium to solve the problem of single and limited PCB power integrity analysis.

[0006] The first aspect of the present application provides a PCB power integrity analysis method, and the method includes: Obtaining a design data set of a target power supply, and performing frequency-domain target impedance calculation processing on the design data set to obtain an impedance spectrum requirement curve; Performing multi-order resonance point matching processing on the impedance spectrum requirement curve and the decoupling capacitor library in the design data set to obtain a decoupling network configuration table; Performing power plane eddy current field simulation processing on the decoupling network configuration table and the stack-up structure in the design data set to obtain a current density distribution map; Performing thermal and electrical coupling analysis processing on the current density distribution map and the via data in the design data set to obtain a local temperature rise hot spot list; Perform a ground bounce noise transfer function calculation process on the local temperature rise hot spot list and the packaging model in the design dataset to obtain a noise coupling coefficient matrix; Perform a frequency-domain impedance superposition verification process on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

[0007] In an optional implementation manner, the performing a frequency-domain target impedance calculation process on the design dataset to obtain an impedance spectrum requirement curve includes: Perform target data extraction on the design dataset to obtain a subset of impedance calculation parameters; Perform a frequency-domain target impedance calculation process on the subset of impedance calculation parameters to obtain a frequency and impedance dataset; Perform interpolation and smoothing processing on the frequency and impedance dataset to obtain the impedance spectrum requirement curve.

[0008] In an optional implementation manner, the performing a multi-order resonance point matching process on the impedance spectrum requirement curve and the decoupling capacitor library in the design dataset to obtain a decoupling network configuration table includes: Perform capacitance impedance modeling on the decoupling capacitor library in the design dataset to obtain a frequency-domain impedance dataset of all capacitors; According to the frequency-domain impedance dataset and the impedance spectrum requirement curve, use a preset particle swarm optimization algorithm to obtain an optimal capacitor combination set; Perform a total impedance response calculation according to the optimal capacitor combination set to obtain a total impedance response set of all optimal capacitor combinations; Perform an error analysis process according to the total impedance response set and the impedance spectrum requirement curve to obtain an optimal capacitor configuration set; Generate the decoupling network configuration table according to the decoupling capacitor library and the optimal capacitor configuration set.

[0009] In an optional implementation manner, the performing a power plane eddy current field simulation process on the decoupling network configuration table and the stack-up structure in the design dataset to obtain a current density distribution map includes: Perform electromagnetic modeling processing according to the stack-up structure in the design dataset to obtain a coupling model; Perform a power plane eddy current field simulation process according to the optimal capacitor configuration set in the decoupling network configuration table and the coupling model to obtain a distribution matrix of the current in the power plane of the coupling model; Perform current density calculation according to the distribution matrix and the power plane to obtain a current density distribution dataset of all regions; Generate the current density distribution map based on the power supply plane, the preset mapping method, and the current density distribution data set of all regions.

[0010] In an alternative embodiment, the thermal and electrical coupling analysis processing of the current density distribution map and the via data in the design data set to obtain the local temperature rise hot spot list includes: Construct a geometric model based on the via data in the design data set to obtain a via distribution model; Perform a joint simulation processing of current density and heat conduction on the via distribution model according to the current density distribution data set in the current density distribution map to obtain the heat power density distribution data set of all regions; Perform a superposition analysis according to the heat power density distribution data set and the current density distribution data set to obtain the temperature rise data of each region; Analyze and process the temperature rise data according to a preset temperature rise threshold to identify the abnormal regions in the via distribution model where the temperature rise data exceeds the temperature rise threshold; Generate the local temperature rise hot spot list according to the abnormal regions.

[0011] In an alternative embodiment, the ground bounce noise transfer function calculation processing of the local temperature rise hot spot list and the package model in the design data set to obtain the noise coupling coefficient matrix includes: Perform circuit and mechanical coupling modeling processing on the package model in the design data set to obtain the electrical and structural characteristic data set of the package model; Extract the package model regions corresponding to the abnormal regions from the package model according to the local temperature rise hot spot list to obtain an abnormal package region set; Generate a ground bounce noise source and transmission path model according to the abnormal package region set and the electrical and structural characteristic data set; Perform ground bounce noise transfer function calculation processing on the ground bounce noise source and transmission path model to obtain the noise coupling coefficients at different frequencies; Perform frequency domain analysis processing on the noise coupling coefficients to obtain the noise coupling coefficient matrix.

[0012] In an alternative embodiment, the frequency domain impedance superposition verification processing of the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain the power supply integrity compliance report includes: Perform frequency domain impedance superposition processing according to the noise coupling coefficients in the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain the actual impedance response set of all frequency bands; Perform error analysis on the actual impedance response set and the impedance spectrum requirement curve to obtain the impedance error value for each frequency band; Perform evaluation processing based on the impedance error value to obtain out-of-specification frequency band information; Generate the power integrity compliance report according to the out-of-specification frequency band information.

[0013] The second aspect of this application provides a PCB power integrity analysis device, and the device includes: An impedance calculation module, configured to obtain a design data set of a target power supply, and perform frequency-domain target impedance calculation processing on the design data set to obtain an impedance spectrum requirement curve; A decoupling network module, configured to perform multi-order resonance point matching processing on the impedance spectrum requirement curve and the decoupling capacitor library in the design data set to obtain a decoupling network configuration table; A current density module, configured to perform power plane eddy current field simulation processing on the decoupling network configuration table and the stack structure in the design data set to obtain a current density distribution map; A local temperature rise module, configured to perform thermal and electrical coupling analysis processing on the current density distribution map and the via data in the design data set to obtain a local temperature rise hot spot list; A coefficient matrix module, configured to perform ground bounce noise transfer function calculation processing on the local temperature rise hot spot list and the package model in the design data set to obtain a noise coupling coefficient matrix; A superposition verification module, configured to perform frequency-domain impedance superposition verification processing on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

[0014] The third aspect of this application provides an electronic device, the electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, it implements the steps of the PCB power integrity analysis method described above.

[0015] The fourth aspect of this application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the PCB power integrity analysis method described above: In summary, this application at least includes the following beneficial technical effects: 1. From frequency-domain target impedance calculation, decoupling network optimization, power plane simulation, thermal and electrical coupling analysis, to the calculation of the transfer function of noise coupling, a systematic and all-round analysis process is formed. Each step deeply analyzes different aspects of the PCB power supply system to ensure that potential power integrity problems are not overlooked.

[0016] 2. By optimizing the decoupling capacitor bank through methods such as multi - order resonance point matching and particle swarm optimization, the impedance response of the PCB can be effectively reduced, power supply noise can be reduced, and thus the decoupling effect can be improved.

[0017] 3. The local temperature rise hot - spot list obtained through thermo - electrical coupling analysis helps to identify areas with excessive temperature and take timely heat dissipation measures to avoid electrical failures or performance degradation caused by local overheating. Brief Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a flowchart of a PCB power integrity analysis method provided by an embodiment of the present application; Figure 2 is a functional module diagram of a PCB power integrity analysis device provided by an embodiment of the present application; Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed Embodiments

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0021] As Figure 1 shown, it is a flowchart of the PCB power integrity analysis method provided by an embodiment of the present application. The PCB power integrity analysis method provided by an embodiment of the present application includes the following steps.

[0022] Step S1: Obtain the design data set of the target power supply and perform frequency - domain target impedance calculation processing on the design data set to obtain the impedance spectrum requirement curve.

[0023] Among them, the design dataset of the target power supply includes but is not limited to detailed information such as the layout between the power plane and the ground plane, via distribution, the number and location of decoupling capacitors, etc. The design dataset usually comes from PCB design files (e.g., Gerber files), power network topology structure files, and the operating parameters of the power supply system. The design dataset can be obtained through appropriate design tools (e.g., circuit design software or electromagnetic simulation software).

[0024] By extracting impedance calculation parameters such as power network topology data, maximum transient current, allowable voltage fluctuation, and highest concerned frequency from the design dataset, an impedance calculation parameter subset is obtained. And the frequency-domain target impedance calculation is performed on the impedance calculation parameter subset through the following formula to obtain the target impedance of the target power supply system at different frequencies (i.e., frequency and impedance data).

[0025] Among them, is the target impedance, which is used to represent the impedance value of the target power supply system at frequency . is the allowable voltage fluctuation, which is used to represent the maximum voltage change range allowed for the target power supply system when the load changes. is the maximum transient current, which is used to represent the maximum current in the target power supply system. is the highest concerned frequency, usually 5 times the chip switching frequency. is the frequency value within the highest concerned frequency. The target impedance is the impedance requirement of the target power supply system network. By setting the target impedance within the corresponding frequency range, the stability of the target power supply system can be ensured, power noise can be suppressed, and excessive voltage fluctuations can be prevented.

[0026] By calculating the target impedance for each frequency value, the target impedance corresponding to all frequencies within the highest concerned frequency is obtained, and then all the target impedances and frequency values are summarized and combined into a frequency and impedance dataset. Further, through a preset interpolation method (e.g., linear interpolation or cubic spline interpolation), the missing data deduced is inserted between the known data points to obtain a more refined frequency and impedance dataset. At the same time, the noise in the frequency and impedance dataset is removed by smoothing filtering, making the frequency and impedance dataset smoother to avoid unnecessary spikes or mutations, which helps to improve the stability and accuracy of the target power supply system.

[0027] After interpolation and smoothing, adjacent frequency and impedance data points in the frequency and impedance datasets are fitted to obtain a continuous and smooth impedance spectrum demand curve. The impedance spectrum demand curve intuitively reflects the ideal impedance values of the target power supply system at various frequencies, facilitating designers to optimize and adjust the target power supply system according to the impedance spectrum demand curve, and ensuring the stable operation of the target power supply system within all operating frequency bands.

[0028] Step S2: Perform multi-order resonance point matching processing on the impedance spectrum demand curve and the decoupling capacitor library in the design dataset to obtain a decoupling network configuration table.

[0029] It should be understood that the impedance characteristics of each capacitor will exhibit different behaviors at different frequencies. Generally, the impedance of a capacitor is not only related to its capacitance value, but also related to factors such as its series resistance and series inductance. By optimizing the capacitor configuration, an appropriate decoupling ability can be provided for the target power supply system within the target frequency band. According to the decoupling capacitor library in the design dataset, the frequency-domain impedance of the capacitor is modeled through the following formula to facilitate accurately simulating its behavior at different frequencies during the decoupling network optimization process of the target power supply system.

[0030] Where, is the frequency-domain impedance of the capacitor, used to represent the resistance of the capacitor at frequency . ESR is the equivalent series resistance of the capacitor, used to represent the effect of the internal resistance of the capacitor. ESL is the equivalent series inductance of the capacitor, used to represent the self-inductance effect of the capacitor. C is the capacitance value of the capacitor. is the frequency value within the highest concerned frequency. The impedance characteristics (i.e., frequency-domain impedance data) of each capacitor calculated through the frequency-domain impedance modeling formula in the capacitor impedance modeling are used to represent the law of the impedance of the capacitor changing with frequency, and are important parameters for the selection of decoupling capacitors. After obtaining the frequency-domain impedance data of each capacitor, the frequency-domain impedance data of all capacitors are aggregated to form a frequency-domain impedance dataset.

[0031] After obtaining the frequency-domain impedance dataset, an optimization algorithm is needed to select the optimal capacitor combination so that the number, type, and deployment location of the capacitors after optimization can make the network of the target power supply system meet the impedance requirements within the target frequency band.

[0032] This application uses the particle swarm optimization algorithm to optimize the frequency-domain impedance dataset to obtain the optimal capacitance combination. Specifically, the particle swarm is initialized according to the power supply design requirements and capacitance library information in the design dataset, where each particle represents a capacitance combination. The effect of each particle is evaluated through the following fitness function, and then the capacitance combination that minimizes the fitness function (i.e., makes the total impedance response as close as possible to the target impedance spectrum requirement curve) is selected to obtain the optimal capacitance combination set.

[0033] Among them, is the fitness value of the particle, which is used to represent the quality of the current capacitance combination. is the target impedance of the target impedance spectrum requirement curve at the frequency under. is the total impedance response calculated according to the current capacitance combination. N is the number of frequency bands for calculating the error.

[0034] According to the optimal capacitance combination set, the total impedance response corresponding to the optimal capacitance combination (i.e., the total impedance response set) is calculated through the following formula.

[0035] Among them, is the total impedance response, which is used for the sum of all capacitance combinations and the PCB inherent impedance at the frequency under. is the frequency-domain impedance of the kth capacitor. is the PCB inherent impedance. M is the number of capacitors. The total impedance response refers to the system impedance response under the combined action of multiple capacitors and other components in the power supply network. The total impedance response set of the optimal capacitance combination needs to be compared with the target impedance spectrum requirement curve to ensure that the target power supply system can meet the preset impedance requirements.

[0036] Through the following formula, error analysis processing is carried out based on the total impedance response set of the optimal capacitance combination and the target impedance spectrum requirement curve.

[0037] Among them, is the error at the frequency under, which is used to represent the difference between the target impedance and the actual impedance response. is the value of the target impedance spectrum requirement curve at the frequency under. is the calculated total impedance response. Error analysis further optimizes the capacitance configuration to the optimal capacitance configuration set by calculating the difference between the actual response and the target response.

[0038] Finally, a decoupling network configuration table is generated according to the optimal capacitor configuration set. The decoupling network configuration table details information such as the model, quantity, location, and operating frequency band of all selected capacitors, aiming to optimize the decoupling effect of the power supply system. The decoupling network configuration table can be used as a reference for capacitor configuration in actual circuit design to ensure that the power supply system has appropriate impedance characteristics in different frequency bands.

[0039] Step S3: Perform power plane eddy current field simulation processing on the decoupling network configuration table and the stack structure in the design dataset to obtain a current density distribution map.

[0040] Among them, the stack structure includes but is not limited to the structure of the power plane and the ground plane. Electromagnetic modeling based on the stack structure in the design dataset calculates the electromagnetic field distribution in the power network through numerical simulation methods based on the structure of the power plane and the ground plane. In order to accurately simulate the distribution of current in the power plane, electromagnetic coupling between the power layer, the ground plane, and the signal layer needs to be considered during the modeling process. The electromagnetic modeling formula can be expressed as the following formula: Among them, is the curl of the magnetic field, used to represent the change of the electromagnetic field. is the current density, used to represent the distribution of current in the power plane. is the imaginary unit, used to represent the influence of complex frequency. is the angular frequency, equal to 2πf. is the permittivity, used to represent the electrical characteristics of the material. E is the electric field strength. The coupling model between the power plane and the ground plane established through the electromagnetic modeling formula is used to describe the change of the electromagnetic field, especially the mutual relationship between the current density and the electric field and magnetic field.

[0041] Power plane eddy current field simulation is to simulate the flow of current in the power plane by solving the electromagnetic field model. Using the coupling model generated in the previous step, the decoupling capacitor configuration is combined with the power plane simulation to simulate the flow of current on the power plane. The eddy current field simulation formula can be expressed as the following formula: Among them, is the current density, used to represent the current intensity at the position (x, y). is the conductivity of the material, used to represent the conductive ability of the power plane. is the curl of the magnetic field, which is used to represent the interaction between the current and the electromagnetic field at the position (x, y). Eddy current field simulation helps to simulate the flow path of the current in the power plane and provides the current density data of the current in each grid cell. Further, all the grid cells in the power plane and their corresponding current density data are summarized to form a distribution matrix.

[0042] Further, after obtaining the distribution matrix, it is necessary to calculate the density value of the current in each region of the power plane, that is, to divide the intensity value of the current by the area of the region to obtain the current density of each region. The current density is calculated by the following formula: where is the current density, representing the current intensity at the position (x, y). is the current value, representing the magnitude of the current at the position (x, y). is the grid area, representing the size of the region at the position (x, y).

[0043] It should be understood that in order to visually display the current intensity distribution in each region of the power plane and facilitate the analysis and identification of regions with excessive current concentration or uneven distribution, the embodiments of the present application preset a color mapping method to map the current density distribution data set to the power plane. In the color mapping method, a gradient from warm colors to cold colors is used to mark the change of the current density distribution in each region of the power plane. Exemplarily, regions with higher current density are marked as red, regions with lower current density are marked as blue, and a color scale is used to represent regions with different densities.

[0044] Specifically, according to the region coordinates in the current density distribution data set, the actual position corresponding to the region coordinates on the power plane is determined. At the same time, according to the current density value in the current density distribution data set, the color to be used for the actual position is determined, so as to map the selected color value to the corresponding actual position on the power plane. Finally, the power plane is converted into a three-dimensional current density distribution map.

[0045] Step S4: Perform thermal and electrical coupling analysis on the current density distribution map and the via data in the design data set to obtain a list of local temperature rise hot spots.

[0046] Among them, the via data includes, but is not limited to, the geometric dimensions, positions, and material properties of each via. A via distribution model is constructed according to the via data in the design data set, which is used to describe the path of the current passing through the vias between the power plane and the ground plane and its influence. The geometric modeling includes the following formula: where $P_J$ is the Joule heat power, representing the heat generated when passing through the via. $I$ is the current, representing the current value passing through the via. $R$ is the resistance of the via, which depends on the geometric dimensions and material properties of the via. $A$ is the cross-sectional area of the via, representing the size of the via. Calculating the Joule heat power helps to understand the process of the energy converted into heat due to the resistance when the current passes through the via. Describing the geometric characteristics of the via and the path of current flow through geometric modeling and Joule heat power calculation, and describing how the interaction between current and resistance in each region of the via affects the temperature rise based on the heat generated by the resistance when the current passes through the via.

[0047] After obtaining the via distribution model, a joint simulation of current density and heat conduction is performed in combination with the current density distribution dataset. Among them, the current density distribution map provides the intensity of the current in each region, and the via distribution model provides the geometric data of the via. By simulating the Joule heat generated when the current passes through the via and calculating the heat distribution in each region according to the heat power density distribution. The formula for the heat power density is expressed as follows: Among them, $q(x,y)$ is the heat power density at the position $(x,y)$, representing the heat generated per unit volume in this region. $J(x,y)$ is the current density, representing the current intensity at the position $(x,y)$. $\sigma$ is the conductivity of the material, representing the ability of the material to conduct current. Calculate the heat power density at the given position $(x,y)$ one by one through the heat power density calculation formula, so as to obtain the heat power distribution of each region.

[0048] It should be understood that the heat generated when the current passes through the via or the power plane will spread in the power supply system. Therefore, it is necessary to combine the heat power density and the current density to analyze the temperature change. By superimposing the heat power density and the current density, the temperature change or temperature rise in each region can be obtained. The formula for the temperature rise is expressed as follows: Among them, $k$ is the thermal conductivity, representing the heat conduction ability of the material. $T$ is the temperature, representing the temperature at a certain point. $q(x,y)$ is the heat power density, representing the heat generated at this position. $\nabla\cdot(k\nabla T)$ is the divergence of the heat conduction equation, describing the transfer of heat in the material. Simulate the diffusion of heat by considering the thermal conductivity of the material and the heat power density generated in this region to obtain the temperature rise data. The temperature rise data will help to identify the regions with higher temperatures in the target power supply system, and these regions may cause overheating of the device and potential failures.

[0049] After obtaining the temperature rise data for each region, regions with temperatures exceeding this threshold are identified based on a preset temperature rise threshold. The temperature rise threshold is typically set based on design specifications or the maximum operating temperature limit of the power supply components. When the temperature rise data exceeds the temperature rise threshold, these regions are marked as abnormal regions in the via distribution model. Finally, a local temperature rise hot spot list is generated based on the temperature rise information of the abnormal regions in the via distribution model. The local temperature rise hot spot list includes, but is not limited to, the coordinates of the abnormal regions and the temperature rise data.

[0050] Step S5: Perform a ground bounce noise transfer function calculation process on the local temperature rise hot spot list and the package model in the design dataset to obtain a noise coupling coefficient matrix.

[0051] It should be understood that ground bounce noise is used to describe the electromagnetic interference noise source caused by current changes or temperature fluctuations in PCB design and packaging. Specifically, it refers to the noise generated by the electromagnetic coupling between the ground plane and the power plane, especially the current fluctuations or electrical noise caused by the ground bounce effect (i.e., thermal expansion, stress, or mechanical deformation within the package).

[0052] The package model includes, but is not limited to, the package characteristics of the integrated circuit chip, signal pins, power pins, and the physical and electrical characteristics of the connection to the PCB. When performing circuit and mechanical coupling modeling based on the package model in the design dataset, the coupling process of the package model needs to consider both electrical and mechanical characteristics, especially the impact of stress and thermal expansion effects generated in the temperature rise region on electrical characteristics and noise. The electrical and structural characteristic modeling formula is as follows: Where, is the transfer function, which describes how noise is transferred from the source to other circuit parts. s is the complex frequency, representing the response of the system in the frequency domain. is the resistance parameter inside the package, representing the resistance in the signal path. is the inductance parameter of the package, representing the inductance in the signal path. is the capacitance parameter of the package, representing the capacitance in the signal path. The electrical and structural characteristic modeling formula describes the electrical and mechanical coupling relationship between the ground bounce noise source and the package model, especially how noise is transferred through the resistance, inductance, and capacitance paths of the package to obtain the electrical and structural characteristic dataset.

[0053] Meanwhile, according to the abnormal area coordinates and temperature rise data in the local temperature rise hot spot list, the corresponding packaging areas (i.e., the set of abnormal packaging areas) are extracted from the packaging model. The set of abnormal packaging areas are areas with relatively high temperature rise, which usually cause an increase in noise or a change in electrical characteristics in the power supply system. Therefore, it is necessary to further analyze the set of abnormal packaging areas as special areas in the packaging model.

[0054] Combining the obtained set of abnormal packaging areas with the corresponding electrical and structural characteristic data sets, a ground bounce noise source and transmission path model is generated. The ground bounce noise source and transmission path model mainly describes how the noise caused by the overheated area (i.e., the ground bounce noise source) propagates in the power network and affects the power integrity. The ground bounce noise source is usually closely related to temperature changes, mechanical deformations, and electrical responses. Therefore, when generating this model, the electrical and mechanical characteristics of the temperature rise area need to be combined to analyze its impact on signal noise. The formula for the ground bounce noise source and transmission path model is as follows: Where, is the noise coupling coefficient, representing the intensity of the noise signal transmitted from the noise source to the target area. is the voltage of the noise signal, representing the voltage response of the noise source. is the instantaneous current of the noise source, representing the current generated by the noise source in the power supply. The formula for the ground bounce noise source and transmission path model describes the noise transmission process from the noise source to the target area, helping to quantify the impact of the ground bounce noise source on the power supply system.

[0055] After obtaining the ground bounce noise source and transmission path model, by performing the calculation process of the ground bounce noise transfer function on this model, the noise coupling coefficients at different frequencies can be obtained. By calculating the ground bounce noise transfer function, the impact of the noise source can be obtained, that is, how the noise propagates from the source (such as the temperature rise hot spot) to other areas in the power supply system, and the calculation is carried out through the corresponding electrical and mechanical couplings, so as to represent the intensity of the noise propagation at different frequencies. Since the ground bounce noise transfer function is still an electrical and mechanical coupling calculation, the same mathematical formula as that used in the electrical and structural characteristic modeling is adopted for the ground bounce noise transfer function calculation, so it will not be elaborated here. For details, please refer to the calculation formula for the electrical and structural characteristic modeling. The noise coupling coefficients obtained through the ground bounce noise transfer function calculation quantify the propagation intensity of the noise signal at different frequencies and are important parameters for evaluating the impact of the noise in the target power supply system.

[0056] After obtaining the noise coupling coefficients, by performing frequency domain analysis on the noise coupling coefficients, the noise coupling coefficient matrix is obtained, which describes the coupling intensity of the noise to the target power supply system at different frequencies. The formula for the frequency domain analysis of the noise coupling coefficient is as follows: Among them, is the noise coupling coefficient matrix, which represents the coupling strength of noise in the power supply system. is the noise coupling coefficient, which represents the transfer strength of the noise signal. is the impedance spectrum requirement curve, which represents the target impedance of the power supply system.

[0057] Step S6: Perform frequency-domain impedance superposition verification processing on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

[0058] Among them, the noise coupling coefficient matrix represents the coupling strength of noise at different frequencies, and the impedance spectrum requirement curve describes the ideal target impedance of the power supply system at different frequencies. By combining these two parameters, the actual impedance response of the target power supply system in all frequency bands can be calculated. The frequency-domain impedance superposition processing formula is as follows: Among them, is the actual impedance response, which represents the actual impedance value of the power supply system at frequency under. is the PCB inherent impedance, which represents the impedance of the PCB part in the power supply system. is the noise coupling coefficient matrix, which represents the coupling strength of noise at different frequencies. is the calculated frequency point. The frequency-domain impedance superposition processing formula combines the inherent impedance of the PCB with the noise coupling coefficient to obtain the actual impedance response set of the target power supply system at different frequencies, so as to map the impedance behavior of the target power supply system under actual working conditions.

[0059] After obtaining the actual impedance response set, error analysis is performed by comparing the actual impedance response set with the impedance spectrum requirement curve, so as to quantify the difference between the actual impedance and the target impedance according to the obtained impedance error value, and thus evaluate whether the power supply system meets the design requirements. The error analysis formula is as follows: Among them, is the impedance error at frequency under, which represents the difference between the target impedance and the actual impedance. is the target impedance of the impedance spectrum requirement curve at frequency under. is the actual impedance response, which represents the actual impedance of the power supply system at frequency under.

[0060] After obtaining the impedance error values for each frequency band, the impedance error values are compared one by one according to a preset allowable error threshold to identify the out-of-specification frequency band information. An out-of-specification frequency band refers to a frequency band within which the impedance response of the power supply system fails to meet the design requirements, and these frequency bands usually cause noise problems or power instability in the power supply system.

[0061] Finally, according to the obtained out-of-specification frequency band information and in accordance with the set report format, a power integrity compliance report for the target power supply system is generated. The power integrity compliance report details the impedance errors, out-of-specification frequency bands, and optimization suggestions of the power supply system. Based on the power integrity compliance report, designers can understand the performance of the power supply system under actual working conditions and take corresponding measures for improvement.

[0062] This application is applied to the field of power supply detection technology. By obtaining the design data set and power distribution network of the target power supply, calculating the impedance spectrum demand curve through frequency-domain target impedance calculation of the power distribution network, performing multi-order resonance point matching on the impedance spectrum demand curve and the decoupling capacitor bank in the design data set to obtain the decoupling network configuration table, further analyzing the decoupling network configuration table and the stack-up structure in the design data set through power plane eddy current field simulation to generate a current density distribution map, thereby performing thermal and electrical coupling analysis on the current density distribution map and the via data in the design data set to obtain a local temperature rise hot spot list, and then calculating the ground bounce noise transfer function of the local temperature rise hot spots and the package model in the design data set to obtain a noise coupling coefficient matrix, and finally combining the noise coupling coefficient matrix and the impedance spectrum demand curve for frequency-domain impedance superposition verification to obtain a power integrity compliance report. This application realizes a comprehensive analysis of power supply design through comprehensive technologies such as multi-order resonance point matching, eddy current field simulation, current density distribution, and thermal and electrical coupling analysis, improving the accuracy and reliability of power integrity analysis.

[0063] As Figure 2 shown, it is a functional module diagram of a PCB power integrity analysis device provided by an embodiment of this application.

[0064] In some embodiments, the PCB power integrity analysis device 2 may include multiple functional modules composed of computer program segments. The computer programs of each program segment in the PCB power integrity analysis device 2 can be stored in the memory of the server and executed by at least one processor to execute the functions of the PCB power integrity analysis method (see Figure 1 description).

[0065] In this embodiment, the PCB power integrity analysis device 2 can be divided into multiple functional modules according to the functions it performs. The functional modules may include: an impedance calculation module 21, a decoupling network module 22, a current density module 23, a local temperature rise module 24, a coefficient matrix module 25, and a superposition verification module 26. The module referred to in the present invention means a series of computer program segments that can be executed by at least one processor and can complete fixed functions, and are stored in a memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0066] The impedance calculation module 21 is configured to obtain a design data set of a target power supply and perform frequency-domain target impedance calculation processing on the design data set to obtain an impedance spectrum requirement curve.

[0067] In an optional implementation manner, the impedance calculation module 21 is specifically configured to: Extract target data from the design data set to obtain a subset of impedance calculation parameters; Perform frequency-domain target impedance calculation processing on the subset of impedance calculation parameters to obtain a frequency-impedance data set; Perform interpolation and smoothing processing on the frequency-impedance data set to obtain the impedance spectrum requirement curve.

[0068] The decoupling network module 22 is configured to perform multi-order resonance point matching processing on the impedance spectrum requirement curve and the decoupling capacitor library in the design data set to obtain a decoupling network configuration table.

[0069] In an optional implementation manner, the decoupling network module 22 is specifically configured to: Perform capacitance impedance modeling on the decoupling capacitor library in the design data set to obtain a frequency-domain impedance data set of all capacitors; According to the frequency-domain impedance data set and the impedance spectrum requirement curve, use a preset particle swarm optimization algorithm to obtain an optimal capacitor combination set; Perform total impedance response calculation according to the optimal capacitor combination set to obtain a total impedance response set of all optimal capacitor combinations; Perform error analysis processing according to the total impedance response set and the impedance spectrum requirement curve to obtain an optimal capacitor configuration set; Generate the decoupling network configuration table according to the decoupling capacitor library and the optimal capacitor configuration set.

[0070] The current density module 23 is configured to perform power plane eddy current field simulation processing on the decoupling network configuration table and the stack structure in the design data set to obtain a current density distribution map.

[0071] In an optional embodiment, the current density module 23 is specifically configured to: Perform electromagnetic modeling processing according to the stack structure in the design dataset to obtain a coupling model; Perform power plane eddy current field simulation processing according to the optimal capacitance configuration set in the decoupling network configuration table and the coupling model to obtain a distribution matrix of the current in the power plane of the coupling model; Calculate the current density according to the distribution matrix and the power plane to obtain a current density distribution dataset for all regions; Generate the current density distribution map according to the power plane, a preset mapping method, and the current density distribution dataset for all regions.

[0072] The local temperature rise module 24 is configured to perform thermal and electrical coupling analysis processing on the current density distribution map and the via data in the design dataset to obtain a local temperature rise hot spot list.

[0073] In an optional embodiment, the local temperature rise module 24 is specifically configured to: Construct a geometric model according to the via data in the design dataset to obtain a via distribution model; Perform joint simulation processing of current density and heat conduction on the via distribution model according to the current density distribution dataset in the current density distribution map to obtain a thermal power density distribution dataset for all regions; Perform superposition analysis according to the thermal power density distribution dataset and the current density distribution dataset to obtain the temperature rise data for each region; Analyze and process the temperature rise data according to a preset temperature rise threshold to identify abnormal regions in the via distribution model where the temperature rise data exceeds the temperature rise threshold; Generate the local temperature rise hot spot list according to the abnormal regions.

[0074] The coefficient matrix module 25 is configured to perform ground bounce noise transfer function calculation processing on the local temperature rise hot spot list and the package model in the design dataset to obtain a noise coupling coefficient matrix.

[0075] In an optional embodiment, the coefficient matrix module 25 is specifically configured to: Perform circuit and mechanical coupling modeling processing on the package model in the design dataset to obtain an electrical and structural characteristic dataset of the package model; Extract the package model regions corresponding to the abnormal regions from the package model according to the local temperature rise hot spot list to obtain a set of abnormal package regions; Generate a ground bounce noise source and transmission path model based on the abnormal encapsulation area set and the electrical and structural characteristic data set; Perform ground bounce noise transfer function calculation processing on the ground bounce noise source and transmission path model to obtain noise coupling coefficients at different frequencies; Perform frequency domain analysis processing on the noise coupling coefficients to obtain the noise coupling coefficient matrix.

[0076] The superposition verification module 26 is used to perform frequency domain impedance superposition verification processing on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

[0077] In an optional embodiment, the superposition verification module 26 is specifically used for: Perform frequency domain impedance superposition processing based on the noise coupling coefficients in the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain an actual impedance response set for all frequency bands; Perform error analysis on the actual impedance response set and the impedance spectrum requirement curve to obtain impedance error values for each frequency band; Perform evaluation processing based on the impedance error values to obtain out-of-specification frequency band information; Generate the power integrity compliance report based on the out-of-specification frequency band information.

[0078] It should be understood that the various variations and specific embodiments of the methods provided in the above embodiments are equally applicable to the PCB power integrity analysis device in this embodiment. Through the foregoing detailed description of the PCB power integrity analysis method, those skilled in the art can clearly know the implementation method of the PCB power integrity analysis device in this embodiment. For the sake of brevity of the specification, it will not be elaborated here.

[0079] As Figure 3 shown, it is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0080] In a preferred embodiment of the present invention, the electronic device 3 may include, but is not limited to: a memory 31, at least one processor 32, and at least one communication bus 33.

[0081] Those skilled in the art should understand that Figure 3 the structure of the electronic device 3 shown does not constitute a limitation of the embodiments of the present invention. The electronic device 3 may further include more or fewer other hardware or software than shown, or different component arrangements.

[0082] In some embodiments, the electronic device 3 is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, a microprocessor, an application specific integrated circuit, a programmable gate array, a digital signal processor, and an embedded device, etc.

[0083] It should be noted that the electronic device 3 is only an example, and other existing or future electronic products that can be adapted to this application should also be included within the protection scope of this application and are hereby incorporated by reference.

[0084] In some embodiments, a computer program is stored in the memory 31, and when the computer program is executed by the at least one processor 32, all or part of the steps in the PCB power integrity analysis method as described above are implemented. The memory 31 includes a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc memories, magnetic disk memories, tape memories, or any other computer-readable medium that can be used to carry or store data. Further, the computer-readable storage medium mainly includes a storage program area and a storage data area. Among them, the storage program area can store an operating system, application programs required for at least one function, etc.

[0085] In some embodiments, the at least one processor 32 is the control core (Control Unit) of the electronic device 3, connecting various components of the entire electronic device 3 through various interfaces and circuits. By running or executing programs or modules stored in the memory 31, and invoking data stored in the memory 31, it performs various functions of the electronic device 3 and processes data. For example, when the at least one processor 32 executes the computer program stored in the memory 31, it implements all or part of the steps of the PCB power integrity analysis method described in the embodiments of the present application; or implements all or part of the functions of the PCB power integrity analysis device. The at least one processor 32 may be composed of integrated circuits. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple integrated circuits with the same or different functions packaged, including a combination of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc.

[0086] In some embodiments, the at least one communication bus 33 is set to enable connection communication between the memory 31 and the at least one processor 32, etc. Although not shown, the electronic device 3 may further include a power supply (such as a battery) for powering each component. Preferably, the power supply can be logically connected to the at least one processor 32 through a power management device, so as to implement functions such as management of charging, discharging, and power consumption management through the power management device. The power supply may also include any components such as one or more DC or AC power supplies, a recharge device, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 3 may also include various sensors, a Bluetooth module, a Wi-Fi module, etc., which will not be elaborated here.

[0087] The integrated unit implemented in the form of the above software functional module can be stored in a computer-readable storage medium. The above software functional module is stored in a storage medium, including several instructions for causing an electronic device (which may be a personal computer, an electronic device, or a network device, etc.) or a processor to execute part of the methods described in the embodiments of the present application.

[0088] In several embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0089] The module described as a separation component may or may not be physically separated. The component shown as a module may or may not be a physical unit, and it may be located in one place or distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] The above are all preferred embodiments of this application, and the protection scope of this application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of this application shall be covered within the protection scope of this application.

Claims

1. A method for analyzing the power integrity of a PCB, characterized in that, The method includes: Obtaining a design data set of a target power supply, and performing frequency-domain target impedance calculation processing on the design data set to obtain an impedance spectrum requirement curve; Performing multi-order resonance point matching processing on the impedance spectrum requirement curve and the decoupling capacitor library in the design data set to obtain a decoupling network configuration table; Performing power plane eddy current field simulation processing on the decoupling network configuration table and the stack structure in the design data set to obtain a current density distribution map; Performing thermal and electrical coupling analysis processing on the current density distribution map and the via data in the design data set to obtain a local temperature rise hot spot list; Performing ground bounce noise transfer function calculation processing on the local temperature rise hot spot list and the package model in the design data set to obtain a noise coupling coefficient matrix; Performing frequency-domain impedance superposition verification processing on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

2. The PCB power integrity analysis method according to claim 1, wherein The performing frequency-domain target impedance calculation processing on the design data set to obtain an impedance spectrum requirement curve includes: Performing target data extraction on the design data set to obtain an impedance calculation parameter subset; Performing frequency-domain target impedance calculation processing on the impedance calculation parameter subset to obtain a frequency and impedance data set; Performing interpolation and smoothing processing on the frequency and impedance data set to obtain the impedance spectrum requirement curve.

3. The PCB power integrity analysis method according to claim 1, wherein The performing multi-order resonance point matching processing on the impedance spectrum requirement curve and the decoupling capacitor library in the design data set to obtain a decoupling network configuration table includes: Performing capacitance impedance modeling on the decoupling capacitor library in the design data set to obtain a frequency-domain impedance data set of all capacitors; Using a preset particle swarm optimization algorithm to obtain an optimal capacitor combination set according to the frequency-domain impedance data set and the impedance spectrum requirement curve; Performing total impedance response calculation according to the optimal capacitor combination set to obtain a total impedance response set of all optimal capacitor combinations; Performing error analysis processing according to the total impedance response set and the impedance spectrum requirement curve to obtain an optimal capacitor configuration set; Generating the decoupling network configuration table according to the decoupling capacitor library and the optimal capacitor configuration set.

4. The PCB power integrity analysis method according to claim 3, wherein The performing power plane eddy current field simulation processing on the decoupling network configuration table and the stack structure in the design data set to obtain a current density distribution map includes: Performing electromagnetic modeling processing according to the stack structure in the design data set to obtain a coupling model; Performing power plane eddy current field simulation processing according to the optimal capacitor configuration set in the decoupling network configuration table and the coupling model to obtain a distribution matrix of the current in the power plane of the coupling model; Performing current density calculation according to the distribution matrix and the power plane to obtain a current density distribution data set of all regions; Generating the current density distribution map according to the power plane, a preset mapping method, and the current density distribution data set of all regions.

5. The PCB power integrity analysis method according to claim 1, wherein The performing thermal and electrical coupling analysis processing on the current density distribution map and the via data in the design data set to obtain a local temperature rise hot spot list includes: Construct a geometric model based on the via data in the design dataset to obtain a via distribution model; Perform a combined simulation of current density and heat conduction on the via distribution model according to the current density distribution dataset in the current density distribution map to obtain the heat power density distribution dataset for all regions; Perform superposition analysis based on the heat power density distribution dataset and the current density distribution dataset to obtain the temperature rise data for each region; Analyze and process the temperature rise data according to a preset temperature rise threshold to identify abnormal regions in the via distribution model where the temperature rise data exceeds the temperature rise threshold; Generate the local temperature rise hot spot list based on the abnormal regions; 6. The PCB power integrity analysis method according to claim 5, wherein The calculation process of the ground bounce noise transfer function for the local temperature rise hot spot list and the package model in the design dataset to obtain the noise coupling coefficient matrix includes: Perform circuit-mechanical coupling modeling on the package model in the design dataset to obtain the electrical and structural characteristic dataset of the package model; Extract the package model regions corresponding to the abnormal regions from the package model according to the local temperature rise hot spot list to obtain an abnormal package region set; Generate a ground bounce noise source and transmission path model based on the abnormal package region set and the electrical and structural characteristic dataset; Perform ground bounce noise transfer function calculation on the ground bounce noise source and transmission path model to obtain the noise coupling coefficients at different frequencies; Perform frequency domain analysis on the noise coupling coefficients to obtain the noise coupling coefficient matrix; 7. The PCB power integrity analysis method according to claim 1, wherein The frequency domain impedance superposition verification process for the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain the power integrity compliance report includes: Perform frequency domain impedance superposition based on the noise coupling coefficients in the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain the actual impedance response set for all frequency bands; Perform error analysis on the actual impedance response set and the impedance spectrum requirement curve to obtain the impedance error value for each frequency band; Perform evaluation based on the impedance error value to obtain the information on the out-of-specification frequency bands; Generate the power integrity compliance report based on the information on the out-of-specification frequency bands; 8. A PCB power integrity analysis device, characterized in that, The device includes: An impedance calculation module for obtaining the design dataset of the target power supply and performing frequency domain target impedance calculation on the design dataset to obtain the impedance spectrum requirement curve; A decoupling network module for performing multi-order resonance point matching on the impedance spectrum requirement curve and the decoupling capacitor bank in the design dataset to obtain a decoupling network configuration table; A current density module for performing power plane eddy current field simulation on the decoupling network configuration table and the stack-up structure in the design dataset to obtain a current density distribution map; A local temperature rise module for performing thermal and electrical coupling analysis on the current density distribution map and the via data in the design dataset to obtain a local temperature rise hot spot list; The coefficient matrix module is used to perform a ground bounce noise transfer function calculation process on the local temperature rise hot spot list and the package model in the design dataset to obtain a noise coupling coefficient matrix; The superposition verification module is used to perform a frequency-domain impedance superposition verification process on the noise coupling coefficient matrix and the impedance spectrum requirement curve to obtain a power integrity compliance report.

9. An electronic device, characterized in that, The electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the PCB power integrity analysis method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the PCB power integrity analysis method according to any one of claims 1 to 7 are implemented.

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