A method for implementing a Verilog-A model of field-effect transistor noise considering noise correlation

Abstract

The present invention discloses a method for implementing a Verilog-A model of field effect transistor noise considering noise correlation, and relates to the field of transistor noise technology. The method comprises: establishing a noise module of the intrinsic part of the transistor, wherein the noise module of the intrinsic part of the transistor is characterized by drain channel noise, gate induced noise, and the correlation between the two noises, converting the two related drain channel noise sources and gate induced noise sources into three unrelated noise sources, including a drain noise source, a gate noise source, and a gate correction noise source, and calculating the equivalent current of the gate-drain noise source, introducing frequency parameters and imaginary components, and embedding the noise module in the transistor Verilog-A model. The present invention breaks through the problem that the traditional modeling method based on Verilog-A is difficult to characterize the imaginary components of noise-related factors and their frequency correlation, and realizes the accurate characterization of noise correlation in the Verilog-A language.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor noise, and in particular to a method for realizing a Verilog-A model of field effect transistor noise considering noise correlation. Background Art

[0002] As a core component of microwave integrated circuits (MICs), transistors' noise characteristics directly impact circuit and system performance, especially for high-frequency applications. Therefore, establishing accurate microwave noise models is crucial for optimizing the noise characteristics of MICs. Verilog-A is a standard programming language for transistor models. Designers can define device behavior characteristics by writing model equations based on Verilog-A. Its powerful characterization capabilities have made this technology widely used in semiconductor device modeling. However, in practical noise modeling, the limitations of the existing Verilog-A programming syntax make it difficult to directly define noise correlations, particularly for imaginary and frequency-dependent terms, using equivalent circuit elements combined with analytical formulas, as is done in traditional commercial MIC simulation software. This results in a lack of an effective method for describing the correlations between internal noise sources when describing transistor behavior using Verilog-A. Therefore, research on transistor noise correlation characterization methods based on Verilog-A is urgently needed.

[0003] At present, domestic and foreign scholars have carried out a series of research work on transistor noise correlation modeling based on Verilog-A. In 2005, Colin C. McAndrew and others from NXP Semiconductors of the United States first used Verilog-A to partially realize the noise correlation characterization function in a compact model, introducing the non-correlation coefficient cbar The non-correlated and correlated components of the gate noise and drain noise of the MOSFET are described by the complex form of the correlation factor c. However, this method does not have the real part of the correlation factor c. cr The introduction of frequency components makes the model unable to characterize the frequency correlation of gate noise. At the same time, the method does not consider the power spectral density of the correlated noise. In 2006, Michael Schröter et al. from the Dresden University of Technology in Germany separated the correlated noise sources into correlated and uncorrelated parts based on the power spectral density matrix in Verilog-A and characterized them separately. However, this method incorrectly introduced ω in the matrix diagonalization process. 4term, resulting in an overestimation of the minimum noise figure prediction result under high frequency conditions. In 2010, Ramses van der Toorn et al. from the Delft University of Technology in the Netherlands characterized the noise correlation between the base and collector by defining a controlled current source based on a complex correlation coefficient, and introduced a coefficient jw for the size of the controlled current source with the help of the time derivative function (ddt), thereby achieving the characterization of the frequency correlation. However, this method introduces an additional imaginary component j to the real part of the controlled source, resulting in its failure to accurately characterize the noise correlation between the base and collector. In 2012, Anindya Mukherjee et al. from Infineon Technologies in Germany eliminated ω based on the research of Michael Schröter et al. 4 However, in order to simplify the modeling, this method fails to fully characterize the correlation between the base noise source and the collector noise source. In 2015, Anjan Chakravorty et al. from the Indian Institute of Technology decomposed the correlated noise source into correlated and uncorrelated parts by performing orthogonal decomposition on the power spectral density matrix, thereby achieving noise correlation modeling. However, in order to avoid introducing imaginary numbers in the characterization of the noise correlation part during the Verilog-A implementation, this method j ,Will cn Assuming it is a real number, the contribution of the imaginary part of the correlation is ignored, resulting in insufficient accuracy of this method in high-frequency application scenarios.

[0004] The aforementioned Verilog-A implementation methods all attempt to model transistor noise correlation to some extent. However, due to simplified assumptions about correlation factors and the difficulty in introducing frequency parameters and imaginary components into the noise correlation factor in Verilog-A, they still fail to accurately characterize the correlation of the noise power spectrum, resulting in inaccurate noise models for high-frequency applications. Comprehensively and accurately describing noise correlations in Verilog-A remains a pressing issue for high-precision microwave noise modeling.

[0005] Therefore, it is an urgent problem for those skilled in the art to propose a method for implementing a field effect transistor noise Verilog-A model that takes noise correlation into account to solve the difficulties existing in the prior art. Summary of the Invention

[0006] In view of this, the present invention provides a method for implementing a Verilog-A model of field-effect transistor noise that takes noise correlation into account. This method overcomes the problem that traditional Verilog-A-based modeling methods are difficult to characterize the imaginary components of noise-related factors and their frequency correlation, and realizes accurate characterization of noise correlation in the Verilog-A language.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A method for implementing a Verilog-A model of field effect transistor noise considering noise correlation includes the following steps:

[0009] S1. Characterize the intrinsic noise of the transistor by drain-channel noise, gate-induced noise, and the correlation between drain-channel noise and gate-induced noise.

[0010] Among them, the drain channel noise is generated by the equivalent noise current source connected in parallel to the drain terminal. Description, the gate induced noise is represented by the equivalent noise current source connected in parallel with the gate terminal Description, the correlation between drain channel noise and gate induced noise is described by the correlation noise factor C;

[0011] S2. Based on the transfer matrix theory, the two related drain channel noise sources and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources , thus obtaining the final noise module;

[0012] S3. Embed the final noise module into the transistor Verilog-A model. Combined with the predefined nonlinear model module in the transistor Verilog-A model, the equivalent noise current component is superimposed on the definition of the intrinsic key branch current to obtain a transistor noise Verilog-A model that integrates noise and nonlinear characteristics.

[0013] S4. Compare and verify the established transistor Verilog-A model that integrates noise and nonlinear characteristics with the noise definition elements in commercial integrated circuit simulation software.

[0014] Optionally, in S2, based on the transfer matrix theory, two related drain channel noise sources are and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources , so the specific content of the final noise module is:

[0015] S21: Drain noise source calculate;

[0016] S22: Gate noise source and gate-corrected noise sources calculate;

[0017] S23: Gate noise equivalent noise current and drain noise equivalent noise current Calculate and get the final noise module.

[0018] Optional, S21 for drain noise source The specific contents of the calculation are:

[0019] Drain noise sources The corresponding power spectral density is defined as , the expression is:

[0020] ;

[0021] in, is the thermodynamic temperature, is the Boltzmann constant, is the fitting parameter related to drain channel noise;

[0022] The power spectral density of the drain noise source Further calculations yield the drain noise source: The equivalent current , the expression is:

[0023] ;

[0024] in, is the drain noise source power spectral density, is the drain identification string, The white noise function in Verilog-A is used to calculate the equivalent noise current of a specific branch under noise power injection.

[0025] Optionally, the gate noise source in S22 and gate-corrected noise sources The specific contents of the calculation are:

[0026] S221: Gate noise sources The calculation is divided into the calculation of gate noise power spectrum and the calculation of the irrelevant correction term of gate noise source;

[0027] For gate noise power spectrum calculation, the gate noise power spectrum density is defined as , the expression is:

[0028] ;

[0029] in, is the thermodynamic temperature, is the Boltzmann constant, are the fitting parameters related to gate induced noise;

[0030] For the calculation of the irrelevant correction term of the gate noise source, the non-correlation coefficient is defined as To assist in correction , the expression is:

[0031] ;

[0032] in, is the correlation noise factor. When the noise sources are completely correlated, , the irrelevant part is zero. When the two noise sources are completely irrelevant, , indicating that the two noise sources are completely independent; is the square root operation function;

[0033] S222: Gate Correction Noise Source The calculation of is divided into real number calculation and imaginary number calculation;

[0034] For gate correction noise sources The real number calculation uses the frequency reading function $realfreq to correct the gate noise source The real part of the equivalent current ign_dn_tran introduces frequency dependence, and the expression is:

[0035] ;

[0036] in, is the coupling coefficient, $realfreq is the frequency reading function used to read the simulation frequency;

[0037] For gate correction noise sources The imaginary term of the gate correction noise source is calculated by using the time derivative function ddt to introduce the frequency correlation and imaginary number j into the imaginary part of the equivalent noise current ign_dn_tran. The expression is:

[0038] ;

[0039] Among them, ki is the coupling coefficient, and ddt() is the time derivative function used to derive the time domain.

[0040] Optionally, the gate noise equivalent noise current in S23 and drain noise equivalent noise current Calculation results show that the final noise module has the following content:

[0041] The equivalent noise currents of gate noise and drain noise are:

[0042] ;

[0043] ;

[0044] Among them, gi, si, and di are the node names of the gate, source, and drain respectively;

[0045] Thus the final noise module is obtained.

[0046] Optionally, in S3, the final noise module, i.e., the equivalent noise current of the gate noise and the drain noise, is embedded into the transistor Verilog-A model. Combined with the predefined nonlinear model module in the transistor Verilog-A model, the equivalent branch current of the gate noise is loaded between the gate and source nodes, and the equivalent branch current of the drain noise is loaded between the drain and source nodes. The final gate-source and drain-source branch currents are obtained as follows:

[0047] ;

[0048] ;

[0049] in, and are the equivalent noise currents of gate noise and drain noise respectively, and They are nonlinear gate-source current and nonlinear drain-source current models respectively;

[0050] Thus, a transistor noise Verilog-A model that integrates noise and nonlinear characteristics is obtained.

[0051] It can be seen from the above technical solution that, compared with the prior art, the present invention provides a method for implementing a Verilog-A model of field effect transistor noise taking into account noise correlation, which has the following beneficial effects:

[0052] The present invention combines the two related drain channel noise sources in the traditional noise model and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources By using the time domain derivative function, the imaginary term is introduced in the frequency domain, and the actual simulation frequency is extracted to accurately characterize the gate correction noise source. The real and imaginary components of the noise correlation factor are characterized by the real and imaginary parts, which breaks through the problem that the traditional Verilog-A based modeling method is difficult to characterize the imaginary components of the noise correlation factor and its frequency correlation, and realizes the accurate characterization of noise correlation in the Verilog-A language. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0054] Figure 1 A flow chart of a method for implementing a field effect transistor noise Verilog-A model taking into account noise correlation provided by the present invention;

[0055] Figure 2 The equivalent circuit topology diagram of the Pucel noise model provided by the present invention;

[0056] Figure 3 Schematic diagram of converting two related drain channel noise sources and gate induced noise sources provided by the present invention into three unrelated noise sources, wherein the three unrelated noise sources include a drain noise source, a gate noise source and a gate correction noise source;

[0057] Figure 4 The present invention provides V ds =1V simulation result comparison, 4a is the minimum noise coefficient NFmin Result comparison chart, 4b is the noise resistor Rn Result comparison chart, 4c is the optimal source reflection coefficient Sopt A comparison of the amplitude and phase results;

[0058] Figure 5 The present invention provides V ds =2V simulation result comparison, 5a is the minimum noise coefficient NFmin Result comparison chart, 5b is the noise resistor Rn Result comparison chart, 5c is the optimal source reflection coefficient Sopt A comparison of the amplitude and phase results. DETAILED DESCRIPTION

[0059] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0060] Reference Figure 1 As shown, the present invention discloses a method for implementing a Verilog-A model of field effect transistor noise considering noise correlation, comprising the following steps:

[0061] S1. Characterize the intrinsic noise of the transistor by drain-channel noise, gate-induced noise, and the correlation between drain-channel noise and gate-induced noise.

[0062] Among them, the drain channel noise is generated by the equivalent noise current source connected in parallel to the drain terminal. Description, the gate induced noise is represented by the equivalent noise current source connected in parallel with the gate terminal Description, the correlation between drain channel noise and gate induced noise is described by the correlation noise factor C;

[0063] S2. Based on the transfer matrix theory, the two related drain channel noise sources and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources , thus obtaining the final noise module;

[0064] S3. Embed the final noise module into the transistor Verilog-A model. Combined with the predefined nonlinear model module in the transistor Verilog-A model, the equivalent noise current component is superimposed on the definition of the intrinsic key branch current to obtain a transistor noise Verilog-A model that integrates noise and nonlinear characteristics.

[0065] S4. Compare and verify the established transistor Verilog-A model that integrates noise and nonlinear characteristics with the noise definition elements in commercial integrated circuit simulation software.

[0066] Furthermore, based on the transfer matrix theory, the two related drain channel noise sources are and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources , so the specific content of the final noise module is:

[0067] S21: Drain noise source calculate;

[0068] S22: Gate noise source and gate-corrected noise sources calculate;

[0069] S23: Gate noise equivalent noise current and drain noise equivalent noise current Calculate and get the final noise module.

[0070] Furthermore, S21 is a drain noise source. The specific contents of the calculation are:

[0071] Drain noise sources The corresponding power spectral density is defined as , the expression is:

[0072] ;

[0073] in, is the thermodynamic temperature, is the Boltzmann constant, is the fitting parameter related to drain channel noise;

[0074] The power spectral density of the drain noise source Further calculations yield the drain noise source: The equivalent current , the expression is:

[0075] ;

[0076] in, is the drain noise source power spectral density, is the drain identification string, The white noise function in Verilog-A is used to calculate the equivalent noise current of a specific branch under noise power injection.

[0077] Furthermore, the gate noise source in S22 and gate-corrected noise sources The specific contents of the calculation are:

[0078] S221: Gate noise sources The calculation is divided into the calculation of gate noise power spectrum and the calculation of the irrelevant correction term of gate noise source;

[0079] For gate noise power spectrum calculation, the gate noise power spectrum density is defined as , the expression is:

[0080] ;

[0081] in, is the thermodynamic temperature, is the Boltzmann constant, are the fitting parameters related to gate induced noise;

[0082] For the calculation of the irrelevant correction term of the gate noise source, the non-correlation coefficient is defined as To assist in correction , the expression is:

[0083] ;

[0084] in, is the correlation noise factor. When the noise sources are completely correlated, , the irrelevant part is zero. When the two noise sources are completely irrelevant, , indicating that the two noise sources are completely independent; is the square root operation function;

[0085] S222: Gate Correction Noise Source The calculation of is divided into real number calculation and imaginary number calculation;

[0086] For gate correction noise sources The real number calculation uses the frequency reading function $realfreq to correct the gate noise source The real part of the equivalent current ign_dn_tran introduces frequency dependence, and the expression is:

[0087] ;

[0088] in, is the coupling coefficient, $realfreq is the frequency reading function used to read the simulation frequency;

[0089] For gate correction noise sources The imaginary term of the gate correction noise source is calculated by using the time derivative function ddt to introduce the frequency correlation and imaginary number j into the imaginary part of the equivalent noise current ign_dn_tran. The expression is:

[0090] ;

[0091] Among them, ki is the coupling coefficient, and ddt() is the time derivative function used to derive the time domain.

[0092] Specifically, in S221, the non-correlation coefficient cbar Combined with the gate induced noise power spectrum density NoisePwrG, the gate noise source is calculated The equivalent current ign_tran is expressed as:

[0093]

[0094] in, cbar is the nonlinear correlation coefficient, NoisePwerG is the gate-induced noise power spectral density, "gate" is the gate identification string, and white_noise is the white noise function in Verilog-A, which is used to calculate the equivalent noise current of a specific branch under noise power injection;

[0095] The real and imaginary terms in S222 contain two coupling coefficients kr and ki, respectively, and their expressions are:

[0096]

[0097]

[0098] Among them, P is the drain channel noise fitting parameter, R is the gate induced noise fitting parameter, and are the imaginary and real parts of the relevant noise factor C, gm is the transconductance, Cgs is the gate-source capacitance, sqrt () is the square root operation function;

[0099] Combining the real and imaginary terms, the gate-corrected noise source is calculated as The equivalent current ign_dn_tran is expressed as:

[0100]

[0101] Among them, ign_dn_tran_r is the gate correction noise source The real part of the equivalent current, ign_dn_tran_i is the gate correction noise source The imaginary part of the equivalent current.

[0102] Furthermore, the gate noise equivalent noise current in S23 is and drain noise equivalent noise current Calculation results show that the final noise module has the following content:

[0103] The equivalent noise currents of gate noise and drain noise are:

[0104] ;

[0105] ;

[0106] Among them, gi, si, and di are the node names of the gate, source, and drain respectively;

[0107] Thus the final noise module is obtained.

[0108] Furthermore, in S3, the final noise module, i.e., the equivalent noise current of gate noise and drain noise, is embedded into the transistor Verilog-A model. Combined with the pre-defined nonlinear model module in the transistor Verilog-A model, the equivalent branch current of gate noise is loaded between the gate and source nodes, and the equivalent branch current of drain noise is loaded between the drain and source nodes. The final gate-source and drain-source branch currents are obtained as follows:

[0109] ;

[0110] ;

[0111] in, and are the equivalent noise currents of gate noise and drain noise respectively, and They are nonlinear gate-source current and nonlinear drain-source current models respectively;

[0112] Thus, a transistor noise Verilog-A model that integrates noise and nonlinear characteristics is obtained.

[0113] In a specific embodiment, the following contents are included: (1) Taking the Pucel noise model as an example, the equivalent circuit model topology of the Pucel noise model is as follows: Figure 2 As shown, in Figure 2 In the figure, the intrinsic noise of the transistor is characterized by the drain channel noise, gate induced noise and the correlation between the two noises. The drain channel noise is represented by the equivalent noise current source connected in parallel to the drain terminal. The gate induced noise is represented by the equivalent noise current source connected in parallel with the gate terminal. representation.

[0114] (2) Considering that the correlation between two equivalent voltage / current sources cannot be directly defined based on analytical formulas in Verilog-A, the two related drain channel noise sources are and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source , Gate noise source and gate-corrected noise sources , the conversion process is as follows Figure 3 shown.

[0115] ① For drain noise sources The specific contents of the calculation are:

[0116] Drain noise sources The corresponding power spectral density is defined as , the expression is:

[0117] ;

[0118] in, is the thermodynamic temperature, is the Boltzmann constant, is the fitting parameter related to drain channel noise;

[0119] The power spectral density of the drain noise source Further calculations yield the drain noise source: The equivalent current , the expression is:

[0120] ;

[0121] in, is the drain noise source power spectral density, is the drain identification string, The white noise function in Verilog-A is used to calculate the equivalent noise current of a specific branch under noise power injection.

[0122] ② Gate noise source and gate-corrected noise sources The specific contents of the calculation are:

[0123] Gate noise sources The calculation is divided into the calculation of gate noise power spectrum and the calculation of the irrelevant correction term of gate noise source;

[0124] For gate noise power spectrum calculation, the gate noise power spectrum density is defined as , the expression is:

[0125] ;

[0126] in, is the thermodynamic temperature, is the Boltzmann constant, are the fitting parameters related to gate induced noise;

[0127] For the calculation of the irrelevant correction term of the gate noise source, the non-correlation coefficient is defined as To assist in correction , the expression is:

[0128] ;

[0129] in, is the correlation noise factor. When the noise sources are completely correlated, , the irrelevant part is zero. When the two noise sources are completely irrelevant, , indicating that the two noise sources are completely independent; is the square root operation function;

[0130] By the non-correlation coefficient Combined with gate induced noise power spectral density , the gate noise source is calculated The equivalent current , the expression is:

[0131] ;

[0132] in, is the nonlinear correlation coefficient, is the gate induced noise power spectral density, is the gate identification string, The white noise function in Verilog-A is used to calculate the equivalent noise current of a specific branch under noise power injection;

[0133] Gate Correction Noise Sources The calculation of is divided into real number calculation and imaginary number calculation;

[0134] The real term and imaginary term contain two coupling coefficients respectively and , the expressions are:

[0135] ;

[0136] ;

[0137] in, is the drain channel noise fitting parameter, is the gate induced noise fitting parameter, and Correlation noise factors The imaginary and real parts of is the transconductance, is the gate-source capacitance, is the square root operation function;

[0138] For gate correction noise sources The real number calculation uses the frequency reading function $realfreq to correct the gate noise source The real part of the equivalent current ign_dn_tran introduces frequency dependence, and the expression is:

[0139] ;

[0140] in, is the coupling coefficient, $realfreq is the frequency reading function used to read the simulation frequency;

[0141] For gate correction noise sources The imaginary term of the gate correction noise source is calculated by using the time derivative function ddt to introduce the frequency correlation and imaginary number j into the imaginary part of the equivalent noise current ign_dn_tran. The expression is:

[0142] ;

[0143] Among them, ki is the coupling coefficient, ddt() is the time derivative function used to derive the time domain;

[0144] Combining the real and imaginary terms, the gate-corrected noise source is calculated as The equivalent current ign_dn_tran is expressed as:

[0145] ;

[0146] Among them, ign_dn_tran_r is the gate correction noise source The real part of the equivalent current, ign_dn_tran_i is the gate correction noise source The imaginary part of the equivalent current.

[0147] ③Equivalent noise current for gate noise and drain noise equivalent noise current Calculation results show that the final noise module has the following content:

[0148] The equivalent noise currents of gate noise and drain noise are:

[0149] ;

[0150] ;

[0151] Among them, gi, si, and di are the node names of the gate, source, and drain respectively;

[0152] Thus the final noise module is obtained.

[0153] (3) Combined with the pre-defined nonlinear model module in the transistor Verilog-A model, by superimposing the equivalent noise current component in the definition of the intrinsic key branch current, a transistor noise Verilog-A model that integrates noise and nonlinear characteristics can be obtained. Figure 3 In the equivalent model topology shown, the equivalent branch current of gate noise is loaded between the gate and source nodes, and the equivalent branch current of drain noise is loaded between the drain and source nodes. The final gate-source and drain-source branch currents are:

[0154] ;

[0155] ;

[0156] in, and are the equivalent noise currents of gate noise and drain noise respectively, and They are nonlinear gate-source current and nonlinear drain-source current models respectively;

[0157] Thus, a transistor noise Verilog-A model that integrates noise and nonlinear characteristics is obtained.

[0158] In another specific embodiment, a transistor noise Verilog-A model that combines noise and nonlinear characteristics is verified.

[0159] To verify the effectiveness of the proposed method, comparative experiments were conducted using different control groups. The Pucel noise model parameters used in each group were extracted from a 4×25μm GaAs pHEMT device. The first group corresponded to the noise module established in the present invention, which considers transistor noise correlation; the second group corresponded to a noise model established using the traditional Verilog-A noise modeling method, which does not consider noise correlation; and the third group corresponded to a noise model established using a noise equivalent circuit topology combined with noise correlation controls implemented in commercial integrated circuit simulation software.

[0160] The noise characteristics of each group under different bias conditions were compared and verified, where the gate-source bias voltage range is V gs =0.6~0.8V (step: 0.2V), the drain-source bias voltage range is V ds =1~2V (step: 1V), frequency range (Frequency) is 20~40GHz (step: 0.1GHz). Verification parameters include minimum noise figure NFmin , noise resistance Rn , optimal source reflection coefficient Sopt The amplitude and phase of . The verification and comparison results are as follows Figure 4 , Figure 5 As shown. Among them, Figure 4 for V ds =1V simulation result comparison, 4a is the minimum noise coefficient NFmin Result comparison chart, 4b is the noise resistor Rn Result comparison chart, 4c is the optimal source reflection coefficient SoptA comparison of amplitude and phase results; Group A is the noise simulation results of the first group of models; Group B is the noise simulation results of the second group of models; Group C is the noise simulation results of the third group of models. Figure 5 for V ds =2V simulation result comparison, 5a is the minimum noise coefficient NFmin Result comparison chart, 5b is the noise resistor Rn Result comparison chart, 5c is the optimal source reflection coefficient Sopt A comparison of amplitude and phase results; Group A is the noise simulation results of the first group of models; Group B is the noise simulation results of the second group of models; Group C is the noise simulation results of the third group of models.

[0161] In order to evaluate the impact of noise correlation on the noise modeling accuracy, the accuracy of each noise parameter of the group B model in the four groups of bias conditions is calculated in the range of 20~40 GHz. The results are shown in Table 1, where bias I: V gs =0.6V, V ds =1V; Bias II: V gs =0.8V, V ds =1V; Bias III: V gs =0.6V, V ds =2V and bias IV: V gs =0.8V, V ds =2V.

[0162] Table 1 Noise model error

[0163]

[0164] ;

[0165] in, is the model simulation value; is the reference data (here the simulation results of group C are used as the reference data); N It is the serial number of each frequency point in the frequency range.

[0166] Depend on Figure 5 As shown in Table 1, the noise modeling simulation results without considering the noise correlation have a larger deviation than those with considering the noise correlation, among which the error of the minimum noise coefficient is as high as 49.50%, and the error of the optimal source reflection coefficient is SoptThe maximum amplitude error reached 14.79%, and the minimum phase accuracy was only 29.35%, indicating that ignoring noise correlation in noise modeling will lead to significant errors. Therefore, considering noise correlation is a key technology for achieving accurate noise modeling. The simulation results of the noise model established based on the present invention are basically consistent with the simulation results of the noise model established in commercial integrated circuit simulation software using equivalent circuit topology and noise correlation definition elements, verifying the effectiveness and accuracy of the present invention.

[0167] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for implementing a Verilog-A model of field effect transistor noise considering noise correlation, characterized in that: The following steps are involved: S1. Characterize the intrinsic noise of the transistor by drain-channel noise, gate-induced noise, and the correlation between drain-channel noise and gate-induced noise. Among them, the drain channel noise is generated by the equivalent noise current source connected in parallel to the drain terminal. Description, the gate induced noise is represented by the equivalent noise current source connected in parallel with the gate terminal Description, the correlation between drain channel noise and gate induced noise is described by the correlation noise factor C; S2. Based on the transfer matrix theory, the two related drain channel noise sources and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source Gate noise sources and gate-corrected noise sources Thus the final noise module is obtained; S3. Embed the final noise module into the transistor Verilog-A model. Combined with the predefined nonlinear model module in the transistor Verilog-A model, the equivalent noise current component is superimposed on the definition of the intrinsic key branch current to obtain a transistor noise Verilog-A model that integrates noise and nonlinear characteristics. S4. Compare and verify the transistor Verilog-A model that integrates noise and nonlinear characteristics with the noise definition elements in commercial integrated circuit simulation software; In S2, based on the transfer matrix theory, the two related drain channel noise sources are and gate induced noise sources Converted to three unrelated noise sources, namely the drain noise source Gate noise sources and gate-corrected noise sources The specific content of the final noise module is: S21: Drain noise source calculate; S22: Gate noise source and gate-corrected noise sources calculate; S23: Gate noise equivalent noise current I noise (gi, si) and drain noise equivalent noise current I noise (di,si) calculation to obtain the final noise module; S21 drain noise source The specific contents of the calculation are: Drain noise sources The corresponding power spectrum density is defined as NoisePwrD, and the expression is: NoisePwrD=4*k*T*gm*P; Where T is the thermodynamic temperature, k is the Boltzmann constant, and P is the fitting parameter related to the drain channel noise; The drain noise source is further calculated from the drain noise source power spectral density NoisePwrD The equivalent current idn_tran is expressed as: idn_tran=white_noise(NoisePwTD,"drain"); Where NoisePwrD is the power spectral density of the drain noise source, "drain" is the drain identifier string, and white_noise is the white noise function in Verilog-A, which is used to calculate the equivalent noise current of a specific branch under noise power injection. Gate noise source in S22 and gate-corrected noise sources The specific contents of the calculation are: S221: Gate noise sources The calculation is divided into the calculation of gate noise power spectrum and the calculation of the irrelevant correction term of gate noise source; For gate noise power spectrum calculation, the gate noise power spectrum density is defined as NoisePwrG, and the expression is: NoisePwrG=Cgs 2 *4*k*T*R / gm; Where T is the thermodynamic temperature, k is the Boltzmann constant, and R is the fitting parameter related to gate induced noise; For the calculation of the irrelevant correction term of the gate noise source, the non-correlation coefficient cbar is defined to assist in correcting NoisePwrG. The expression is: cbar=sqrt(1.0-C 2 ); Where C is the correlation noise factor. When the noise sources are completely correlated, cbar = 0, and the irrelevant part is zero. When the two noise sources are completely unrelated, cbar = 1, indicating that the two noise sources are completely independent. sqrt() is the square root operation function. S222: Gate Correction Noise Source The calculation of is divided into real number calculation and imaginary number calculation; For gate correction noise sources The real number calculation uses the frequency reading function $realfreq to correct the gate noise source The real part of the equivalent current ign_dn_tran introduces frequency dependence, and the expression is: ign_dn_tran_r=kr*2*π*$realfreq*idn_tran; Wherein, kr is the coupling coefficient, $realfreq is the frequency reading function used to read the simulation frequency; For gate correction noise sources The imaginary term of the gate correction noise source is calculated by using the time derivative function ddt to introduce the frequency correlation and imaginary number j into the imaginary part of the equivalent noise current ign_dn_tran. The expression is: ign_dn_tran_i=ki*ddt(idnn_tran); Among them, ki is the coupling coefficient, and ddt() is the time derivative function used to derive the time domain.

2. The method for implementing a field effect transistor noise Verilog-A model considering noise correlation according to claim 1, characterized in that: The gate noise equivalent noise current I in S23 noise (gi,si) and drain noise equivalent noise current I noise (gi,si) calculation, the specific content of the final noise module is: The equivalent noise currents of gate noise and drain noise are: I noise (gi,si)=ign_tran+igndntran; AND noise (di,si)=idn_tran; Among them, gi, si, and di are the node names of the gate, source, and drain respectively; Thus the final noise module is obtained.

3. The method for implementing a field effect transistor noise Verilog-A model considering noise correlation according to claim 1, characterized in that: In S3, the final noise module, i.e., the equivalent noise current of gate noise and drain noise, is embedded into the transistor Verilog-A model. Combined with the pre-defined nonlinear model module in the transistor Verilog-A model, the equivalent branch current of gate noise is loaded between the gate and source nodes, and the equivalent branch current of drain noise is loaded between the drain and source nodes. The final gate-source and drain-source branch currents are obtained as follows: I(give,say)=I noise (give,say)+I gs_nolinear ; Among them, I noise (gi,si) and I noise (di, si) are the equivalent noise currents of gate noise and drain noise respectively, I gs_nolinear and I ds_nolinear They are nonlinear gate-source current and nonlinear drain-source current models respectively; Thus, a transistor noise Verilog-A model that integrates noise and nonlinear characteristics is obtained.

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