SoC chip GPIO interface verification method based on bare computer system-level software simulation

Abstract

The invention discloses an SoC chip GPIO (General Purpose Input / Output) interface verification method based on bare computer system-level software simulation, which relates to the technical field of chip testing and comprises the following steps of: configuring an input / output mode and an electrical characteristic of a pin in a GPIO interface according to the function type of the GPIO interface to be verified; generating a test excitation signal and sending the test excitation signal to a pin configured to be in an output mode; collecting a response state of the GPIO interface after receiving the test excitation signal, and obtaining a function verification result according to the response state and a preset criterion; and outputting a function verification result. According to the SoC chip GPIO interface verification method based on bare computer system-level software simulation, function verification of the GPIO interface can be carried out under the condition that a virtual peripheral model does not need to be built, the function verification efficiency of the GPIO interface can be improved, the simulation time needed by function verification is shortened, the GPIO interface verification environment is simplified, and the function verification cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a method for verifying the GPIO interface of an SoC chip based on bare-metal system-level software simulation. Background Art

[0002] Existing SoC (System on Chip) chips usually include a core, a storage system, peripheral interfaces, a communication bus, an interrupt module, and a clock module. The peripheral interfaces include high-speed peripherals and low-speed peripherals. The GPIO (General-purpose input / output) interface, as a low-speed peripheral interface, is a way for the SoC chip to interact with the external environment and can be configured as an input or output mode. In the input mode, the GPIO interface can read valid signals from external devices such as sensors and buttons; in the output mode, the GPIO interface can control external devices such as LED display lights. Moreover, the GPIO interface can also be configured as a specific function through an internal multiplexing mechanism, such as the pins of interfaces like SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), and USB (Universal Serial Bus). Therefore, the GPIO interface is a very basic and important part of the SoC chip interface. During the chip R & D process, it is generally necessary to fully verify the functions of the GPIO interface of the SoC chip to ensure the correctness of the final chip product.

[0003] The system-level verification of the SoC chip mainly focuses on the input and output of each component, and focuses on verifying the signal interaction between different subsystems and implementing use cases closer to the actual scenario. Currently, the bare-metal system-level software simulation of the GPIO interface of the SoC chip is usually verified by constructing a virtual peripheral model that conforms to the interface transmission behavior to form the communication between the SoC chip and the peripheral. Specifically, by configuring the transmission direction and mode of the GPIO interface of the SoC chip to be tested, and using the virtual peripheral model to match the transmission characteristics of the GPIO interface, the data transmission between the master and slave devices of the chip and the virtual peripheral is realized. However, although the existing method can comprehensively simulate and test the functions of the GPIO interface, this method requires constructing a virtual peripheral model to complete the communication between the master and slave devices, which increases the simulation time of the communication between the SoC chip to be tested and the virtual peripheral model, and the verification efficiency is low. For the bare-metal system-level software simulation of the GPIO interface of a large SoC chip, due to the increase in the number of GPIO interfaces, the software simulation time required for the communication between the master and slave devices also increases, and the verification efficiency will be further reduced, and the interface verification environment is also relatively complex. Summary of the Invention

[0004] To solve some or all of the technical problems existing in the above-mentioned prior art, the present invention provides a method for verifying the GPIO interface of an SoC chip based on bare-metal system-level software simulation.

[0005] The technical solution of the present invention is as follows:

[0006] Provided is a method for verifying the GPIO interface of an SoC chip based on bare-metal system-level software simulation, the method comprising:

[0007] According to the function type of the GPIO interface to be verified, configure the input / output mode and electrical characteristics of the pins in the GPIO interface;

[0008] Generate a test excitation signal and send it to the pins configured in the output mode;

[0009] Collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion;

[0010] Output the function verification result.

[0011] In some optional embodiments, the function type includes at least one of: basic transmission function, interrupt response function, and debounce circuit function.

[0012] In some optional embodiments, when the function type of the GPIO interface to be verified is the basic transmission function, the configuring the input / output mode and electrical characteristics of the pins in the GPIO interface, generating a test excitation signal and sending it to the pins configured in the output mode, collecting the response status of the GPIO interface after receiving the test excitation signal, and obtaining the function verification result according to the response status and the preset criterion, includes:

[0013] Configure half of the pins in the GPIO interface in the output mode, configure the remaining half of the pins in the GPIO interface in the input mode, and pair and connect the pins configured in the output mode and the pins configured in the input mode so that a pin configured in the output mode is connected to a pin configured in the input mode to form a data transmission link;

[0014] Generate a test excitation signal and send it to the pins configured in the output mode so that the pins output a specified level value;

[0015] Read the level values of the pins configured in the input mode respectively. If the level value of the pin configured in the input mode is the same as the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is normal. If the level value of the pin configured in the input mode is different from the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is abnormal.

[0016] In some alternative embodiments, the pins with odd positions in the GPIO interface are configured in output mode, the pins with even positions in the GPIO interface are configured in input mode, and the pins configured in output mode are paired and connected with the adjacent pins configured in input mode.

[0017] In some alternative embodiments, first generate a first test excitation signal and send it to the pins configured in output mode to make the pins output one of high level and low level, and then generate a second test excitation signal and send it to the pins configured in output mode to make the pins output the other of high level and low level.

[0018] In some alternative embodiments, when the GPIO interface function type to be verified is the interrupt response function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in output mode, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion, including:

[0019] Configure several pins in the GPIO interface as interrupt ports and set the interrupt trigger condition;

[0020] Generate an interrupt trigger signal and send it to the pins configured as interrupt ports;

[0021] Collect the response status of the GPIO interface after receiving the interrupt trigger signal. If the GPIO interface enters the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is normal. If the GPIO interface does not enter the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is abnormal.

[0022] In some alternative embodiments, the interrupt trigger condition includes one of high level trigger, low level trigger, rising edge trigger, and falling edge trigger.

[0023] In some alternative embodiments, when the GPIO interface function type to be verified is the debounce circuit function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in output mode, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion, including:

[0024] Configure at least four pins in the GPIO interface as interrupt ports and set the interrupt trigger condition as high level trigger;

[0025] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal greater than two pulse widths of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt after receiving the high-level signal and enters a preset interrupt handling program, it is determined that the debounce circuit has a normal recognition function for stable long pulses; otherwise, it is determined that the debounce circuit has an abnormal recognition function for stable long pulses.

[0026] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal less than one pulse width of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit has a normal suppression function for short pulse noise; otherwise, it is determined that the debounce circuit has an abnormal suppression function for short pulse noise.

[0027] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and span two rising edges of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt after receiving the high-level signal and enters a preset interrupt handling program, it is determined that the debounce circuit has a normal fault tolerance determination function for signals spanning two clock edges; otherwise, it is determined that the debounce circuit has an abnormal fault tolerance determination function for signals spanning two clock edges.

[0028] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and span only one rising edge of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit has a normal filtering function for discontinuous sampling signals; otherwise, it is determined that the debounce circuit has an abnormal filtering function for discontinuous sampling signals.

[0029] In some alternative embodiments, the method further includes:

[0030] Construct a test excitation module, which is used to connect to the pins configured as output mode in the GPIO interface and generate and send test excitation signals to the pins configured as output mode.

[0031] In some alternative embodiments, the method further includes:

[0032] Construct a result collection and verification module, which is used to connect to the pins in the GPIO interface, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain and output the function verification result according to the response status and the preset criteria.

[0033] The main advantages of the technical solution of the present invention are as follows:

[0034] The GPIO interface verification method of the SoC chip based on bare-metal system-level software simulation of the present invention constructs a data transmission link between the GPIO interface pins by setting the input / output mode and electrical characteristics of the pins in the GPIO interface, inputs a test excitation signal to the GPIO pins, and verifies the function of the GPIO interface according to whether the response status of the GPIO interface after receiving the test excitation signal meets the expectation. It can complete the master-slave device communication for GPIO interface function verification without constructing a virtual peripheral model, improve the function verification efficiency of the GPIO interface, reduce the simulation time required for function verification, simplify the GPIO interface verification environment, and reduce the function verification cost. Description of the Drawings

[0035] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1 It is a schematic flowchart of a GPIO interface verification method for an SoC chip based on bare-metal system-level software simulation provided by an embodiment of the present invention;

[0037] Figure 2 It is a schematic diagram of the principle of the GPIO interface verification method for an SoC chip based on bare-metal system-level software simulation provided by an embodiment of the present invention;

[0038] Figure 3 It is a schematic diagram of the principle when the basic transmission function verification is performed for the GPIO interface verification method for an SoC chip based on bare-metal system-level software simulation provided by an embodiment of the present invention;

[0039] Figure 4 It is a schematic diagram of the principle when the interrupt response function verification is performed for the GPIO interface verification method for an SoC chip based on bare-metal system-level software simulation provided by an embodiment of the present invention;

[0040] Figure 5 It is a schematic diagram of the principle when the debounce circuit function verification is performed for the GPIO interface verification method for an SoC chip based on bare-metal system-level software simulation provided by an embodiment of the present invention. Detailed Embodiments

[0041] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0042] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the drawings.

[0043] Referring to Figure 1-2 , an SoC chip GPIO interface verification method based on bare-metal system-level software simulation is provided in an embodiment of the present invention. The method includes the following steps:

[0044] Step 1, configure the input / output mode and electrical characteristics of the pins in the GPIO interface according to the GPIO interface function type to be verified;

[0045] In the embodiment of the present invention, according to actual requirements, determine the GPIO interface function type of the SoC chip to be verified, and configure the input / output mode and electrical characteristics of the pins in the GPIO interface according to the GPIO interface function type to be verified.

[0046] It should be noted that when configuring the pins in the GPIO interface, only the pins required to be used need to be configured according to actual requirements.

[0047] Step 2, generate a test excitation signal and send it to the pins configured in the output mode;

[0048] In the embodiment of the present invention, generate a test excitation signal and send it to the pins configured in the output mode according to the GPIO interface function type to be verified.

[0049] In the embodiment of the present invention, a GPIO verification environment can be constructed, and the constructed GPIO verification environment can be used to generate a test excitation signal.

[0050] Step 3, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion;

[0051] In the embodiment of the present invention, according to the GPIO interface function type of the SoC chip to be verified, a corresponding function verification criterion is preset in advance. After the GPIO interface receives the test excitation signal, collect the response status of the GPIO interface after receiving the test excitation signal, and perform function verification according to the response status and the preset criterion to obtain the function verification result.

[0052] Step 4, output the function verification result.

[0053] The GPIO interface verification method for SoC chips based on bare-metal system-level software simulation provided by the embodiments of the present invention can verify the function of the GPIO interface by setting the input / output mode and electrical characteristics of the pins in the GPIO interface, constructing a data transmission link between the GPIO interface pins, inputting a test excitation signal to the GPIO pins, and determining whether the response state of the GPIO interface after receiving the test excitation signal meets the expectations. It can complete the master-slave device communication for GPIO interface function verification without constructing a virtual peripheral model, improve the function verification efficiency of the GPIO interface, reduce the simulation time required for function verification, simplify the GPIO interface verification environment, and reduce the function verification cost.

[0054] Further, in the embodiments of the present invention, the GPIO interface function types include at least one of basic transmission function, interrupt response function, and debounce circuit function.

[0055] Reference Figure 3 , further, in the embodiments of the present invention, when the GPIO interface function type to be verified is the basic transmission function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in the output mode, collect the response state of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response state and the preset criterion. Specifically, it includes the following steps:

[0056] Configure half of the pins in the GPIO interface in the output mode, configure the remaining half of the pins in the GPIO interface in the input mode, and pair and connect the pins configured in the output mode and the pins configured in the input mode so that a pin configured in the output mode is connected to a pin configured in the input mode to form a data transmission link;

[0057] Generate a test excitation signal and send it to the pins configured in the output mode to make the pins output a specified level value;

[0058] Read the level values of the pins configured in the input mode respectively. If the level value of the pin configured in the input mode is the same as the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is normal. If the level value of the pin configured in the input mode is different from the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is abnormal.

[0059] In the embodiments of the present invention, the basic transmission function verification of the GPIO interface can be achieved by adopting the above method.

[0060] Further, in the embodiments of the present invention, in order to improve the verification efficiency of the basic transmission function verification of the GPIO interface and reduce verification operations, the pins with odd numbers in the GPIO interface are configured in the output mode, the pins with even numbers in the GPIO interface are configured in the input mode, and the pins configured in the output mode are paired and connected with the adjacent pins configured in the input mode.

[0061] Specifically, taking the GPIO interface including 32 pins numbered 0 to 31 as an example, the pins with even numbers are configured in the output mode, the pins with odd numbers are configured in the input mode, and the pin numbered i is paired and connected with the pin numbered i + 1 to form a data transmission link, where i = 0, 2, 4......30.

[0062] In the embodiments of the present invention, by adopting the above pin configuration method and pairing connection method, it is convenient to perform the pairing connection of pins, thereby improving the verification efficiency.

[0063] Further, in the embodiments of the present invention, in order to fully verify the basic transmission function of the GPIO interface and ensure the accuracy and reliability of the verification results, when performing the basic transmission function verification, a first test excitation signal is first generated and sent to the pins configured in the output mode to make the pins output one of the high level and the low level, and then the level values of the pins configured in the input mode are respectively read. If the level value of the pin configured in the input mode is the same as the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is normal; if the level value of the pin configured in the input mode is different from the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is abnormal; then a second test excitation signal is generated and sent to the pins configured in the output mode to make the pins output the other of the high level and the low level, and then the level values of the pins configured in the input mode are respectively read. If the level value of the pin configured in the input mode is the same as the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is normal; if the level value of the pin configured in the input mode is different from the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is abnormal.

[0064] Reference Figure 4 Furthermore, in the embodiments of the present invention, when the function type of the GPIO interface to be verified is the interrupt response function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in the output mode, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion, which specifically includes the following steps:

[0065] Configure several pins in the GPIO interface as interrupt ports and set the interrupt trigger conditions;

[0066] Generate an interrupt trigger signal and send it to the pins configured as interrupt ports;

[0067] Collect the response status of the GPIO interface after receiving the interrupt trigger signal. If the GPIO interface enters the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is normal. If the GPIO interface does not enter the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is abnormal.

[0068] In the embodiment of the present invention, when verifying the interrupt response function, the pins configured as interrupt ports can be selected according to the actual situation. For example, the first to eighth pins in the GPIO interface are configured as interrupt ports.

[0069] In the embodiment of the present invention, the above method can be used to verify the interrupt response function of the GPIO interface.

[0070] Further, in the embodiment of the present invention, the interrupt trigger conditions include one of high-level trigger, low-level trigger, rising-edge trigger, and falling-edge trigger.

[0071] Further, in the embodiment of the present invention, in order to fully verify the interrupt response function of the GPIO interface and ensure the accuracy and reliability of the verification result, when verifying the interrupt response function, the interrupt response function is verified respectively for the high-level trigger condition, low-level trigger condition, rising-edge trigger condition, and falling-edge trigger condition.

[0072] Reference Figure 5 , further, in the embodiment of the present invention, when the function type of the GPIO interface to be verified is the debounce circuit function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in the output mode, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion, which specifically includes the following steps:

[0073] Configure at least four pins in the GPIO interface as interrupt ports and set the interrupt trigger condition to high-level trigger;

[0074] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal greater than two pulse widths of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt and enters a preset interrupt handling program after receiving the high-level signal, it is determined that the debounce circuit has a normal recognition function for stable long pulses; otherwise, it is determined that the debounce circuit has an abnormal recognition function for stable long pulses.

[0075] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal less than one pulse width of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit has a normal suppression function for short pulse noise; otherwise, it is determined that the debounce circuit has an abnormal suppression function for short pulse noise.

[0076] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and span two rising edges of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt and enters a preset interrupt handling program after receiving the high-level signal, it is determined that the debounce circuit has a normal fault tolerance determination function for signals crossing two clock edges; otherwise, it is determined that the debounce circuit has an abnormal fault tolerance determination function for signals crossing two clock edges.

[0077] Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and only span one rising edge of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit has a normal filtering function for non-continuous sampling signals; otherwise, it is determined that the debounce circuit has an abnormal filtering function for non-continuous sampling signals.

[0078] In the embodiments of the present invention, when verifying the function of the debounce circuit, the pins configured as interrupt ports can be selected according to the actual situation. For example, the first to fourth pins in the GPIO interface are configured as interrupt ports.

[0079] In the embodiments of the present invention, the above method can be used to fully verify the function of the debounce circuit of the GPIO interface.

[0080] Furthermore, in the embodiments of the present invention, in order to facilitate the verification of the GPIO interface of the SoC chip, a GPIO verification environment including a test stimulus module and a result collection and verification module is constructed. The constructed GPIO verification environment is used to generate test stimulus signals and collect the response status of the GPIO interface after receiving the test stimulus signals, and obtain and output the functional verification result according to the response status and the preset criteria.

[0081] Specifically, in the embodiments of the present invention, the test stimulus module is used to connect to the pins configured as the output mode in the GPIO interface, and is used to generate test stimulus signals and send them to the pins configured as the output mode; the result collection and verification module is used to connect to the pins in the GPIO interface, and is used to collect the response status of the GPIO interface after receiving the test stimulus signals, and obtain and output the functional verification result according to the response status and the preset criteria.

[0082] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. In addition, in this article, "front", "rear", "left", "right", "upper" and "lower" are all referenced based on the placement state shown in the drawings.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A verification method for the GPIO interface of an SoC chip based on bare-metal system-level software simulation, characterized in that Including: Configuring the input / output mode and electrical characteristics of the pins in the GPIO interface according to the type of GPIO interface function to be verified; Generating a test excitation signal and sending it to the pins configured in the output mode; Collecting the response status of the GPIO interface after receiving the test excitation signal, and obtaining the function verification result according to the response status and the preset criterion; Outputting the function verification result.

2. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 1, characterized in that The function types include at least one of: basic transmission function, interrupt response function, and debounce circuit function.

3. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 2, wherein When the function type of the GPIO interface to be verified is the basic transmission function, the configuring the input / output mode and electrical characteristics of the pins in the GPIO interface, generating a test excitation signal and sending it to the pins configured in the output mode, collecting the response status of the GPIO interface after receiving the test excitation signal, and obtaining the function verification result according to the response status and the preset criterion include: Configuring half of the pins in the GPIO interface in the output mode, configuring the remaining half of the pins in the GPIO interface in the input mode, and pairing and connecting the pins configured in the output mode and the pins configured in the input mode so that a pin configured in the output mode is connected to a pin configured in the input mode to form a data transmission link; Generating a test excitation signal and sending it to the pins configured in the output mode so that the pins output a specified level value; Reading the level values of the pins configured in the input mode respectively. If the level value of the pin configured in the input mode is the same as the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is normal. If the level value of the pin configured in the input mode is different from the level value output by the pin configured in the output mode paired with it, it is determined that the transmission function of the current two pins is abnormal.

4. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 3, wherein Configuring the pins with odd positions in the GPIO interface in the output mode, configuring the pins with even positions in the GPIO interface in the input mode, and pairing and connecting the pins configured in the output mode and the adjacent pins configured in the input mode.

5. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 3, wherein First generating a first test excitation signal and sending it to the pins configured in the output mode so that the pins output one of high level and low level, and then generating a second test excitation signal and sending it to the pins configured in the output mode so that the pins output the other of high level and low level.

6. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 2, characterized in that When the function type of the GPIO interface to be verified is the interrupt response function, the configuring the input / output mode and electrical characteristics of the pins in the GPIO interface, generating a test excitation signal and sending it to the pins configured in the output mode, collecting the response status of the GPIO interface after receiving the test excitation signal, and obtaining the function verification result according to the response status and the preset criterion include: Configuring several pins in the GPIO interface as interrupt ports and setting the interrupt trigger condition; Generating an interrupt trigger signal and sending it to the pins configured as interrupt ports; Collect the response status of the GPIO interface after receiving the interrupt trigger signal. If the GPIO interface enters the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is normal. If the GPIO interface does not enter the preset interrupt handling program after receiving the interrupt trigger signal, it is determined that the interrupt response function is abnormal.

7. The method for verifying the GPIO interface of the SoC chip based on bare-metal system-level software simulation according to claim 6, wherein The interrupt trigger conditions include one of high-level trigger, low-level trigger, rising-edge trigger, and falling-edge trigger.

8. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to claim 2, wherein When the GPIO interface function type to be verified is the debounce circuit function, configure the input / output mode and electrical characteristics of the pins in the GPIO interface, generate a test excitation signal and send it to the pins configured in the output mode, collect the response status of the GPIO interface after receiving the test excitation signal, and obtain the function verification result according to the response status and the preset criterion, including: Configure at least four pins in the GPIO interface as interrupt ports, and set the interrupt trigger condition to high-level trigger; Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal greater than two pulse widths of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt and enters the preset interrupt handling program after receiving the high-level signal, it is determined that the debounce circuit's recognition function for stable long pulses is normal; otherwise, it is determined that the debounce circuit's recognition function for stable long pulses is abnormal. Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal less than one pulse width of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit's suppression function for short pulse noise is normal; otherwise, it is determined that the debounce circuit's suppression function for short pulse noise is abnormal. Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and straddle two rising edges of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface triggers an interrupt and enters the preset interrupt handling program after receiving the high-level signal, it is determined that the debounce circuit's fault tolerance determination function for cross-double clock edge signals is normal; otherwise, it is determined that the debounce circuit's fault tolerance determination function for cross-double clock edge signals is abnormal. Generate a high-level signal and send it to one of the multiple pins configured as interrupt ports, and make the holding time of the high-level signal between one pulse width and two pulse widths of the debounce clock cycle and straddle only one rising edge of the debounce clock cycle. Collect the response status of the GPIO interface after receiving the high-level signal. If the GPIO interface does not trigger an interrupt after receiving the high-level signal, it is determined that the debounce circuit's filtering function for non-continuous sampling signals is normal; otherwise, it is determined that the debounce circuit's filtering function for non-continuous sampling signals is abnormal.

9. The GPIO interface verification method for the SoC chip based on bare-metal system-level software simulation according to any one of claims 1-8, characterized in that The method further includes: Construct a test excitation module, which is used to connect to the pins configured in the output mode in the GPIO interface, and is used to generate test excitation signals and send them to the pins configured in the output mode.

10. The method for verifying the GPIO interface of an SoC chip based on bare-metal system-level software simulation according to claim 9, characterized in that The method further includes: Construct a result collection and verification module, which is used to connect to the pins in the GPIO interface, and is used to collect the response status of the GPIO interface after receiving the test excitation signal, and obtain and output the function verification result according to the response status and the preset criteria.

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