Memory device, memory system, and method of operating memory device

Abstract

A memory device, a memory system, and a method of operating the memory device are provided. The memory device for performing a refresh operation includes: a refresh management circuit configured to perform a refresh operation on the memory device based on a refresh command received from a host; a counter configured to count a number of refresh operations performed by the refresh management circuit; and a temperature information analysis module configured to obtain temperature information about a plurality of memory cells included in the memory device, in which the refresh management circuit is further configured to perform a predetermined number of refresh operations during a first time period, the temperature information is received based on determining that a predetermined number of refresh operations have been performed, and a refresh rate of the memory device for a second time period is adjusted based on the temperature information.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0001670, filed with the Korean Intellectual Property Office on January 4, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a memory device, a memory system, and a method of operating a memory device, and more particularly, to a memory device that adjusts a refresh rate according to temperature. Background Art

[0003] A memory device including a volatile memory may periodically perform a refresh operation to preserve data. However, continuous refresh operations may deteriorate the durability of memory cells. Summary of the Invention

[0004] Provided is a memory device that sets an optimal refresh rate according to temperature.

[0005] Also provided is a method of maintaining the durability of memory cells in a memory device according to an embodiment and increasing the lifespan or reliability of memory cells by setting an optimal refresh rate according to temperature.

[0006] According to one aspect of the disclosure, a memory device for performing a refresh operation includes: a refresh management circuit configured to perform a refresh operation on the memory device based on a refresh command received from a host; a counter configured to count the number of refresh operations performed by the refresh management circuit; and a temperature information analysis module configured to obtain temperature information about a plurality of memory cells included in the memory device, wherein the refresh management circuit is further configured to: perform a predetermined number of refresh operations during a first period, receive the temperature information based on determining that the predetermined number of refresh operations have been performed, and adjust a refresh rate of the memory device for a second period based on the temperature information.

[0007] According to one aspect of the disclosure, a method of operating a memory device for performing a refresh operation includes: performing a refresh operation on the memory device based on a refresh command received from a host; counting the number of refresh operations performed; obtaining temperature information about a plurality of memory cells of the memory device; and adjusting a refresh rate of the memory device for a second period based on determining that a predetermined number of refresh operations have been performed during a first period, based on the temperature information.

[0008] According to one aspect of the disclosure, a memory system for performing a refresh operation on a memory device includes: a host configured to generate a plurality of commands corresponding to the memory device; a refresh management circuit configured to perform a refresh operation on the memory device based on a refresh command received from the host; a counter configured to count the number of refresh operations performed by the refresh management circuit; and a temperature information analysis module configured to obtain temperature information about a plurality of memory cells included in the memory device, wherein the refresh management circuit is further configured to: perform a predetermined number of refresh operations during a first time period, receive the temperature information based on the predetermined number of refresh operations being performed, and adjust a refresh rate of the memory device for a second time period based on the temperature information. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram showing a memory system according to an embodiment.

[0011] Figure 2 and Figure 3 is a block diagram showing a memory device according to an embodiment.

[0012] Figure 4 is a block diagram showing a refresh management circuit according to an embodiment.

[0013] Figure 5 is a flowchart of a method of operating a memory system according to an embodiment.

[0014] Figure 6 is a flowchart of adjusting a refresh rate according to temperature information in a method of operating a memory system according to an embodiment.

[0015] Figure 7 is a flowchart showing a process of performing a refresh rate reset operation in a method of operating a memory system according to an embodiment.

[0016] Figure 8 is a graph showing a trend of a limit value of a refresh operation that a memory device can perform during a time period according to temperature according to an embodiment.

[0017] Figure 9 is a block diagram showing components of a memory device according to an embodiment. DETAILED DESCRIPTION

[0018] The following description is provided only as an example, and various changes and modifications can be made to the described embodiments without departing from the scope of the disclosure. Therefore, the embodiments should not be construed as limited to the specific embodiments described below, and should be understood to include all changes, equivalents, and substitutions within the scope of the disclosure.

[0019] As is traditional in the art, embodiments are described in terms of functional blocks, units, and / or modules and illustrated in the figures. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) formed by using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, software (such as microcode) can be used to program the blocks, units, and / or modules to perform the various functions discussed herein, and the blocks, units, and / or modules can be selectively driven by firmware and / or software. Optionally, each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor (such as one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, without departing from the current scope, each block, unit, and / or module of the embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules. In addition, without departing from the current scope, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0020] Figure 1 is a block diagram showing a memory system 10 according to an embodiment.

[0021] Referring to Figure 1 , the memory system 10 according to an embodiment may include a memory device 100 and a host 200.

[0022] The memory device 100 according to an embodiment may receive a refresh command Refresh_CMD and other commands (such as a command Other_CMD) from the host 200. The command Other_CMD according to an embodiment may be a command different from the refresh command Refresh_CMD, and may be a command indicating one or more of a plurality of operations of the memory device 100. For example, the command Other_CMD may include a read command or a write command for the memory device 100.

[0023] The memory device 100 according to an embodiment may receive a refresh command Refresh_CMD from a host 200 and perform a refresh operation based on the refresh command Refresh_CMD. The refresh operation according to an embodiment may represent an operation of maintaining data stored in memory cells included in the memory device 100 during a predetermined period of time.

[0024] The memory device 100 according to an embodiment may be configured to determine the number of times the refresh operation is performed. "Determining the number of times the refresh operation is performed" may be referred to as "determining the number of refresh operations performed". For example, the memory device 100 may include a counter to determine the number of refresh operations performed and determine whether a predetermined number of refresh operations have been performed during a predetermined period of time. According to an embodiment, the predetermined number may be a value set for each temperature range or temperature interval and may be determined or set during the manufacture of the memory device 100. However, the embodiment is not limited thereto, and the predetermined number may be modified according to, for example, a user input or a command received from the host.

[0025] The memory device 100 according to an embodiment may determine temperature information about a plurality of memory cells. For example, the memory device 100 may determine temperature information about a plurality of memory cells in real time and adjust a refresh rate based on the temperature information. For example, the memory device 100 may adjust the refresh rate to correspond to a temperature range or temperature interval corresponding to the temperature information. The temperature information about the memory cells according to an embodiment may represent information about the temperature of the memory cells (e.g., the average temperature of the memory cells). In addition, adjusting the refresh rate according to an embodiment may represent adjusting the number of times the refresh operation is performed during a predetermined period of time, or adjusting, for example, the number of refresh operations to be performed during a predetermined period of time.

[0026] According to an embodiment, in response to first temperature information, the memory device may determine a first refresh rate corresponding to the first temperature information. In response to second temperature information, the memory device may determine a second refresh rate corresponding to the second temperature information. For example, when the second temperature information is higher than the first temperature information, the second refresh rate may be larger than the first refresh rate. In other words, the memory device may increase the refresh rate as the temperature increases.

[0027] According to an embodiment, in response to first temperature information, the memory device may determine a first refresh period corresponding to the first temperature information. In response to second temperature information, the memory device may determine a second refresh period corresponding to the second temperature information. For example, when the second temperature information is higher than the first temperature information, the second refresh period may be smaller than the first refresh period. In other words, the memory device may decrease the refresh period as the temperature increases.

[0028] For example, the memory device 100 may perform a predetermined number of refresh operations during a first time period, receive temperature information when the refresh operations are performed a predetermined number of times, and adjust the refresh rate for a second time period based on the received temperature information. In an embodiment, "performing the refresh operations a predetermined number of times" may be referred to as "performing a predetermined number of refresh operations". The first time period and the second time period according to an embodiment may respectively represent the time periods before and after adjusting the refresh rate. For example, the memory device 100 may perform a predetermined number of refresh operations during the first time period, adjust the refresh rate based on the temperature information, and then perform the refresh operations according to the adjusted refresh rate in the second time period.

[0029] The host 200 according to an embodiment may generate a plurality of commands for the memory device 100 and send the generated commands to the memory device 100. For example, the host 200 may generate a refresh command Refresh_CMD and a command Other_CMD, and send the generated refresh command Refresh_CMD and the generated command Other_CMD to the memory device 100. The refresh command Refresh_CMD according to an embodiment may be a signal instructing the memory device 100 to perform a refresh operation on the memory cells of the memory device 100. The command Other_CMD according to an embodiment is a command other than the refresh command Refresh_CMD and may be a command instructing a plurality of operations of the memory device 100. For example, the command Other_CMD may include a read command or a write command for the memory device 100.

[0030] Figure 2 and Figure 3 is a block diagram illustrating a memory device 100 according to an embodiment.

[0031] Referring to Figure 2 and Figure 3 , the memory device 100 according to an embodiment may include a refresh processor 110 and a memory cell array 120.

[0032] The refresh processor 110 according to an embodiment may send a refresh signal Refresh to the memory cell array 120 and may perform a refresh operation on the memory cell array 120. For example, the refresh processor 110 may perform a refresh operation on a plurality of memory cells included in the memory cell array 120. The refresh processor 110 according to an embodiment may perform the refresh operation based on the refresh command Refresh_CMD received from the host 200. The refresh operation according to an embodiment may represent an operation of maintaining data stored in the memory cells included in the memory cell array 120 during a predetermined time period.

[0033] The refresh processor 110 according to an embodiment may be configured to determine the number of times a refresh operation is performed, or for example, the number of refresh operations performed. For example, the refresh processor 110 may include a counter to determine the number of refresh operations performed, and determine whether the refresh operation has been performed a predetermined number of times during a predetermined period, or for example, whether a predetermined number of refresh operations have been performed during a predetermined period.

[0034] The refresh processor 110 according to an embodiment may determine temperature information about a plurality of memory cells. For example, the refresh processor 110 may determine temperature information about a plurality of memory cells in real time and adjust the refresh rate based on the temperature information. The temperature information about the memory cells according to an embodiment may represent information about the temperature of the memory cells (e.g., the average temperature of the memory cells). In addition, adjusting the refresh rate according to an embodiment may represent adjusting the number of times a refresh operation is performed during a predetermined period.

[0035] For example, the refresh processor 110 may perform a predetermined number of refresh operations during a first period, receive temperature information when the predetermined number of refresh operations have been performed, and adjust the refresh rate for a second period based on the received temperature information. For example, the refresh processor 110 according to an embodiment may perform a predetermined number of refresh operations during a first period, adjust the refresh rate based on the temperature information, and then perform refresh operations according to the adjusted refresh rate during a second period.

[0036] The memory cell array 120 according to an embodiment may include a plurality of memory cells. The memory device 100 according to an embodiment may be a volatile memory. For example, the memory cell array 120 may include memory cells constituting a volatile memory device. The memory device 100 according to an embodiment may include a volatile memory (such as static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)).

[0037] Further referring to Figure 3 the refresh processor 110 according to an embodiment may include a refresh management circuit 111, a counter 112, a temperature information analysis module 113, and / or a flag signal controller 114.

[0038] The refresh management circuit 111 according to an embodiment may perform a refresh operation based on a refresh command Refresh_CMD received from a host 200. For example, the refresh management circuit 111 may receive temperature information T_Info about a plurality of memory cells in real time, and adjust a refresh rate based on the temperature information T_Info. The refresh management circuit 111 according to an embodiment may perform a predetermined number of refresh operations in a predetermined time period, and when the predetermined number of refresh operations has been performed, the refresh management circuit 111 may adjust the refresh rate and perform a refresh operation in a new time period. For example, the refresh management circuit 111 may perform a predetermined number of refresh operations during a first time period, receive the temperature information T_Info when the predetermined number of refresh operations has been performed, and adjust the refresh rate of a second time period based on the received temperature information T_Info. For example, the refresh management circuit 111 according to an embodiment may perform a predetermined number of refresh operations during a first time period, adjust the refresh rate based on the temperature information T_Info, and then perform a refresh operation according to the adjusted refresh rate in a second time period.

[0039] The refresh management circuit 111 according to an embodiment may be configured to stop a refresh operation when a flag signal Flag is activated. The flag signal Flag according to an embodiment may be a signal that notifies or indicates a reason for having occurred a "stop refresh operation" in the refresh management circuit 111. A reason for stopping a refresh operation according to an embodiment may be any one of completion of a predetermined number of refresh operations, reception of a command Other_CMD other than a refresh command, and change of temperature information T_Info.

[0040] The refresh management circuit 111 according to an embodiment may stop a refresh operation when a command Other_CMD other than a refresh command Refresh_CMD is received. For example, when a read command and / or a write command is received by the memory device 100, the refresh management circuit 111 may stop a refresh operation, and reset a refresh rate of a new time period.

[0041] The refresh management circuit 111 according to an embodiment may stop a refresh operation when a predetermined number of refresh operations has been performed. For example, the refresh management circuit 111 may perform a predetermined number of refresh operations, receive an activated flag signal Flag, and stop a refresh operation. After the refresh operation is stopped, the refresh management circuit 111 according to an embodiment may reset a refresh rate based on the temperature information T_Info, and perform at least one refresh operation in a new time period.

[0042] When the temperature information T_Info is changed, the refresh management circuit 111 according to an embodiment may ignore the refresh command Refresh_CMD and adjust the refresh rate. For example, when the change in the temperature information T_Info satisfies a predetermined criterion, the refresh management circuit 111 may adjust the refresh rate by ignoring the received refresh command Refresh_CMD. The refresh management circuit 111 according to an embodiment may ignore the refresh command Refresh_CMD at a predetermined interval. The predetermined criterion regarding the change in the temperature information T_Info according to an embodiment may be a criterion input during the manufacture of the memory device 100. However, the embodiment is not limited thereto, and the predetermined criterion may be modified according to, for example, user input or a command received from the host 200.

[0043] The counter 112 according to an embodiment may determine the number of refresh operations that have been performed or are being performed during any particular time period. The counter 112 may count the number of refresh operations. For example, the counter 112 may determine whether a predetermined number of refresh operations have been performed and may activate the flag signal Flag when the predetermined number of refresh operations have been performed. The counter 112 according to an embodiment may send the activated flag signal Flag to the refresh management circuit 111. When the flag signal Flag is received, the refresh management circuit 111 according to an embodiment may be configured to stop the refresh operation. The predetermined number according to an embodiment may be a value input during the manufacture of the memory device 100 and may be changed according to the temperature information for a predetermined time period. However, the embodiment is not limited thereto, and the predetermined number may be modified according to, for example, user input or a command received from the host 200.

[0044] The temperature information analysis module 113 according to an embodiment may determine the temperature information T_Info regarding a plurality of memory cells of the memory device. For example, the temperature information analysis module 113 may determine the temperature information T_Info regarding the memory cells in real time and send the determined temperature information T_Info to the refresh management circuit 111. When the change in the temperature information T_Info satisfies a predetermined criterion, the refresh management circuit 111 according to an embodiment may adjust the refresh rate by ignoring the received refresh command Refresh_CMD. The refresh management circuit 111 according to an embodiment may ignore the refresh command Refresh_CMD at a predetermined interval. The predetermined criterion regarding the change in the temperature information T_Info according to an embodiment may be a criterion input during the manufacture of the memory device 100. However, the embodiment is not limited thereto, and the predetermined criterion may be modified according to, for example, user input or a command received from the host 200.

[0045] The flag signal controller 114 according to an embodiment may determine whether a command Other_CMD other than the refresh command Refresh_CMD is received. The flag signal controller 114 according to an embodiment may be configured to send a flag reset signal Flag Reset to the counter 112 and a refresh rate reset signal Refresh Rate Reset to the refresh management circuit 111 when a command Other_CMD other than the refresh command Refresh_CMD is received.

[0046] When a command Other_CMD other than the refresh command Refresh_CMD is received, the flag signal controller 114 according to an embodiment may send a flag reset signal Flag Reset to the counter 112. When the flag reset signal FlagReset is received, the counter 112 may be reset, and a flag signal Flag is generated and sent to the refresh management circuit 111. The refresh management circuit 111 according to an embodiment may stop the refresh operation when a command Other_CMD other than the refresh command Refresh_CMD is received. For example, when a read command or a write command is received by the memory device 100, the refresh management circuit 111 may stop the refresh operation and reset the refresh rate for a new time period based on the refresh rate reset signal Refresh Rate Reset.

[0047] Figure 4 is a block diagram showing the refresh management circuit 111 according to an embodiment.

[0048] Referring to Figure 4 , the refresh management circuit 111 according to an embodiment may include an input interface 111a, an output interface 111b, and a plurality of logic circuits (e.g., a first logic circuit 111_1, a second logic circuit 111_2, a third logic circuit 111_3, ……, and an Nth logic circuit 111_N).

[0049] The input interface 111a according to an embodiment may receive a plurality of signals. For example, the input interface 111a may receive at least one of a refresh command Refresh_CMD, a flag signal Flag, a refresh rate reset signal Refresh Rate Reset, and temperature information T_Info. The input interface 111a according to an embodiment may receive at least one of the flag signal Flag, the refresh rate reset signal RefreshRate Reset, and the temperature information T_Info, and send the refresh command Refresh_CMD to a logic circuit among the plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N that meets a predetermined criterion. For example, when the refresh rate of a first time period is set by the first logic circuit 111_1, a refresh operation is performed, and the temperature information T_Info is changed after the refresh operation of the first time period is performed, the input interface 111a may send the refresh command Refresh_CMD to the second logic circuit 111_2.

[0050] The plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N according to an embodiment may set the refresh rate according to a predetermined criterion.

[0051] The refresh rate determined by the first logic circuit 111_1 according to an embodiment may be 1:1, and the refresh rate determined by the second logic circuit 111_2 may be 2:1. The refresh rate according to an embodiment may represent a ratio between the number of times the refresh command Refresh_CMD is received and the number of times the refresh operation is performed. For example, when the refresh rate determined by the first logic circuit 111_1 is 1:1, the first logic circuit 111_1 may perform a number of refresh operations equal to the number of times the refresh command Refresh_CMD is received. In another example, when the refresh rate determined by the second logic circuit 111_2 is 2:1, the second logic circuit 111_2 may perform one refresh operation based on the refresh command Refresh_CMD being received twice. Therefore, when the refresh rate determined by the second logic circuit 111_2 according to an embodiment is 2:1, the second logic circuit 111_2 may ignore the refresh command Refresh_CMD at a ratio of 2:1 (for example, may ignore every other refresh command Refresh_CMD). In another example, when the refresh rate determined by the third logic circuit 111_3 is 3:1, the third logic circuit 111_3 may perform one refresh operation every time the refresh command Refresh_CMD is received three times. When the refresh rate determined by the third logic circuit 111_3 according to an embodiment is 3:1, the third logic circuit 111_3 may ignore the refresh command Refresh_CMD at a ratio of 3:1 (for example, may ignore two out of every three refresh commands Refresh_CMD).

[0052] However, the refresh rate determined by the plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N is not limited thereto, and various ratios can be determined by the plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N. For example, when the refresh rate determined by the Nth logic circuit 111_N is N:1, whenever the refresh command Refresh_CMD is received N times, the Nth logic circuit 111_N can perform a refresh operation once. When the refresh rate determined by the Nth logic circuit 111_N according to the embodiment is N:1, the Nth logic circuit 111_N can ignore the refresh command Refresh_CMD at a ratio of N:1 (for example, (N - 1) of every N refresh commands Refresh_CMD can be ignored).

[0053] The output interface 111b according to the embodiment can output a refresh signal Refresh including the refresh rate information set by any one of the plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N. For example, the output interface 111b can send the refresh signal Refresh including the refresh rate information set by any one of the plurality of logic circuits 111_1, 111_2, 111_3, ……, and 111_N to Figure 2 or Figure 3 the memory cell array 120 of.

[0054] Figure 5 is a flowchart of a method of operating a memory system according to an embodiment.

[0055] Referring to Figure 1 and Figure 5 In operation S510, the memory device 100 according to the embodiment can receive a refresh command Refresh_CMD from the host 200.

[0056] When the refresh command Refresh_CMD is received, in operation S520, the memory device 100 according to the embodiment can perform a refresh operation on the memory device 100 based on the refresh command Refresh_CMD received from the host 200. The refresh operation according to the embodiment can represent an operation of maintaining data stored in the memory cells included in the memory device 100 during a predetermined period.

[0057] When the refresh operation is performed, in operation S530, the memory device 100 according to the embodiment can determine the number of times the refresh operation is performed (for example, the number of refresh operations performed).

[0058] The memory device 100 according to an embodiment may be configured to determine the number of refresh operations being performed. For example, the memory device 100 may include a counter that determines the number of refresh operations being performed and determines whether a predetermined number of refresh operations have been performed during a predetermined time period.

[0059] As a result of determining the number of refresh operations being performed, when it is determined that a predetermined number of refresh operations have been performed, at operation S540, the memory device 100 according to an embodiment may determine temperature information regarding a plurality of memory cells of the memory device 100.

[0060] The refresh processor 110 according to an embodiment may be configured to determine the number of times a refresh operation is performed. For example, the refresh processor 110 may include a counter that determines the number of refresh operations being performed and determines whether a predetermined number of refresh operations have been performed during a predetermined time period. The predetermined time period according to an embodiment may be a time period determined during the manufacture of the memory device 100. The predetermined number according to an embodiment may be a value set for each temperature range during the manufacture of the memory device 100. However, the embodiment is not limited thereto, and at least one of the predetermined time period and the predetermined number may be modified according to, for example, a user input or a command received from the host 200.

[0061] When the temperature information regarding the plurality of memory cells is determined, at operation S550, the memory device 100 according to an embodiment may adjust the refresh rate.

[0062] The memory device 100 according to an embodiment may determine temperature information regarding a plurality of memory cells. For example, the memory device 100 may determine the temperature information regarding the plurality of memory cells in real time and adjust the refresh rate based on the temperature information. The temperature information regarding the memory cells according to an embodiment may represent information regarding the temperature of the memory cells (e.g., the average temperature of the memory cells). In addition, adjusting the refresh rate according to an embodiment may represent adjusting the number of times a refresh operation is performed during a predetermined time period.

[0063] For example, the memory device 100 may perform a predetermined number of refresh operations during a first time period, receive the temperature information when the predetermined number of refresh operations have been performed, and adjust the refresh rate for a second time period based on the received temperature information. The first time period and the second time period according to an embodiment may represent the time periods before and after adjusting the refresh rate, respectively. For example, the memory device 100 may perform a predetermined number of refresh operations during the first time period, adjust the refresh rate based on the temperature information, and then perform the refresh operation according to the adjusted refresh rate during the second time period.

[0064] Figure 6It is a flowchart for adjusting a refresh rate according to temperature information in a method of operating a memory system according to an embodiment.

[0065] Referring to Figure 2 、 Figure 3 and Figure 6 In operation S610, the memory device 100 according to an embodiment may perform a predetermined number of refresh operations during a first time period.

[0066] For example, the memory device 100 may perform a predetermined number of refresh operations during a first time period, receive temperature information when the predetermined number of refresh operations have been performed, and adjust the refresh rate of a second time period based on the received temperature information. The first time period and the second time period according to an embodiment may respectively represent the time periods before and after adjusting the refresh rate. For example, the memory device 100 may perform a predetermined number of refresh operations during a first time period, adjust the refresh rate based on the temperature information, and then perform refresh operations according to the adjusted refresh rate during a second time period.

[0067] In operation S620, the memory device 100 according to an embodiment may determine whether a predetermined number of refresh operations have been performed. The predetermined number according to an embodiment may be a value set for each temperature range when manufacturing the memory device 100. However, the embodiment is not limited thereto, and the predetermined number may be modified according to, for example, user input or a command received from the host 200.

[0068] When it is determined that the predetermined number of refresh operations has been completed, in operation S630, the memory device 100 according to an embodiment may stop the refresh operation of the first time period. The memory device 100 according to an embodiment may be configured to stop the refresh operation when the flag signal Flag is activated. The flag signal Flag according to an embodiment may be a signal that notifies or indicates the reason for which "stopping the refresh operation" has occurred in the memory device 100. The reason for stopping the refresh operation according to an embodiment may be any one of the completion of a predetermined number of refresh operations, the reception of a command Other_CMD other than the refresh command, and the change of temperature information T_Info.

[0069] However, when it is determined that the predetermined number of refresh operations has not been performed, the memory device 100 according to an embodiment may perform the refresh operation until the refresh operation of the first time period is completed.

[0070] When the refresh operation of the first time period is stopped, in operation S640, the memory device 100 according to an embodiment may receive the temperature information T_Info. The temperature information about the memory cells according to an embodiment may represent information about the temperature of the memory cells (e.g., the average temperature of the memory cells).

[0071] When temperature information is received, at operation S650, the memory device 100 according to an embodiment may adjust the refresh rate of the memory device 100 in a second time period based on the received temperature information. Adjusting the refresh rate according to an embodiment may mean adjusting the number of refresh operations to be performed during a predetermined time period.

[0072] For example, the memory device 100 may receive temperature information T_Info about a plurality of memory cells in real time and adjust the refresh rate based on the temperature information T_Info. The memory device 100 according to an embodiment may perform a predetermined number of refresh operations in a predetermined time period, and when the predetermined number of refresh operations has been performed, the memory device 100 may adjust the refresh rate and perform refresh operations in a new time period. For example, the memory device 100 may perform a predetermined number of refresh operations during a first time period, receive temperature information T_Info when the predetermined number of refresh operations has been performed, and adjust the refresh rate in a second time period based on the received temperature information T_Info. For example, the memory device 100 according to an embodiment may perform a predetermined number of refresh operations during a first time period, adjust the refresh rate based on the temperature information T_Info, and then perform refresh operations in a second time period according to the adjusted refresh rate.

[0073] Figure 7 is a flowchart showing a process of performing a refresh rate reset operation in a method of operating a memory system according to an embodiment.

[0074] Refer to Figure 2 、 Figure 3 and Figure 7 and, at operation S710, the memory device 100 according to an embodiment may control a flag signal Flag.

[0075] The memory device 100 according to an embodiment may determine the number of times the refresh operation is performed. For example, the memory device 100 may determine whether a predetermined number of refresh operations have been performed and may activate the flag signal Flag when the predetermined number of refresh operations has been performed. The memory device 100 according to an embodiment may send the activated flag signal Flag to the refresh management circuit 111. When the flag signal Flag is received, the refresh management circuit 111 according to an embodiment may be configured to stop the refresh operation. The predetermined number of times of performing the refresh operation according to an embodiment may be a value input when manufacturing the memory device 100 and may be changed according to temperature information and / or a predetermined time period. However, the embodiment is not limited thereto, and the predetermined number may be modified according to, for example, user input or a command received from the host 200.

[0076] In operation S720, the memory device 100 according to an embodiment may determine whether a command Other_CMD other than the refresh command Refresh_CMD is received.

[0077] The command Other_CMD according to an embodiment is a command other than the refresh command Refresh_CMD, and may be a command indicating multiple operations of the memory device 100. For example, the command Other_CMD may include a read command or a write command for the memory device 100.

[0078] When it is determined that a command Other_CMD other than the refresh command Refresh_CMD is received, in operation S730, the memory device 100 according to an embodiment may send a flag reset signal Flag Reset to the counter 112. In addition, when it is determined that a command Other_CMD other than the refresh command Refresh_CMD is received, in operation S740, the memory device 100 according to an embodiment may send a refresh rate reset signal Refresh Rate Reset to the refresh management circuit 111.

[0079] The memory device 100 according to an embodiment may determine whether a command Other_CMD other than the refresh command Refresh_CMD is received. The memory device 100 according to an embodiment may be configured to, when a command Other_CMD other than the refresh command Refresh_CMD is received, send a flag reset signal Flag Reset to the counter 112 and send a refresh rate reset signal Refresh Rate Reset to the refresh management circuit 111.

[0080] When a command Other_CMD other than the refresh command Refresh_CMD is received, the memory device 100 according to an embodiment may send a flag reset signal Flag Reset to the counter 112. When the flag reset signal Flag Reset is received, the counter 112 may be reset, and a flag signal Flag is generated and the flag signal Flag is sent to the refresh management circuit 111. The refresh management circuit 111 according to an embodiment may stop the refresh operation when a command Other_CMD other than the refresh command Refresh_CMD is received. For example, when a read command or a write command is received by the memory device 100, the refresh management circuit 111 may stop the refresh operation and reset the refresh rate for a new time period based on the refresh rate reset signal Refresh Rate Reset.

[0081] However, when it is determined that no command Other_CMD other than the refresh command Refresh_CMD is received, the memory device 100 according to the embodiment may continue to perform the refresh operation.

[0082] Figure 8 is a graph showing the trend of the limit value of the refresh operation to be performed during the refresh operation period according to the embodiment according to temperature.

[0083] In accordance with Figure 8 the graph of the embodiment, the x-axis represents temperature, and the y-axis represents the maximum refresh operation acceptance limit of the memory device 100 according to temperature. Figure 8 shows the limit value of the refresh period according to temperature. According to the embodiment, the memory device 100 may perform a refresh operation (or an auto-refresh operation) in response to a refresh command received from the host 200 (or a memory controller). The memory device 100 may perform a self-refresh operation. The memory device 100 may perform a self-refresh operation without the intervention of the host 200. Even if no refresh command is received from the host 200, the memory device 100 may perform a self-refresh operation.

[0084] The refresh period [tREF(self)] corresponding to the self-refresh operation Self may have a higher limit than the refresh period [tREF(MR4)] corresponding to the refresh operation MR4 performed based on a predetermined criterion. In other words, in terms of the refresh period according to temperature, the refresh period [tREF(self)] corresponding to the self-refresh operation Self may have a higher limit than the refresh period [tREF(MR4)] corresponding to the refresh operation MR4 (or the auto-refresh operation) performed based on a predetermined criterion. For example, at the same temperature, the refresh period [tREF(self)] corresponding to the self-refresh operation Self may be longer than the refresh period [tREF(MR4)] corresponding to the refresh operation MR4 (or the auto-refresh operation) performed based on a predetermined criterion.

[0085] Referring to Figure 8, when the refresh operation MR4 executed based on a predetermined criterion is continuously performed on the memory device 100 according to an embodiment, the durability of the memory cells of the memory device 100 may converge to be similar to the durability of the memory cells of the memory device 100 corresponding to the self-refresh operation Self. According to an embodiment, the memory device 100 according to the embodiment may adjust the refresh rate or the refresh period based on temperature in response to receiving a preset number or more of refresh commands. For example, at a first temperature, the memory device 100 may perform a refresh operation with a first refresh period in response to a refresh command. At the first temperature, the memory device 100 may perform a refresh operation with a second refresh period in response to receiving a preset number or more of refresh commands. The second refresh period may be longer than the first refresh period. Accordingly, the memory device 100 may reduce current consumption. The memory device 100 according to the embodiment may maintain the durability of the memory cells by performing a refresh operation based on a predetermined standard according to temperature.

[0086] Figure 9 is a block diagram showing components of a memory device according to an embodiment.

[0087] Referring to Figure 9 , the memory device 100 may include a memory cell array (MCA) 120, a row decoder 121a, a word line (WL) driver 122, a column decoder 121b, an input / output (I / O) gating circuit 123, a mode register set (MRS) 124, a control logic circuit 125, an address buffer 126, an on-die termination (ODT) circuit 127, a reference voltage (VREF) generation circuit 128, a data input buffer 129a, and a data output buffer 129b.

[0088] The memory cell array 120 may include a plurality of memory cells arranged in a matrix form including rows and columns. The memory cell array 120 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the memory cells in a row, and the plurality of bit lines BL may be connected to the memory cells in a column.

[0089] The row decoder 121a can be selectively connected to any one of the word lines WL of the memory cell array 120. The address buffer 126 can receive the address ADDR and output the row address ROW_ADDR and the column address COL_ADDR. The row decoder 121a can decode the row address ROW_ADDR received from the address buffer 126, select any one of the word lines WL corresponding to the row address ROW_ADDR, and connect the selected word line WL to the word line driver 122 that activates the selected word line WL. The column decoder 121b can select a predetermined number of bit lines BL among the bit lines BL of the memory cell array 120. The column decoder 121b can generate a column selection signal CSL by decoding the column address COL_ADDR received from the address buffer 126, and connect the bit line BL selected by the column selection signal CSL to the input / output gating circuit 123. The input / output gating circuit 123 can include a read data latch for storing the read data of the bit line BL selected by the column selection signal CSL and a write driver for writing the write data to the memory cell array 120. The data DQ (e.g., read data) stored in the read data latch of the input / output gating circuit 123 can be provided to the data bus through the data output buffer 129b. The data DQ (e.g., write data) can be applied to the memory cell array 120 through the data input buffer 129a connected to the data bus and through the write driver of the input / output gating circuit 123.

[0090] The control logic circuit 125 can receive the clock signal CLK and the command CMD and generate control signals CTRLS for controlling the operation timing of the memory cell array 120 and / or the memory operation. The control logic circuit 125 can use the control signals CTRLS to read data from the memory cell array 120 and write data to the memory cell array 120.

[0091] The MRS 124 can store information used by the control logic circuit 125 to configure the operation of the memory device 100 to set the operation conditions of the memory device 100. The MRS 124 can include a register that stores parameter codes of various operation parameters and control parameters for setting the operation conditions of the memory device 100. The parameter codes can be received by the memory device 100 through the command / address bus. The control logic circuit 125 provides the control signals CTRLS to the circuits of the memory device 100 to operate as set by the operation parameters and control parameters stored in the MRS 124.

[0092] The ODT circuit 127 may provide termination resistance when enabled for the command / address bus and / or the data bus. The termination resistance may improve the signal integrity (SI) of signals received through the bus. The enabling of the ODT circuit 127 and the magnitude of the termination resistance provided to the bus may be set by recording appropriate parameter codes into the MRS 124.

[0093] The reference voltage generation circuit 128 may provide a reference voltage VREF used by the circuits of the memory device 100. For example, the reference voltage VREF may be used by the control logic circuit 125 to compare with the voltage of a signal received from the command bus to determine the logical value of the signal. The reference voltage VREF and / or the range of the reference voltage VREF may be set by recording reference voltage operation parameter codes in the MRS 124.

[0094] The data input buffer 129a may provide write data received through the data bus to the input / output gating circuit 123.

[0095] The data output buffer 129b may provide read data stored in the read data latch of the input / output gating circuit 123 to the memory controller through the data bus.

[0096] Although some embodiments have been specifically shown and described herein, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device for performing a refresh operation, the memory device comprising: A refresh management circuit configured to perform a refresh operation on the memory device based on a refresh command received from a host; A counter configured to count the number of refresh operations performed by the refresh management circuit; And A temperature information analysis module configured to obtain temperature information about a plurality of memory cells included in the memory device, wherein the refresh management circuit is further configured to: Perform a predetermined number of refresh operations during a first time period, Based on determining that the predetermined number of refresh operations have been performed, receive the temperature information, and Based on the temperature information, adjust the refresh rate of the memory device in a second time period.

2. The memory device according to claim 1, wherein, The counter is further configured to: based on determining that the predetermined number of refresh operations have been performed, activate a flag signal, and wherein the refresh management circuit is further configured to: based on the flag signal being activated, stop performing the refresh operation.

3. The memory device according to claim 1, wherein, The refresh management circuit is further configured to: based on a command other than the refresh command being received, stop performing the refresh operation.

4. The memory device according to claim 3, wherein, The refresh management circuit is further configured to: after the refresh operation is stopped, reset the refresh rate.

5. The memory device according to claim 1, wherein, The refresh management circuit is further configured to: ignore the refresh command and adjust the refresh rate based on a change in the temperature information.

6. The memory device according to claim 1, further comprising: A flag signal controller configured to determine whether a command other than the refresh command is received.

7. The memory device according to claim 6, wherein, Based on the command being received, the flag signal controller is further configured to: send a flag reset signal to the counter and a refresh rate reset signal to the refresh management circuit.

8. A method of operating a memory device for performing a refresh operation, the method comprising: Performing a refresh operation on the memory device based on a refresh command received from a host; Counting the number of refresh operations performed; Obtaining temperature information about a plurality of memory cells of the memory device; And Based on determining that a predetermined number of refresh operations have been performed during a first time period, adjusting the refresh rate of the memory device in a second time period based on the temperature information.

9. The method according to claim 8, wherein, The step of counting the number of refresh operations performed includes: based on determining that the predetermined number of refresh operations have been performed, activating a flag signal, and wherein, based on the flag signal being activated, the refresh operation is stopped.

10. The method according to claim 8, wherein, Based on a command other than the refresh command being received, the refresh operation is stopped.

11. The method according to claim 10, wherein, After the refresh operation is stopped, the refresh rate is reset.

12. The method according to claim 8, wherein The refresh command is ignored and the refresh rate is adjusted based on a change in the temperature information.

13. The method according to claim 8 further comprises: Based on a command other than the refresh command being received, the flag signal is controlled by sending a flag reset signal to the counter and a refresh rate reset signal to the refresh management circuit.

14. A memory system for performing a refresh operation on a memory device, the memory system comprising: A host configured to generate a plurality of commands corresponding to the memory device; A refresh management circuit configured to perform a refresh operation on the memory device based on a refresh command received from the host; A counter configured to count the number of refresh operations performed by a refresh management circuit; and A temperature information analysis module configured to obtain temperature information about a plurality of memory cells included in the memory device, wherein the refresh management circuit is further configured to: Perform a predetermined number of refresh operations during a first time period, Receive the temperature information based on the predetermined number of refresh operations having been performed, and Adjust the refresh rate of the memory device for a second time period based on the temperature information.

15. The memory system according to claim 14, wherein The counter is further configured to: Activate a flag signal based on the predetermined number of refresh operations having been performed, and wherein the refresh management circuit is further configured to: Stop the refresh operation based on the flag signal being activated.

16. The memory system according to claim 14, wherein, The refresh management circuit is further configured to: Stop the refresh operation based on a command other than a refresh command being received.

17. The memory system according to claim 16, wherein, The refresh management circuit is further configured to: Reset the refresh rate after the refresh operation is stopped.

18. The memory system according to claim 14, wherein, The refresh management circuit is further configured to: Ignore the refresh command and adjust the refresh rate based on a change in the temperature information.

19. The memory system according to claim 14, further comprising: A flag signal controller configured to determine whether a command other than a refresh command is received.

20. The memory system according to claim 19, wherein, Based on the command being received, the flag signal controller is further configured to: Send a flag reset signal to the counter and a refresh rate reset signal to the refresh management circuit.

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