Operation method of memory system and memory system

Abstract

The invention provides an operation method of a storage system, which comprises the following steps of: accumulating data writing times of individual written storage units in a memory to generate writing accumulated values corresponding to the individual written storage units; and according to the pattern of the adjacent storage unit of the individual written storage unit, when the writing accumulated value reaches a threshold value set according to the pattern, performing data refreshing operation on the adjacent storage unit. Through the operation method of the storage system and the storage system provided by the invention, the write-in interference can be managed more finely, the sacrifice of system performance caused by write-in interference (WD, write-in interference) medium management can be optimized to the greatest extent, and the influence of bias drift on the storage unit can be reduced.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and particularly to an operation method of a storage system and a storage system. Background Art

[0002] Memory is the foundation of information technology. As a candidate for the next-generation non-volatile semiconductor memory, Phase Change Random Access Memory (PCM) has received extensive attention due to its advantages such as high-speed reading, high erasable and writable times, non-volatility, small component size, low power consumption, strong vibration resistance, and radiation resistance, especially 3D PCM. Therefore, with the increase in storage capacity and the development of PCM technology, using PCM as the storage unit of a large-capacity storage system has also become a trend.

[0003] However, how to prevent the stored data in PCM from being affected by the read and write operations of adjacent storage units is an important issue, so there is a need to propose an operation method that can solve these problems. Summary of the Invention

[0004] The purpose of the present application is to provide an operation method of a storage system and a storage system, which are used to solve the problem of data drift caused by the write bias of storage units.

[0005] In a first aspect, the present application provides an operation method of a storage system, and the operation method includes:

[0006] Accumulating the number of data write operations of individual written storage units in the memory to generate a write cumulative value corresponding to each of the individual written storage units; and

[0007] According to the state of adjacent storage units of each of the individual written storage units, when the write cumulative value reaches a threshold set according to the state, performing a data refresh operation on the adjacent storage units.

[0008] Optionally, the operation method further includes setting a corresponding plurality of thresholds according to various states of the adjacent storage units.

[0009] Optionally, the state includes at least one of the position of the adjacent storage unit or the ambient temperature.

[0010] Optionally, the position of the adjacent storage unit includes at least one of the same bit line, the same word line, or the same stack as the written storage unit.

[0011] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to whether the adjacent memory cell and the memory cell to be written are on the same bit line or on the same word line.

[0012] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different stacks where the adjacent memory cells are located.

[0013] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different stacks where the adjacent memory cells are located and whether the adjacent memory cell and the memory cell to be written are on the same bit line or on the same word line.

[0014] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different ambient temperatures of the adjacent memory cells, and the memory is a phase change memory (PCM).

[0015] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different stacks where the adjacent memory cells are located and the different ambient temperatures of the adjacent memory cells.

[0016] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different ambient temperatures of the adjacent memory cells and whether the adjacent memory cell and the memory cell to be written are on the same bit line or on the same word line.

[0017] Optionally, the step of setting the plurality of corresponding thresholds includes setting different ones of the plurality of thresholds according to the different stacks where the adjacent memory cells are located, the different ambient temperatures of the adjacent memory cells, and whether the adjacent memory cell and the memory cell to be written are on the same bit line or on the same word line. Optionally, the operation method further includes: receiving information about the ambient temperature of the memory as the information about the ambient temperature of the adjacent memory cells, and selecting, according to the ambient temperature information, the threshold set according to the state from the plurality of thresholds.

[0018] Optionally, the operation method further includes: after performing a data refresh operation on the adjacent memory cells, resetting the write cumulative value of the memory cell to be written.

[0019] In a second aspect, the present application provides a storage system, the storage system includes:

[0020] A memory; and

[0021] A controller, connected to the memory, is configured to control the memory and is configured to execute the aforementioned operation method and any optional operation method.

[0022] Through the operation method of the storage system and the storage system provided by this application, write interference can be managed more precisely, the sacrifice of system performance caused by write disturbance (WD) media management can be optimized to the greatest extent, the influence of bias drift on storage cells can be reduced, read errors caused by excessive drift due to bias can be prevented, and the power-on data retention time can be increased. Brief Description of the Drawings

[0023] Combined with the accompanying drawings and through a detailed description of the specific embodiments of this application, the technical solutions and other beneficial effects of this application will become obvious.

[0024] Figure 1 It is a functional module block diagram of a storage system according to some embodiments of this application.

[0025] Figure 2 It is a functional module block diagram of the peripheral circuit of a memory according to some embodiments of this application.

[0026] Figure 3a It is a circuit schematic diagram of a memory array of a memory according to some embodiments of this application.

[0027] Figure 3b It is a structural diagram of a phase change memory cell according to some embodiments of this application.

[0028] Figure 4 It is a step schematic diagram of an operation method of a storage system according to some embodiments of this application.

[0029] Figure 5 It is a corresponding schematic diagram of sample thresholds according to some embodiments of this application.

[0030] Figure 6 It is a step schematic diagram of another operation method according to some embodiments of this application.

[0031] Figure 7 It is a schematic diagram of threshold setting in an operation method according to some embodiments of this application.

[0032] Figure 8 It is a further corresponding schematic diagram of sample thresholds according to some embodiments of this application.

[0033] Figure 9 It is a step schematic diagram of yet another operation method according to some embodiments of this application. Detailed implementation manners

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0035] It should be understood that although terms such as first and second can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component without departing from the scope of the present application.

[0036] It should be understood that when a component is described as being "on" another component or "connected" to another component, it can be directly on the other component or connected to the other component, or there can also be inserted components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0037] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically, and / or along a conical surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above, and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive layers and contact layers and one or more dielectric layers.

[0038] It should be noted that the drawings provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the drawings and are not drawn according to the number, shape, and size of the components in actual implementation, the type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0039] In this article, Cartesian coordinates are used to represent directions. Based on the substrate, the "Z" represents the first direction, and the first direction is the direction perpendicular to the substrate; the "X" represents the second direction parallel to the substrate; the "Y" represents the third direction parallel to the substrate and perpendicular to the X.

[0040] First, please refer to Figure 1 , Figure 1A functional schematic block diagram of a storage system provided according to some embodiments of the present application.

[0041] As Figure 1 shown, a storage system 1 provided according to some embodiments of the present application includes a controller 100 and a memory 200; the controller 100 is electrically connected to the memory 200 and is used to control the memory 200. The memory 200 further controls the storage array 10 in the memory through the peripheral circuit 20 in the memory 200, and various operations can be performed on each storage unit (not shown) in the storage array.

[0042] In some embodiments, the storage system 1 can be implemented as, for example, a memory module, a high-end SSD, a high-bandwidth memory (HBM), a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the Peripheral Component Interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a CompactFlash (CF) card, a SmartMedia card, or a Memory Stick, etc.

[0043] As Figure 2 shown, the memory 200 mainly includes a storage array 10 and a peripheral circuit 20 that connects to and controls the storage array 10. The peripheral circuit 20 generally includes at least a row decoder 210, a word line voltage generator 211, a word line driver 212, a column decoder 220, a bit line driver 222, a bit line voltage generator 221, a reference current / voltage generator 261, a sense amplifier comparator 260, and a logic control module 230 that is connected to the foregoing devices and is used to receive operation instructions to control the foregoing devices.

[0044] The row decoder 210 receives a row address signal from the bus 290 and decodes the row address signal to select an addressed word line.

[0045] The word line driver 212 is connected to multiple word lines WL<0:m>, the word line voltage generator 211, and the row decoder 210. The word line driver 212 receives a row address selection signal and a word line drive voltage, and outputs the word line drive voltage to the multiple word lines WL according to the row address selection signal. <m>At least one row of memory cells connected to at least one word line WL.

[0046] The bit line driver 222, the bit line voltage generator 221, and the column decoder 220 belong to the column driving circuit and are connected as Figure 2 shown. The bit line voltage generator 221 and the column decoder 220 are connected to the logic control module 230 to receive the control of the logic control module 230.

[0047] The column decoder 220 receives the column address signal and decodes the column address signal to select the addressed bit line to which the operation target memory cell is connected. The bit line voltage generator 221 generates the voltage required for each selected bit line BL and outputs the set voltage to each corresponding selected bit line BL.

[0048] The bit line driver 222 is connected to multiple bit lines BL, the bit line voltage generator 221, and the column decoder 220. The bit line driver 222 receives the bit line voltage and the column address selection signal, and according to the column address selection signal, outputs the set bit line voltage to the multiple bit lines BL <n>At least one column of memory cells connected to at least one bit line BL.

[0049] The peripheral circuit 20 further includes a sense amplifier comparator 260, a reference current / voltage generator 261, a data latch 270, etc. The sense amplifier comparator 260 is connected to the reference current / voltage generator 261 and multiple bit lines BL<0:n> and is connected to the data latch 270. The sense amplifier comparator 260 is used to compare with the reference value generated by the reference current / voltage generator 261 after receiving the read data when reading data, determine the data stored in the selected memory cell, and then store the data in the data latch 270. Together with the data read from other bit lines, it passes through the input / output interface 280 and is output to the data bus 290 for output.

[0050] Based on the structural design of the peripheral circuit 20 of the above-mentioned memory, the operations of the memory can include an erase operation, a read operation, a programming operation, or a set and reset operation. Moreover, when performing the foregoing various operations, the controller 100 will receive logical address information according to an L2P (logical address to physical address) mapping table, and according to the L2P mapping table, send out the physical address. After receiving the physical address, the peripheral circuit 20 will select appropriate word lines WL and bit lines BL through the row decoder 210 and the column decoder 220, address the memory cells in the memory array 10, and then bias the selected word lines WL and bit lines BL through the word line driver 212 and the bit line driver 222, and then perform various operations on the selected memory cells. Moreover, when addressing, in some embodiments, the logical addresses are arranged in the order of the word line WL and bit line BL addresses. For example, Figure 3a As shown in a memory array, it will first address on a WL, traverse different BLs, and then switch to the next WL for addressing.

[0051] It can be understood that although the memory 200 and the controller 100 are collectively referred to as a storage system here, in some embodiments, the controller 100 can also be integrated with the memory 200 on a single chip. Therefore, the so-called storage system here can actually also be a memory, not limited to the naming of a system.

[0052] Please continue to refer to Figure 3a , Figure 3a FIG. is a circuit diagram showing an example of the memory array 10 as a memory according to some embodiments of the present application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row and multi-column array, and word lines WL and bit lines BL that respectively connect the plurality of memory cells 11 in multiple rows and columns on a plane. Each row of memory cells includes a plurality of memory cells 11 arranged along the row direction. Each column of memory cells includes a plurality of memory cells 11 arranged along the column direction (i.e., the second direction). Figure 3a Only the memory cells of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1 are schematically shown, where n represents any positive integer greater than 2. In fact, the number of rows and columns of memory cells in the memory depends on its storage capacity.

[0053] It should be understood that the memory cells in the memory array can be memory cells of various types of structures, such as floating gate memory cells, nitride layer structure (ONO) memory cells, resistive memory cells (RRAM), phase change structure memory cells (PCM / PCRAM / SOM), etc. This application does not limit this. However, this application is particularly applicable to phase change structure memory cells. Therefore, the phase change structure memory cell PCM will be taken as an example for illustration below, but it should be understood that it is not limited thereto.

[0054] Figure 3a The illustrated memory cell is a phase change memory cell 11. The phase change memory cell 11 includes a bidirectional threshold switch ((Ovonic Threshold Switch, OTS) 111 and a phase change memory cell (PCM cell) 112 connected in series between the word line WL and the bit line BL. The bidirectional threshold switch ((Ovonic Threshold Switch, OTS) 111 and the phase change memory cell (PCM cell) 112 are both composed of phase change materials. However, in some technologies, since the phase change memory cell 112 is used as the threshold setting for data storage, in this embodiment, the two phase change materials in the memory cell 11 are respectively called the bidirectional threshold switch (OTS) 111 and the phase change memory cell (PCM storage cell) 112.

[0055] Figure 3b This is a schematic diagram of the structure of a three-dimensional (3D) memory cell provided by some embodiments of the present application. As Figure 3b shown, the structure of the 3D phase change memory cell provided by some embodiments of the present application includes: a top electrode 11a and a bottom electrode 11b respectively connected to the word line WL in the X direction and the bit line BL in the Y direction, and a phase change memory cell 112, an intermediate electrode 11c, and a bidirectional threshold switch (OTS) 111 located between the top electrode 11a and the bottom electrode 11b in the Z direction. It should be understood that in some embodiments, the intermediate electrode 11c may not be provided. Therefore, the present application is not limited to the structure disclosed herein.

[0056] The phase change memory cell 112 includes one or more phase change materials such as those based on germanium-antimony-tellurium (Ge-Sb-Te, GST), and one example thereof can be Ge2Sb2Te5. The phase change materials currently used more often are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. The phase change material can have a large resistivity contrast between different phases (e.g., crystalline phase and amorphous phase). For example, the phase change material can exhibit a relatively low resistivity in the crystalline phase, but a relatively high resistivity in the amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than that in the crystalline phase.

[0057] When the phase change material is heated, it can switch between different phases to achieve the writing of information (data) (including setting (set) and resetting (reset)). In this embodiment, the electrodes 11a and 11c can heat the phase change memory cell 112 via OTS111 to change the phase of the heated region 112f in the phase change cell 112, thereby reducing the resistance of the phase change memory cell 112 (setting (set)). The top electrode 11a and the bottom electrode 11b are oppositely arranged, and their positions can be interchanged and overlap with the outer bit line BL and word line WL to form a 3D phase change memory.

[0058] In some embodiments, the OTS device is composed of a phase change material such as Ge-Te-As-Si. At this time, the threshold voltage Vth of OTS 111 will be controlled by the applied voltage polarity and change, more specifically, the threshold voltage change ΔVth will occur with the change of the applied voltage polarity. Utilizing this ΔVth, even without the phase change cell 112, setting (set) and resetting (reset) can still be achieved, and the OTS device is independently used as a binary storage device. Therefore, in this example, OTS111 is called a SOM memory cell (selector only memory) or an SSM memory cell (self-selecting memory).

[0059] Therefore, it can be understood that the phase change memory (PCM) described in this application includes various deformed PCMs, such as Xpoint type PCMs, and selector only memories SOM (selector only memory) or SSM (self-selecting memory) composed of the aforementioned OTS, etc., and includes various phase change memories arranged in two-dimensional (2D) and three-dimensional (3D), as well as PCMs with single-pole or multi-level storage.

[0060] Further, in some embodiments of the present application, when performing read and write operations on a certain cell, for example Figure 3a for the storage unit 11(S), a relatively high voltage bias, such as Vhh and Vll, will be applied to the corresponding WLn (word line) and BLn (bit line); for the unselected WLn+1 / n-1 and BLn+1 / n-1, a zero bias or a low bias, such as Vuw and Vub, will be maintained to ensure the non-conducting state.

[0061] Also, by way of example, when, for example, selecting to perform a write operation on Figure 3a the storage unit 11(s), a write voltage Vwrite will be applied to the corresponding BLn (bit line), and a zero bias V0 will be applied to the WLn (bit line); for the unselected adjacent storage units 11(a) and 11(b), a low bias, such as Vwrite / 2, will be applied to the corresponding word line and bit line WLn+1 / n-1 and BLn+1 / n-1.

[0062] For other unselected cells on the same WLn and BLn as the selected storage unit 11(s), although they will not be selected for conduction or writing, there will still be a certain bias voltage across the storage unit 11, and these storage units 11 will have a problem of bias shift. That is, due to the threshold voltage shift of other storage units caused by the operating bias on the same bit line and word line, it is necessary to perform a data refresh operation on the relevant storage units 11 under certain conditions or within a certain period of time.

[0063] In addition, in further research of the present application, it is found that the storage unit 11(a) on the same word line WLn as the selected storage unit 11(s), and the storage unit 11(a) on the same bit line BLn as the selected storage unit 11(s), may have different bias shifts due to different selected storage units at different times. For example, when selecting the storage unit 11(s) or 11(a), the number of times the word line WLn and the bit line BLn are biased is different, and coupled with the different individual bias magnitudes of the word line and the bit line, there will also be different bias shifts between the storage unit 11(a) and the storage unit 11(a). Therefore, it is necessary to further solve this problem.

[0064] In some embodiments, for the problems of bias shift and power-on data retention time, there are those who adopt the method of medium management, that is, by transferring the write position to average the write position. However, such an operation still has the problem of bias shift after multiple writes.

[0065] Therefore, according to some embodiments of the present application, as Figure 4 shown, the present application further provides an operation method for a storage system, including:

[0066] Step S1: Accumulate the number of data write operations for individual memory cells being written, and generate a write accumulation value corresponding to each of the individual memory cells being written;

[0067] Step S2: According to the state of adjacent memory cells of each of the individual memory cells being written, when the write accumulation value reaches a threshold set according to the state, perform a data refresh operation on the adjacent memory cells.

[0068] Specifically, referring to Figure 1 、 Figure 3a 、 Figure 4 and Figure 5 , in Step S1, accumulate the number of data write operations for individual memory cells 11(s) in memory 200 being written, and generate a write accumulation value WCs (write counter) corresponding to each of the individual memory cells 11(s) being written. For example, whenever a write operation is performed on memory cell 11(s), the accumulation value WCs of the memory cell 11(s) to be written is accumulated once. Another example, whenever a write operation is performed on memory cell 11(b), the write accumulation value WCb of the memory cell 11(b) to be written is accumulated once.

[0069] In some embodiments, the initial value of the write accumulation value can be 0 or, for example, 2000. For each data write operation, the write accumulation value of the memory cell 11(s) corresponding to the data write operation is incremented by 1 (with an initial value of 0) or decremented by 1 (with an initial value of, for example, 2000), that is, the write accumulation value can count up or count down. When the initial value is set to 0, for each data write operation, the write accumulation value of the memory cell 11(s) corresponding to the data write operation is incremented by 1. When the initial value is set to be greater than or equal to the threshold described in the previous Step S2, for each data write operation, the corresponding write accumulation value of the memory cell 11(s) performing the data write operation is decremented by 1.

[0070] Also, it can be understood that when the accumulation value counts up by +1, it is easy to understand that the accumulation value is the up-counting value itself; however, when the accumulation value counts down by -1, the number of accumulation operations described here is not equal to the down-counting value itself, but refers to the difference between the down-counting value and the initial value. For example, when the initial value is 2000 or a larger value and counting down, when the down-counting value reaches 500, the so-called number of accumulation operations here refers to 2000 - 500, which is 1500 times, rather than the value 500. In this way, when comparing and judging the multiple accumulation values, the statement "the write accumulation value reaches a threshold set according to the state" can be applied to both the up-counting and down-counting scenarios.

[0071] In step S2, according to the states of the adjacent memory cells (11(a) or 11(b)) of each of the memory cells 11(s) to be written, when the write cumulative value WCs reaches a threshold Cth set according to the state, a data refresh operation is performed on the adjacent memory cells (11(a) or 11(b)). For example Figure 5 As shown, corresponding to state 1 and state 2, different corresponding thresholds of 1000 times and 1500 times are set respectively.

[0072] In some embodiments of the present application, this state 1 may refer to the adjacent memory cell 11(a) on the same word line WLn as the memory cell 11(s) to be written, and state 2 may refer to the adjacent memory cell 11(b) on the same bit line BLn as the memory cell 11(s) to be written. However, as described below, the state may also refer to other states, which will be described later. When state 1 and state 2 respectively represent the adjacent memory cells 11(a) and 11(b) on different address lines as mentioned above, it means that when the write cumulative value WCs of the memory cell 11(s) to be written reaches 1000 times, a data refresh operation is performed on the adjacent memory cell 11(a) on the same word line WLn as the memory cell 11(s) to be written. When the write cumulative value WCs of the memory cell 11(s) to be written reaches 1500 times, a data refresh operation is performed on the adjacent memory cell 11(b) on the same bit line BLn as the memory cell 11(s) to be written.

[0073] Through such an arrangement, it will be possible to more finely process the data refresh operations of the adjacent memory cells on different address lines, and because the write biases of the word line and the bit line are different, it is possible to reduce the excessive data refresh operation on the bit line caused by the data refresh operations of the word line and the bit line being performed simultaneously.

[0074] Figure 6 Further, an operation method of a memory system according to some embodiments of the present application is shown. In Figure 6 the shown operation method, in addition to Figure 4 steps S1 and S2 shown, it further includes:

[0075] Step S0: Set a plurality of corresponding thresholds according to the various states of the adjacent memory cells; and

[0076] Step S3: After performing a data refresh operation on the adjacent memory cells, reset the write cumulative value of the memory cell to be written.

[0077] Specifically, in step S3, after performing a data refresh operation on the aforementioned adjacent memory cells, such as 11(a) or 11(b), the write cumulative value of the written memory cell is reset. In some embodiments, the write cumulative value can be reset after the adjacent memory cells in the word line and bit line directions have been refreshed. In some other embodiments, when the adjacent memory cells have been written before the write cumulative value reaches the threshold, they do not need to be refreshed. In some other embodiments, when the adjacent memory cells have been written before the write cumulative value reaches the threshold, the cumulative number of writes of the adjacent memory cells can be deducted as the cumulative value. Therefore, the so-called refresh here can be set in various ways as needed. The cumulative value can be an upper count or a lower count, and can also be an absolute value or a relative value.

[0078] In step S0, setting a plurality of corresponding thresholds according to various states of the adjacent memory cells 11(a) or 11(b) can include various examples. That is, in addition to the state where the aforementioned adjacent memory cells are different in the adjacent direction (bit line direction or word line direction), various other states can be added, and a plurality of corresponding thresholds Cth are set.

[0079] In some embodiments, the state includes at least one of the position of the adjacent memory cell or the ambient temperature, and the position of the adjacent memory cell includes at least one of the same bit line, the same word line, or the same stack as the written memory cell.

[0080] Specifically, as Figure 7 shown, step S0 can be an example of step S01. That is, according to the state where the adjacent memory cells are different in the adjacent direction (bit line direction or word line direction) on the same bit line or the same word line.

[0081] Again, as Figure 7 shown, step S0 can be an example of step S02. That is, in terms of the position of the adjacent memory cells, in addition to the state where the aforementioned adjacent memory cells are different in the adjacent direction (bit line direction or word line direction) on the same bit line BL or the same word line WL, different threshold settings can also be given according to the stack S (stack) position of the adjacent memory cells 11(a) or 11(b) of the written memory cell 11(s). When there are multiple stacks S, different multiple thresholds Cth are given.

[0082] In some embodiments, the threshold Cth decreases as the data error rate of the stack S increases. That is, for example, if the data error rate of the first stack S1 is relatively high, a lower threshold is set; if the data error rate of the second stack S2 is relatively low, a threshold higher than that of the first stack S1 is set, so that the memory cells in the first stack S1 can be refreshed more quickly for compensation.

[0083] In some embodiments, as Figure 7 shown, the step S0 of setting the corresponding multiple thresholds may be an example of step S03. That is, different multiple thresholds are set according to the different ambient temperatures T of the adjacent memory cells, and the memory is a phase change memory (PCM). That is, when the ambient temperature T of the memory where the written memory cell 11(s) and the adjacent memory cells 11(a) or 11(b) are located changes, different thresholds Cth are given. Therefore, different multiple thresholds are set according to the various ambient temperatures T in which the memory may be placed.

[0084] In some embodiments, the threshold Cth decreases as the ambient temperature T increases. That is, when the ambient temperature T is relatively high, the probability of refreshing should be increased; when the ambient temperature T is relatively low, the probability of refreshing can be decreased.

[0085] In some embodiments, as Figure 7 shown, the step S0 of setting the corresponding multiple thresholds may be an example of step S012. That is, different multiple thresholds Cth are set according to the difference in the stack S where the adjacent memory cells are located and whether the adjacent memory cells and the written memory cell are on the same bit line BL or the same word line WL. That is, in addition to giving different thresholds according to which stack S the memory cell and the adjacent memory cell are in, the threshold Cth of the adjacent memory cells in the same stack is further given different thresholds according to whether they are adjacent in the direction of the bit line BL or the word line WL.

[0086] In some embodiments, as Figure 7 shown, the step S0 of setting the corresponding multiple thresholds may be an example of step S023. That is, different multiple thresholds Cth are set according to the difference in the stack S where the adjacent memory cells are located and the different ambient temperatures T of the adjacent memory cells. In addition to giving different thresholds according to which stack S the memory cell and the adjacent memory cell are in, the threshold of each stack S is further given different thresholds according to the possible ambient temperature T of the adjacent memory cells.

[0087] In some embodiments, as Figure 7 As shown, the step S0 of setting the corresponding multiple thresholds may be an example of step S013, that is, different multiple thresholds Cth are set according to the difference in the ambient temperature T of the adjacent memory cells and whether the adjacent memory cells and the memory cell to be written are on the same bit line BL or on the same word line WL.

[0088] In some embodiments, as Figure 7 shown, the step S0 of setting the corresponding multiple thresholds may be an example of step S0123, that is, different multiple thresholds Cth are set according to the difference in the stack S where the adjacent memory cells are located, the difference in the ambient temperature T of the adjacent memory cells, and whether the adjacent memory cells and the memory cell to be written are on the same bit line BL or on the same word line WL.

[0089] Specifically, as Figure 8 shown, various modes and mode combinations are further shown, as well as the thresholds corresponding to various mode combinations. For example, for adjacent cells in the bit line direction, there are different thresholds depending on whether they are in stack 1 (S1) or stack 2 (S2). For adjacent memory cells in the bit line direction within the same stack S, they are divided into three thresholds according to different ambient temperatures, such as 70 degrees, 40 degrees, and 25 degrees. Thus, adjacent memory cells in the bit line direction are set with six thresholds of 1000, 1500, 2000, 400, 600, and 800 due to different positions and ambient temperatures. In some embodiments, these set values are set in a stack table and stored in a memory.

[0090] As Figure 8 shown, adjacent memory cells in the word line direction are also set with 6 thresholds, but the thresholds for each relative position and temperature are different from those in the bit line direction. For example, for stack S2, the thresholds in the bit line direction are higher than those in the word line direction, but for stack S1, the thresholds in the bit line direction are lower than those in the word line direction. That is, various modes can be set according to the actual situation.

[0091] In some embodiments, the operation method further includes:

[0092] Step S11: Receiving information about the ambient temperature of the memory as information about the ambient temperature of the adjacent memory cells, and

[0093] Step S12: Selecting, according to the ambient temperature information, the threshold set according to the mode from the multiple thresholds.

[0094] Specifically, as Figure 9 As shown, after step S0 or step S1, step S11 is performed to receive information on the ambient temperature T of the memory 200 as the information on the ambient temperature T of the adjacent memory cells; then, step S12 is performed to select, from the multiple thresholds, the threshold set according to the mode based on the ambient temperature T. It can be understood that the actual ambient temperature may not exactly match the preset temperature. In this case, the closest set temperature is taken as the mode. For example Figure 8 the ambient temperature settings shown are only 70, 40, and 25 degrees. If the actual measurement result is 50 degrees, the closer 40 degrees is taken as the ambient temperature mode, and then, based on the 40-degree ambient temperature, the threshold suitable for the mode is selected.

[0095] Through the operation method of the storage system provided by the present application, write interference can be managed more precisely, the sacrifice of system performance caused by WD media management can be optimized to the greatest extent, the influence of bias drift on memory cells can be reduced, read errors caused by excessive bias-induced drift can be prevented, and the power-on data retention time can be increased.

[0096] According to the operation method of the storage system provided by some of the foregoing embodiments, some embodiments of the present application also correspondingly provide a storage system as shown in Figure 1 and FIG. 3, including:

[0097] A memory 200, including a memory array 10 composed of multiple memory cells 11; and

[0098] A controller 100, electrically connected to the memory 200, for controlling the memory 200, and the controller 100 is configured to execute the foregoing various steps, including steps S0 to S3, steps S11 and S12, and steps S01, S02, S03, S012, S023, S013, S0123, etc.

[0099] The operations of these configurations have been described in the corresponding operation methods described above and can be implemented in conjunction with the software and firmware of the controller. Therefore, they will not be repeated here. For specific content, please refer to the foregoing description.

[0100] Through the storage system disclosed in the present application, the beneficial effects corresponding to the various operation methods and configurations described above can also be achieved, that is, not only can the influence of bias drift be reduced, which helps to reduce the problem of bias drift, thereby supporting a longer power-on data retention time.

[0101] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.< / n> < / m>

Claims

1. A method for operating a storage system, characterized in that, The operation method includes: accumulating the number of data write operations of individual memory cells written in the memory to generate a write accumulation value corresponding to each of the individual written memory cells; and performing a data refresh operation on the adjacent memory cells when the write accumulation value reaches a threshold set according to the state of the adjacent memory cells of each of the individual written memory cells.

2. The operating method according to claim 1, characterized in that, The operation method further includes setting a corresponding plurality of the thresholds according to various states of the adjacent memory cells.

3. The operating method according to claim 2, characterized in that, The state includes at least one of the position of the adjacent memory cells or the ambient temperature.

4. The operating method according to claim 3, characterized in that, The position of the adjacent memory cells includes at least one of being on the same bit line, the same word line, or the same stack as the written memory cell.

5. The operating method according to claim 4, characterized in that, The step of setting the corresponding plurality of the thresholds includes setting different ones of the plurality of thresholds according to whether the adjacent memory cells and the written memory cell are on the same bit line or the same word line.

6. The operating method according to claim 4 or 5, characterized in that, The step of setting the corresponding plurality of the thresholds further includes setting different ones of the plurality of thresholds according to the difference in the stack where the adjacent memory cells are located.

7. The operating method according to claim 4 or 5, characterized in that, The step of setting the corresponding plurality of the thresholds includes setting different ones of the plurality of thresholds according to the difference in the ambient temperature of the adjacent memory cells, and the memory is a phase change memory (PCM).

8. The operating method according to claim 7, wherein, The step of setting the corresponding plurality of the thresholds includes setting different ones of the plurality of thresholds according to the difference in the stack where the adjacent memory cells are located.

9. The operating method according to claim 7, characterized in that, The operation method further includes: receiving information about the ambient temperature of the memory as the information about the ambient temperature of the adjacent memory cells, and selecting the threshold set according to the state from the plurality of thresholds according to the ambient temperature information.

10. The operating method according to claim 1, characterized in that, The operation method further includes: after performing the data refresh operation on the adjacent memory cells, resetting the write accumulation value of the written memory cell.

11. A storage system, characterized in that, The storage system includes: a memory; and a controller connected to the memory for controlling the memory, and the controller is configured to execute the operation method according to any one of claims 1 to 10.

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