Result storage device and method of ATE (automatic test equipment)

Abstract

The invention discloses a result storage device and method of ATE test equipment. The storage device comprises a test result generation module, a mode selection module, a parallel storage management module and a DDR storage array. The test result generation module is used for sampling and judging the multiple channels and generating test results of the multiple DUTs. And the mode selection module stores the test result of the DUT in the DDR storage array through a coverage mode or a holding mode. And the parallel storage management module configures a parallel storage mode according to the test results of the DUT in different application scenarios, and performs multi-cycle parallel storage on the test results of the DUT. And the DDR storage array is used for storing the test result of the DUT. By arranging the mode selection module and the parallel storage management module, efficient storage and flexible management of test results are achieved, and the overall performance of the ATE test equipment is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of automated testing of digital integrated circuits, and particularly to a result storage device and method for an ATE test device. Background Art

[0002] In the field of integrated circuit testing, an ATE (Automatic Test Equipment) needs to simultaneously test a large number of DUTs (Devices Under Test) and store the test results. With the continuous progress of integrated circuit manufacturing processes, the integration and complexity of a single chip are constantly increasing, and the corresponding test items and data volume are also showing an explosive growth. As a result, the current storage method has problems with low data processing efficiency when facing parallel testing of multiple DUTs.

[0003] First of all, the current test result storage system lacks a flexible storage mode switching mechanism. During the actual testing process, the storage requirements for test results vary greatly for different test items. For example, in reliability testing, historical test data needs to be retained for cumulative analysis, while in functional testing, the latest test results need to be updated quickly. Due to the inability to flexibly switch the storage mode according to actual needs, the test efficiency is reduced, and the requirements of different test scenarios cannot be met.

[0004] Secondly, existing storage management schemes often adopt a fixed storage unit allocation method and cannot dynamically adjust storage resources according to different numbers of DUTs. During the actual testing process, the number of test objects may change at any time. Sometimes 16 DUTs need to be tested simultaneously, and sometimes only 2 - 4 DUTs may need to be tested. This rigid storage architecture results in low utilization of storage resources and is difficult to adapt to the dynamic changes in the test scale. Especially during large-scale parallel testing, the fixed storage allocation method will lead to waste or shortage of storage resources.

[0005] Thirdly, in the process of writing data in traditional test result storage schemes, data congestion often occurs due to the lack of an efficient data management mechanism, affecting the overall performance of the test device. For example, during high-speed testing, a large amount of test data floods into the storage system simultaneously. Due to the lack of an effective data buffering and scheduling mechanism, data write delays or losses are likely to occur. For test data that needs to be accessed frequently, the existing technology lacks an effective cache management mechanism, resulting in repeated reading and writing of DDR (Double Data Rate Synchronous Dynamic Random Access Memory) memories for duplicate data, reducing the data access efficiency and increasing the system power consumption.

[0006] Finally, in terms of the use of DDR storage resources, the existing technologies often adopt a simple sequential writing method, without fully considering the hardware characteristics and access patterns of DDR memories. This approach not only fails to maximize the performance of DDR memories but also wastes storage bandwidth due to frequent random accesses. Meanwhile, the lack of effective address management and data organization methods during data storage results in low retrieval and analysis efficiency of test results. Summary of the Invention

[0007] The objective of the present invention is to provide a result storage device and method for an ATE test device, so as to solve the existing technical problems such as low data processing efficiency, single storage mode, and low storage resource utilization rate.

[0008] To solve the above technical problems, the present invention provides a result storage device and method for an ATE test device. The storage device includes: a test result generation module, a mode selection module, a parallel storage management module, and a DDR storage array;

[0009] The test result generation module is used to sample and judge multiple channels, group the channel test results according to DUTs, and synchronously generate test results of multiple DUTs;

[0010] The mode selection module is connected to the output end of the test result generation module, and stores the test results of the DUTs in the DDR storage array in different modes;

[0011] The input end of the parallel storage management module is connected to the output end of the mode selection module, and stores the test results of the DUTs in the DDR storage array in different modes;

[0012] The parallel storage management module, with its input end connected to the output end of the mode selection module, supports the test results of all DUTs and configures parallel storage modes according to the test results of DUTs in different application scenarios;

[0013] The DDR storage array is connected to the output end of the parallel storage management module and is used to store the test results of the DUTs;

[0014] Among them, the mode selection module includes an overwrite mode and a hold mode. The overwrite mode directly overwrites and writes the latest test data into the DDR storage array, and the hold mode merges the original test results and writes the results of multiple cycles as an overall result into the DDR storage array;

[0015] The parallel storage management module includes multiple parallel storage modes and stores the test results of the DUTs in a multi-cycle parallel manner.

[0016] Further, the test result generation module includes:

[0017] A plurality of P / F storage units, each of which is connected to a test channel and temporarily stores the pass / fail results generated by the test channel;

[0018] A channel selection configuration unit, connected to the P / F storage unit, and correspondingly configures the test channel and the DUT type;

[0019] A result mode configuration unit for configuring the storage mode of the test results;

[0020] A DUT result generation unit, connected to the P / F storage unit and the result mode configuration unit, for generating the final DUT test results and outputting the DUT results.

[0021] Further, the coverage mode includes:

[0022] A first high-speed data FIFO, connected to the output end of the test result generation module;

[0023] A dynamic pointer, connected to the first high-speed data FIFO;

[0024] A high-speed block address continuous write controller, connected to the output end of the dynamic pointer, for batch writing test result data;

[0025] A random address direct write controller, connected to the first high-speed data FIFO, for single-point writing test result data.

[0026] Further, the hold mode includes:

[0027] An on-chip overlay part, connected to the output end of the test result generation module;

[0028] A second high-speed data FIFO, connected to the output end of the on-chip overlay part;

[0029] A cache part, connected to the output end of the second high-speed data FIFO.

[0030] Further, the cache part includes:

[0031] A current result cache part, connected to the output end of the second high-speed data FIFO;

[0032] A DDR paging cache part, bidirectionally connected to the output end of the current result cache part and the DDR storage array.

[0033] Further, the parallel storage mode includes:

[0034] 16 DUT parallel storage mode, each DDR storage unit stores 1 result data;

[0035] 8 DUT parallel storage mode, each DDR storage unit stores 2 result data;

[0036] 4 DUT parallel storage mode, each DDR storage unit stores 4 result data;

[0037] 2 DUT parallel storage mode, each DDR storage unit stores 8 result data.

[0038] A method for storing results of an ATE test device, comprising the following steps:

[0039] Collect DUT test results: Test multiple DUTs through a test result generation module and collect the test results;

[0040] Select a storage mode: Select a overwrite mode or a keep mode to store the DUT test results according to the test requirements;

[0041] Configure parallel storage: Select a corresponding parallel storage mode according to the DUT test results for data storage.

[0042] Further, the collecting of the DUT test results includes:

[0043] Connect the channels of the ATE test device to the DUT pins through multiple groups of cables;

[0044] Store the pass / fail results generated by the test channels into the P / F storage unit;

[0045] Configure the test channels and the DUT types through a channel selection configuration unit, synchronously sample and judge multiple channels;

[0046] Group the channel test results by DUT, synchronously generate and output the test results of multiple DUTs.

[0047] Further, the selecting of the storage mode includes:

[0048] In the overwrite mode:

[0049] Store the test results into the first high-speed data FIFO, point to the data in the first high-speed data FIFO through a dynamic pointer, and then batch write the test result data through a high-speed block address continuous write controller;

[0050] Or, store the test results into the first high-speed data FIFO, and perform single-point data writing through a random address direct write controller;

[0051] In the hold mode: The test results are superimposed through the on-chip superimposing part, and the superimposed data is stored in the second high-speed data FIFO. When the data in the second high-speed data FIFO accumulates to the capacity of one page, the data of this page is temporarily stored in the current result cache part, and data interaction is performed between the DDR paging cache part and the DDR storage array.

[0052] Further, the configured parallel storage includes:

[0053] When the number of DUTs detected is from 9 to 16, the 16-DUT parallel storage mode is selected, and each DDR storage unit stores 1 result data;

[0054] When the number of DUTs detected is from 5 to 8, the 8-DUT parallel storage mode is selected, and each DDR storage unit stores 2 result data;

[0055] When the number of DUTs detected is from 2 to 4, the 4-DUT parallel storage mode is selected, and each DDR storage unit stores 4 result data;

[0056] When the number of DUTs detected is from 0 to 1, the 2-DUT parallel storage mode is selected, and each DDR storage unit stores 8 result data.

[0057] Compared with the prior art, the present invention has at least the following beneficial effects:

[0058] By setting the mode selection module and the parallel storage management module, the present invention realizes the efficient storage and flexible management of test results; the configurations of the coverage mode and the hold mode meet the requirements of different test scenarios, the dynamic adjustment of the parallel storage mode improves the utilization rate of storage resources, and the settings of the high-speed data FIFO and the cache part solve the data congestion problem, significantly improving the overall performance of the ATE test equipment.

[0059] Further, by adopting a dynamic pointer and different write controllers, combined with the on-chip superposition and multi-level cache mechanism, the data write speed and access efficiency are effectively improved; the configurations of multiple parallel storage modes realize the reasonable allocation of storage resources, meet the requirements of different-scale DUT tests, and at the same time optimize the hardware utilization efficiency of the DDR memory. Description of the Drawings

[0060] Figure 1 It is the overall structural block diagram of the storage device in an embodiment of the present invention;

[0061] Figure 2 It is the structural block diagram of the result generation module of the storage device in an embodiment of the present invention;

[0062] Figure 3Structural block diagram of the storage device coverage mode in an embodiment of the present invention;

[0063] Figure 4 Structural block diagram of the storage device hold mode in an embodiment of the present invention;

[0064] Figure 5 Structural block diagram of the storage device parallel storage mode in an embodiment of the present invention.

[0065] Reference numerals in the drawings: 1, test result generation module; 11, P / F storage unit; 12, channel selection configuration unit; 13, result mode configuration unit; 14, DUT result generation unit; 2, mode selection module; 21, coverage mode; 211, first high-speed data FIFO; 212, dynamic pointer; 213, high-speed block address continuous write controller; 214, random address direct write controller; 22, hold mode; 221, on-chip superposition part; 222, second high-speed data FIFO; 223, cache part; 2231, current result cache part; 2232, DDR paging cache part; 3, parallel storage management module; 4, DDR storage array. Detailed implementation manners

[0066] The result storage device and method of an ATE test device of the present invention will be described in more detail below with reference to the schematic diagrams, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the present invention.

[0067] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present invention will be clearer according to the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0068] Embodiment 1

[0069] As Figures 1 to 5 shown, an embodiment of the present invention provides a result storage device and method of an ATE test device. The storage device includes a test result generation module 1, a mode selection module 2, a parallel storage management module 3, and a DDR storage array 4.

[0070] Specifically, as Figure 1As shown, the test result generation module 1 is used to sample and judge multiple channels, group the channel test results according to the DUTs, and synchronously generate the test results of multiple DUTs. The test result generation module 1 connects the channels of the ATE test equipment to the DUT pins through multiple groups of cables, making full use of the parallel expansion ability of the programmable logic device, that is, the ability to support multi-channel and multi-DUT parallel testing, sampling and judging multiple channels simultaneously, grouping the channel test results according to the DUTs, and synchronously generating the test results of multiple DUTs, significantly improving the efficiency.

[0071] The mode selection module 2 is connected to the output end of the test result generation module 1, and stores the test results of the DUTs in the DDR storage array 4 in different modes.

[0072] Among them, the mode selection module 2 includes an overwrite mode 21 and a hold mode 22. The overwrite mode 21 directly overwrites and writes the latest test data into the DDR storage array 4. The hold mode 22 combines the original test results and combines the results of multiple cycles into an overall result and writes it into the DDR storage array 4, enabling the mode selection module 2 to select the overwrite mode 21 or the hold mode 22 to store the test results according to the test requirements, meeting the needs of different test scenarios through flexible mode switching, thereby shortening the test time and improving the production efficiency.

[0073] The input end of the parallel storage management module 3 is connected to the output end of the mode selection module 2, supports the test results of all DUTs, and configures the parallel storage mode according to the test results of the DUTs in different application scenarios. Among them, the parallel storage management module 3 includes multiple parallel storage modes, and can perform multi-cycle parallel storage on the test results of the DUTs. The parallel storage management module 3 configures the corresponding parallel storage mode according to the actual DUT test results, enabling dynamic allocation of storage resources and saving resources.

[0074] The DDR storage array 4 is connected to the output end of the parallel storage management module 3 and is used to store the test results of the DUTs. The DDR storage array 4 is composed of multiple groups of DDR storage chips and uses multiple groups of access interfaces for parallel access. In the case of multi-DUT parallel storage of results, it can fully ensure the throughput bandwidth of data access and support the ECC (error checking and correction) function to ensure the accuracy of data storage, so that data can be accessed and managed at high speed.

[0075] In this embodiment, as Figure 2As shown in the figure, the test result generation module 1 includes a plurality of P / F storage units 11, a channel selection configuration unit 12, a result mode configuration unit 13, and a DUT result generation unit 14. Each of the plurality of P / F storage units 11 is connected to a test channel and temporarily stores the pass / fail results (i.e., Figure 2 the pass / fail in

[0076] ) generated by the test channel, facilitating the stable acquisition of correct test results during subsequent channel selection.

[0077] Specifically, the channel selection configuration unit 12 is connected to the P / F storage unit 11 to correspondingly configure the test channel and the DUT type. The channel selection configuration unit 12 is a dynamically configurable unit that can be flexibly matched according to the test requirements of different DUT types. Since the number of channels, channel attributes, and result acquisition sites used in the test scenarios of different DUTs are different, the channel selection configuration unit 12 needs to dynamically configure specific channel attributes and accurately select the corresponding channel test results according to the specific test requirements of the DUT and the pin connection situation, making the test results more accurate and effective.

[0078] The result mode configuration unit 13 is used to configure the storage mode of the test results. The result mode configuration unit 13 further configures the storage mode required for DUT results and can flexibly set the storage format and method of the test results according to different test requirements and application scenarios. For example, the result mode configuration unit 13 can merge 8-bit test results into one byte for storage, or compress and store the results of multiple test cycles to reduce the occupation of storage space. In addition, it also supports the selection of the storage order of MSB (most significant bit first) or LSB (least significant bit first) to adapt to different data processing requirements. This flexible mode configuration can not only meet the diverse requirements for storage methods in different test scenarios but also facilitate subsequent automated analysis and processing. For example, when repairing the damaged area of the DUT, a suitable storage mode can quickly locate and extract relevant test data, thereby improving the repair efficiency. At the same time, for the data analysis and mining of a large number of test results, a reasonable storage format can significantly improve the efficiency and accuracy of data processing and provide strong support for in-depth analysis.

[0079] Specifically, the DUT result generation unit 14 formats the test results according to the configured mode (such as data compression, bit-width merging, storage order, etc.) to ensure that the generated final result data meets the requirements of subsequent storage and analysis. After the processing is completed, the DUT result generation unit 14 outputs the standardized DUT test results, providing accurate and efficient data support for subsequent result storage, data analysis, fault diagnosis, and other operations.

[0080] In this embodiment, as Figure 3 shown, the coverage mode 21 includes a first high-speed data FIFO 211, a dynamic pointer 212, a high-speed block address continuous write controller 213, and a random address direct write controller 214.

[0081] The first high-speed data FIFO 211 is connected to the output end of the test result generation module 1 and is used to cache the key components of the DUT test results generated during the test process, so that the test data will not be lost before reaching the DDR storage array 4. The dynamic pointer 212 is connected to the first high-speed data FIFO 211, so that it can continuously query the data volume in the first high-speed data FIFO 211 and dynamically record the data volume in the first high-speed data FIFO 211. The high-speed block address continuous write controller 213 is connected to the output end of the dynamic pointer 212 and is used to batch-write the test result data. The random address direct write controller 214 is connected to the first high-speed data FIFO 211 and is used to single-point write the test result data.

[0082] In the high-speed mode, the dynamic pointer 212 continuously monitors the data volume in the first high-speed data FIFO 211 and real-time records the filling state of the FIFO. When the DDR storage array 4 allows writing, the high-speed block address continuous write controller 213 writes the result data in the high-speed data FIFO into the DDR storage array 4 at one time according to the data volume recorded by the dynamic pointer 212. The process of writing the result data in the high-speed data FIFO into the DDR storage array 4 at one time is continuously repeated until the entire test process is completed.

[0083] In the random mode, since the addresses written to the DDR storage array 4 are randomly generated, the random address direct write controller 214 reads the data from the first high-speed data FIFO 211 one by one and writes each test result one by one when the DDR storage array 4 allows writing. The process of writing each test result one by one will continue until the test process ends and the data in the FIFO is completely read and written into the DDR storage array 4.

[0084] In this embodiment, as Figure 4As shown, the holding mode 22 includes an in-chip superposition part 221, a second high-speed data FIFO 222, and a cache part 223.

[0085] The in-chip superposition part 221 is connected to the output end of the test result generation module 1. The in-chip superposition part 221 is used for in-chip superposition of result data with the same address. The in-chip superposition part 221 uses SRAM (Static Random Access Memory) as the buffer area. This storage method has the characteristics of small access latency and large data throughput, and is very suitable for the superposition operation of result data. However, due to the limited capacity and high cost of SRAM, it is mainly used for the superposition of a small amount of data, and the storage of massive data still depends on DDR memory chips.

[0086] The second high-speed data FIFO 222 is connected to the output end of the in-chip superposition part 221. The second high-speed data FIFO 222 serves as a buffer between the system clock domain and the DDR access clock domain, and is used to temporarily store the data completed by the in-chip superposition part 221. These data enter the second high-speed data FIFO 222 for standby with the system clock as a reference. When the next-level processing module, that is, the second high-speed cache module, needs to use it, it will obtain the data from the FIFO with the DDR access clock as a reference and convert it to the DDR access clock domain to complete the subsequent result storage operation.

[0087] The cache part 223 is connected to the output end of the second high-speed data FIFO 222, and is used to store the historical results of the DDR storage array 4 and match the paging configuration of the in-chip superposition part 221.

[0088] Furthermore, the cache part 223 includes a current result cache part 2231 and a DDR paging cache part 2232. The current result cache part 2231 is connected to the output end of the second high-speed data FIFO 222. The DDR paging cache part 2232 is bidirectionally connected to the output end of the current result cache part 2231 and the DDR storage array 4.

[0089] The superimposed result data obtained by the cache part 223 from the second high-speed data FIFO 222 is stored in the current result cache part 2231 in a paged form. Different from the on-chip superimposition part 221, the data superimposed by the cache part 223 is the historical result data from the DDR storage array 4. When the result data is obtained from the second high-speed data FIFO 222, the historical data of the corresponding page in the DDR storage array 4 is read at one time according to the address information carried by the data, and is filled into the DDR page cache part 2232 for standby. The result data within the paging address range is continuously filled into the current result cache part 2231 until a new paging address appears. At this time, the DDR storage array 4 continuously reads the data in the current result cache part 2231 and the DDR page cache part 2232 at the same time, superimposes the result data and rewrites it into the corresponding page of the DDR storage array 4. After the writing is completed, the new paging historical data is immediately read from the DDR storage array 4 and written into the DDR page cache part 2232 for the data superimposition operation of the next page. During the entire DDR access process, the unprocessed result data is temporarily stored in the second high-speed data FIFO 222 to avoid data loss.

[0090] In this embodiment, the parallel storage mode includes 16 DUT parallel storage mode, 8 DUT parallel storage mode, 4 DUT parallel storage mode and 2 DUT parallel storage mode, so as to increase the space utilization rate of the DDR storage array 4 and make the storage resources be flexibly scheduled. It should be noted that the parallel storage mode only manages the style of storing the result data into the DDR and has no association with the data superimposition function.

[0091] The 16 DUT parallel storage mode evenly distributes the space of the DDR storage array 4 to 16 DUTs, and each DDR storage unit stores 1 result data, which is suitable for large-scale parallel testing. The 8 DUT parallel storage mode stores 2 result data in each DDR storage unit, which can improve the storage density. The 4 DUT parallel storage mode stores 4 result data in each DDR storage unit, which can balance the storage efficiency and access speed. The 2 DUT parallel storage mode stores 8 result data in each DDR storage unit, maximizing the utilization rate of the storage space.

[0092] It can be understood that multiple DUT results can be placed in a basic storage unit of a DDR, and each storage unit can correspond to one or more result data entries, which can also be understood as the storage addresses of one or more result data. The DDR space organizes and stores the result data with this storage unit as the smallest structure.

[0093] Taking the 16 DUT parallel storage mode as an example, when the 16 DUT parallel mode is adopted, each DDR storage unit will contain the result data of 16 DUTs and store them in a synchronous parallel manner. However, if less than 16 DUTs are actually used in the ATE test scenario, the storage space corresponding to the unused DUTs will still be occupied, resulting in waste of storage space.

[0094] To improve the utilization efficiency of the storage space, the present invention can dynamically adjust the usage mode of the storage unit according to the actual number of DUTs through a flexible parallel storage management mode, thereby avoiding waste of storage space and significantly improving the space utilization rate of the DDR storage array 4. According to actual application requirements, it can be further extended to other parallel storage modes to meet different test scenarios.

[0095] For example, the 8 DUT parallel mode is applicable to application scenarios where the number of DUTs is between 5 and 8. At this time, each DDR storage unit will store the result data of 2 entries, that is, the result data of 2 groups of DUT1 to DUT8. Compared with the 16 DUT storage mode, the same DDR space can store twice the number of entries of result data.

[0096] The 4 DUT parallel mode is applicable to application scenarios where the number of DUTs is between 2 and 4. At this time, each DDR storage unit will store the result data of 4 entries, that is, the result data of 4 groups of DUT1 to DUT8. Compared with the 16 DUT storage mode, the same DDR space can store four times the number of entries of result data.

[0097] The 2 DUT parallel mode is applicable to the application scenario where the number of DUTs is 2. At this time, each DDR storage unit will store the result data of 8 entries, that is, the result data of 8 groups of DUT1 to DUT8. Compared with the 16 DUT storage mode, the same DDR space can store eight times the number of entries of result data.

[0098] Embodiment 2

[0099] A method for storing the results of an ATE test device includes the following steps:

[0100] Collect DUT test results: Test multiple DUTs through the test result generation module 1 and collect the test results.

[0101] Select a storage mode: Select the overwrite mode 21 or the hold mode 22 to store the DUT test results according to the test requirements.

[0102] Configure parallel storage: Select the corresponding parallel storage mode for data storage according to the DUT test results.

[0103] The storage method performs multi-channel parallel sampling through the test result generation module 1 to improve data acquisition efficiency. By selecting the storage mode, in scenarios such as functional testing where quick result updates are required, the overwrite mode 21 is selected, and high-speed data updates are achieved through the high-speed block address continuous write controller 213; in scenarios such as reliability testing where historical data needs to be retained, the hold mode 22 is selected, and the cumulative analysis of data is realized through the on-chip overlay part 221 and the cache part 223. In addition, by configuring the parallel storage mode, dynamic optimized allocation of storage resources is achieved, enabling the maximum utilization of storage efficiency.

[0104] In this embodiment, the acquisition of DUT test results includes:

[0105] Connect the channels of the ATE test equipment to the DUT pins through multiple groups of cables;

[0106] Store the pass / fail results generated by the test channels into the P / F storage unit 11;

[0107] Configure the test channels and DUT types through the channel selection configuration unit 12, and perform synchronous sampling and judgment on multiple channels;

[0108] Group the channel test results by DUT, and synchronously generate and output the test results of multiple DUTs.

[0109] Taking the case where the DUT pin only contains channel_1.1 as an example, the pass / fail test results generated by channel_1.1 are first temporarily stored in the P / F storage unit 11, and 1 bit of result data is generated in each test cycle. Subsequently, the channel selection configuration unit 12 associates and configures the test results of channel_1.1 with DUT1 to ensure that the test results can be correctly mapped to the corresponding DUT.

[0110] Immediately afterwards, the result mode configuration unit 13 sets the storage mode of the test results. Taking byte storage as an example, it is configured to store the result data once every 8 cycles, that is, the DUT result generation unit 14 will integrate the test results generated within 8 cycles and store them in parallel as one byte. The process of the result mode configuration unit 13 setting the storage mode of the test results not only improves the storage efficiency but also provides a standardized data format for subsequent storage operations.

[0111] Finally, the DUT result generation unit 14 performs parallel storage of the result data once every 8 cycles according to the mode of the result mode configuration unit 13, and reassembles the test results of the DUT for subsequent storage of the result data into the DDR storage array 4.

[0112] The result generation process of other DUTs is similar to that of DUT1, and the result data of all DUTs are generated and processed in a parallel and synchronous manner. In the subsequent result data storage process, the data will be organized and processed according to the entry address, and the entire storage process is also carried out in parallel for multiple DUTs, thereby further improving the storage efficiency and the overall performance of the system.

[0113] Furthermore, the selected storage mode includes an overwrite mode 21 and a hold mode 22.

[0114] In the overwrite mode 21, the test results are stored in the first high-speed data FIFO 211, and the data in the first high-speed data FIFO 211 is pointed to by a dynamic pointer 212. Then, the test result data is batch-written through a high-speed block address continuous write controller 213.

[0115] Alternatively, the test results are stored in the first high-speed data FIFO 211, and single-point data writing is performed through a random address direct write controller 214.

[0116] In the hold mode 22, the test results are superimposed through an on-chip superimposed part 221, and the superimposed data is stored in a second high-speed data FIFO 222. When the data in the second high-speed data FIFO 222 accumulates to the capacity of one page, the data of this page is temporarily stored in the current result cache part 2231, and data interaction is performed with a DDR paging cache part 2232 and a DDR storage array 4.

[0117] Taking the hold mode 22 as an example, after the DUT test result data is generated, it first enters the on-chip superimposed part 221 for address determination. Assuming that the superimposed paging is set to 1024 addresses (i.e., within the address range of 0 to 1023), when the address of the result data is between 0 and 1023, the data will be processed in the on-chip superimposed part 221. The on-chip superimposed part 221 will perform a superimposing operation on the result data with the same address and continuously write the superimposed result data into the second high-speed data FIFO 222.

[0118] When there is data in the second high-speed data FIFO 222, the current result cache part 2231 will continuously read the data in the second high-speed data FIFO 222 and store it in the cache of the current result cache part 2231. At the same time, when the first result data arrives, the DDR paging cache part 2232 will, according to the address information of the result data, locate the corresponding page in the DDR storage array 4 and read the historical data of this page into the DDR paging cache part 2232 for standby at one time.

[0119] Before the address of the result data exceeds 1023, the entire process will continue, that is: on-chip superposition → the second high-speed data FIFO → the current result cache. During this process, the DDR storage array 4 will not be directly accessed, thereby reducing the number of DDR accesses, and through block address operations, significantly reducing the latency and time consumption of DDR access.

[0120] When the storage address of the result data exceeds 1023, the on-chip superposition part 221 will clear the superposition data of the current page to prevent the original data from interfering with the new page data, and start the superposition process for the new page result data. At this time, the data in the current result cache part 2231 and the DDR page cache part 2232 will be read out synchronously, and the superposition result of the current page will be merged with the historical data in the DDR storage array 4, and the merged data will be rewritten into the corresponding page of the DDR storage array 4.

[0121] After the writing is completed, the DDR page cache part 2232 will read the new historical data from the DDR storage array 4 according to the new page address and update the content in the cache to prepare for the data superposition operation of the next page. During the entire DDR access process, if the data cannot be processed immediately due to DDR operations (such as refreshing, row and column selection, etc.), the second high-speed data FIFO 222 will be used as a buffer to temporarily store these data to ensure that the data will not be lost and wait for the next writing opportunity. By this method, the ATE test device in the hold mode 22 reduces the number of accesses to the DDR storage array 4 through the on-chip superposition and cache mechanisms, and improves the storage efficiency, data integrity and reliability.

[0122] Furthermore, in this embodiment, the configured parallel storage includes:

[0123] When it is detected that the number of DUTs is from 9 to 16, the 16DUT parallel storage mode is selected, and each DDR storage unit stores 1 result data.

[0124] When it is detected that the number of DUTs is from 5 to 8, the 8DUT parallel storage mode is selected, and each DDR storage unit stores 2 result data.

[0125] When it is detected that the number of DUTs is from 2 to 4, the 4DUT parallel storage mode is selected, and each DDR storage unit stores 4 result data.

[0126] When it is detected that the number of DUTs is from 0 to 1, the 2DUT parallel storage mode is selected, and each DDR storage unit stores 8 result data.

[0127] Taking the 8-DUT parallel mode as an example, when the parallel storage management module 3 is configured in this mode, each storage entry contains the result data from 8 DUTs, and the result data of each DUT contains the data of 8 test cycles (defined by the result generation module). In this mode, the spatial storage unit of the parallel storage management module 3 is planned as shown in Figure 5 the storage method shown, that is, each DDR storage unit contains the result data of 2 storage entries, so that the data will be subjected to parallel compression storage once before entering the DDR storage array 4, improving the utilization rate of the space of the DDR storage array 4.

[0128] As the test progresses, new result data will be continuously superimposed on the corresponding pages until the entire test process is completed and all result data are written into the DDR storage array 4. At this time, the final result data stored in the DDR storage array 4 reflects the complete information of the entire test scenario, that is, the test work is all completed.

[0129] In summary, the present invention realizes the efficient storage and flexible management of test results by setting the mode selection module and the parallel storage management module; the configurations of the coverage mode 21 and the hold mode 22 meet the requirements of different test scenarios, the dynamic adjustment of the parallel storage mode improves the utilization rate of storage resources, and the settings of the high-speed data FIFO and the cache part solve the data congestion problem, significantly improving the overall performance of the ATE test equipment.

[0130] Furthermore, by adopting dynamic pointers and different write controllers, combined with the in-chip superposition and multi-level cache mechanisms, the data write speed and access efficiency are effectively improved; the configurations of various parallel storage modes realize the reasonable allocation of storage resources, meet the requirements of different-scale DUT tests, and at the same time optimize the hardware utilization efficiency of the DDR memory.

[0131] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A result storage device for an ATE test equipment, characterized in that, Including: A test result generation module, a mode selection module, a parallel storage management module, and a DDR storage array; The test result generation module is used to sample and judge multiple channels, group the channel test results according to the DUT, and synchronously generate the test results of multiple DUTs; The mode selection module is connected to the output end of the test result generation module, and stores the test results of the DUT in the DDR storage array in different modes; The input end of the parallel storage management module is connected to the output end of the mode selection module, and configures the parallel storage mode according to the test results of the DUT in different application scenarios; Among them, the mode selection module includes an overwrite mode and a hold mode. In the overwrite mode, the latest test data is directly overwritten and written into the DDR storage array. In the hold mode, the original test results are merged, and the results of multiple cycles are merged into an overall result and written into the DDR storage array; The parallel storage management module includes multiple parallel storage modes, and performs multi-cycle parallel storage on the test results of the DUT.

2. The result storage device according to claim 1, wherein The test result generation module includes: Multiple P / F storage units, each of which is connected to a test channel and temporarily stores the pass / fail results generated by the test channel; A channel selection configuration unit, connected to the P / F storage unit, and correspondingly configures the test channel and the DUT type; A result mode configuration unit, used to configure the storage mode of the test results; A DUT result generation unit, connected to the P / F storage unit and the result mode configuration unit, used to generate the final DUT test results and output the DUT results.

3. The result storage device according to claim 1, wherein The overwrite mode includes: A first high-speed data FIFO, connected to the output end of the test result generation module; A dynamic pointer, connected to the first high-speed data FIFO; A high-speed block address continuous write controller, connected to the output end of the dynamic pointer, and used to batch write test result data; A random address direct write controller, connected to the first high-speed data FIFO, and used to single-point write test result data.

4. The result storage device according to claim 1, characterized in that, The hold mode includes: An on-chip superposition part, connected to the output end of the test result generation module; A second high-speed data FIFO, connected to the output end of the on-chip superposition part; A cache part, connected to the output end of the second high-speed data FIFO.

5. The result storage device according to claim 4, wherein The cache part includes: A current result cache part, connected to the output end of the second high-speed data FIFO; A DDR paging cache part, bidirectionally connected to the output end of the current result cache part and the DDR storage array.

6. The result storage device according to claim 1, wherein The parallel storage modes include: 16 DUT parallel storage mode, each DDR storage unit stores 1 result data; 8 DUT parallel storage mode, each DDR storage unit stores 2 result data; 4 DUT parallel storage mode, each DDR storage unit stores 4 result data; 2 DUT parallel storage mode, each DDR storage unit stores 8 result data.

7. A result storage method for an ATE test device, characterized in that, Including the following steps: Collect DUT test results: Test multiple DUTs through a test result generation module and collect the test results; Select storage mode: Select the overwrite mode or the keep mode to store the DUT test results according to the test requirements; Configure parallel storage: Select the corresponding parallel storage mode for data storage according to the DUT test results.

8. The result storage method according to claim 7, characterized in that, The collection of DUT test results includes: Connect the channels of the ATE test equipment to the DUT pins through multiple groups of cables; Store the pass / fail results generated by the test channels into the P / F storage unit; Configure the test channels and the DUT types through a channel selection configuration unit, sample multiple channels synchronously, and make judgments; Group the channel test results by DUT, and synchronously generate and output the test results of multiple DUTs.

9. The result storage method according to claim 7, characterized in that The selection of the storage mode includes: In the overwrite mode: Store the test results into the first high-speed data FIFO, point to the data in the first high-speed data FIFO through a dynamic pointer, and then batch write the test result data continuously through a high-speed block address write controller; Or, store the test results into the first high-speed data FIFO, and perform single-point data writing through a random address direct write controller; In the keep mode: Perform superposition processing on the test results through the in-chip superposition part, store the superposed data into the second high-speed data FIFO. When the data in the second high-speed data FIFO accumulates to the capacity of one page, temporarily store the data of this page in the current result cache part, and perform data interaction between the DDR paging cache part and the DDR storage array.

10. The result storage method according to claim 7, characterized in that, The configuration of parallel storage includes: When the number of detected DUTs is 9 to 16, select the 16DUT parallel storage mode, and each DDR storage unit stores 1 result data; When the number of detected DUTs is 5 to 8, select the 8DUT parallel storage mode, and each DDR storage unit stores 2 result data; When the number of detected DUTs is 2 to 4, select the 4DUT parallel storage mode, and each DDR storage unit stores 4 result data; When the number of detected DUTs is 0 to 1, select the 2DUT parallel storage mode, and each DDR storage unit stores 8 result data.

Images