Embedded power semiconductor package with sidewall contacts

Abstract

A method of forming a semiconductor package includes providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and an adjacent stabilizing metal section; arranging the lead frame on a temporary carrier; arranging a semiconductor die on the temporary carrier within the central opening; forming a dielectric material, the dielectric material filling the central opening and encapsulating the semiconductor die; forming a first recess in the dielectric material over the semiconductor die so as to expose a first surface of the semiconductor die; electrically connecting a terminal of the semiconductor die with the metal frame; and forming exposed external contacts of the semiconductor package by the tie bars.

Description

BACKGROUND OF THE INVENTION

[0001] Semiconductor power device packages are used in many applications such as automotive and industrial applications. A semiconductor power device package may include one or more discrete power semiconductor devices rated to control large voltages and / or currents, such as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), diodes, etc., and in some cases may include driver devices configured to control the discrete power semiconductor devices. Different types of package configurations are used for power applications. One type of package configuration used in power applications is an embedded package. The embedded package embeds the die within a PCB-like structure that both encapsulates the die and provides electrical interconnection to externally accessible bond pads. There is a desire to improve the performance, cost, and manufacturability of embedded packages. SUMMARY OF THE INVENTION

[0002] Disclosed is a method of forming a semiconductor package. According to an embodiment, the method includes: providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connecting the metal frame to adjacent stable metal sections; disposing the lead frame on a temporary carrier; disposing a semiconductor die on the temporary carrier within the central opening; forming a dielectric material that fills the central opening and encapsulates the semiconductor die; forming a first groove in the dielectric material above the semiconductor die to expose a first surface of the semiconductor die; electrically connecting terminals of the semiconductor die to the metal frame; and forming exposed external contacts of the semiconductor package from the tie bars.

[0003] Disclosed is a semiconductor package. According to an embodiment, the semiconductor package includes: a metal frame forming at least a partially enclosed shape around a central opening; cut tie bars connected to the metal frame; a semiconductor die disposed within the central opening; and a dielectric material filling the central opening and encapsulating the semiconductor die, wherein terminals of the semiconductor die are electrically connected to the metal frame, and wherein the semiconductor package includes exposed external contacts of the semiconductor package formed from the cut tie bars. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The elements in the drawings need not be to scale relative to each other. The same reference numerals represent corresponding like parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Embodiments are shown in the drawings and described in detail below.

[0005] Figure 1A and Figure 1B Shows a power semiconductor package according to an embodiment. Figure 1Ashows a cross-sectional perspective view of a power semiconductor package, and Figure 1B shows a side perspective view of the power semiconductor package.

[0006] Figure 2A and Figure 2B shows a power semiconductor package according to an embodiment. Figure 2A shows a cross-sectional perspective view of a power semiconductor package, and Figure 2B shows a side perspective view of the power semiconductor package.

[0007] Figure 3A and Figure 3B shows a power semiconductor package according to an embodiment. Figure 3A shows a cross-sectional perspective view of a power semiconductor package, and Figure 3B shows a side perspective view of the power semiconductor package.

[0008] Figure 4 shows a lead frame for forming a power semiconductor package according to an embodiment.

[0009] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H and Figure 5I shows selected method steps in a method of forming a semiconductor package according to an embodiment.

[0010] Figure 6 The power semiconductor package according to an embodiment is shown by the cross-sectional perspective view. Detailed Description

[0011] Embodiments of a power semiconductor package having a favorable contact configuration and a corresponding method of forming a power semiconductor package are disclosed. The power semiconductor package includes one or more semiconductor dies that are embedded within the package and connected to externally accessible bond pads. The power semiconductor package is formed by providing a metal frame that at least partially surrounds a central opening. The one or more semiconductor dies are disposed within the central opening and encapsulated by a dielectric material. The metal frame provides a cost-effective solution for forming an embedded package structure. The metal frame can be configured as a vertical via structure that provides an electrical connection between a back surface terminal of the semiconductor die and a bond pad disposed on a lower docking side of the semiconductor package. The metal frame is provided by a lead frame structure having ties connected between the metal frame and an adjacent stable structure. Advantageously, the ties that mechanically support the metal frame during package assembly are incorporated into the final package structure and form exposed external contacts of the power semiconductor package. The method advantageously reduces processing costs by eliminating the need to remove the ties or otherwise insulate the ties from the external environment. Additionally, the exposed surface of the tie can advantageously form a so-called LTI (lead tip inspection) feature.

[0012] Reference Figure 1A and Figure 1B , semiconductor package 100 includes a metal frame 102. The metal frame 102 may include a conductive metal such as copper, aluminum, nickel, silver, palladium, gold, etc., and alloys thereof. The metal frame 102 may include a core metal region and one or more plating layers formed on the core metal region for protection, adhesion, corrosion prevention, etc. The metal frame 102 forms at least a partially enclosed shape around a central opening 104. From a planar perspective view of the metal frame 102, the metal frame 102 defines the shape of the central opening 104. The description that the metal frame 102 forms at least a partially enclosed shape refers to the fact that there may be one or more interruptions in the continuity of the metal frame 102 such that the central opening 104 is not completely enclosed by the metal frame 102. For example, as Figure 4 shown, the metal frame 102 forms a partially enclosed shape around the central opening 104, where there is one interruption on one side of the metal frame 102. In other embodiments, there may be multiple interruptions in the metal frame 102. In other embodiments, there may be no interruptions in the metal frame 102, i.e., the metal frame 102 forms a completely enclosed shape around the central opening 104. Assuming that the metal frame 102 abuts at least 50% of the total diameter of the central opening 104 and the remaining diameter of the central opening 104 is defined by an intersecting plane along which the inner edge side of the metal frame 102 extends, the metal frame 102 forms a partially enclosed shape around the central opening 104 within the meaning of this specification.

[0013] Again referenceFigure 1A and Figure 1B , semiconductor package 100 includes a semiconductor die 106 disposed within a central opening 104 of a metal frame 102. Generally, semiconductor die 106 may be configured as any type of device. According to an embodiment, semiconductor die 106 is configured as a power device, i.e., a device rated to accommodate a voltage of 100V (volts), 600V, 1200V or higher and / or rated to accommodate a current of at least 1A (ampere), 10A, 50A, 100A or higher. Examples of such power devices include MOSFETs (metal-oxide-semiconductor field-effect transistors), HEMTs (high electron mobility transistors), IGBTs (insulated-gate bipolar transistors), JFETs (junction field-effect transistors), diodes. Semiconductor die 106 may be formed in any device technology and may include group-IV semiconductor materials (e.g., silicon, silicon germanium, silicon carbide, etc.), and / or group-III-V semiconductor materials (e.g., gallium nitride, gallium arsenide, etc.). According to an embodiment, semiconductor die 106 is configured as a vertical device that is configured to conduct a vertical current between a first load terminal 108 and a second load terminal 110. The first load terminal 108 and the second load terminal 110 are voltage-blocking terminals of the device. For example, the first load terminal 108 and the second load terminal 110 may respectively correspond to the drain terminal and the source terminal of a MOSFET (and vice versa), may correspond to the collector terminal and the emitter terminal of an IGBT (and vice versa), etc. As shown, semiconductor die 106 includes a first surface facing an upper side 112 of semiconductor package 100 and a second surface facing a lower side 114 of semiconductor package 100 (i.e., the side of semiconductor package 100 that mates with an external carrier such as a PCB (printed circuit board)). The first surface of the illustrated semiconductor die 106 corresponds to the back surface of semiconductor die 106 that includes the second load terminal 110, and the second surface of the illustrated semiconductor die 106 corresponds to the main surface of semiconductor die 106 that includes the first load terminal 108 and a gate terminal 116. The gate terminal 116 is configured to control the conductive connection between the first load terminal 108 and the second load terminal 110 in a generally known manner.

[0014] The semiconductor package 100 can be configured to form a power switching device that is part of a power conversion circuit. For example, the semiconductor package 100 can be configured as a high-side switch or a low-side switch of a half-bridge circuit. A half-bridge circuit refers to a type of circuit topology used in power conversion circuits such as DC-to-DC converters, DC-to-AC converters, etc. Instead of the single die configuration shown in the figure, the semiconductor package 100 can have a multi-die configuration. For example, the semiconductor package 100 can include two power semiconductor device dies that respectively form the high-side switch and the low-side switch of the half-bridge circuit. These semiconductor dies can be arranged within the opening of a metal frame or within different openings 104. Individually or in combination, the semiconductor package 100 can include additional semiconductor dies that are not configured as power dies (e.g., low voltage and / or logic devices). For example, the semiconductor package 100 can include a driver die that is arranged within another opening of the metal frame 102 and encapsulated according to the techniques described below, where the driver die is configured to control the switching operation of the semiconductor die configured as a power switching device.

[0015] The semiconductor package 100 includes a dielectric material 118 that fills the central opening 104 and encapsulates the semiconductor die 106. The dielectric material 118 can include a resin material (such as a bismaleimide triazine (BT) resin), a prepreg material (such as FR-4, FR-5, CEM-4), or other types of encapsulation materials. The dielectric material 118 can be formed as part of a lamination process, whereby multiple constituent laminate layers are stacked on top of each other. An example of the lamination process is described below.

[0016] According to an embodiment, at least one of the terminals of the semiconductor die 106 is electrically connected to the metal frame 102. In this way, the metal frame 102 can be used as a via structure that provides an electrical connection between the back surface of the semiconductor die 102 and the lower side 114 of the semiconductor package 100. In the illustrated embodiment, the second load terminal 110 of the semiconductor die 106 is electrically connected to the metal frame 102 and is thus electrically accessible at the lower side 114 of the semiconductor package 100. The semiconductor package 100 includes a first metallization layer 120 formed at the upper side 112 of the semiconductor package 100 and forming an electrical connection between the second load terminal 110 and the metal frame 102. The electrical connection is made possible by forming a groove in the dielectric material 118. Specifically, a first groove 122 is formed in the dielectric material 118 above the back surface of the semiconductor die 106. The second load terminal 110 of the semiconductor die 106 is exposed by the first groove 122. Additionally, a second groove 124 is formed in the dielectric material 118 above the metal frame 102. Each second groove 122 exposes the upper surface of the metal frame 102, thereby allowing a metal connection thereto. The first metallization layer 120 is conformally deposited on the dielectric material 118, thereby forming an electrical connection with the second load terminal 110 and the metal frame 102. The semiconductor package 100 further includes a second metallization layer 126 formed at the lower side 114 of the semiconductor package 100. The second metallization layer 126 is directly formed on the first load terminal 108, the gate terminal 116, and the metal frame 102 and forms separate and externally accessible bond pads of the semiconductor package 100. These bond pads can be mated with an external carrier such as a PCB or a power electronics device substrate (e.g., an AMB (active metal brazing) substrate, an IMS (insulated metal substrate), etc.) by soldering the bond pads to corresponding metal pads, for example. The semiconductor package 100 further includes a solder mask 128 at the lower interface side of the semiconductor package 100 to electrically isolate each bond pad and facilitate direct board mounting of the semiconductor package 100. The solder mask 128 can include a solder resist material such as paint, epoxy resin, a liquid photoimageable solder mask 128, a dry film photoimageable solder mask 128, etc.

[0017] The semiconductor package 100 is configured with exposed external contacts 130 disposed at an outer edge side of the semiconductor package 100. The exposed external contacts 130 extend laterally to a lower side 114 of the semiconductor package 100. The exposed external contacts 130 can be used as LTI (lead tip inspection) features. When the semiconductor package 100 is mounted on an external device such as a printed circuit board, the LTI features allow for optical inspection of the solder joints by exposing the metal-solder interface at the outer edge of the package. Individually or in combination, when the semiconductor package 100 is mounted on an external carrier, the exposed external contacts 130 can provide additional electrical contact points that can be used for electrical contact with the external environment.

[0018] According to an embodiment, the external contact 130 is formed by a tie bar 132. The tie bar 132 is a metal structure for mechanically supporting the metal frame 102 during package construction and prior to encapsulation. As Figure 4 shown, the semiconductor package 100 can be produced from a lead frame 200 that includes a plurality of metal frames 102, each metal frame defining one of the central openings 104. A plurality of tie bars 132 extend between each of the metal frames 102 and adjacent stable metal sections of the lead frame 200.

[0019] Embodiments disclosed herein configure the semiconductor package 100 such that at least a portion of the tie bar 132 remains intact, i.e., the tie bar 132 is not trimmed or otherwise completely removed. The remaining portion of the tie bar 132 is exposed at the outer edge side of the semiconductor package 100, thereby forming the exposed external contact 130 that extends laterally to the lower interface side of the semiconductor package 100. According to an embodiment, the exposed external contact 130 includes the sidewall surfaces of the tie bar 132. These sidewall surfaces can correspond to the surfaces of the tie bar 132 that are cut (e.g., etched, laser ablated, mechanically drilled, etc.) during the package singulation process, as will be described in further detail below. Alternatively, these sidewall surfaces can correspond to the surfaces of the tie bar 132 that are etched prior to package singulation, as will be described in further detail below. As Figure 1B shown, the outer edge side of the semiconductor package 100 can include a plurality of external contacts 130 provided by individual tie bars 132, where each of these individual tie bar 132 structures forms a connection with an internally disposed metal frame 102.

[0020] According to an embodiment, the exposed external contact 130 additionally includes the lower surface of the tie bar 132 that intersects the sidewall surfaces of the tie bar 132. For example, as Figure 1AAs shown, the lower surface of the tie bar 132 extends to the outer edge side of the semiconductor package 100 and intersects the side wall surface of the tie bar 132 that extends laterally to the lower side 114 of the semiconductor package 100. In this way, the tie bar 132 can form a complete LTI feature of the semiconductor package 100, thus allowing inspection at the corners of the package terminals.

[0021] Reference Figure 2A and Figure 2B , a semiconductor package 100 according to an embodiment is shown. The semiconductor package 100 is similar to Figure 1A and Figure 1B 's semiconductor packages, except that the tie bar 132 is thinner than the metal frame 102 surrounding the central opening 104. In this case, the lead frame 200 used to form the semiconductor package 100 has been processed to remove metal from the tie bar portion of the lead frame 200. Therefore, the exposed external contacts 130 formed by the tie bar 132 of the semiconductor package 100 have a smaller vertical extension, for example, as Figure 2B shown. The dielectric material 118 is formed above the tie bar 132 with reduced thickness, thus maintaining the shape of the semiconductor package 100.

[0022] Reference Figure 3A and Figure 3B , a semiconductor package 100 according to an embodiment is shown. The semiconductor package 100 is similar to Figure 2A and Figure 2B 's semiconductor packages, except that the tie bar 132 has been processed by an etching process before the package monolithization step. Therefore, the external contacts 130 formed by the tie bar 132 of the semiconductor package 100 correspond to the etched surface of the tie bar 132. As shown, these etched surfaces can have a curved shape and produce indentations at the lower outer corners of the etched surface. This curved shape of the exposed external contacts 130 can enhance solderability and / or lead tip inspection.

[0023] Reference Figure 4, shows a lead frame 200 for forming a plurality of semiconductor packages 100 according to an embodiment. The lead frame 200 may be provided by a metal sheet of a conductive metal such as copper, aluminum, nickel, silver, palladium, gold, etc., and their alloys. The lead frame 200 may include a core metal region and one or more plating layers on the core metal region for protection, adhesion, corrosion prevention, etc. The geometry of the lead frame 200 may be generated by metal processing techniques (e.g., stamping, punching, cutting, etc.). As shown, the lead frame 200 includes a plurality of metal frames 102, each metal frame defining one of the central openings 104. Each metal frame 102 is physically connected to an adjacent stable metal section by a tie bar 132. The adjacent stable metal sections may refer to the peripheral structure of the lead frame 200 adjacent to the outermost metal frame among the metal frames 102. The adjacent stable metal sections may also refer to adjacent metal frames that are adjacent to each other in the metal frame 102. The tie bar 132 maintains the structural integrity of the lead frame 200 during processing and before package monomerization.

[0024] Reference Figures 5A to 5I , shows selected method steps for forming a semiconductor package 100 according to various embodiments. Each figure shows a first package component 200 on the left side of the figure, a second package component 202 in the center of the figure, and a third package component 204 on the right side of the figure. The method steps performed on the first package component 200 can be used to produce the semiconductor package 100 described in Reference Figure 1A and Figure 1B . The method steps performed on the second package component 202 can be used to produce the semiconductor package 100 described in Reference Figure 2A and Figure 2B . The method steps performed on the third package component 204 can be used to produce the semiconductor package 100 described in Reference Figure 3A and Figure 3B .

[0025] Referring to Figure 5A , a lead frame 200 is provided. The lead frame 200 may correspond to Reference Figure 4The described lead frame 200. The first encapsulation component 200, the second encapsulation component 202, and the third encapsulation component 204 each show a cross-section of an encapsulation site from the lead frame 200, which has one of the metal frames 102 and a corresponding tie bar 132 connected to the metal frame 102. In the case of the first encapsulation component 200, the lead frame 200 is provided with a tie bar 132 and a metal frame 102 having the same thickness. In the case of the second encapsulation component 202 and the third encapsulation component 204, the lead frame 200 is provided such that the tie bar 132 has a reduced thickness compared to the metal frame 102. For example, a semi-etching step can be performed on the lead frame 200. Semi-etching refers to a technique in which a metal structure such as a lead frame is partially etched to selectively reduce the thickness of the structure in certain features. Generally, the semi-etching step can reduce the thickness of the lead frame 200 by at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, etc. Thus, the thickness of the tie bar 132 can be at least 70%, at least 60%, at least 50%, at least 40%, at least 30%, etc. of the metal frame 102.

[0026] Reference Figure 5B , the lead frame 200 is placed on the temporary carrier 202. Generally, the temporary carrier 202 can be any flat surface suitable for processing and transferring electronic components through various semiconductor processing tools. In one example, the temporary carrier 202 includes a thermal release tape.

[0027] Reference Figure 5C , the semiconductor die 106 is disposed on the temporary carrier 202. The semiconductor die 106 is placed within the central opening 104 of the metal frame 102 and is spaced from the metal frame 102 in each direction. The semiconductor die 106 can have any device configuration as described above.

[0028] Reference Figure 5D , a dielectric material 118 is formed to fill the central opening 104 of the metal frame 102 and encapsulate the semiconductor die 106. As shown, the dielectric material 118 is formed to fill the lateral space between the semiconductor die 106 and the metal frame 102. Additionally, the dielectric material 118 is initially formed to completely cover the semiconductor die 106 and the metal frame 102. According to an embodiment, the dielectric material 118 is formed by a lamination technique. Lamination refers to a process in which multiple constituent layers of the dielectric material 118 are continuously formed. For example, the lamination technique can include forming a resin (such as a bismaleimide triazine (BT) resin) region that secures the central opening 104 and encapsulates and secures the semiconductor die 106 within the metal frame 102. One or more additional constituent layers of the dielectric material 118 can be formed on top of the resin. These additional constituent layers can include prepreg materials such as FR-4, FR-5, CEM-4, etc.

[0029] Reference Figure 5E Figure 5E , a groove is formed in the dielectric material 118. Specifically, a first groove 122 is formed in the dielectric material 118 above the back surface of the semiconductor die 106, thereby exposing the second load terminal 110 of the semiconductor die 106 ( Figures 5A to 5I not shown in). Additionally, a second groove 124 is formed in the dielectric material 118 above the metal frame 102, thereby exposing the upper surface of the metal frame 102. Generally, the first groove 122 and the second groove 124 can be formed by various techniques, such as etching, laser ablation, mechanical drilling, etc.

[0030] Reference Figure 5F Figure 5F , the temporary carrier 202 is removed from the lower side of the packaging assembly. Due to the hardened dielectric material 118, each semiconductor component can remain intact in further processing steps without the need for the temporary carrier 202. In the case where the temporary carrier 202 is a thermal release tape, this removal can involve heating the component to an appropriate temperature and peeling the thermal release tape from the component.

[0031] Reference Figure 5G Figure 5G , an additional etching process is performed only on the third packaging component 204 shown only on the right side of the figure. Thus, Figure 5G Figure 5G the additional etching process can be omitted from the process sequence performed on the first packaging component 200 and the second packaging component 202. As described above, the additional etching process removes material from the lead frame 200 near the tie bar 132, thereby forming a dent and a curved surface of the tie bar 132. At this time, the adjacent packaging parts are mechanically joined to each other by the dielectric material 118.

[0032] Reference Figure 5H Figure 5H , a metallization processing step is performed. These metallization processing steps form the first metallization layer 120 and the second metallization layer 126 of the semiconductor package 100 as described above. The first metallization layer 120 and the second metallization layer 126 can be formed by metal plating processes such as electroplating and electroless plating. As shown in the figure, the first metallization layer 120 can be conformally deposited to contact the semiconductor die 106 and the metal frame 102 and extend along the surface of the dielectric material 118. At the lower side 114 of the semiconductor package 100, the second metallization layer 126 can be patterned to form isolated bonding pads. This can be done by selectively blocking the deposition of metal or by performing subsequent etching on the deposited metal.

[0033] Reference Figure 5I, a solder mask 128 region is formed. The solder mask 128 region is formed between the lateral spaces of the first metallization layer 120 and the second metallization layer 126 where these layers are absent. The solder mask 128 region can be formed by screen printing a liquid solder mask 128 material. After forming the solder mask 128, additional processing steps can be performed to complete the semiconductor package 100. These additional processes can include, for example, a cleaning step. Individually or in combination, additional processing steps can be performed to improve the surface quality of the metallization, such as protection, solderability, etc. For example, an ENEPIG (electroless nickel electroless palladium immersion gold) process can be performed to improve solderability and reduce oxidation.

[0034] After performing the processing steps described with reference to Figures 5A - 5I , a package singulation step is performed to produce individual semiconductor packages 100 from the first package component 200, the second package component 202, and the third package component 204. The package singulation step includes a cutting process of separating the physically connected semiconductor package 100 components into individual semiconductor packages 100. This cutting process can be performed by various techniques, such as mechanical sawing, etching, laser ablation, etc. In the case of the first package component 200 and the second package component 202, the cutting process cuts the tie bars 132 and the dielectric material 118 above the tie bars 132, thereby producing an outer side of the package having flat exposed external contacts 130 and dielectric material 118 coplanar with the exposed external contacts 130. In the case of the third package component 204, the cutting process cuts the dielectric material 118 between the sides of the semiconductor package 100, thereby producing an outer side of the package having a flat surface of the dielectric material 118 and a curved surface of the tie bar 132 (i.e., the previously etched surface), the curved surface bending inward from the dielectric material 118.

[0035] Reference Figure 6 , shows a semiconductor package 100 according to an embodiment. The semiconductor package 100 is similar to Figure 1A and Figure 1BThe semiconductor package includes, in addition thereto, a metal connection member 134 that extends directly between the semiconductor die 106 and the metal frame 102. The metal connection member 134 is disposed below the upper surface of the metal frame 102. Thus, the metal connection member 134 forms a direct metal path from the semiconductor die 106 to the metal frame 102 that is below the upper surface of the dielectric material 118. The metal connection member 134 forms a heat conduction path between the semiconductor die 106 and the metal frame 102, thereby improving the heat dissipation ability of the semiconductor package 100. The metal connection member 134 can also form an electrical connection between the semiconductor die 106 and the metal frame 102. For example, the second terminal 110 of the semiconductor die 106 can be electrically connected to the metal connection member 134, for example, through metallization formed at the rear surface of the semiconductor die 106 or through connection to the sidewall of the semiconductor die 106. This results in a shorter distance and a lower resistance path than the connection provided by the first metallization layer 120. Thus, the metal connection member 134 can supplement or replace the connection between the second load terminal 110 and the metal frame 102 provided by the first metallization layer 120.

[0036] The metal connection member 134 can be provided by placing or forming metal between the semiconductor die 106 and the metal frame 102 before forming the dielectric material 118. For example, the metal connection member can be provided by an electroplated metal region 134 formed on the sides of the semiconductor chip 106 and the metal frame 102. The metal connection member 134 that extends directly between the semiconductor die 106 and the metal frame 102 can be incorporated into any embodiment of the semiconductor package 100 disclosed herein. Optionally, the metal connection member 134 can be disposed between electrical insulation structures (as shown). These electrical insulation structures can correspond to solder mask materials for filling holes between metal structures of the metal connection member 134.

[0037] Although the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the present disclosure.

[0038] Example 1: A method of forming a semiconductor package, the method comprising: providing a lead frame that includes a metal frame that at least partially surrounds a central opening and a plurality of ties that connect the metal frame to adjacent stable metal sections; disposing the lead frame on a temporary carrier; disposing a semiconductor die in the central opening on the temporary carrier; forming a dielectric material that fills the central opening and encapsulates the semiconductor die; forming a first recess in the dielectric material above the semiconductor die to expose a first surface of the semiconductor die; electrically connecting a terminal of the semiconductor die to the metal frame; and forming exposed external contacts of the semiconductor package from the ties.

[0039] Example 2: The method according to Example 1, wherein the exposed external contact includes the sidewall surface of the tie bar.

[0040] Example 3: The method according to Example 2, wherein the exposed external contact further includes the lower surface of the tie bar that intersects the sidewall surface of the tie bar.

[0041] Example 4: The method according to Example 1, further comprising performing a package monolithization process that severs the tie bar from the adjacent stable metal section, and wherein the exposed external contact is provided from the severed surface of the tie bar.

[0042] Example 5: The method according to Example 1, further comprising performing an etching process to remove material from the tie bar, and wherein the exposed external contact is provided by the surface of the tie bar etched by the etching process.

[0043] Example 6: The method according to Example 1, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal, wherein the first surface of the semiconductor die is the rear surface of the semiconductor die including the second load terminal, wherein electrically connecting the terminals of the semiconductor die to the metal frame includes forming a first metallization layer on the upper side of the semiconductor package that electrically connects the second load terminal to the metal frame, and wherein the exposed external contact forms a lead tip inspection feature electrically connected to the second load terminal of the semiconductor die.

[0044] Example 7: The method according to Example 1, wherein the lead frame is provided such that the tie bar is thinner than the metal frame, and wherein the dielectric material fills the region between the upper surface of the tie bar and the upper surface of the metal frame.

[0045] Example 8: The method according to Example 1, further comprising forming a metal connection member that extends directly between the semiconductor die and the metal frame, wherein the metal connection member is disposed below the upper surface of the metal frame.

[0046] Example 9: The method according to Example 8, wherein the metal connection member electrically connects the terminals from the first surface of the semiconductor die to the metal frame.

[0047] Example 10: A semiconductor package includes: a metal frame that forms at least a partially enclosed shape around a central opening; a severed tie bar connected to the metal frame; a semiconductor die disposed within the central opening; and a dielectric material that fills the central opening and encapsulates the semiconductor die, wherein terminals of the semiconductor die are electrically connected to the metal frame, and wherein the semiconductor package includes an exposed external contact of the semiconductor package formed by the severed tie bar.

[0048] Example 11: The semiconductor package according to Example 10, wherein the exposed external contact includes a sidewall surface of the severed tie bar.

[0049] Example 12: The semiconductor package according to Example 11, wherein the exposed external contact further includes a lower surface of the severed tie bar that intersects the sidewall surface of the severed tie bar.

[0050] Example 13: The semiconductor package according to Example 10, wherein a first groove is formed in the dielectric material above a first surface of the semiconductor die.

[0051] Example 14: The semiconductor package according to Example 13, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal.

[0052] Example 15: The semiconductor package according to Example 14, wherein the first surface of the semiconductor die is a rear surface of the semiconductor die that includes the second load terminal, wherein the semiconductor package includes a first metallization layer on an upper side of the semiconductor package that electrically connects the second load terminal to the metal frame, and wherein the exposed external contact forms a lead tip inspection feature electrically connected to the second load terminal of the semiconductor die.

[0053] Example 16: The semiconductor package according to Example 10, wherein the severed tie bar is thinner than the metal frame, and wherein the dielectric material fills a region between an upper surface of the severed tie bar and an upper surface of the metal frame.

[0054] Example 17: The semiconductor package according to Example 10, further including a metal connector extending directly between the semiconductor die and the metal frame, wherein the metal connector is disposed below an upper surface of the metal frame.

[0055] Example 18: The semiconductor package according to Example 17, wherein the metal connector electrically connects the terminal from the first surface of the semiconductor die to the metal frame.

[0056] Spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., are used for convenience in description to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to orientations different from those shown in the figures. Further, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc. and are not intended to be limiting. Throughout the specification, like terms refer to like elements.

[0057] As used herein, the terms "having", "including", "including (including)", "comprising", etc. are open terms that indicate the presence of the element or feature, but do not exclude additional elements or features. Unless the context clearly dictates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0058] Considering the variations and applications of the above scope, it should be understood that the present invention is not limited by the foregoing description, nor by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. A method of forming a semiconductor package, the method comprising: Providing a lead frame, the lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and adjacent stable metal sections; Arranging the lead frame on a temporary carrier; Arranging a semiconductor die in the central opening on the temporary carrier; Forming a dielectric material that fills the central opening and encapsulates the semiconductor die; Forming a first groove in the dielectric material above the first surface of the semiconductor die to expose the first surface of the semiconductor die; Electrically connecting the terminals of the semiconductor die to the metal frame; And Forming exposed external contacts of the semiconductor package from the tie bars.

2. The method according to claim 1, wherein, The exposed external contacts include the sidewall surfaces of the tie bars.

3. The method according to claim 2, wherein, The exposed external contacts further include the lower surfaces of the tie bars that intersect the sidewall surfaces of the tie bars.

4. The method according to claim 1 further comprises performing a package monomerization process that severs the tie rod from the adjacent stable metal section, and wherein, The exposed external contacts are provided by the cut surfaces of the tie bars.

5. The method according to claim 1 further comprises performing an etching process to remove material from the tie rod, and wherein, The exposed external contacts are provided by the surfaces of the tie bars etched by an etching process.

6. The method according to claim 1, wherein, The semiconductor die is configured as a vertical power transistor configured to conduct vertical current between a first load terminal and a second load terminal, wherein the first surface of the semiconductor die is the rear surface of the semiconductor die including the second load terminal, wherein electrically connecting the terminals of the semiconductor die to the metal frame includes forming a first metallization layer on the upper side of the semiconductor package that electrically connects the second load terminal to the metal frame, and wherein the exposed external contacts form a lead tip inspection feature electrically connected to the second load terminal of the semiconductor die.

7. The method according to claim 1, wherein, The lead frame is provided such that the tie bars are thinner than the metal frame, and wherein the dielectric material fills the region between the upper surface of the tie bars and the upper surface of the metal frame.

8. The method according to claim 1 further includes forming a metal connection member extending directly between the semiconductor die and the metal frame, wherein, The metal connection is disposed below the upper surface of the metal frame.

9. The method according to claim 8, wherein The metal connection electrically connects the terminals from the first surface of the semiconductor die to the metal frame.

10. A semiconductor package, comprising: A metal frame that forms at least a partially enclosed shape around a central opening; Cut tie bars connected to the metal frame; A semiconductor die disposed in the central opening; And A dielectric material that fills the central opening and encapsulates the semiconductor die, wherein the terminals of the semiconductor die are electrically connected to the metal frame; and wherein the semiconductor package includes exposed external contacts of the semiconductor package formed by the cut tie bars.

11. The semiconductor package according to claim 10, wherein, The exposed external contacts include the sidewall surfaces of the cut tie bars.

12. The semiconductor package according to claim 11, wherein, The exposed external contacts further include the lower surfaces of the cut tie bars that intersect the sidewall surfaces of the cut tie bars.

13. The semiconductor package according to claim 10, wherein, A first groove is formed in the dielectric material above the first surface of the semiconductor die.

14. The semiconductor package according to claim 13, wherein, The semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal.

15. The semiconductor package according to claim 14, wherein, The first surface of the semiconductor die is a back surface of the semiconductor die including the second load terminal, wherein the semiconductor package includes a first metallization layer on an upper side of the semiconductor package, the first metallization layer electrically connecting the second load terminal to the metal frame, and wherein the exposed external contact forms a lead tip inspection feature electrically connected to the second load terminal of the semiconductor die.

16. The semiconductor package according to claim 10, wherein, The severed tie bar is thinner than the metal frame, and wherein the dielectric material fills a region between an upper surface of the severed tie bar and an upper surface of the metal frame.

17. The semiconductor package according to claim 10 further includes a metal connecting member extending directly between the semiconductor die and the metal frame, wherein, The metal connection member is disposed below an upper surface of the metal frame.

18. The semiconductor package according to claim 17, wherein, The metal connection member electrically connects a terminal from the first surface of the semiconductor die to the metal frame.

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