Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. A through hole is formed in a glass substrate based on a through hole layout pattern; respectively forming a first metal layer and a second metal layer on the first surface and the second surface, and forming a connecting metal layer in the through hole; etching the first metal layer and the second metal layer at the same time to obtain a first patterned metal layer and a second patterned metal layer; forming a first dielectric layer on the first patterned metal layer; the first dielectric layer is made of silicide; performing etching processing on the first dielectric layer based on the through hole layout pattern, so that the connecting metal layer in the through hole is exposed in the first dielectric layer; and forming a connection structure above the connection metal layer to obtain a first semiconductor structure. The semiconductor structure can have a low thermal expansion coefficient, the semiconductor structure can be prevented from being damaged when the semiconductor structure is subjected to annealing and other processes with large temperature differences, stress changes on the surfaces of the two sides of the glass substrate can be more consistent, and the product yield of the semiconductor structure is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Through Silicon Via (TSV) is a vertical interconnection technology that penetrates a silicon wafer or chip and is widely used in the manufacturing process of semiconductor structures. When manufacturing a semiconductor structure, usually a circuit layer and other film layers are formed on a substrate, and electrical connections between multiple circuit layers are achieved through TSV technology. However, in the related art, there is a problem of a relatively high coefficient of thermal expansion in the semiconductor structure, which severely restricts the service life of semiconductor devices. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a semiconductor structure and a method for manufacturing the same, which can enable the semiconductor structure to have a lower coefficient of thermal expansion, can avoid damage when the semiconductor structure is subjected to processes with large temperature differences such as annealing, and also makes the stress changes on both sides of the glass substrate more consistent, improving the product yield of the semiconductor structure. The specific solutions are as follows:

[0004] On the one hand, this application provides a method for manufacturing a semiconductor structure, including:

[0005] Forming vias in a glass substrate based on a via layout pattern; the glass substrate has a first surface and a second surface;

[0006] Forming a first metal layer and a second metal layer on the first surface and the second surface respectively, and forming a connecting metal layer in the vias;

[0007] Performing an etching process on the first metal layer and the second metal layer simultaneously to obtain a first patterned metal layer and a second patterned metal layer;

[0008] Forming a first dielectric layer on the first patterned metal layer; the material of the first dielectric layer is silicide;

[0009] Performing an etching process on the first dielectric layer based on the via layout pattern to expose the connecting metal layer in the vias in the first dielectric layer;

[0010] Forming a connecting structure above the connecting metal layer to obtain a first semiconductor structure.

[0011] Optionally, forming a first dielectric layer on the first patterned metal layer includes:

[0012] While forming a first dielectric layer on the first patterned metal layer, a second dielectric layer is formed on the second patterned metal layer; the material of the second dielectric layer is silicide.

[0013] Optionally, etching the first dielectric layer based on the via layout pattern to expose the connection metal layer in the via in the first dielectric layer, includes:

[0014] Etching the first dielectric layer and the second dielectric layer simultaneously based on the via layout pattern to expose the connection metal layer in the via in the first dielectric layer and the second dielectric layer.

[0015] Optionally, etching the first metal layer and the second metal layer simultaneously to obtain a first patterned metal layer and a second patterned metal layer, includes:

[0016] Forming a first patterned photoresist layer and a second patterned photoresist layer above the first metal layer and the second metal layer respectively;

[0017] Performing exposure and development processes based on the first patterned photoresist layer and the second patterned photoresist layer to obtain the first patterned metal layer and the second patterned metal layer;

[0018] Removing the first patterned photoresist layer and the second patterned photoresist layer.

[0019] Optionally, forming a first metal layer and a second metal layer on the first surface and the second surface respectively, and forming a connection metal layer in the via, includes:

[0020] Depositing a first metal material layer; the first metal material layer covers the first surface and the second surface, and covers the sidewalls of the via;

[0021] Depositing a second metal material layer; the second metal material layer covers the first surface and the second surface, and completely fills the inside of the via to obtain the first metal layer, the second metal layer, and the connection metal layer.

[0022] Optionally, before forming a connection structure above the connection metal layer, the method further includes:

[0023] Forming a shielding layer above the first dielectric layer; the material of the shielding layer is a metal material;

[0024] Etching the shielding layer based on the via layout pattern to expose the connection metal layer in the shielding layer.

[0025] Optionally, before forming the first dielectric layer on the first patterned metal layer, the method further includes:

[0026] Forming a reinforcement structure above the first patterned metal layer;

[0027] Etching the first dielectric layer based on the via layout pattern to expose the connection metal layer in the via in the first dielectric layer, including:

[0028] Etching the first dielectric layer and the reinforcement structure based on the via layout pattern to expose the connection metal layer in the via in the first dielectric layer and the reinforcement structure.

[0029] Optionally, the method further includes:

[0030] Forming a second semiconductor structure;

[0031] Performing a first thermocompression bonding on the first semiconductor structure and the second semiconductor structure based on the connection structure to obtain a first bonded structure; during the first thermocompression bonding, the first bonding temperature is 80°C to 100°C, the first bonding pressure is 0.1 Mpa to 0.2 Mpa, and the first bonding time is 20 s to 60 s;

[0032] When the first bonded structure meets the bonding requirements, performing a second thermocompression bonding on the first semiconductor structure and the second semiconductor structure to obtain a second bonded structure; during the second thermocompression bonding, the second bonding temperature is 100°C to 300°C, the second bonding pressure is 0.3 Mpa to 3 Mpa, the second bonding time is 10 min to 20 min, and both the second bonding temperature and the second bonding pressure increase in a gradient manner.

[0033] Optionally, the method further includes:

[0034] Sealing the periphery of the second bonded structure.

[0035] In another aspect, an embodiment of the present application further provides a semiconductor structure, including:

[0036] A second metal layer, a glass substrate, a first metal layer, a first dielectric layer, and a connection structure stacked in sequence; the glass substrate has vias, a connection metal layer is disposed in the vias, and the connection structure is located above the connection metal layer.

[0037] An embodiment of the present application provides a semiconductor structure and a method for manufacturing the same. A through hole is formed in a glass substrate based on a through hole layout pattern; the glass substrate has a first surface and a second surface; a first metal layer and a second metal layer are respectively formed on the first surface and the second surface, and a connecting metal layer is formed in the through hole; the first metal layer and the second metal layer are etched simultaneously to obtain a first patterned metal layer and a second patterned metal layer; a first dielectric layer is formed on the first patterned metal layer; the material of the first dielectric layer is silicide; the first dielectric layer is etched based on the through hole layout pattern so that the connecting metal layer in the through hole is exposed in the first dielectric layer; a connecting structure is formed above the connecting metal layer to obtain a first semiconductor structure.

[0038] In the embodiment of the present application, using a glass substrate as the substrate for carrying the metal layer and using silicide as the first dielectric layer can enable the semiconductor structure to have a lower coefficient of thermal expansion, can avoid damage to the semiconductor structure during processes with large temperature differences such as annealing, and can effectively improve the service life of the semiconductor structure. In addition, by simultaneously forming two metal layers (i.e., the first metal layer and the second metal layer) on both sides of the glass substrate, this method of fabricating metal layers on both sides can effectively avoid the problem of warping deformation of the glass substrate caused by large stress differences between the two side surfaces during the manufacturing process, and can make the stress changes on both side surfaces of the glass substrate more consistent, improving the product yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0040] Figure 1 The flowchart shows a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0041] Figure 2 The schematic diagram shows the formation process of a stacked body with a single dielectric layer provided by an embodiment of the present application;

[0042] Figure 3 The schematic diagram shows the formation process of a stacked body with a double dielectric layer provided by an embodiment of the present application;

[0043] Figure 4 The schematic diagram shows a first semiconductor structure with a single dielectric layer provided by an embodiment of the present application;

[0044] Figure 5Shows a schematic diagram of a first semiconductor structure with a double dielectric layer provided by an embodiment of the present application;

[0045] Figure 6 Shows a schematic diagram of a bonding structure provided by an embodiment of the present application;

[0046] Figure 7 Shows a schematic diagram of another bonding structure provided by an embodiment of the present application;

[0047] Figure 8 Shows a schematic diagram of partial film layers of a bonding structure provided by an embodiment of the present application. Detailed implementation manners

[0048] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings.

[0049] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0050] Secondly, the present application will be described in detail in conjunction with the schematic diagrams. When detailing the embodiments of the present application, for ease of explanation, the cross-sectional views showing the device structures will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0051] For ease of understanding, the following will describe in detail a semiconductor structure and a method for preparing the same provided by an embodiment of the present application in conjunction with the accompanying drawings.

[0052] Refer to Figure 1 As shown, it is a schematic flow diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application, and the method may include the following steps.

[0053] S101, form a through hole 102 in the glass substrate 101 based on the layout pattern of the through hole 102.

[0054] The layout pattern of the vias 102 is a pre-set distribution pattern of the vias 102. Multiple vias 102 can be formed on the glass substrate 101 based on the layout pattern of the vias 102, and the multiple vias 102 are arranged according to the layout pattern of the vias 102. The glass substrate 101 can be an ultra-thin glass substrate 101, and the thickness can be 50 - 200 um, so as to further reduce the thickness of the semiconductor structure and improve the device integration. Since the vias 102 are formed on the glass substrate 101, the vias 102 can be understood as the vias 102 of the Through Glass Via (TGV) technology, which are used to realize the interconnection between multiple metal layers.

[0055] The glass substrate 101 has a first surface 1011 and a second surface 1012. The first surface 1011 can be the upward surface of the glass substrate 101, and the second surface 1012 can be the downward surface of the glass substrate 101. Refer to Figure 2 As shown, it is a schematic diagram of the formation process of a stacked body with a single dielectric layer provided by an embodiment of the present application. In (1), the glass substrate 101 has multiple through vias 102, the first surface 1011 is the upper surface, and the second surface 1012 is the lower surface.

[0056] In practical applications, the formation of the vias 102 can specifically adopt a composite process of laser modification and via 102 etching. For each glass substrate 101, this composite process can be used to form the vias 102. For example, ultra-thin glass substrates 1011 to ultra-thin glass substrates 101n with a thickness of 50 um - 200 um and having vias 102 can be obtained. The vias 102 are arranged according to the drawing (i.e., the layout pattern of the vias 102), the aperture can be 25 - 60 um, mark identification positioning is realized at the four corners of the glass substrate 101, and the glass substrate 101 is divided into the first surface 1011 and the second surface 1012.

[0057] Among them, laser modification can be carried out using femtosecond or picosecond laser ultrashort pulses. The duration of the femtosecond pulse is 10 - 15 seconds, the duration of the picosecond pulse is 10 - 12 seconds, and the wavelength can be selected in the range of 343 - 1064 nm; further, near-infrared: 1030 - 1064 nm, visible light: 515 - 532 nm, ultraviolet: 343 - 355 nm. Preferably, femtosecond laser ultrashort pulses can be used to modify the glass substrate 101, and the laser wavelength is 1030 nm.

[0058] The etching of the vias 102 can be achieved by using one or a combination of HF, alkaline solution wet etching, or plasma etching. Preferably, a combination of HF and alkaline solution wet etching can be used, which has high efficiency, low cost, and can ensure that the hole walls are round.

[0059] S102. Form a first metal layer 103 and a second metal layer 104 on the first surface 1011 and the second surface 1012 respectively, and form a connecting metal layer 105 in the through hole 102.

[0060] Specifically, referring to Figure 2 (2) therein, metal can be deposited on the glass substrate 101, so as to form a first metal layer 103 on the first surface 1011, a second metal layer 104 on the second surface 1012, and a connecting metal layer 105 in the through hole 102. Among them, the first metal layer 103 and the second metal layer 104 are used to form circuit layers subsequently, and the connecting metal layer 105 is used to realize the connection between different circuit layers. The material of the metal layer is not specifically limited.

[0061] In a possible implementation manner, S102 forming a first metal layer 103 and a second metal layer 104 on the first surface 1011 and the second surface 1012 respectively, and forming a connecting metal layer 105 in the through hole 102 may include S1021 - S1022.

[0062] S1021. Deposit a first metal material layer.

[0063] Specifically, a first metal material layer can be deposited on the glass substrate 101 first. Since it is generally difficult to completely cover the through hole 102, the first metal material layer is mainly located on the first surface 1011 and the second surface 1012, and on the side walls of the through hole 102, that is, the first metal material layer covers the first surface 1011 and the second surface 1012, and covers the side walls of the through hole 102. The first metal material layer can form a chemical bond with the glass substrate 101, and can have a good bonding force with the second metal material layer, and can also relieve the thermal expansion difference during subsequent annealing.

[0064] In practical applications, the deposition of the first metal material layer can be carried out by magnetron sputtering, so as to achieve double-sided coating on both sides of the glass substrate 101. The material of the first metal material layer can be copper, aluminum, titanium, chromium, silver, gold, etc., and further preferably one or more of titanium, copper, and chromium. The thickness of the first metal material layer can be 500nm - 3um.

[0065] S1022. Deposit a second metal material layer.

[0066] To ensure that the through-hole 102 can be completely filled with the metal material, it is necessary to deposit the metal material again, that is, to deposit and form the second metal material layer. The second metal material layer will continue to cover the first surface 1011 and the second surface 1012, and will also be deposited in the through-hole 102 until the through-hole 102 is completely filled. That is, the second metal material layer covers the first surface 1011 and the second surface 1012, and completely fills the inside of the through-hole 102 to obtain the first metal layer 103, the second metal layer 104, and the connecting metal layer 105.

[0067] At this time, the first metal layer 103 can be understood as the first metal material layer and the second metal material layer located on the first surface 1011, the second metal layer 104 is the first metal material layer and the second metal material layer located on the second surface 1012, and the connecting metal layer 105 is the first metal material layer and the second metal material layer located in the through-hole 102.

[0068] In practical applications, the process of depositing the second metal material layer can adopt the method of double-sided pulse electroplating. The thickness of the second metal material layer can be slightly larger than the thickness of the first metal material layer to achieve complete filling of the through-hole 102. The thickness of the second metal material layer can be 15 - 35um. Double-sided pulse electroplating can more precisely control the deposition of metal ions, improve the uniformity, density, and performance of the coating. And further, the glass substrate 101 after pulse electroplating is annealed in a vacuum (or filled with inert gas), the annealing temperature is 360 - 420°C, and the annealing time is 30 - 60 Min to remove the internal stress generated by the metal during the electroplating process and enhance the performance of the device.

[0069] In this way, by depositing the metal material multiple times to form the first metal layer 103, the second metal layer 104, and the connecting metal layer 105, it can be ensured that the connecting metal layer 105 in the through-hole 102 can completely fill the through-hole 102, ensuring the stability and reliability of the electrical connection.

[0070] S103, etch the first metal layer 103 and the second metal layer 104 simultaneously to obtain the first patterned metal layer 106 and the second patterned metal layer 107.

[0071] Specifically, the two side surfaces of the glass substrate 101 can be etched simultaneously, so as to obtain the first patterned metal layer 106 and the second patterned metal layer 107 simultaneously. The first patterned metal layer 106 is the metal layer with the circuit pattern, which can also be recorded as the first circuit layer, and the second patterned metal layer 107 can be recorded as the second circuit layer. As shown in (4) of Figure 2 reference, the first surface 1011 has the first patterned metal layer 106, and the second surface 1012 has the second patterned metal layer 107.

[0072] The double-sided preparation of the circuit layer can not only improve efficiency, but also effectively solve the problem of warping and breakage of the glass substrate 101 caused by uneven stress during the single-sided manufacturing process. In addition, the substrate can be further subjected to AOI circuit detection, X-ray, on-line electrical performance testing and repair to detect whether the circuit layer meets the requirements.

[0073] In a possible implementation, S103 etches the first metal layer 103 and the second metal layer 104 simultaneously to obtain the first patterned metal layer 106 and the second patterned metal layer 107, which may include S1031 - S1033.

[0074] S1031, form a first patterned photoresist layer 111 and a second patterned photoresist layer 112 above the first metal layer 103 and the second metal layer 104 respectively.

[0075] Specifically, a first patterned photoresist layer 111 can be formed above the first metal layer 103, and a second patterned photoresist layer 112 can be formed above the second metal layer 104. The pattern of the first patterned photoresist layer 111 is the circuit layout pattern of the first circuit layer, and the pattern of the second patterned photoresist layer 112 is the circuit layout pattern of the second circuit layer. The patterns of the first patterned photoresist layer 111 and the second patterned photoresist layer 112 can be the same or different. Refer to Figure 2 In (3) of, a first patterned photoresist layer 111 and a second patterned photoresist layer 112 are formed on the glass substrate 101, and their patterns are different.

[0076] S1032, perform exposure and development processing based on the first patterned photoresist layer 111 and the second patterned photoresist layer 112 to obtain the first patterned metal layer 106 and the second patterned metal layer 107.

[0077] Specifically, the first metal layer 103 can be exposed and developed according to the first patterned photoresist layer 111 to obtain the first patterned metal layer 106. At the same time, the second metal layer 104 is exposed and developed based on the second patterned photoresist layer 112 to obtain the second patterned metal layer 107.

[0078] In practical applications, these two photoresist layers are used to expose the first surface 1011 and the second surface 1012, and the developing solution is soaked in the basket on both sides to obtain the corresponding masks for the circuit patterns of the first surface 1011 and the second surface 1012 (i.e., the first patterned photoresist layer 111 and the second patterned photoresist layer 112). Then, the etching solution of the corresponding metal material is soaked in the basket on both sides to realize pattern transfer, so as to remove the excess metal material, thereby realizing substrate circuit patterning and manufacturing the first circuit layer and the second circuit layer.

[0079] S1033, remove the first patterned photoresist layer 111 and the second patterned photoresist layer 112.

[0080] After the pattern transfer of the photoresist layer is completed, the first patterned photoresist layer 111 and the second patterned photoresist layer 112 can be removed. Specifically, the residual photoresist can be removed by using a photoresist stripping solution and the substrate can be cleaned.

[0081] In this way, through the pattern transfer process of the photoresist layer, the pattern clarity and accuracy of the first patterned metal layer 106 and the second patterned metal layer 107 can be improved, and the accuracy of the circuit layout can be enhanced.

[0082] S104, form a first dielectric layer 108 on the first patterned metal layer 106.

[0083] Specifically, the first dielectric layer 108 can be deposited above the first patterned metal layer 106. The material of the first dielectric layer 108 can be a silicide, such as insulating inorganic substances like silicon oxide, silicon nitride, etc. The first dielectric layer 108 has characteristics such as transparency or semi - transparency, chemical stability, heat resistance, and good mechanical properties. The first dielectric layer 108 can be formed by methods such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sol - gel method, evaporation, sputtering, dipping, or spin - coating. The film thickness of the first dielectric layer 108 can be 3 - 5 um, and the thicknesses of subsequent other dielectric layers can also be within this range. Specifically, referring to Figure 2 in (5), there is a first dielectric layer 108 above the first patterned metal layer 106.

[0084] In a possible implementation, S104 forming the first dielectric layer 108 on the first patterned metal layer 106 can include S1041.

[0085] S1041, while forming the first dielectric layer 108 on the first patterned metal layer 106, form a second dielectric layer 110 on the second patterned metal layer 107.

[0086] Specifically, in order to further ensure the stress consistency on both sides of the glass substrate 101, dielectric layers can be formed on both surfaces simultaneously, that is, while forming the first dielectric layer 108 on the first patterned metal layer 106, a second dielectric layer 110 is also formed on the second patterned metal layer 107. The material of the second dielectric layer 110 is a silicide. The materials of the first dielectric layer 108 and the second dielectric layer 110 can be the same to ensure that these two dielectric layers can be formed simultaneously.

[0087] Reference Figure 3 As shown in (5) of Figure 3 , a first dielectric layer 108 can be formed on the first surface 1011, and a second dielectric layer 110 can be formed on the second surface 1012. For Figure 3 the other drawings in Figure 3 , which are similar to those in Figure 2 Figure 2 , will not be elaborated here.

[0088] In this way, by setting the double-sided dielectric layer, the advantage is that it can ensure that the double-sided stresses of the glass substrate 101 are consistent, the glass substrate 101 is not easily bent and warped, and it can also protect the metal that does not need to be exposed, preventing the metal from being oxidized or damaged in subsequent processes.

[0089] S105, etch the first dielectric layer 108 based on the via 102 layout pattern, so that the connection metal layer 105 in the via 102 is exposed in the first dielectric layer 108.

[0090] Specifically, since the via 102 is used to realize the interconnection between different patterned metal layers (i.e., circuit layers), the connection metal layer 105 in the via 102 needs to be exposed. Therefore, the first dielectric layer 108 can be etched according to the via 102 layout pattern, so that the position where the via 102 is located is exposed, facilitating the subsequent connection metal layer 105 to be electrically connected to the circuit layer.

[0091] In actual operation, the photoresist layer etching method can be used to expose the via 102. As shown in (5) of Figure 2 Figure 2 , a photoresist layer can be formed on the first dielectric layer 108. Based on the via 102 layout pattern, after exposure and development, a third patterned photoresist layer 113 is obtained. Then, the pattern of the third patterned photoresist layer 113 is transferred into the first dielectric layer 108, thus completing the exposure of the via 102. Referring to Figure 2 (6) of Figure 2 , a patterned first dielectric layer 108 is obtained, and the patterned first dielectric layer 108 can expose the via 102.

[0092] When the dielectric layer is silicon dioxide, the silicon dioxide layer in the hole area can be etched by soaking in HF etching solution to expose the underlying metal, and then the residual glue / film is removed and the metal oxide layer is removed. When removing the metal oxide layer, the corresponding etching solution can be selected according to the metal. For example, for copper metal, copper chloride, hydrogen peroxide, acetic acid, hydrochloric acid, dilute sulfuric acid can be selected singly or in combination.

[0093] If only the first dielectric layer is provided on one side of the first surface 1011 and no dielectric layer is provided on the second surface 1012, the second surface 1012 can be protected by attaching a protective film, or a non-dielectric layer can be provided for overall surface masking.

[0094] In a possible implementation, S105 etches the first dielectric layer 108 based on the layout pattern of the through-hole 102, so that the connection metal layer 105 in the through-hole 102 is exposed in the first dielectric layer 108, which may include S1051.

[0095] S1051 etches the first dielectric layer 108 and the second dielectric layer 110 simultaneously based on the layout pattern of the through-hole 102, so that the connection metal layer 105 in the through-hole 102 is exposed in the first dielectric layer 108 and the second dielectric layer 110.

[0096] Specifically, when preparing two dielectric layers on both sides, if the connection metal layer 105 in the through-hole 102 needs to electrically connect both the circuit layer above it and the circuit layer below it, both ends of the through-hole 102 need to be exposed. Of course, if the second patterned metal layer 107 is at the bottom, the bottom of the through-hole 102 does not need to be exposed in its second dielectric layer 110.

[0097] That is to say, the first dielectric layer 108 and the second dielectric layer 110 can be etched simultaneously, with the layout pattern of the through-hole 102 as the etching basis, so that both ends of the through-hole 102 are exposed at the same time, so that the connection metal layer 105 in the through-hole 102 can achieve upward and downward electrical connections, ensuring the electrical connection effect.

[0098] In practical applications, referring to Figure 3 shown in (5) therein, the through-hole 102 can be exposed by etching the photoresist layer. A photoresist layer can be formed on the first dielectric layer 108 and the second dielectric layer 110. Based on the layout pattern of the through-hole 102, after exposure and development, the third patterned photoresist layer 113 and the fourth patterned photoresist layer 114 are obtained at the same time, and then the pattern is transferred to the two dielectric layers, thus completing the exposure of the upper and lower ends of the through-hole 102. Referring to Figure 3 in (6) therein, the patterned first dielectric layer 108 and the second dielectric layer 110 are obtained, and the complete exposure of both ends of the through-hole 102 is achieved.

[0099] S106 forms a connection structure 109 above the connection metal layer 105 to obtain the first semiconductor structure 100.

[0100] Specifically, since the connection metal layer 105 is located inside the groove, the connection metal layer 105 needs to be led out. Therefore, a connection structure 109 can be formed above the connection metal layer 105. The material of the connection structure 109 is a metal material, so as to obtain the first semiconductor structure 100. Referring to Figure 2 shown in (7) therein, a connection structure 109 can be formed above each through-hole 102 to realize the lead-out of the metal connection layer, which is convenient for electrical connection with other circuit layers.

[0101] In practical applications, the connection structure 109 may include connection posts 1091 and solder joints 1092. The connection posts 1091 may be formed first and then the solder joints 1092. The solder joints 1092 may be lead-free solder balls, conductive adhesives, conductive polymer materials, etc. The diameter of the solder joints 1092 may be 15 - 35 μm for bonding to the lower layer.

[0102] Specifically, CCD can be used to accurately locate the mark, and conductive materials can be injected into the holes by metal inkjet printing and gold paste hole filling printing. Further, robotic arm needles can be used to accurately inject conductive adhesives into the holes, thereby obtaining the connection structure 109 and realizing metallization of the through-hole 102 area. The conductive adhesive may include one or more of copper, silver, gold, aluminum, zinc, and other conductive compounds, and the curing method may include baking and UV curing.

[0103] In summary, in this application, the glass substrate 101 is used as the substrate for carrying the metal layer. During the process of realizing electrical connection between the double metal layers through the TGV through-holes in the glass substrate 101, silicide is used as the first dielectric layer 108. The first dielectric layer 108 is located above the first circuit layer, which can make the semiconductor structure have a lower coefficient of thermal expansion, can avoid damage to the semiconductor structure during processes with large temperature differences such as annealing, and can effectively improve the service life of the semiconductor structure. In addition, by simultaneously forming two metal layers (i.e., the first metal layer 103 and the second metal layer 104) on both sides of the glass substrate 101, this way of preparing metal layers on both sides can effectively avoid the problem of warping and deformation of the glass substrate 101 caused by large differences in surface stress on both sides during the preparation process, and can make the stress changes on both sides of the glass substrate 101 more consistent, improving the product yield of the semiconductor structure. Since the cost of the glass substrate 101 is low, it can reduce the process cost. In addition, it can also simplify the process flow, improve the mechanical stability and high-frequency electrical characteristics of the semiconductor structure.

[0104] Reference Figure 4 As shown, it is a schematic diagram of a first semiconductor structure 100 with a single dielectric layer provided by an embodiment of this application. There is a first dielectric layer 108 on one side of the first patterned metal layer 106, and the connection structure 109 includes connection posts 1091 and solder joints 1092. Reference Figure 5 As shown, it is a schematic diagram of a first semiconductor structure 100 with a double dielectric layer provided by an embodiment of this application. There is a first dielectric layer 108 on one side of the first patterned metal layer 106, and a second dielectric layer 110 on one side of the second patterned metal layer 107.

[0105] In a possible implementation, the method may further include S201 - S203.

[0106] S201, form a second semiconductor structure.

[0107] Specifically, another semiconductor structure, i.e., the second semiconductor structure, can be formed. The formation process of the second semiconductor structure is the same as that of the first semiconductor structure 100 and will not be elaborated here. Refer to Figure 2 (7) and (8) in which respectively show the first semiconductor structure 100 and the second semiconductor structure.

[0108] S202, based on the connection structure 109, perform the first thermocompression bonding on the first semiconductor structure 100 and the second semiconductor structure to obtain the first bonded structure.

[0109] Specifically, the first semiconductor structure 100 and the second semiconductor structure can be bonded together to obtain a complete bonded structure. Refer to Figure 2 as shown in (9) in which.

[0110] To ensure the bonding effect, the bonding can be divided into two times. During the first thermocompression bonding process, the first bonding temperature can be 80°C to 100°C, the first bonding pressure is 0.1 Mpa to 0.2 Mpa, and the first bonding time is 20 s to 60 s.

[0111] S203, when the first bonded structure meets the bonding requirements, perform the second thermocompression bonding on the first semiconductor structure 100 and the second semiconductor structure to obtain the second bonded structure.

[0112] Specifically, during the second thermocompression bonding process, the second bonding temperature can be 100°C to 300°C, the second bonding pressure is 0.3 Mpa to 3 Mpa, the second bonding time is 10 min to 20 min, and both the second bonding temperature and the second bonding pressure increase in a gradient manner.

[0113] In actual operation, the adsorption chuck can be made to adsorb the glass substrate 101 of the second semiconductor structure, and the mark is accurately positioned by using CCD recognition. The connection structure 109 in the first semiconductor structure 100 is thermocompression bonded to the second semiconductor structure to achieve fitting and stacking. The temperature can be 100 - 300°C, the pressure is 0.3 - 3 Mpa, and the alignment accuracy is ±1 μm. Perform the second circuit detection on the bonded structure, and the electrical connection performance between the metal pads of each layer is good, and the connection resistance is less than 6 mΩ.

[0114] During the two - time thermocompression bonding process, after being accurately positioned by an advanced optical positioning system and a six - axis motion platform, pre - compression and high - temperature formal compression can be carried out to achieve real - time detection and adjustment of tight and gap - free bonding. Pre - compression means that during the first thermocompression bonding, initial pressure and temperature are applied to the glass substrate 101, with the pressure being 0.1 - 0.2 mpa, the temperature being 80 - 100 °C, and the time being 20 - 60 S. During this period, real - time monitoring and adjustment are carried out. After confirming the accuracy, formal compression, that is, the second thermocompression bonding, is carried out by step - by - step pressure application - gradient temperature increase. The pressure is 0.3 - 3 mpa, the pressure is increased at a rate of 0.1 - 0.3 mpa / Min, the temperature is 100 - 300 °C, the temperature is increased at a rate of 2 - 10 °C / Min, and the time is 10 - 20 Min.

[0115] In this way, by performing the bonding process in a distributed manner, the bonding accuracy can be guaranteed, enabling the two semiconductor structures to achieve precise alignment.

[0116] In a possible implementation, the method may further include sealing the periphery of the second bonding structure.

[0117] Specifically, the edge of the substrate can be sealed. The edge - sealing can be silicone resin dispensing edge - sealing or vacuum filling to ensure the stability and tightness of the bonding structure and improve the device quality.

[0118] Reference Figure 6 As shown, it is a schematic diagram of a bonding structure provided by an embodiment of the present application. The second semiconductor structure has a second glass substrate 201, a third patterned metal layer (third circuit layer) 206, and a fourth patterned metal layer (fourth circuit layer) 207. There is also a sealing glue 115 on the side of the bonding structure (i.e., the stacked body), and there is a first dielectric layer 108 between the two semiconductor structures. Reference Figure 7 As shown, it is a schematic diagram of another bonding structure provided by an embodiment of the present application. There is a first dielectric layer 108 and a fourth dielectric layer 210 between the two semiconductor structures.

[0119] In a possible implementation, before forming the connection structure 109 above the connection metal layer 105 in S106, the method further includes S107 - S108.

[0120] S107, forming a shielding layer 116 above the first dielectric layer 108.

[0121] Specifically, the shielding layer 116 can be deposited above the first dielectric layer 108. The material of the shielding layer 116 can be a metal material, such as a conductive metal thin layer, silicon carbide, etc. The shielding layer 116 is arranged between the circuit layers and connected to the ground electrode, and the thickness can be 200 nm - 5 um.

[0122] S108. Etch the shielding layer 116 based on the layout pattern of the vias 102, so that the connecting metal layer 105 is exposed in the shielding layer 116.

[0123] Specifically, the shielding layer 116 can be etched according to the positions of the vias 102, so that the connecting metal layer 105 at the positions of the vias 102 is exposed. In this way, when setting the double-sided dielectric layer, a metal shielding layer 116 can be set between the double dielectric layers to absorb interference signals and reflect electromagnetic noise, ensuring the purity and stability of signal transmission.

[0124] In a possible implementation, before forming the first dielectric layer 108 on the first patterned metal layer 106, the method may further include forming a reinforcing structure 117 above the first patterned metal layer 106. Then, etching the first dielectric layer 108 based on the layout pattern of the vias 102 to expose the connecting metal layer 105 in the vias 102 in the first dielectric layer 108 includes: etching the first dielectric layer 108 and the reinforcing structure 117 based on the layout pattern of the vias 102 to expose the connecting metal layer 105 in the vias 102 in the first dielectric layer 108 and the reinforcing structure 117.

[0125] Among them, the reinforcing structure 117 is located between the first patterned metal layer 106 and the first dielectric layer 108. The material of the reinforcing structure 117 can be a glass fiber reinforced layer, a silicon compound mixed reinforced layer, a polymer reinforced film, and further optionally a silicon nitride, aluminum oxide or zirconia mixed coating, and the thickness can be 8-10 um. In order to facilitate the exposure of the connecting metal layer 105, it is necessary to etch and remove the reinforcing structure 117 and the first dielectric layer 108 above the vias 102. The presence of the reinforcing structure 117 can further improve the hardness of the glass substrate 101 and improve the device quality. In addition, a heat dissipation structure can also be included in the semiconductor structure, and the heat dissipation structure can be a metal layer with a high thermal conductivity, a graphite sheet, etc., with a thickness of 5-10 um.

[0126] Reference Figure 8 As shown, it is a partial film layer schematic diagram of a bonding structure provided by an embodiment of the present application. In the first semiconductor structure 100 located below, the sequentially stacked first patterned metal layer 106, reinforcing structure 117, first dielectric layer 108 and shielding layer 116 are shown. In the second semiconductor structure located above, the sequentially stacked fourth dielectric layer 210 and fourth patterned metal layer 207 are shown. In addition, the shielding layer 116 needs to be connected to the ground electrode 118 to ensure its grounding.

[0127] In the embodiments of the present application, the electrical connection of multiple substrates and multiple circuit layers with an ultra-thin glass substrate 101 as the base can be realized, and circuit packaging can be adhered to form a multi-layer ultra-thin glass stack. The multi-layer ultra-thin glass stack can be formed by sequentially stacking and adhering at least two ultra-thin glass substrates 101. Each layer realizes the patterning of TGV vias 102, metallization of holes, and circuits on both sides. In addition, the stack provided in the present application is closed by an enhanced structure 117, a heat dissipation structure, a shielding structure, and potting, so that the packaging structure is optimized in terms of mechanical properties, electrical properties, thermal properties, etc. Taking a single glass substrate 101 as a unit module, each substrate is strictly tested and then adhered to achieve multi-layer packaging, making the multi-layer circuit modular, improving the connection reliability of the multi-layer circuit, simplifying the process of preparing the multi-layer circuit, and effectively ensuring the yield of its finished products.

[0128] Next, a specific example of the formation process of the multi-layer stack is given.

[0129] Step 1: After laser-modifying the glass substrate 101, the through-holes 102 are etched to obtain ultra-thin glass substrates 1011 and 1014 with a thickness of 0.15 mm and through-holes 102, and ultra-thin glass substrates 1012 and 1013 with a thickness of 0.07 mm and through-holes 102. The aperture of the through-hole 102 is 40 um, and mark identification positioning is realized at the four corners of the glass substrate 101.

[0130] Step 2: Magnetron sputtering double-sided coating is performed on the glass substrates 1011 to 1014 respectively, and Ti / Cu transition layers with a thickness of 100 / 500 nm are set inside and on the surface of the holes, so as to form a first metal material layer; further, double-sided pulse electroplating of copper is performed on the glass substrate 101, and metallization filling of the holes is realized. The surface copper thickness is 25 um. After pulse electroplating, the substrate is vacuum annealed at 360 °C for 30 min. Further, it is soaked in a copper etching solution to reduce the copper thickness to 15 um, so as to form a second metal material layer.

[0131] Step 3: Corresponding circuit masks are set for substrates 1 to 4 respectively. A commercially available photosensitive dry film is used as a photoresist, and the glass substrate 101 is double-sided coated with a laminator. The substrate is supported by a 0.7 mm carrier plate during the coating process. Using mark positioning, double-sided exposure is performed respectively according to the corresponding circuit drawings, and the basket is soaked in the developer. After the corresponding circuit mask appears, the basket is soaked in a copper etching solution, and the copper circuits on both sides of the substrate are patterned to obtain the first circuit layer, the second circuit layer... the seventh circuit layer, and the eighth circuit layer. After removing the residual photoresist with a photoresist remover, the substrate is cleaned and the circuit is detected.

[0132] Step 4: An enhanced structure 117 is set for the seventh circuit layer of substrate 4, and a mixture of 60% silicon nitride, 30% zirconia, and 10% alumina is spin-coated at 8 um and cured at 300 °C for 30 min.

[0133] Step 5: Set dielectric layers made of silicon dioxide on Circuit Layers 1 to 8 respectively, and use magnetron sputtering to deposit 3 um of silicon dioxide. Double-sidedly coat with photosensitive dry film, use the mark for positioning, and perform double-sided exposure respectively according to the corresponding hole area drawings. Immerse the basket in the developer to expose the mask in the hole area (the second circuit layer is not exposed), and further immerse the basket in HF etching solution to expose the copper layer at the bottom of the hole. After removing the photoresist with the stripping solution, pass through a solution of 1 part by mass of 37 wt% hydrochloric acid, 1 part by mass of 30 wt% hydrogen peroxide, and 8 parts by mass of water to remove the copper oxide layer, with the copper removal amount < 1 um and the temperature at 26 °C.

[0134] Step 6: Set the shielding layer 116 on the dielectric layer above the fifth circuit layer of the substrate 3, and use magnetron sputtering to deposit 3 um of copper. Use the mark for positioning and perform exposure and development according to the corresponding hole area drawings. After exposing the mask in the hole area, immerse the basket in copper etching solution to remove the copper layer in the hole area and the area expanded by 10 um outward, and electrically connect the ground pole connection column 1091 to the shielding layer 116.

[0135] Step 7: Let the adsorption chuck adsorb the substrate 2, with the fourth circuit layer facing up and place it on the positioning disk at Station 1. Use the mark for precise positioning, and let the robotic arm syringe precisely inject conductive adhesive into the holes to prepare the dielectric layer connection columns 1091 on the fourth circuit layer and perform pre-baking at a temperature of 80 °C for 3 Min.

[0136] Let the adsorption chuck adsorb the substrate 1, with the first circuit layer facing up and place it on the positioning disk at Station 2. Use the mark for precise positioning, and let the robotic arm syringe precisely inject conductive adhesive into the holes to prepare the dielectric layer connection columns 1091 and bumps on the first circuit. Let the adsorption chuck adsorb the substrate 2, with the fourth circuit layer facing down, use the mark for precise positioning, and perform high-temperature lamination with the first substrate to achieve bonding and stacking. Pre-laminate, apply an initial pressure of 0.1 mpa to the substrate, at a temperature of 80 °C for 20 S, and monitor and adjust in real time during this period. After confirming the accuracy, perform formal lamination. The initial pressure for formal lamination is 0.2 mpa, increasing at a rate of 0.1 mpa / Min, the initial temperature is 80 °C, increasing at a rate of 8 °C / Min, and the time is 10 Min. Conduct the second circuit inspection on the substrate.

[0137] Step 8: Complete all the bonding of the substrates in sequence, that is, bond the first circuit above the 0.15 mm first substrate with the fourth circuit below the 0.07 mm second substrate, and stack in sequence the sixth circuit below the 0.07 mm third substrate and the eighth circuit layer below the 0.15 mm fourth substrate; fill with nitrogen and further cure at a temperature of 280 °C for 15 Min; perform UV curing on the silicone resin sealant at the four peripheral edges of the stacked body.

[0138] Step 9: Set a number of chip I / O pads on the dielectric layer of the seventh circuit to achieve the docking between the chip and the seventh circuit.

[0139] Based on the manufacturing method of the above semiconductor structure, an embodiment of the present application further provides a semiconductor structure. Refer to Figure 4 As shown, the semiconductor structure includes a second metal layer 104, a glass substrate 101, a first metal layer 103, a first dielectric layer 108, and a connection structure 109 that are stacked in sequence; a through hole 102 is provided in the glass substrate 101, and a connection metal layer 105 is provided in the through hole 102, and the connection structure 109 is located above the connection metal layer 105.

[0140] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0141] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application by using the methods and technical contents disclosed above, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Forming vias in a glass substrate based on a via layout pattern; The glass substrate has a first surface and a second surface; Forming a first metal layer and a second metal layer on the first surface and the second surface respectively, and forming a connecting metal layer in the vias; Performing an etching process on the first metal layer and the second metal layer simultaneously to obtain a first patterned metal layer and a second patterned metal layer; Forming a first dielectric layer on the first patterned metal layer; The material of the first dielectric layer is silicide; Performing an etching process on the first dielectric layer based on the via layout pattern to expose the connecting metal layer in the vias in the first dielectric layer; Forming a connection structure above the connecting metal layer to obtain a first semiconductor structure.

2. The method according to claim 1, characterized in that Forming a first dielectric layer on the first patterned metal layer, including: While forming the first dielectric layer on the first patterned metal layer, forming a second dielectric layer on the second patterned metal layer; the material of the second dielectric layer is silicide.

3. The method according to claim 2, wherein Performing an etching process on the first dielectric layer based on the via layout pattern to expose the connecting metal layer in the vias in the first dielectric layer, including: Performing an etching process on the first dielectric layer and the second dielectric layer simultaneously based on the via layout pattern to expose the connecting metal layer in the vias in the first dielectric layer and the second dielectric layer.

4. The method according to claim 1, characterized in that, Performing an etching process on the first metal layer and the second metal layer simultaneously to obtain a first patterned metal layer and a second patterned metal layer, including: Forming a first patterned photoresist layer and a second patterned photoresist layer above the first metal layer and the second metal layer respectively; Performing exposure and development processes based on the first patterned photoresist layer and the second patterned photoresist layer to obtain the first patterned metal layer and the second patterned metal layer; Removing the first patterned photoresist layer and the second patterned photoresist layer.

5. The method according to claim 1, characterized in that Forming a first metal layer and a second metal layer on the first surface and the second surface respectively, and forming a connecting metal layer in the vias, including: Depositing a first metal material layer; the first metal material layer covers the first surface and the second surface, and covers the sidewalls of the vias; Depositing a second metal material layer; the second metal material layer covers the first surface and the second surface, and completely fills the interior of the vias to obtain the first metal layer, the second metal layer, and the connecting metal layer.

6. The method according to claim 1, wherein Before forming a connection structure above the connecting metal layer, the method further includes: Forming a shielding layer above the first dielectric layer; the material of the shielding layer is a metal material; Performing an etching process on the shielding layer based on the via layout pattern to expose the connecting metal layer in the shielding layer.

7. The method according to claim 1, characterized in that, Before forming a first dielectric layer on the first patterned metal layer, the method further includes: Forming a reinforcing structure above the first patterned metal layer; Etching the first dielectric layer based on the via layout pattern to expose the connecting metal layer in the via in the first dielectric layer, including: Etching the first dielectric layer and the reinforcing structure based on the via layout pattern to expose the connecting metal layer in the via in the first dielectric layer and the reinforcing structure.

8. The method according to claim 1, characterized in that, The method further includes: Forming a second semiconductor structure; Performing a first thermocompression bonding on the first semiconductor structure and the second semiconductor structure based on the connecting structure to obtain a first bonded structure; during the first thermocompression bonding process, the first bonding temperature is 80°C to 100°C, the first bonding pressure is 0.1 Mpa to 0.2 Mpa, and the first bonding time is 20 s to 60 s; When the first bonded structure meets the bonding requirements, performing a second thermocompression bonding on the first semiconductor structure and the second semiconductor structure to obtain a second bonded structure; during the second thermocompression bonding process, the second bonding temperature is 100°C to 300°C, the second bonding pressure is 0.3 Mpa to 3 Mpa, the second bonding time is 10 min to 20 min, and both the second bonding temperature and the second bonding pressure increase in a gradient manner.

9. The method according to claim 8, wherein The method further includes: Sealing the periphery of the second bonded structure.

10. A semiconductor structure, characterized in that, Including: A second metal layer, a glass substrate, a first metal layer, a first dielectric layer, and a connecting structure stacked in sequence; The glass substrate has vias, a connecting metal layer is provided in the vias, and the connecting structure is located above the connecting metal layer.

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