Chip packaging method and chip

Abstract

The invention discloses a chip packaging method and a chip, and belongs to the technical field of chip packaging. The chip packaging method comprises the following steps: performing wafer testing on a first target wafer, and determining a power consumption test value of each to-be-packaged chip on the first target wafer; dividing each chip to be packaged into a plurality of chip sets according to the size of the power consumption test value, and calculating allowable packaging thermal resistance according to the power consumption range of each chip set; determining a packaging optimization structure corresponding to the packaging thermal resistance satisfied by each chip set; and packaging each to-be-packaged chip on the first target wafer by using the corresponding packaging optimization structure. According to the invention, grouping is carried out according to the power consumption of each to-be-packaged chip on the wafer, and a corresponding packaging optimization scheme is selected for packaging according to the packaging thermal resistance of each chip set, so that the high-power-consumption chip uses high-heat-dissipation packaging, the low-power-consumption chip uses low-heat-dissipation packaging, the problems of thermal redundancy and insufficient heat dissipation are solved on the premise of meeting the chip performance, and the packaging efficiency is improved. And low-cost and high-performance packaging is achieved.

Description

Technical Field

[0001] This application belongs to the technical field of chip packaging, and particularly relates to a chip packaging method and a chip. Background Art

[0002] With the improvement of chip integration, the heat generated by the chip is also increasing continuously. If the heat cannot be dissipated in time, it will cause the chip temperature to rise. Excessive temperature will lead to a sharp increase in the failure rate and malfunction rate of semiconductor devices. Therefore, before chip processing, package thermal design is required, that is, by reasonably designing the package structure, materials and heat dissipation methods of the chip to ensure that the heat generated during the operation of the chip can be effectively dissipated, and to avoid the decline of chip performance and reliability caused by overheating.

[0003] Inevitable process deviations exist in the chip manufacturing process. For chips on different batches of wafers and chips at different positions on the same wafer, process parameters such as effective channel length and critical dimensions are inconsistent, resulting in differences in leakage current between different chips. Therefore, the difference in leakage current further leads to differences in static power consumption and total power consumption between chips. Thus, during the chip development process, even if the same package thermal design is used for each chip, due to the difference in static power consumption between chips, there may be problems such as high package cost caused by excessive package heat dissipation capacity and easy occurrence of thermal redundancy, or insufficient package heat dissipation capacity leading to chip performance degradation and thermal runaway. Summary of the Invention

[0004] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application proposes a chip packaging method and a chip, which use different package thermal optimization structures for chips with different power consumption ranges, and while meeting the chip performance, solve the problems of thermal redundancy and insufficient heat dissipation at the same time, achieving low-cost and high-performance packaging.

[0005] In a first aspect, this application provides a chip packaging method, including: Performing wafer testing on a first target wafer to determine the power consumption test values of each chip to be packaged on the first target wafer; Dividing each chip to be packaged into multiple chip groups according to the magnitude of the power consumption test value, and calculating the allowable package thermal resistance corresponding to each chip group according to the power consumption range of each chip group; Determining the package optimization structure corresponding to each chip group that meets the package thermal resistance; Packaging each chip to be packaged on the first target wafer using the corresponding package optimization structure.

[0006] According to an embodiment of this application, dividing each chip to be packaged into multiple chip groups according to the magnitude of the power consumption test value, and calculating the allowable package thermal resistance corresponding to each chip group according to the power consumption range of each chip group, includes: Divide the total power consumption range defined by each power consumption test value into a target number of sub - ranges, and the chips to be encapsulated corresponding to each sub - range form a chip group; Calculate the allowable package thermal resistance according to the power consumption range corresponding to each sub - range.

[0007] According to an embodiment of the present application, the package thermal resistance corresponding to each sub - range is calculated based on the maximum power consumption test value of the sub - range, and the package thermal resistance is determined according to the following formula: R = (TJ - Ta) / P Where, R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value within the range.

[0008] According to an embodiment of the present application, the chip packaging method further includes: Generate a wafer power consumption distribution map according to the distribution of chip groups on several first target wafers. The wafer power consumption distribution map determines the distribution area of each chip to be encapsulated based on the power consumption test value of the chip to be encapsulated; Package each chip to be encapsulated on the second target wafer with a package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map. The second target wafer has the same structure as the first target wafer.

[0009] According to an embodiment of the present application, the wafer power consumption distribution map includes a power consumption distribution area, and the chips to be encapsulated of the same chip group are distributed within the power consumption distribution area; Package each chip to be encapsulated on the second target wafer with a package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map, including: Determine the package thermal resistance corresponding to the power consumption distribution area on the second target wafer according to the wafer power consumption distribution map; Package each chip to be encapsulated within each power consumption distribution area with a package optimization structure corresponding to the package thermal resistance.

[0010] According to an embodiment of the present application, the wafer power consumption distribution map further includes a critical test area, which is located between multiple power consumption distribution areas and distributes chips to be encapsulated of multiple chip groups; Package each chip to be encapsulated on the second target wafer with a package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map, and further includes: Test the power consumption of each chip to be encapsulated within the corresponding critical test area on the second target wafer; Package each chip to be encapsulated within the critical test area with the corresponding package optimization structure according to the power consumption test value.

[0011] According to an embodiment of the present application, each power consumption distribution area and critical test area are alternately arranged in sequence on the wafer in the direction from the inside to the outside, and the outer area surrounds the inner area. The critical test area is distributed with the chips to be packaged of the chip groups corresponding to two adjacent power consumption distribution areas, and the power consumption test value of the chips to be packaged in the outer power consumption distribution area is greater than that of the chips to be packaged in the inner power consumption distribution area.

[0012] According to an embodiment of the present application, the package optimization structure involves at least one of material optimization, substrate optimization, package form optimization, and external heat dissipation optimization.

[0013] According to an embodiment of the present application, the material optimization involves the thermal conductivity coefficient of the packaging material, and involves at least one of carrier board material optimization, molding compound material optimization, chip bonding adhesive material optimization, underfill material optimization, and interface thermal conductive adhesive material optimization.

[0014] According to an embodiment of the present application, the substrate optimization involves at least one of whether to open a window in the solder mask of the packaging substrate, the window opening area, the window opening shape, and the copper cladding rate of the substrate.

[0015] According to an embodiment of the present application, the package form optimization involves at least one of ball grid array package, land grid array package, and flip chip ball grid array package.

[0016] According to an embodiment of the present application, the external heat dissipation optimization involves at least one of radiator optimization, fan cooling optimization, and liquid cooling optimization.

[0017] In a second aspect, the present application provides a chip, and the chip is manufactured according to the foregoing chip packaging method.

[0018] According to the chip packaging method and the chip of the present application, by grouping according to the power consumption of each chip to be packaged on the wafer and selecting a corresponding package optimization scheme for the package thermal resistance of each chip group for packaging, the effect that high-power chips use high-heat dissipation packaging and low-power chips use low-heat dissipation packaging is achieved. On the premise of meeting the chip performance, the problems of thermal redundancy and insufficient heat dissipation are solved simultaneously, and low-cost and high-performance packaging is achieved.

[0019] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is one of the flow schematic diagrams of the chip packaging method provided by the embodiment of the present application; Figure 2 It is the second flowchart of the chip packaging method provided by the embodiment of the present application; Figure 3 It is the third flowchart of the chip packaging method provided by the embodiment of the present application; Figure 4 It is the first structural diagram of the chip packaging structure provided by the embodiment of the present application; Figure 5 It is the second structural diagram of the chip packaging structure provided by the embodiment of the present application; Figure 6 It is the third structural diagram of the chip packaging structure provided by the embodiment of the present application; Figure 7 It is the fourth flowchart of the chip packaging structure provided by the embodiment of the present application; Figure 8 It is the schematic diagram of the power consumption distribution map after wafer testing provided by the embodiment of the present application.

[0021] Reference numerals: Chip to be packaged 1, encapsulant 2, interconnect bonding wire 3, packaging substrate 4, adhesive tape 5, solder ball 6, pad 7, auxiliary chip heat sink 8. Detailed implementation manners

[0022] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings. In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Where the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0023] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not indicate that the present disclosure necessarily has a first element, component, region, layer, or part.

[0024] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0025] In the related art, the chip package needs to be thermally designed according to factors such as the power consumption of the chip, the working environment, and the heat dissipation requirements. Usually, a determined chip power consumption value is obtained through power consumption simulation first, and then based on this power consumption value, thermal simulation is carried out in simulation software, and finally the package structure and materials that meet the chip heat dissipation requirements are determined. Therefore, if the package structure, material parameters, and package processing parameters of the chips are all the same, then their heat dissipation performances are basically the same, that is, the package thermal resistances of all chips are basically the same. For chips with high heat dissipation requirements, the difficulty of their package thermal design is very high. Especially in a high-temperature environment, it is required that the thermal resistance of the package is small enough to meet the normal heat dissipation of the chip at high temperature, so as to ensure that the highest temperature of the chip, that is, the junction temperature, does not exceed the specified temperature. Therefore, the accurate evaluation of chip power consumption plays an important role in package thermal design.

[0026] The power consumption of a chip includes dynamic power consumption and static power consumption. Among them, dynamic power consumption refers to the power consumption generated when the circuit is working, which can be further divided into switching power consumption and short-circuit power consumption. Switching power consumption is the power consumption generated by charging and discharging the load capacitance when the circuit flips. Short-circuit power consumption refers to the short-circuit power consumption between NMOS and PMOS during the circuit state transition. The dynamic power consumption of a chip mainly depends on the capacitance load of the circuit, chip voltage, operating frequency, and signal switching rate. Therefore, for a batch of chips in the same working state, their dynamic power consumption is basically the same.

[0027] Static power consumption is the power consumption generated when the state of the circuit does not flip, that is, when the chip circuit is in an inactive or static state. It mainly includes subthreshold leakage current, gate leakage current, Drain current caused by Gate, and power consumption caused by junction reverse bias current. Static power consumption is related to the leakage current of the chip. The leakage current is affected by the manufacturing process of the chip. Due to inevitable process deviations in the chip manufacturing process, the process parameters such as the effective channel length and critical dimension of chips on different batches of wafers and chips at different positions on the same wafer are not consistent, resulting in differences in the leakage current of different chips. The difference in leakage current further leads to differences in the static power consumption and total power consumption between chips.

[0028] At the same time, as the temperature rises, the leakage current shows an exponential increase trend. When the chip operates at high temperature, the proportion of static power consumption in the total power consumption of the chip increases sharply.

[0029] In summary, in the conventional chip development process, even if the dynamic power consumption of each chip is the same and the same package thermal design is used, due to the difference in static power consumption between chips, the chip junction temperature during operation will still be inconsistent. When a chip with low power consumption uses a package with a fixed thermal resistance, the package heat dissipation can easily meet the requirements of the chip, resulting in high package cost and easy occurrence of thermal redundancy. When a chip with high power consumption uses a package with the same thermal resistance, it is difficult for the package heat dissipation to meet the requirements of the chip, and there are problems such as chip performance degradation and thermal runaway.

[0030] This application proposes a chip packaging method and a chip. By grouping the chips to be packaged on the wafer according to their power consumption and selecting corresponding package optimization schemes for the package thermal resistance of each chip group for packaging, it enables high-power chips to use high-heat dissipation packages and low-power chips to use low-heat dissipation packages. On the premise of meeting the chip performance, it solves the problems of thermal redundancy and insufficient heat dissipation at the same time, achieving low-cost and high-performance packaging.

[0031] In this application, the "first target wafer" and "second target wafer" mentioned refer to different individual wafers produced with the same wafer structure during wafer mass production. For example, among a large number of wafers produced in one mass production, a part is used as the "first target wafer" and the other part is the "second target wafer". Or, in multiple mass production batches of a certain type of wafer, the "first target wafer" is the wafer produced in the first batch or several batches at the beginning, and the "second target wafer" is the wafer produced in subsequent batches.

[0032] Referring to Figure 1 , Figure 1 shows the flow of a chip packaging method. An embodiment of the present application proposes a chip packaging method. In this embodiment, the chip packaging method includes step 10, step 20, step 30, and step 40.

[0033] Step 10: Perform wafer testing on the first target wafer to determine the power consumption test values of each chip to be packaged on the first target wafer; Step 20: Divide each chip to be packaged into multiple chip groups according to the magnitude of the power consumption test value, and calculate the allowable corresponding packaging thermal resistance according to the power consumption range of each chip group; Step 30: Determine the packaging optimization structure corresponding to the packaging thermal resistance of each chip group; Step 40: Package each chip to be packaged on the first target wafer using the corresponding packaging optimization structure.

[0034] It should be noted that the number of first target wafers tested in wafer testing can be multiple, and the number of chips to be packaged on each wafer is also multiple. Each chip to be packaged is a bare die. All the chips to be packaged in this embodiment have the same circuit architecture, which is equivalent to that all the chips to be packaged on the first target wafer have the same dynamic power consumption. In addition, the chips to be packaged on the subsequent-mentioned "second target wafer" have the same circuit architecture as those on the "first target wafer".

[0035] Wafer testing (CP, Chip Probing) is an important link in the integrated circuit (IC) manufacturing process. It occurs after the wafer manufacturing process stage and aims to ensure the quality of the chips entering the packaging link. Wafer testing can be carried out using a probe station and a tester. During the testing process, basic electrical parameters such as connectivity testing (DC failing, power short), leakage current (Ileakage), power consumption (SIDD), and functional test items can be obtained.

[0036] This embodiment is mainly for obtaining power consumption test values. Due to different actual leakage current and other characteristics of each chip to be packaged, the obtained power consumption test values are different. Thus, the static power consumption differences between the chips to be packaged can be reflected by testing the power consumption test values.

[0037] During the wafer testing process, the test temperature of the first target wafer is any value within the temperature range in which the chip to be packaged can operate. For example, if the operating range of the chip to be packaged is between -50°C and 120°C, the test temperature can be any value within this range, such as 0°C, 50°C, or 100°C. Moreover, all chips to be packaged have the same test temperature during the wafer testing process to avoid distortion of the power consumption differences caused by test temperature differences. Of course, the temperature range in which the chip to be packaged can operate is determined based on the specific circuit architecture and material selection of the chip to be packaged.

[0038] After sorting the chips to be packaged according to the power consumption test values from small to large and grouping them, the power consumption differences between the chips to be packaged within each chip group are small. Thus, after being packaged with the same package optimization structure, it can ensure meeting the heat dissipation requirements without much redundancy.

[0039] Refer to Figure 2 , Figure 2 shows a chip packaging process. As an example, after wafer manufacturing is completed, wafer CP testing is performed. According to the power consumption values of all the tested chips, chips with different power consumption ranges are defined as different Bins. Chips with low power consumption from a to b are defined as Bin1, chips with medium power consumption from b to c are defined as Bin2, chips with high power consumption from c to d are defined as Bin3, and chips with ultra-high power consumption from d to e are defined as Bin4. At the same time, under the conditions of the specified ambient operating temperature and chip junction temperature threshold, through the formula calculation method, the corresponding package thermal resistance ranges for different Bins can be obtained. The upper limit of the thermal resistance for interval Bin1 is defined as B, the upper limit of the thermal resistance for interval Bin2 is defined as C, the upper limit of the thermal resistance for interval Bin3 is defined as D, and the upper limit of the thermal resistance for interval Bin4 is defined as E. In terms of package thermal design, there are usually four major types of methods to optimize the package thermal resistance, namely package material optimization, package substrate optimization, package form optimization, and external heat dissipation optimization, forming four optimization schemes. The chips corresponding to interval Bin1 are packaged using optimization scheme 1 to obtain product one with low heat dissipation packaging, the chips corresponding to interval Bin2 are packaged using optimization scheme 2 to obtain product two with medium heat dissipation packaging, the chips corresponding to interval Bin3 are packaged using optimization scheme 3 to obtain product three with high heat dissipation packaging, and the chips corresponding to interval Bin4 are packaged using optimization scheme 4 to obtain product four with ultra-high heat dissipation packaging.

[0040] Refer to Figure 3 , Figure 3The flowchart of a chip packaging method is shown. In some embodiments, each chip to be packaged is divided into multiple chip groups according to the magnitude of the power consumption test value, and the allowable packaging thermal resistance of each chip group is calculated based on its power consumption range, including: Step 21: Divide the total power consumption range defined by each power consumption test value into a target number of sub-ranges, and the chips to be packaged corresponding to within a sub-range form a chip group; Step 22: Calculate the allowable packaging thermal resistance according to the power consumption range corresponding to each sub-range.

[0041] One way to divide into a target number of ranges can be: Determine the total power consumption range according to the minimum and maximum values of the power consumption test values, and then divide this total power consumption range into a target number of equal-span ranges. Each chip to be packaged within an equal-span range forms a chip group.

[0042] Another way to divide the chip groups can also be: Divide the total number of chips to be packaged equally into a target number of groups, where the number of grouped chips in each group is the total number divided by the target number; then select the chips to be packaged with the number of grouped chips in ascending order of the power consumption test values as a chip group.

[0043] As an example, the minimum value of the power consumption test values of all chips to be packaged is 1.73W, and the maximum value is 2.82W. In ascending order, taking the division into four ranges Bin1, Bin2, Bin3, and Bin4 as an example, the power range of range Bin1 is [1.73W, 2W), the power range of range Bin2 is [2W, 2.27W), the power range of range Bin3 is [2.27W, 2.55W), and the power range of range Bin4 is [2.55W, 2.82W].

[0044] In some embodiments, the number of chip groups is determined according to the number of solutions of the packaging optimization structure, and the number of chip groups is equal to the number of solutions.

[0045] It can be understood that different chip groups will be packaged using different packaging optimization structures. Therefore, the number of chip groups should be less than or equal to the number of solutions of the packaging optimization structures that can be achieved. To make full use of different packaging optimization structures, the number of chip groups can be made equal to the number of solutions. The relevant content of the packaging optimization structure will be described later.

[0046] In another example, the minimum power consumption test value of all chips to be encapsulated is 1.73W, and the maximum value is 2.82W. They are divided into five intervals: Bin1, Bin2, Bin3, Bin4, and Bin5. The power range of interval Bin1 is [1.73W, 1.948W), the power range of interval Bin2 is [1.948W, 2.166W), the power range of interval Bin3 is [2.166W, 2.384), the power range of interval Bin4 is [2.384W, 2.602W), and the power range of interval Bin5 is [2.602W, 2.82W].

[0047] In some embodiments, the corresponding package thermal resistance within each sub-interval is calculated based on the maximum power consumption test value of the sub-interval, and the package thermal resistance is determined according to the following formula: R = (TJ - Ta) / P Where, R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value within the interval.

[0048] The chip junction temperature threshold is determined according to the specific circuit architecture and material selection of the chips to be encapsulated, etc. The ambient operating temperature can be the maximum value within the operating range of the product to which the chips to be encapsulated are applied. For example, the chips to be encapsulated can be applied to consumer electronics products, industrial electronics products, and automotive electronics products, and their specific operating temperature ranges are different.

[0049] As an example, it is set that the ambient operating temperature is 85°C and the chip junction temperature threshold is 125°C. The corresponding package thermal resistance for each interval is calculated based on the maximum power consumption test value corresponding to the interval and according to the above formula. Taking the power consumption test values of all chips to be encapsulated divided into four intervals: Bin1, Bin2, Bin3, and Bin4 as an example, the maximum power consumption test value of interval Bin1 is 2W, and the calculated package thermal resistance is 20°C / W; the maximum power consumption test value of interval Bin2 is 2.27W, and the calculated package thermal resistance is 17.62°C / W; the maximum power consumption test value of interval Bin3 is 2.55W, and the calculated package thermal resistance is 15.69°C / W; the maximum power consumption test value of interval Bin4 is 2.82W, and the calculated package thermal resistance is 14.18°C / W. Thus, for the chips to be encapsulated in Bin1, the upper limit of its thermal resistance is defined as 20°C / W; for the chips to be encapsulated in Bin2, the upper limit of its thermal resistance is defined as 17.62°C / W; for the chips to be encapsulated in Bin3, the upper limit of its thermal resistance is defined as 15.69°C / W; for the chips to be encapsulated in Bin4, the upper limit of its thermal resistance is defined as 14.18°C / W.

[0050] The encapsulation optimization structure refers to the thermal resistance optimization design of the encapsulation structure to improve the heat dissipation capacity of the encapsulation structure, which usually involves the heat generation and heat transfer capabilities of materials and structures, as well as aspects such as auxiliary heat dissipation. For example, the encapsulation optimization structure involves at least one of material optimization, substrate optimization, encapsulation form optimization, and external heat dissipation optimization.

[0051] It should be noted that in each type of optimization method, the optimization parameters can be further controlled to obtain different levels of encapsulation thermal resistance optimization with different strengths. Therefore, by combining various optimization methods and parameters, different optimization schemes can be formed to achieve the expected thermal resistance range.

[0052] In some embodiments, material optimization involves the thermal conductivity of the encapsulation materials, and involves at least one of carrier board material optimization, molding compound material optimization, chip bonding adhesive material optimization, underfill material optimization, and interface thermal conductive adhesive material optimization.

[0053] Carrier board materials can be divided into flexible substrates and rigid substrates. Flexible substrate materials include PI (polyimide), PET (polyester), and PEEK (polyether ether ketone), etc. Rigid substrates include FR4 (Flame-Retardant 4), ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine), and ceramics, etc. Molding compounds are divided into organic and inorganic types. Inorganic materials are mainly glass and ceramics, etc., while organic materials include epoxy resins, polyimides, thermoplastics, etc. Chip bonding adhesives mainly include epoxy resin chip bonding adhesives, acrylic chip bonding adhesives, and polyurethane adhesives, etc. Underfill materials mainly include flip chip underfills and BGA underfills, etc. Interface thermal conductive adhesive materials include thermal conductive silicone sheets, thermal conductive pastes, thermal conductive gels, thermal conductive double-sided tapes, thermal conductive greases, etc. When optimizing materials, corresponding optimization schemes can be formulated by selecting the above various materials and comprehensively considering aspects such as thermal conductivity and heat resistance.

[0054] In some embodiments, substrate optimization involves at least one of whether to open a window in the solder mask of the encapsulation substrate, the window opening area, the window opening shape, and the copper clad ratio of the substrate.

[0055] The solder mask on the substrate is the solder resist layer. By opening a window in the solder mask, the circuit part on the substrate can be exposed, thereby improving heat dissipation. The window opening area and window opening shape also affect the heat dissipation of the solder mask window. The copper clad ratio of the substrate refers to the ratio of the area covered by the copper foil on the substrate to the entire substrate area, which directly affects the heat dissipation performance of the substrate.

[0056] In some embodiments, the package form optimization involves at least one of wire bonding ball grid array (WBBGA), wire bonding land grid array (WBLGA), and flip chip ball grid array (FCBGA).

[0057] WBBGA fabricates an array of solder balls at the bottom of the package substrate as the I / O terminals of the chip to interconnect with the substrate, and it is a package form that connects the chip to the substrate by wire bonding. WBLGA also uses wire bonding to connect to the substrate, but the contact form is a planar grid. WBLGA uses point contact technology (contacts) to achieve interconnection with the substrate, and the contacts are all on the substrate. Its interconnection principle is similar to that of WBBGA, but the contacts of WBLGA can be unclamped to replace the chip, while the solder balls of WBBGA are fixed. FCBGA uses spherical solder joints to fix the package to the substrate, and it is a packaging technology that inverts the chip and connects it to the package substrate, with advantages such as high integration, small size, high performance, and low power consumption.

[0058] In some embodiments, the external heat dissipation optimization involves at least one of heat sink optimization, fan cooling optimization, and liquid cooling optimization.

[0059] The external heat dissipation optimization is achieved by selecting the form of external heat dissipation or whether to set up external heat dissipation to achieve different heat dissipation capabilities. The heat sink dissipates heat by designing corresponding heat dissipation structures (such as heat sinks, etc.) to increase the heat exchange area. Fan cooling uses wind to accelerate heat dissipation, and liquid cooling uses liquid for heat exchange to improve the heat dissipation speed.

[0060] As an example, the power consumption test values of all chips to be encapsulated are divided into four intervals Bin1, Bin2, Bin3, and Bin4. For the chips to be encapsulated corresponding to the Bin1 interval, Optimization Scheme 1 is adopted: on the basis of the conventional package thermal design, material optimization is carried out, the chip bonding adhesive and the encapsulant are optimized, and its thermal resistance is 20 °C / W; for the chips to be encapsulated corresponding to the Bin2 interval, Optimization Scheme 2 is adopted: combined optimization of materials and substrates is carried out, specifically, the encapsulant can be optimized and the method of partial window opening of the substrate is used, and its thermal resistance is 17.62 °C / W; for the chips to be encapsulated corresponding to the Bin3 interval, Optimization Scheme 3 is adopted: combined optimization of the substrate and the package form is carried out, specifically, the method of full window opening of the substrate is adopted, and the package form is changed from the initial WBBGA to WBLGA, and its thermal resistance is 15.69 °C / W; for the chips to be encapsulated corresponding to the Bin4 interval, Optimization Scheme 4 is adopted: combined optimization of the package form and external heat dissipation is carried out, specifically, the package form is changed from WBBGA to FCBGA, and at the same time, a heat sink and a fan are added, and its thermal resistance is 14.18 °C / W.

[0061] Refer to Figures 4 - 6 , Figures 4 - 6 which respectively show a chip package structure and have three different heat dissipation capabilities. The chip 1 to be encapsulated is fixed to the package substrate 4 through the chip bonding adhesive 5 and is electrically connected to the package substrate 4 through the interconnect bonding wire 3. The encapsulant 2 is used for encapsulation to fix the chip 1 to be encapsulated and isolate it from the outside.

[0062] Figure 4 Compared with Figure 5 , the main difference is the different welding methods under the package substrate. Figure 4 Welding is achieved by solder balls 6. Figure 5 Welding is achieved by pads 7. Figure 5 The heat dissipation capacity of the package structure shown is greater than that of Figure 4 . Figure 4 Compared with Figure 6 , Figure 6 a finned heat sink 8 is added to further improve the heat dissipation capacity through external heat dissipation. Figure 5 Compared with Figure 6 , Figure 5 the welding method is optimized and welding is achieved by pads 7. Figure 6 A finned heat sink 8 is added to optimize the external heat dissipation. Overall, Figure 6 the heat dissipation capacity of the package structure shown is better than that of Figure 5 . Of course, Figures 4 - 6 the chip package structure shown does not limit the above package optimization structure, and the specific structure can be set according to requirements.

[0063] Refer to Figure 7 ,Figure 7 The flowchart of a chip packaging method is shown. In this embodiment, the chip packaging method further includes step 50 and step 60.

[0064] Step 50: Generate a wafer power consumption distribution map according to the distribution of chip groups on several first target wafers. The wafer power consumption distribution map determines the distribution areas of each chip to be packaged based on the power consumption test values of the chips to be packaged. Step 60: Package each chip to be packaged on the second target wafer with a packaging optimization structure corresponding to the distribution area according to the wafer power consumption distribution map. The second target wafer has the same structure as the first target wafer.

[0065] The wafer power consumption distribution map can indicate the distribution areas of the chips to be packaged with different power consumption test values on the first target wafer. Since the first target wafer and the second target wafer are wafers with the same structure, the wafer power consumption distribution map can also indicate the power consumption test values of the chips to be packaged in each distribution area on the second target wafer.

[0066] When packaging the second target wafer according to the wafer power consumption distribution map, the corresponding packaging optimization structure can be directly determined according to the packaging thermal resistance corresponding to the chip group in each distribution area. Therefore, it is not necessary to perform power consumption tests on each chip to be packaged, simplifying the packaging process.

[0067] In some embodiments, the wafer power consumption distribution map includes power consumption distribution areas, and the chips to be packaged of the same chip group are distributed in the power consumption distribution areas; step 60 includes: determining the packaging thermal resistance corresponding to the power consumption distribution area on the second target wafer according to the wafer power consumption distribution map; packaging each chip to be packaged in each power consumption distribution area with the packaging optimization structure corresponding to the packaging thermal resistance.

[0068] Combined with the foregoing example, on the second target wafer, the distribution area may include a first power consumption distribution area and a second power consumption distribution area. Among them, the first power consumption distribution area distributes the chips to be packaged corresponding to the Bin1 interval. Based on the conventional packaging thermal design, the materials can be directly optimized, and the patch glue and plastic encapsulant are optimized to make its thermal resistance 20 °C / W; the second power consumption distribution area distributes the chips to be packaged corresponding to the Bin2 interval. The combination of materials and substrates can be directly optimized, specifically, the plastic encapsulant can be optimized, and the method of local window opening of the substrate can be used to make its thermal resistance 17.62 °C / W.

[0069] In addition, only two power consumption distribution areas are selected for illustration in the foregoing example for convenience of explanation, but the specific number of power consumption distribution areas is the same as the number of chip groups, and can be specifically set according to the number requirement of the chip groups, and can be specifically referred to the foregoing embodiments.

[0070] In some embodiments, the wafer power consumption distribution map further includes a critical test area, which is located between multiple power consumption distribution areas and is distributed with the chips to be packaged of multiple chip groups; step 60 includes: testing the power consumption of each chip to be packaged in the corresponding critical test area on the second target wafer, and packaging each chip to be packaged in the critical test area by using the corresponding packaging optimization structure according to the power consumption test value.

[0071] It can be understood that in the case of low precision control in the wafer manufacturing process, the power consumption distribution of each chip to be packaged on the wafer does not fully meet the established rules, resulting in a situation where a certain area on the prepared wafer may be distributed with chips to be packaged with a large span of power consumption test values. The power consumption test value range corresponding to this area may involve multiple chip groups on the first target wafer.

[0072] In such cases, it is not suitable to package this area with the packaging optimization structure corresponding to a certain chip group. Therefore, the power consumption of each chip to be packaged in this area can be tested, and the corresponding packaging optimization structure can be determined according to the power consumption test value according to the packaging correspondence on the first target wafer.

[0073] In some embodiments, each power consumption distribution area and the critical test area are alternately arranged in sequence on the wafer in the direction from the inside to the outside, the outer area surrounds the inner area, the critical test area is distributed with the chips to be packaged of the chip groups corresponding to two adjacent power consumption distribution areas, and the power consumption test value of the chips to be packaged in the outer power consumption distribution area is greater than the power consumption test value of the chips to be packaged in the inner power consumption distribution area.

[0074] Refer to Figure 8 , Figure 8 shows a schematic diagram of a wafer power consumption distribution map. As an example, the power consumption of the wafers in the first batch (i.e., the first target wafers) is subjected to overlay processing to obtain the wafer power consumption distribution map. Four power consumption distribution areas and three critical test areas are defined on the wafer. The four power consumption distribution areas respectively correspond to the power consumption test values in the four intervals of Bin1, Bin2, Bin3, and Bin4, and their power ranges are [1.73W, 2W), [2W, 2.27W), [2.27W, 2.55W), and [2.55W, 2.82W] respectively. The first critical test area is located between the Bin1 distribution area and the Bin2 distribution area, and its power range is [1.73W, 2.27W); the second critical test area is located between the Bin1 distribution area and the Bin2 distribution area, and its power range is [2W, 2.55W); the third critical test area is located between the Bin1 distribution area and the Bin2 distribution area, and its power range is [2.27W, 2.82W].

[0075] For the chips to be packaged in the subsequent mass production batches of wafers (i.e., the second target wafers), for the chips to be packaged located in the distribution areas of Bin1, Bin2, Bin3, and Bin4, power consumption testing is not required, and the corresponding package optimization solutions can be directly selected for packaging and processing.

[0076] Perform power consumption testing on the chips to be packaged located in the first critical test area. When the power consumption value is within the range of [1.73W, 2W), select the low heat dissipation packaging solution of Optimization Solution 1 for packaging. When the power consumption value is within the range of [2W, 2.27W), select the medium heat dissipation packaging solution of Optimization Solution 2 for packaging. Perform power consumption testing on the chips to be packaged located in the second critical test area. When the power consumption value is within the range of [2W, 2.27W), select the medium heat dissipation packaging solution of Optimization Solution 2 for packaging. When the power consumption value is within the range of [2.27W, 2.55W), select the high heat dissipation packaging solution of Optimization Solution 3 for packaging. Perform power consumption testing on the chips to be packaged located in the third critical test area. When the power consumption value is within the range of [2.27W, 2.55W), select the high heat dissipation packaging solution of Optimization Solution 3 for packaging. When the power consumption value is within the range of [2.55W, 2.82W], select the ultra-high heat dissipation packaging solution of Optimization Solution 4 for packaging.

[0077] An embodiment of the present application also provides a chip, which is prepared according to the foregoing chip packaging method.

[0078] The chip in this embodiment is packaged by the foregoing chip packaging method. On the premise of meeting the chip performance, it is not easy to have problems of thermal redundancy and insufficient heat dissipation, achieving low-cost and high-performance packaging. For the specific chip packaging method, refer to the foregoing, and this embodiment will not be elaborated herein.

[0079] In this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0080] Although embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A chip packaging method, characterized in that, Including: Performing a wafer test on a first target wafer to determine the power consumption test values of each chip to be packaged on the first target wafer; Dividing each chip to be packaged into multiple chip groups according to the magnitude of the power consumption test value, and calculating the allowable package thermal resistance according to the power consumption ranges of each chip group; Determining the package optimization structure corresponding to the package thermal resistance that each chip group meets; Packaging each chip to be packaged on the first target wafer using the corresponding package optimization structure.

2. The chip packaging method according to claim 1, wherein The step of dividing each chip to be packaged into multiple chip groups according to the magnitude of the power consumption test value, and calculating the allowable package thermal resistance according to the power consumption ranges of each chip group includes: Dividing the total power consumption range defined by each power consumption test value into a target number of sub-ranges, and the chips to be packaged corresponding to each sub-range form a chip group; Calculating the allowable package thermal resistance according to the power consumption ranges corresponding to each sub-range.

3. The chip packaging method according to claim 2, characterized in that The package thermal resistance corresponding to each sub-range is calculated based on the maximum power consumption test value of the sub-range, and the package thermal resistance is determined according to the following formula: R = (TJ - Ta) / P Wherein, R is the package thermal resistance, TJ is the chip junction temperature threshold, Ta is the ambient operating temperature, and P is the maximum power consumption test value within the sub-range.

4. The chip packaging method according to any one of claims 1-3, characterized in that, The chip packaging method further includes: Generating a wafer power consumption distribution map according to the distribution of the chip groups on several first target wafers, and the wafer power consumption distribution map determines the distribution area of each chip to be packaged based on the power consumption test value of the chip to be packaged; Packaging each chip to be packaged on a second target wafer using the package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map, and the second target wafer has the same structure as the first target wafer.

5. The chip packaging method according to claim 4, wherein The wafer power consumption distribution map includes a power consumption distribution area, and the chips to be packaged of the same chip group are distributed within the power consumption distribution area; The step of packaging each chip to be packaged on the second target wafer using the package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map includes: Determining the package thermal resistance corresponding to the power consumption distribution area on the second target wafer according to the wafer power consumption distribution map; Packaging each chip to be packaged within each power consumption distribution area using the package optimization structure corresponding to the package thermal resistance.

6. The chip packaging method according to claim 5, wherein The wafer power consumption distribution map further includes a critical test area, the critical test area is located between multiple power consumption distribution areas, and the chips to be packaged of multiple chip groups are distributed therein; The step of packaging each chip to be packaged on the second target wafer using the package optimization structure corresponding to the distribution area according to the wafer power consumption distribution map further includes: Testing the power consumption of each chip to be packaged within the corresponding critical test area on the second target wafer; Packaging each chip to be packaged within the critical test area using the corresponding package optimization structure according to the power consumption test value.

7. The chip packaging method according to claim 6, wherein Each of the power consumption distribution regions and the critical test region are alternately arranged in sequence on the wafer in the direction from the inside to the outside, with the outer region surrounding the inner region. The critical test region is distributed with the chips to be packaged of the chip sets corresponding to two adjacent power consumption distribution regions, and the power consumption test value of the chips to be packaged in the outer power consumption distribution region is greater than that of the chips to be packaged in the inner power consumption distribution region.

8. The chip packaging method according to any one of claims 1-3, characterized in that, The packaging optimization structure involves at least one of material optimization, substrate optimization, packaging form optimization, and external heat dissipation optimization.

9. The chip packaging method according to claim 8, wherein The material optimization involves the thermal conductivity coefficient of the packaging material, and involves at least one of carrier board material optimization, molding compound material optimization, chip bonding paste material optimization, underfill material optimization, and interface thermal conductive adhesive material optimization; The substrate optimization involves at least one of whether to open a window in the solder mask of the packaging substrate, the window opening area, the window opening shape, and the copper clad ratio of the substrate; The packaging form optimization involves at least one of ball grid array packaging, land grid array packaging, and flip chip ball grid array packaging; The external heat dissipation optimization involves at least one of heat sink optimization, fan cooling optimization, and liquid cooling optimization.

10. A chip, characterized in that, The chip is manufactured by the chip packaging method according to any one of claims 1-9.

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