Pad array packaging structure and manufacturing process thereof

Abstract

The invention discloses a bonding pad array packaging structure and a manufacturing process thereof, and relates to the technical field of device packaging. The packaging structure comprises a first substrate, a second substrate, a device core, a packaging shell, a first bonding pad array and a second bonding pad array, the bottom of the first substrate is arranged on the inner surface of the bottom of the packaging shell, the first bonding pad array is arranged on the outer surface of the bottom of the packaging shell, and the device core is arranged on the top of the first substrate; the top of the second substrate is arranged on the inner surface of the top of the packaging shell, and the second bonding pad array is arranged on the outer surface of the top of the packaging shell; and the device core performs signal transmission through the first bonding pad array and the second bonding pad array. According to the bonding pad array packaging structure and the manufacturing process thereof provided by the embodiment of the invention, high-speed signals are fanned out through the second bonding pad array, so that high-speed signal interconnection between devices is facilitated; and the overall cost of the printed circuit board is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of device packaging, and particularly relates to a pad array packaging structure and a manufacturing process thereof. Background Art

[0002] Ball Grid Array (BGA) is a commonly used device packaging technology, which is often used for packaging devices with a large number of pins. Due to the large number of pins, the fan-out of signal pins has high requirements for the printed circuit board design; and with the increase in the interconnection bus rate, the processing requirements for the printed circuit board material are getting higher and higher. The whole board needs to use high-speed materials, and it is a waste to use high-speed materials for the low-speed signal part. Summary of the Invention

[0003] The present application provides a pad array packaging structure and a manufacturing process thereof, which at least solve the problem of great difficulty in the fan-out design of signal pins of ball grid array packaged devices.

[0004] In a first aspect, the present application provides a pad array packaging structure, including: a first substrate, a second substrate, a device core, a packaging shell, a first pad array, and a second pad array;

[0005] The bottom of the first substrate is disposed on the inner surface of the bottom of the packaging shell, the first pad array is disposed on the outer surface of the bottom of the packaging shell, and the device core is disposed on the top of the first substrate;

[0006] The top of the second substrate is disposed on the inner surface of the top of the packaging shell, and the second pad array is disposed on the outer surface of the top of the packaging shell;

[0007] The device core transmits signals through the first pad array and the second pad array.

[0008] In a second aspect, the present application also provides a manufacturing process of a pad array packaging structure, including:

[0009] Preparing the first substrate and the second substrate, and performing substrate pretreatment on the first substrate and the second substrate;

[0010] Preparing a second pad array on the outer surface of the top of the pretreated second substrate, preparing a first pad array on the outer surface of the bottom of the pretreated first substrate, and bonding the first substrate, the second substrate, and the device core;

[0011] Plastic encapsulating the bonded first substrate, second substrate, and device core.

[0012] The beneficial effects brought by the technical solution provided by the embodiments of the present application are as follows: By implementing a pad array package structure and its manufacturing process provided by the embodiments of the present application, high-speed signals are fanned out through the second pad array, which provides structural convenience for the fan-out of high-speed signals and is conducive to the high-speed signal interconnection between devices; and by separately fanning out low-speed signals and high-speed signals through the first pad array and the second pad array, the overall cost of the printed circuit board is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 is a schematic diagram of a pad array package structure provided by an embodiment of the present application;

[0015] Figure 2 is a schematic diagram of a device connected by a flexible circuit board provided by an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of a device connected by a high-speed cable provided by an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of a manufacturing process of a pad array package structure provided by an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of a printed circuit board assembly process provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the objectives, technical solutions, and advantages of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0020] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The numbers in the drawings of the specification only represent the distinction of each functional component or module, and do not represent the logical relationship between the components or modules. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0021] Next, various embodiments according to the present disclosure will be described in detail with reference to the drawings. It should be noted that in the drawings, the same reference numerals are assigned to components that are substantially the same or have similar structures and functions, and repeated descriptions thereof will be omitted.

[0022] Regarding the problem in the prior art that the hard disk silk screen is tightly coupled with the firmware, the present application provides the following embodiments.

[0023] In some embodiments, as Figure 1 shown, a pad array package structure includes: a first substrate 100, a second substrate 200, a device core 300, a package housing 400, a first pad array 500, and a second pad array 600;

[0024] The bottom 101 of the first substrate 100 is disposed on the inner surface 411 of the bottom of the package housing 400, the first pad array 500 is disposed on the outer surface 412 of the bottom of the package housing 400, and the device core 300 is disposed on the top 102 of the first substrate 100;

[0025] The top 202 of the second substrate 200 is disposed on the inner surface 421 of the top of the package housing 400, and the second pad array 600 is disposed on the outer surface 422 of the top of the package housing 400;

[0026] The device core 300 transmits signals through the first pad array 500 and the second pad array 600.

[0027] The first substrate 100 is internally provided with conductive traces, the second substrate 200 is internally provided with conductive traces, the device core 300 has a plurality of core pads, the plurality of core pads have a first pad area and a second pad area, the first pad array 500 includes a plurality of pads 000, and the second pad array 600 includes a plurality of pads 000;

[0028] The conductive traces provided inside the first substrate 100 are electrically connected to any one of the pads 000 in the first pad array 500, and are electrically connected to any one of the core pads in the first pad area through the bonding wire 700, so that any one of the core pads in the first pad area transmits signals through any one of the pads in the first pad array;

[0029] The conductive traces provided inside the second substrate 200 are electrically connected to any one of the pads 000 in the second pad array 600, and are electrically connected to any one of the core pads in the second pad area through the bonding wire 700, so that any one of the core pads in the second pad area transmits signals through any one of the pads in the second pad array.

[0030] The first substrate 100 and the second substrate 200 provide physical support for the device core 300 to ensure the stable installation of the device core 300 within the package housing 400. It can prevent the device core 300 from being damaged by external forces or vibrations. Through the conductive traces provided inside the first substrate 100 and the second substrate 200, the signals transmitted by the core pads can be fan - out.

[0031] In addition, the first substrate 100 and the second substrate 200 can also conduct the heat generated by the device core 300 to the package housing 400 or the heat sink to prevent overheating from affecting the performance of the device core 300. The thermal expansion coefficients of the materials of the first substrate 100 and the second substrate 200 are close to the thermal expansion coefficient of the substrate material of the device core 300 to reduce the stress during temperature changes and avoid solder joint cracking or structural failure.

[0032] The first pad array 500 and the second pad array 600 correspond to the core pads one by one. The electrical signals received by any one of the pads in the first pad array 500 and the second pad array 600 are conducted to the corresponding core pads for the device core to process the corresponding electrical signals.

[0033] Generally, any one of the pads in the first pad array 500 is a solder ball.

[0034] Preferably, any one of the core pads in the second pad area is a high - speed signal pad.

[0035] In some embodiments, as Figure 2 shown, any one of the pads in the second pad array is a solder ball;

[0036] The second pad array is used to connect a Flexible Printed Circuit (FPC). Through the flexible printed circuit, the interconnection of corresponding pads between two devices can be achieved.

[0037] In some other embodiments, such as Figure 3 shown, the pad array package structure further includes an edge connector 900;

[0038] Any pad in the second pad array is a pin pad, and the pin pad is electrically connected to the edge connector, and signals are transmitted through the gold fingers of the edge connector 900.

[0039] Connecting the gold fingers of the edge connector 900 with a high-speed cable can achieve the interconnection of corresponding pads between two devices.

[0040] By implementing a pad array package structure provided by an embodiment of the present application, fanning out high-speed signals through the second pad array provides structural convenience for fanning out high-speed signals, which is beneficial to the high-speed signal interconnection between devices; and by fanning out low-speed signals and high-speed signals through the first pad array and the second pad array respectively, the overall cost of the printed circuit board is reduced.

[0041] In some other embodiments, such as Figure 4 shown, a manufacturing process of a pad array package structure includes:

[0042] S100: Prepare a first substrate and a second substrate, and perform substrate pretreatment on the first substrate and the second substrate;

[0043] S200: Prepare a second pad array on the outer surface of the top of the pretreated second substrate, prepare a first pad array on the outer surface of the bottom of the pretreated first substrate, and bond the first substrate, the second substrate, and the device core;

[0044] S300: Encapsulate the bonded first substrate, second substrate, and device core.

[0045] Specifically, S100: Prepare a first substrate and a second substrate, and perform substrate pretreatment on the first substrate and the second substrate, including:

[0046] S110: Determine the substrate types of the first substrate and the second substrate;

[0047] S120: Clean the first substrate and the second substrate;

[0048] S130: Pattern the conductive traces inside the first substrate and the conductive traces inside the second substrate;

[0049] S140: Drill through holes in the first substrate and the second substrate, and metallize the through holes to connect the patterned conductive traces.

[0050] Specifically, S200: Prepare a second pad array on the outer surface of the top of the pre-treated second substrate, prepare a first pad array on the outer surface of the bottom of the pre-treated first substrate, and bond the first substrate, the second substrate, and the device core, including:

[0051] S2101: Sputter a seed layer on the surface of the second substrate;

[0052] S2102: Electroplate pads on the seed layer on the surface of the second substrate;

[0053] S2103: Print solder paste on the surface of the electroplated pads;

[0054] S2104: Place the pads on the surface of the electroplated pads after printing the solder paste;

[0055] S2105: Perform low-temperature reflow soldering on the pads to cure the pads on the surface of the electroplated pads;

[0056] S2106: Perform automatic optical inspection on the pads;

[0057] S2107: In response to detecting a defect in the pads, use a laser with a preset wavelength to heat the defective pads and remove the defective pads;

[0058] S2108: Re-assemble the pads to replace the defective pads;

[0059] S2109: Prepare bumps on the core pads of the device core;

[0060] S2110: Thermocompression bond the bonding wires to the core pads;

[0061] S2111: Flip the second substrate and interconnect the device core with the first substrate;

[0062] S2112: Prepare a first pad array on the outer surface of the bottom of the first substrate.

[0063] The seed layer is the base for forming metallized pads. Usually, a magnetron sputtering tool (vacuum degree < 5×10 -6 Torr) is used for seed layer sputtering. Subsequently, electroplating is performed on the seed layer with an electroplating solution to form conductive metallized pads. Usually, the electroplating solution contains CuSO4 (200 g / L) and H2SO4 (50 g / L), and the current density is 3 A / dm 2Under the current of , the power is turned on for 40 minutes to form a copper column with a diameter of 20μm and a height of 50μm. On its basis, chemical gold is plated (thickness is 0.1μm) to prevent oxidation on the surface of the metallized pad. Screen printing is usually used for printing solder paste. The speed of screen printing is 10mm / s and the accuracy is ±5μm. The pad is set on the surface of the electroplated pad after printing the solder paste. A piezoelectric nozzle is usually used to apply the pad to the surface of the solder paste. Through self-alignment, the deviation of the pad setting position is less than 2μm. Low-temperature reflow soldering requires the following processes: preheating (heating from room temperature to 150℃, heating rate 2℃ / s), reflow (peak temperature 180℃, maintained for 30 seconds), cooling (cooling at a temperature rise rate of -3℃ / s) to fix the pad on the surface of the electroplated pad and form a good electrical connection.

[0064] Afterwards, the prepared pads need to be inspected by automatic optical inspection to check whether the pads fixed on the surface of the electroplated pads are intact. Usually, an optical camera with a resolution of 5μm is used to inspect the pads at a speed of 1000 per minute. If there are defective pads, a laser with a wavelength of 980nm is used to remove the defective pads and re-implant the pads.

[0065] After the test is completed, conductive bumps are prepared on the core pads, and bonding wires are hot pressed to form a good electrical connection between the core pads and the corresponding pads through the bonding wires. The electrical signals received by the pads can be transmitted to the corresponding core pads. At this point, the preparation of the second pad array is completed, so that the high-speed signal is fanned out through the second pad array.

[0066] Then, the second substrate is flipped over, the device core is interconnected with the first substrate, and a first pad array is prepared on the outer surface of the bottom of the first substrate. The electrical signal can be conducted to the corresponding core pad through the first pad array. Usually, the first pad array is used to fan out low-speed signals and power signals.

[0067] Specifically, S300: the first substrate, the second substrate and the device core after plastic encapsulation and bonding, including:

[0068] S310: Filling the mold with packaging material;

[0069] S320: placing the bonded first substrate, second substrate and device core in a mold filled with packaging material, and waiting for the packaging material to solidify;

[0070] S330: removing the packaging material remaining on the surfaces of the first pad array and the second pad array.

[0071] For a pad array packaging structure provided in an embodiment of the present application, in the process of assembling a printed circuit board, only a flexible circuit board wire material processing link and a flexible circuit board wire material inspection link need to be added, such as Figure 5As shown, it has a high compatibility with traditional printed circuit board assembly processes.

[0072] It shows that, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this document, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least a part of the steps in [description] can include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0073] By implementing a manufacturing process for a pad array package structure provided in an embodiment of the present application, it is achieved to fan out low-speed signals using a first pad array; and fan out high-speed signals using a second pad array, reducing the overall cost of the printed circuit board.

[0074] Embodiment 1

[0075] A pad array package structure, as Figure 1 shown, includes: a first substrate 100, a second substrate 200, a device core 300, a package housing 400, a first pad array 500, and a second pad array 600;

[0076] The bottom 101 of the first substrate 100 is disposed on the inner surface 411 of the bottom of the package housing 400, the first pad array 500 is disposed on the outer surface 412 of the bottom of the package housing 400, and the device core 300 is disposed on the top 102 of the first substrate 100;

[0077] The top 202 of the second substrate 200 is disposed on the inner surface 421 of the top of the package housing 400, and the second pad array 600 is disposed on the outer surface 422 of the top of the package housing 400;

[0078] The device core 300 conducts signal transmission through the first pad array 500 and the second pad array 600.

[0079] Preferably, any core pad in the second pad region is a high-speed signal pad.

[0080] Embodiment 2

[0081] A pad array package structure, includes: a first substrate 100, a second substrate 200, a device core 300, a package housing 400, a first pad array 500, and a second pad array 600;

[0082] The bottom 101 of the first substrate 100 is disposed on the inner surface 411 of the bottom of the package housing 400, the first pad array 500 is disposed on the outer surface 412 of the bottom of the package housing 400, and the device core 300 is disposed on the top 102 of the first substrate 100;

[0083] The top 202 of the second substrate 200 is disposed on the inner surface 421 of the top of the package housing 400, and the second pad array 600 is disposed on the outer surface 422 of the top of the package housing 400;

[0084] The device core 300 transmits signals through the first pad array 500 and the second pad array 600.

[0085] Conductive traces are provided inside the first substrate 100, conductive traces are provided inside the second substrate 200, the device core 300 has a plurality of core pads, the plurality of core pads have a first pad region and a second pad region, the first pad array 500 includes a plurality of pads 000, and the second pad array 600 includes a plurality of pads 000;

[0086] The conductive trace provided inside the first substrate 100 is electrically connected to any one of the pads 000 in the first pad array 500 and is electrically connected to any one of the core pads in the first pad region through a bonding wire 700, so that any one of the core pads in the first pad region transmits signals through any one of the pads in the first pad array;

[0087] The conductive trace provided inside the second substrate 200 is electrically connected to any one of the pads 000 in the second pad array 600 and is electrically connected to any one of the core pads in the second pad region through a bonding wire 700, so that any one of the core pads in the second pad region transmits signals through any one of the pads in the second pad array.

[0088] Any one of the core pads in the second pad region is a high-speed signal pad for the second pad array to connect to a flexible circuit board. As Figure 2 shown, the interconnection of corresponding pads between two devices can be achieved through the flexible circuit board.

[0089] Any one of the pads in the second pad array is a solder ball.

[0090] Embodiment III

[0091] A pad array package structure includes: a first substrate 100, a second substrate 200, a device core 300, a package housing 400, a first pad array 500, and a second pad array 600;

[0092] The bottom 101 of the first substrate 100 is disposed on the inner surface 411 of the bottom of the package housing 400, the first pad array 500 is disposed on the outer surface 412 of the bottom of the package housing 400, and the device core 300 is disposed on the top 102 of the first substrate 100;

[0093] The top 202 of the second substrate 200 is disposed on the inner surface 421 of the top of the package housing 400, and the second pad array 600 is disposed on the outer surface 422 of the top of the package housing 400;

[0094] The device core 300 transmits signals through the first pad array 500 and the second pad array 600.

[0095] Conductive traces are provided inside the first substrate 100, conductive traces are provided inside the second substrate 200, the device core 300 has a plurality of core pads, the plurality of core pads have a first pad area and a second pad area, the first pad array 500 includes a plurality of pads 000, and the second pad array 600 includes a plurality of pads 000;

[0096] The conductive trace provided inside the first substrate 100 is electrically connected to any one of the pads 000 in the first pad array 500 and is electrically connected to any one of the core pads in the first pad area through a bonding wire 700, so that any one of the core pads in the first pad area transmits signals through any one of the pads in the first pad array;

[0097] The conductive trace provided inside the second substrate 200 is electrically connected to any one of the pads 000 in the second pad array 600 and is electrically connected to any one of the core pads in the second pad area through a bonding wire 700, so that any one of the core pads in the second pad area transmits signals through any one of the pads in the second pad array.

[0098] In some other embodiments, as Figure 3 shown, the pad array package structure further includes an edge connector 900;

[0099] Any one of the pads in the second pad array is a pin pad, the pin pad is electrically connected to the edge connector, and signals are transmitted through the gold fingers of the edge connector 900. The gold fingers of the edge connector 900 are connected by a high-speed cable to realize the interconnection of corresponding pads between two devices.

[0100] Embodiment 4

[0101] A manufacturing process for a pad array package structure includes:

[0102] S100: Prepare the first substrate and the second substrate, and perform substrate pretreatment on the first substrate and the second substrate;

[0103] Specifically, it includes: S110: Determine the substrate types of the first substrate and the second substrate;

[0104] S120: Clean the first substrate and the second substrate;

[0105] S130: Pattern the conductive traces inside the first substrate and the conductive traces inside the second substrate;

[0106] S140: Drill vias through the first substrate and the second substrate, and metallize the vias to connect the patterned conductive traces.

[0107] S200: Prepare a second pad array on the top outer surface of the pre-treated second substrate, prepare a first pad array on the bottom outer surface of the pre-treated first substrate, and bond the first substrate, the second substrate, and the device core;

[0108] Specifically, it includes: S2101: Sputter a seed layer on the surface of the second substrate;

[0109] S2102: Electroplate pads on the seed layer on the surface of the second substrate;

[0110] S2103: Print solder paste on the surface of the electroplated pads;

[0111] S2104: Place the pads on the surface of the electroplated pads after printing solder paste;

[0112] S2105: Perform low-temperature reflow soldering on the pads to cure the pads on the surface of the electroplated pads;

[0113] S2106: Perform automatic optical inspection on the pads;

[0114] S2107: In response to detecting a defect in the pads, use a laser with a preset wavelength to heat the defective pads and remove the defective pads;

[0115] S2108: Re-assemble the pads to replace the defective pads;

[0116] S2109: Prepare bumps on the core pads of the device core;

[0117] S2110: Thermocompression bond the bonding wires to the core pads;

[0118] S2111: Flip the second substrate and interconnect the device core with the first substrate;

[0119] S2112: Prepare a first pad array on the bottom outer surface of the first substrate.

[0120] S300: Encapsulate the bonded first substrate, second substrate, and device core.

[0121] Specifically, it includes: S310: filling the encapsulation material in the mold;

[0122] S320: placing the first substrate, the second substrate and the device core after bonding into the mold filled with the encapsulation material, and waiting for the encapsulation material to solidify;

[0123] S330: removing the encapsulation material remaining on the surfaces of the first pad array and the second pad array.

[0124] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0125] Particularly, according to the embodiments of the present application, the process described above with reference to the flowchart can be implemented as steps controlled by a computer software program. For example, the embodiments of the present application include a computer program product, which includes a computer program loaded on a computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through a communication device, or installed from a memory, or installed from a ROM. When the computer program is executed by an external processor, the above functions defined in the method of the embodiments of the present application are executed.

[0126] It should be noted that the computer-readable medium of the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the embodiments of the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the embodiments of the present application, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0127] The above computer-readable medium can be included in the above server; or it can exist separately without being assembled into the server. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by the server, the server is caused to: obtain the frame rate of an application on the terminal in response to detecting that the peripheral mode of the terminal is not activated; determine whether the user is obtaining the screen information of the terminal when the frame rate meets the screen-off condition; and control the screen to enter the immediate dimming mode in response to the determination result that the user is not obtaining the screen information of the terminal.

[0128] Computer program code for performing the operations of the embodiments of the present application may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., by connecting through the Internet using an Internet service provider).

[0129] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for a system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiment. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0130] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The descriptions of the above embodiments are only used to help understand the method and its core idea of this application. At the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

[0131] The above has introduced in detail a pad array package structure and its manufacturing process provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The above embodiments are only the preferred embodiments of the present application, which are used to help understand the method and its core idea of the present application, and are not intended to limit the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application also fall within the protection scope of the claims of the present application.

Claims

1. A pad array package structure, characterized in that, Comprising: A first substrate, a second substrate, a device core, a package housing, a first pad array, and a second pad array; The bottom of the first substrate is disposed on the inner surface of the bottom of the package housing, the first pad array is disposed on the outer surface of the bottom of the package housing, and the device core is disposed on the top of the first substrate; The top of the second substrate is disposed on the inner surface of the top of the package housing, and the second pad array is disposed on the outer surface of the top of the package housing; The device core transmits signals through the first pad array and the second pad array.

2. The pad array package structure according to claim 1, wherein The first substrate has conductive traces disposed therein, the second substrate has conductive traces disposed therein, the device core has a plurality of core pads, the plurality of core pads have a first pad region and a second pad region, the first pad array includes a plurality of pads, and the second pad array includes a plurality of pads; The conductive traces disposed in the first substrate are electrically connected to any one of the pads in the first pad array and are electrically connected to any one of the core pads in the first pad region through bonding wires, so that any one of the core pads in the first pad region transmits signals through any one of the pads in the first pad array; The conductive traces disposed in the second substrate are electrically connected to any one of the pads in the second pad array and are electrically connected to any one of the core pads in the second pad region through bonding wires, so that any one of the core pads in the second pad region transmits signals through any one of the pads in the second pad array.

3. The pad array package structure according to claim 1, characterized in that Any one of the core pads in the second pad region is a high-speed signal pad.

4. The pad array package structure according to claim 1, wherein, Any one of the pads in the first pad array is a solder ball.

5. The pad array package structure according to any one of claims 1-4, characterized in that, Any one of the pads in the second pad array is a solder ball; The second pad array is used to connect a flexible circuit board.

6. The pad array package structure according to any one of claims 1-4, characterized in that, The pad array package structure further includes an edge connector; Any one of the pads in the second pad array is a pin pad, and the pin pad is electrically connected to the edge connector, and signals are transmitted through the gold fingers of the edge connector.

7. A manufacturing process for a pad array package structure, characterized in that, Comprising: Preparing the first substrate and the second substrate, and performing substrate pretreatment on the first substrate and the second substrate; Preparing the second pad array on the outer surface of the top of the pretreated second substrate, preparing the first pad array on the outer surface of the bottom of the pretreated first substrate, and bonding the first substrate, the second substrate, and the device core; Encapsulating the bonded first substrate, second substrate, and device core.

8. The manufacturing process of the pad array package structure according to claim 7, characterized in that, The preparing the first substrate and the second substrate, and performing substrate pretreatment on the first substrate and the second substrate includes: Determining the substrate types of the first substrate and the second substrate; Cleaning the first substrate and the second substrate; Patternizing the conductive traces inside the first substrate and the conductive traces inside the second substrate; Drilling vias in the first substrate and the second substrate, and metallizing the vias to connect the patternized conductive traces.

9. The manufacturing process of the pad array package structure according to claim 7, characterized in that, Preparing a second pad array on the outer surface of the top of the second substrate after pretreatment, preparing a first pad array on the outer surface of the bottom of the first substrate after pretreatment, and bonding the first substrate, the second substrate, and the device core, including: Sputtering a seed layer on the surface of the second substrate; Electroplating pads on the seed layer on the surface of the second substrate; Printing solder paste on the surface of the electroplated pads; Placing pads on the surface of the electroplated pads after printing solder paste; Performing low-temperature reflow soldering on the pads so that the pads are cured on the surface of the electroplated pads; Performing automatic optical inspection on the pads; In response to detecting a defect in the pads, heating the pads with a defect using a laser with a preset wavelength to remove the pads with a defect; Reassembling pads to replace the pads with a defect; Preparing bumps on the core pads of the device core; Thermocompression bonding the bonding wires to the core pads; Flipping the second substrate to interconnect the device core with the first substrate; Preparing a first pad array on the outer surface of the bottom of the first substrate.

10. The manufacturing process of the pad array package structure according to claim 7, characterized in that, Plastic encapsulating the bonded first substrate, the second substrate, and the device core, including: Filling an encapsulation material in a mold; Placing the bonded first substrate, second substrate, and device core in the mold filled with the encapsulation material and waiting for the encapsulation material to cure; Removing the residual encapsulation material on the surfaces of the first pad array and the second pad array.

Images