A coordinated control method for inverter midpoint balancing and circulating current suppression

Abstract

The present application discloses a method for coordinated control of inverter midpoint balance and circulating current suppression, comprising the following control steps: collecting the three-phase current on the grid side and generating a three-phase bridge arm modulation signal through a grid-connected current control loop; collecting the lower half bus voltage and generating a first zero-sequence component through a midpoint balance control loop; collecting the three-phase current on the grid side and generating a second zero-sequence component through a circulating current suppression control loop; inputting the first zero-sequence component and the second zero-sequence component into a competition logic processing module, and generating a final zero-sequence component using a competition mechanism based on dynamic weight allocation; overmodulating the final zero-sequence component and superimposing it on the three-phase bridge arm modulation signal of the grid-connected current control loop, and then obtaining a control signal of a three-level inverter after PWM modulation. Beneficial effects of the present application: By dynamically coordinating the midpoint balance and circulating current suppression requirements, the present application can achieve efficient coordination between the two and reduce control complexity, and is suitable for low-cost industrial application scenarios.

Description

Technical Field

[0001] The present application relates to the field of inverter technology, and in particular to a method for coordinated control of inverter midpoint balancing and circulating current suppression. Background Art

[0002] In grid-connected inverter systems, three-level topology is widely used due to its advantages such as high efficiency and low harmonics, but the DC side midpoint potential fluctuation and the zero-sequence circulating current problems of the parallel system need to be urgently solved.

[0003] Existing technologies primarily address these issues with two solutions: SVPWM (space vector pulse width modulation) achieves midpoint balance by adjusting the action time of redundant small vectors, but this requires complex vector partitioning and real-time calculations, resulting in high control complexity. The other approach uses SPWM (sinusoidal pulse width modulation) with zero-sequence injection, indirectly controlling the midpoint potential by injecting zero-sequence voltage or indirectly suppressing circulating current by injecting zero-sequence circulating current. However, this approach only addresses a single objective (e.g., midpoint balance or circulating current suppression) and does not address the conflicting effects of coupling the two. Summary of the Invention

[0004] One of the objectives of the present application is to provide a method for coordinated control of inverter midpoint balancing and circulating current suppression that can solve at least one of the defects in the above-mentioned background technology.

[0005] To achieve at least one of the above-mentioned purposes, the technical solution adopted in this application is: a method for coordinated control of inverter midpoint balancing and circulating current suppression, which is applied to a scenario where multiple three-level inverters are connected in parallel, and the following control steps are performed on each three-level inverter: collecting the three-phase current on the grid side and generating a three-phase bridge arm modulation signal through the grid-connected current control loop; collecting the lower half bus voltage and generating a first zero-sequence component through the midpoint balancing control loop; collecting the three-phase current on the grid side and generating a second zero-sequence component through the circulating current suppression control loop; inputting the first zero-sequence component and the second zero-sequence component into a competition logic processing module, and generating a final zero-sequence component using a competition mechanism based on dynamic weight allocation; overmodulating the final zero-sequence component and superimposing it on the three-phase bridge arm modulation signal of the grid-connected current control loop, and then obtaining the control signal of the three-level inverter after PWM modulation.

[0006] Preferably, the midpoint balance control loop includes a comparator and a controller; the generation process of the first zero-sequence component is: multiplying the lower half bus voltage by two and comparing it with the bus voltage in the comparator to obtain the midpoint voltage fluctuation; inputting the midpoint voltage fluctuation into the controller to output the first zero-sequence component.

[0007] Preferably, the circulating current suppression control loop includes a comparator and a controller; the generation process of the second zero-sequence component is: summing the three-phase currents on the grid side and dividing them by three to obtain the zero-sequence circulating current; inputting the zero-sequence circulating current into the comparator and comparing it with zero; and inputting the comparison result into the controller to output the second zero-sequence component.

[0008] Preferably, the competition mode of the competition logic processing module includes an emergency mode, a forced mode and a normal competition mode; the competition logic processing module is suitable for selecting the competition mode according to the relationship between the midpoint voltage fluctuation and the zero-sequence circulating current and the corresponding set threshold value, thereby determining the distribution weight of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component; the final zero-sequence component d z The calculation formula is: z =αd z_1 +βd z_2 ; Among them, d z_1 and d z_2 Denote the first zero-sequence component and the second zero-sequence component respectively, and α and β denote the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively.

[0009] Preferably, the threshold value V corresponding to the midpoint voltage fluctuation is th The calculation formula is: V th =k1(V max -V bus / 2); where k1 represents the voltage safety factor, V max Indicates the maximum withstand voltage of the busbar capacitor, V bus Indicates the bus voltage.

[0010] Preferably, for the threshold value I corresponding to the zero-sequence circulating current th The calculation formula is:

[0011] ;

[0012] Among them, k2 represents the current safety factor, I max Indicates the maximum current allowed by the circuit, i line Indicates the maximum value of the three-phase current on the grid side, i z Indicates zero-sequence circulating current.

[0013] Preferably, when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|<V th and|i z |<I th When , the competition logic processing module is in normal competition mode; at this time, the calculation formulas for the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component are as follows:

[0014] α=(|ΔV| / V th ) / [(|ΔV| / V th )+(|i z | / I th )];β=(|i z | / I th ) / [(|ΔV| / V th )+(|i z | / I th )].

[0015] Preferably, the forced mode of the competition logic processing module includes a voltage forced mode and a circulating current forced mode; when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|≥V th and|i z |<I th When the competition logic processing module is in voltage forced mode, the relationship between weights α and β is: α≥2β, α+β=1; the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|<V th and|i z |≥I th When , the competition logic processing module is in the circulation forced mode; at this time, the relationship between the weights α and β is: β≥2α, α+β=1.

[0016] Preferably, when the midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|≥V th and|i z |≥I th When , the competition logic processing module is in emergency mode; at this time, the following hierarchical control strategy is adopted: the first priority is to reduce the midpoint voltage fluctuation by setting α≥2β; the second priority is to reduce the final zero sequence component d in a single switching cycle. z Insert circulating current suppression pulse compensation Δd z , and then the final zero sequence component d after compensation z ´=d z +Δd z ; Circulating current suppression pulse compensation Δd z The calculation formula is as follows:

[0017] ;

[0018] Among them, K p represents the compensation coefficient, L represents the inductance value, T sw Indicates the switching cycle.

[0019] Preferably, the overmodulation process for the final zero-sequence component includes the following process: according to the current modulation wave d x * Determine the final zero-sequence component d z The limit value, including the upper amplitude d zmax and the lower amplitude d zmin ; Upper amplitude d zmax and the lower amplitude d zmin The calculation formula is:

[0020] d zmax =1-max{d a * , d b * , d c *}, d zmin =-1-min{d a * , d b * , d c *};

[0021] When the final zero-sequence component is close to the upper amplitude, the weights α and β are corrected. The calculation formula of the corrected weights α´ and β´ is: α´=α×(d zmax -d z ) / d zmax ,β´=β×(d zmax -d z ) / d zmax ;

[0022] When the final zero-sequence component is close to the lower amplitude, the weights α and β are corrected. The calculation formula of the corrected weights α" and β" is: α"=α×(d z -d zmin ) / d zmin , β"=β×(d z -d zmin ) / d zmin ;

[0023] Among them, d a * d b * and d c * Represents a three-phase modulated wave.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] This application dynamically coordinates the midpoint balance and circulating current suppression requirements, adopts a simple controller and SPWM modulation, can achieve efficient coordination between the two and reduce control complexity, and is suitable for low-cost industrial application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the modular parallel structure of two three-level inverters.

[0027] Figure 2 Schematic diagram of the overlapping of carrier and modulation waves of a three-level inverter.

[0028] Figure 3 Schematic diagram of the equivalent circuit of the zero-sequence circulating current of the three-level inverter in parallel.

[0029] Figure 4 This is a schematic diagram of the workflow of this application.

[0030] Figure 5 This is a schematic diagram of the specific control loop architecture of this application.

[0031] Figure 6 This is a logic diagram of switching between different competition modes in this application. DETAILED DESCRIPTION

[0032] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that, in the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0033] In the description of this application, it should be noted that for directional words, such as the terms "center", "horizontal", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and so on, indicating the orientation and position relationship are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific scope of protection of this application.

[0034] It should be noted that the terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0035] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0036] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0037] The terms "comprises" and "having" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0038] In order to facilitate the understanding of the technical solution of the present application, the conflict mechanism between the neutral point balance control and the zero-sequence circulating current suppression of the inverter will be analyzed below.

[0039] like Figure 1 The figure shows a modular parallel architecture for two three-level inverters. By using a common AC / DC bus between the two three-level inverters, this architecture can be expanded to include three or more three-level inverters in parallel. The two three-level inverters are labeled three-level inverter #1 and three-level inverter #2. The following uses three-level inverter #1 as an example to illustrate the causes of midpoint fluctuation and the role of zero-sequence voltage in regulating midpoint balance.

[0040] For the three-level inverter #1, since the current i flowing through the DC side midpoint O np The charge and discharge imbalance will cause the midpoint voltage to fluctuate; the current i np Equal to two capacitances C p and C n The busbar capacitance corresponds to the current i cp and i cn The sum of i np =i cp +i cn .

[0041] Current i cp and i cn The calculation formulas are:

[0042] i cp =C p ×dV p / dt,icn=-C n ×dV n / dt.

[0043] Among them, V p and V n Represents two capacitance values ​​C p and C n The voltage value corresponding to the bus capacitance.

[0044] Assumption C p =C n =C, then i np =i cp +i cn =C×d(V p -V n ) / dt=C×dΔV / dt; From this we can get the midpoint voltage fluctuation ΔV affected by the midpoint current i np The influence relationship is: dΔV / dt= i np / C.

[0045] The switching state of the three-phase bridge arm of the three-level inverter is represented by S x To express, only when any bridge arm S xWhen (t)=0, that is, the bridge arm is connected to the midpoint of the busbar, the current will flow through the midpoint, so the midpoint current i np It can also be expressed as follows:

[0046] .

[0047] Among them, a, b and c represent the three-phase bridge arms, i x Indicates the current corresponding to the bridge arm; S x =1 means the bridge arm is connected to the positive bus, which can be represented by P state; S x =0 means the bridge arm is connected to the midpoint, which can be represented by the O state; S x =-1 indicates that the bridge arm is connected to the negative bus, which can be represented by the N state.

[0048] Due to the zero-sequence circulating current of the three-phase system , then the midpoint current i np The formula can be simplified to:

[0049] .

[0050] When performing SPWM modulation, the three-phase duty cycle d x is the switch state S x The average equivalent; therefore, the midpoint current i np The expression can be equivalent to the following:

[0051] .

[0052] In SPWM modulation, the zero-sequence voltage u is often injected z To the three-phase modulation wave, by changing the modulation wave to change the switching state duty cycle of each phase bridge arm, the adjusted modulation wave u x The expression is: x =u x * +u z ; Among them, u x * Represents the original three-phase modulated wave.

[0053] Zero sequence voltage u z The injection of will change the duty cycle d of each phase bridge arm x , then the duty cycle d x It can be expressed by the following formula: x = u x / V bus =(u x * +u z ) / V bus ; Among them, V bus Indicates the bus voltage.

[0054] The duty cycle d x Substitute the expression of midpoint current i into np The formula can be obtained:

[0055] .

[0056] Substituting the above formula into the formula for midpoint voltage fluctuation ΔV, we can obtain:

[0057] .

[0058] Assuming that the circulating current remains unchanged, the following process of generating the modulation signal from SPWM modulation details the impact of the zero-sequence component on the midpoint position.

[0059] like Figure 2 As shown in Figure 2, for three-level inverters, carrier wave stacking and modulation wave overlap are often used to generate modulation signals. a 、u b 、u c The modulation wave is a three-phase modulation wave. The modulation wave is in the P state above carrier 1, the O state below carrier 1, the O state above carrier 2, and the N state below carrier 2. In the POO state, the current flows toward the bus midpoint, while the current in the ONN state flows out of the bus midpoint. When no control is applied, the POO and ONN states last the same amount of time within a switching cycle, so their effects on the midpoint potential are offset.

[0060] By superimposing a zero-sequence component on the modulation wave, the duration of the POO and ONN states can be adjusted, thereby changing the midpoint potential and voltage. Specifically, when a positive zero-sequence component is superimposed, the modulation wave shifts upward, the duration of the POO state increases, the duration of the ONN state decreases, the current flowing into the bus midpoint increases, and the midpoint potential rises. When a negative zero-sequence component is superimposed, the modulation wave shifts downward, the duration of the POO state decreases, the duration of the ONN state increases, the current flowing out of the bus midpoint increases, and the midpoint potential decreases.

[0061] The causes of zero-sequence circulating current are explained below; Figure 1 As shown in Figure 1, in a parallel inverter system, the zero-sequence circulating current is mainly caused by the zero-sequence voltage difference of each module. The zero-sequence circulating currents of three-level inverter #1 and three-level inverter #2 are i z1 =(i a1 +i b1 +i c1 ) / 3、i z2 =(i a2 +i b2 +i c2 ) / 3. Because two units are connected in parallel, there is i z1 =-i z2 , and their zero sequence voltages are uz1 and u z2 , then the zero-sequence voltage difference Δu z =u z1 -u z2 .

[0062] like Figure 3 As shown in the figure, it is a schematic diagram of the equivalent circuit of the zero-sequence circulating current. According to Kirchhoff's voltage law, the relationship between the zero-sequence voltage difference and the zero-sequence circulating current can be obtained as follows: Δu z =2L×di z / dt+2R×i z ; Where L and R are the inductance and resistance values ​​in the equivalent circuit respectively.

[0063] The conflict between midpoint balance and zero-sequence circulating current suppression is analyzed below.

[0064] like Figure 1 As shown in the modular parallel architecture of three-level inverters, assuming that the three-phase original modulation waves of three-level inverter #1 and three-level inverter #2 are the same, but the load currents are different, then:

[0065] Three-level inverter #1: u x1 * =Usin(ωt-θ x ), .

[0066] Three-level inverter #2: u x2 * =Usin(ωt-θ x ), .

[0067] Where ω represents the angular frequency, t represents the time variable, and θ x represents the initial phase of the modulated wave, and They represent the power factor angles of three-level inverters #1 and #2 respectively, k represents the coefficient, and k≠1.

[0068] Based on the aforementioned calculation formula for the midpoint voltage fluctuation ΔV, in order to achieve midpoint balance, it should be:

[0069] Three-level inverter #1: (1).

[0070] Three-level inverter #2: (2).

[0071] Among them, u z1 and u z2 They represent the zero-sequence voltages corresponding to the three-level inverter #1 and #2 respectively; if we want to achieve circulating current balance, we need u z1 =uz2 Obviously, when k≠1 or When the above formula (1) and formula (2) and u z1 =u z2 Therefore, it is impossible to achieve both midpoint balance and zero-sequence circulating current suppression at the same time.

[0072] In view of the contradiction between the above-mentioned midpoint balance and circulating current suppression control, this application proposes a method for coordinated control of inverter midpoint balance and circulating current suppression, which can be applied to the scenario of multiple three-level inverters in parallel. One of the preferred embodiments is as follows: Figure 4 and Figure 5 As shown, each three-level inverter undergoes the following control steps: The three-phase current on the grid side is collected and used to generate a three-phase bridge arm modulation signal through the grid-connected current control loop; the lower half bus voltage is collected and used to generate a first zero-sequence component through the midpoint balance control loop; and the three-phase current on the grid side is collected and used to generate a second zero-sequence component through the circulating current suppression control loop. The first and second zero-sequence components are input into the competition logic processing module, where a competition mechanism based on dynamic weight allocation is used to generate the final zero-sequence component. The final zero-sequence component is overmodulated and superimposed on the three-phase bridge arm modulation signal of the grid-connected current control loop. This final zero-sequence component then undergoes PWM modulation to generate the control signal for the three-level inverter.

[0073] It is understandable that the technical solution of this application can generate dual zero-sequence components based on the midpoint voltage fluctuation and zero-sequence circulating current. Then, a competition mechanism based on dynamic weight allocation is adopted to adaptively process the dual zero-sequence components according to the actual operating conditions of the midpoint voltage fluctuation and zero-sequence circulating current, thereby obtaining the zero-sequence injection amount injected into the three-phase modulated wave, thereby achieving coordinated control of midpoint balance and circulating current suppression. Compared with traditional methods, this application can dynamically coordinate the requirements of midpoint balance and circulating current suppression, thereby achieving efficient coordination between the two and reducing control complexity, making it suitable for low-cost industrial application scenarios.

[0074] In this embodiment, the specific working process of the grid-connected current control loop is a well-known technology for those skilled in the art. For ease of understanding, the following is an example. Figure 1 Taking the three-level inverter #2 in the inverter parallel architecture shown in FIG. 1 as an example, the working process of the grid-connected current control loop is briefly described. Figure 5 As shown, the sampled three-phase current i a2 、i b2 and i c2 After abc→dq transformation, the d-axis current i is obtained d2 and q-axis current i q2 ; The d-axis current i d2 and q-axis current i q2 Respectively with the d-axis current reference i d2 * and q-axis current reference iq2 * Comparison, the error is superimposed on the grid feedforward e after the controller d With e q , and then through dq0→abc transformation to obtain the three-phase bridge arm modulation signal d a2 d b2 and d c2 The three-phase bridge arm modulation signal can be combined with the final zero sequence component d z2 The signals are superimposed and then modulated by PWM to output the switching control signals of the three-phase bridge arms.

[0075] In this embodiment, Figure 5 As shown, the midpoint balance control loop mainly includes a comparator and a controller. Based on the architecture of the midpoint balance control loop, the first zero-sequence component d z_1 The generation process is: sampling the lower half bus voltage V n , the lower half bus voltage V n Multiply by two and add to the bus voltage V bus The comparison is done in the comparator to obtain the midpoint voltage fluctuation ΔV. The midpoint voltage fluctuation ΔV is then input into the controller to output the first zero sequence component d z_1 .

[0076] At the same time, the circulating current suppression control loop also mainly includes a comparator and a controller; based on the architecture of the circulating current suppression control loop, the second zero-sequence component d z_2 The generation process is: the three-phase current i on the grid side a 、i b and i c After summing and dividing by three, we get the zero-sequence circulating current i z ; The zero sequence circulating current i z The input comparator compares with zero; the comparison result is input into the controller and the second zero sequence component d is output. z_2 .

[0077] It is understandable that there are many types of controllers used in the control loop, such as PI control and PR controller. In this embodiment, the PI controller is preferably used. Then, in the controllers of the midpoint balance control loop and the circulating current suppression control loop, the first zero-sequence component d is generated according to the midpoint voltage fluctuation ΔV. z_1 , and according to the zero-sequence circulating current i z Generate the second zero sequence component d z_2 The specific formula is:

[0078] .

[0079] .

[0080] Among them, K p1 and Kp2 Both represent the proportional coefficient, K i1 and K i2 Both represent integral coefficients.

[0081] It should be known that if Figure 5 The working process of the control loop shown corresponds to the three-level inverter #2, then the three-phase current i on the grid side is a 、i b and i c Corresponding to i a2 、i b2 and i c2 , the first zero-sequence component d z_1 and d z_2 Corresponding to d z2_1 and d z2_2 , the midpoint voltage fluctuation ΔV corresponds to ΔV2, and the zero-sequence circulating current i z Corresponding to i z2 , lower half bus voltage V n Corresponding to V n2 , the final zero sequence component d z Corresponding to d z2 .

[0082] In this embodiment, when designing the competition mechanism of the competition logic processing module, the final zero-sequence component d is dynamically allocated according to the working conditions. z The calculation formula is: z =αd z_1 +βd z_2 Among them, d z_1 and d z_2 Represent the first zero-sequence component and the second zero-sequence component respectively, α and β represent the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively. z After the calculation formula is obtained, the values ​​of weights α and β can be assigned according to the actual working conditions, and then the final zero-sequence component d z The specific value of .

[0083] Specifically, based on the actual operating conditions of the inverter, the competition mode of the competition logic processing module may include an emergency mode, a forced mode, and a normal competition mode. Different competition modes correspond to different weight distribution methods. The competition logic processing module can select the competition mode based on the relationship between the midpoint voltage fluctuation and the zero-sequence circulating current and the corresponding set thresholds, and then determine the distribution weights of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component. For ease of understanding, the threshold setting process and the weight distribution process under different competition modes will be described in detail below.

[0084] 1. Setting the threshold.

[0085] For the midpoint voltage fluctuation ΔV, the threshold V th , mainly considering the voltage resistance of the busbar capacitor, so the threshold V can be calculated according to the following formula th settings.

[0086] V th =k1(V max -V bus / 2).

[0087] Among them, k1 represents the voltage safety factor, which can be selected according to the user's application requirements and is between 0.7 and 0.8; V max Indicates the maximum withstand voltage of the bus capacitor.

[0088] For the zero-sequence circulating current i z The corresponding threshold I th , mainly consider the current capability of the device, that is, the maximum current I allowed by the circuit max , so the threshold I can be calculated according to the following formula th settings.

[0089] .

[0090] Among them, k2 represents the current safety factor, which can be selected according to the user's application requirements and is set to 0.5; i line Indicates the maximum value of the three-phase current on the grid side, i line =max{i a ,i b ,i c}.

[0091] 2. Weight allocation strategies under different competition modes.

[0092] (1) When the neutral point voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|<V th and|i z |<I th When , the competition logic processing module is in normal competition mode. At this time, the weights α and β are dynamically allocated according to the size of the deviation. To avoid the impact of the dimension on the allocation, the per-unit value is used for allocation. The calculation formulas for the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component are as follows:

[0093] α=(|ΔV| / V th ) / [(|ΔV| / V th )+(|i z | / I th )].

[0094] β=(|i z | / I th ) / [(|ΔV| / V th )+(|i z | / I th )].

[0095] (2) The forced modes of the competition logic processing module include voltage forced mode and circulating current forced mode.

[0096] The midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|≥V th and|i z |<I th When , the competition logic processing module is in voltage-forcing mode. At this time, the relationship between the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component, respectively, is: α ≥ 2β, α + β = 1. By increasing the weight α and decreasing the weight β, the midpoint voltage fluctuation can be forced to be reduced. The specific values ​​of the weights α and β can be selected according to the actual needs of those skilled in the art. For example, α = 0.9 and β = 0.1 can be used.

[0097] The midpoint voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|<V th and|i z |≥I th When , the competition logic processing module is in circulating current forced mode. At this time, the relationship between the weights α and β corresponding to the first zero-sequence component and the second zero-sequence component, respectively, is: β ≥ 2α, α + β = 1. By increasing the value of weight β and decreasing the value of weight α, the circulating current can be forced to decrease. The specific values ​​of weights α and β can be selected according to the actual needs of those skilled in the art. For example, α = 0.1 and β = 0.9 can be used.

[0098] (3) When the neutral point voltage fluctuation ΔV and the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: |ΔV|≥V th and|i z |≥I th When , the competition logic processing module is in emergency mode; at this time, the following hierarchical control strategy is adopted.

[0099] The first priority is midpoint voltage control: by setting α≥2β, the midpoint voltage fluctuation is preferentially reduced to prevent overvoltage damage to the bus capacitor.

[0100] The second priority is circulating current suppression: by sw The final zero sequence component d z Insert circulating current suppression pulse compensation Δd z , reducing the impact of midpoint balance on circulating current. In this process, the circulating current suppression pulse compensation amount Δd z The calculation formula is as follows:

[0101] .

[0102] Among them, K p Indicates the compensation coefficient, which can be given according to the actual debugging situation; L indicates Figure 3 Inductance values ​​in the equivalent circuit shown.

[0103] It can be understood that after completing the circulating current suppression pulse compensation Δd z After the insertion of the compensation, the final zero sequence component d z ´=d z +Δd z In emergency mode, when the neutral voltage recovers to |ΔV|<V th When the zero-sequence circulating current is suppressed, the circulating current can be switched to the forced circulating current mode until |i z |<I th .

[0104] For ease of understanding, the switching process of different contention modes will be described in detail below. A hysteresis method may be preferably used for mode switching, and the emergency mode is used as an initial state for example.

[0105] like Figure 6 As shown, the initial state is emergency mode. If the midpoint voltage fluctuation |ΔV|<V th -V exit , the emergency mode switches to the circulation forced mode; where V exit Indicates the voltage hysteresis, which can avoid jitter in mode switching. In the circulating current forced mode, if the midpoint voltage fluctuation |ΔV|≥V th , the circulating current forced mode is immediately switched back to the emergency mode; if the zero-sequence circulating current|i z |<I th -I exit , the circulation forced mode switches to the normal competition mode; where I exit Indicates the current hysteresis, which can avoid mode switching jitter. In normal competition mode, if the zero-sequence circulating current |i z |≥I th , the normal competition mode is immediately switched to the circulating current forced mode; if the midpoint voltage fluctuation |ΔV|≥V th, the normal competition mode is immediately switched to the voltage forced mode. In the voltage forced mode, if the midpoint voltage fluctuation |ΔV|<V th -V exit , then the voltage forced mode is switched to the normal competition mode; if the zero sequence circulating current |i z |≥I th , the voltage forced mode is immediately switched to the emergency mode.

[0106] It should be noted that since the switching control signals of the three-phase bridge arms are superimposed with zero-sequence components, overmodulation may occur, which in turn leads to modulation failure. Therefore, the final zero-sequence component needs to be overmodulated before injection; the overmodulation processing of the final zero-sequence component includes the following process:

[0107] According to the current modulation wave d x * Determine the final zero-sequence component d z The limit value, including the upper amplitude d zmax and the lower amplitude d zmin ; Upper amplitude d zmax and the lower amplitude d zmin The calculation formula is: zmax =1-max{d a * , d b * , d c *}, d zmin =-1-min{d a * , d b * , d c *}; where d a * d b * and d c * Represents a three-phase modulated wave.

[0108] When the final zero-sequence component is close to the upper amplitude d zmax , that is, the final zero sequence component and the upper amplitude d zmax When the deviation is less than the specified allowable deviation, the weights α and β are corrected. The calculation formula of the corrected weights α' and β' is: α'=α×(d zmax -d z ) / d zmax ,β´=β×(d zmax -d z ) / d zmax .

[0109] When the final zero-sequence component is close to the lower amplitude d zmin , that is, the final zero sequence component and the lower amplitude d zmin When the deviation is less than the specified allowable deviation, the weights α and β are corrected. The calculation formula of the corrected weights α" and β" is: α"=α×(d z -d zmin ) / d zmin , β"=β×(d z -d zmin ) / d zmin .

[0110] It should be noted that if the competition logic processing module is in emergency mode before the overmodulation process is performed, the final zero-sequence component d in the correction formula for the weights α and β z Inserting circulating current to suppress pulse compensation Δd z The compensation value d z ´.

[0111] The above describes the basic principles, main features, and advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above embodiments. The above embodiments and description merely illustrate the principles of the present application. Various changes and improvements may be made to the present application without departing from the spirit and scope of the present application. These changes and improvements are intended to fall within the scope of the present application. The scope of protection claimed by the present application is defined by the appended claims and their equivalents.

Claims

1. A method for coordinated control of inverter midpoint balancing and circulating current suppression, applied to a scenario where multiple three-level inverters are connected in parallel; characterized in that: The following control steps are performed on each three-level inverter: Collect the three-phase current on the grid side and generate the three-phase bridge arm modulation signal through the grid current control loop; The lower half bus voltage is collected and the first zero sequence component is generated through the midpoint balance control loop; Collect the three-phase current on the grid side and generate the second zero-sequence component through the circulating current suppression control loop; Inputting the first zero-sequence component and the second zero-sequence component into a competition logic processing module, and generating a final zero-sequence component by using a competition mechanism based on dynamic weight allocation; The final zero-sequence component is overmodulated and superimposed on the three-phase bridge arm modulation signal of the grid-connected current control loop, and then the control signal of the three-level inverter is obtained after PWM modulation; The competition modes of the competition logic processing module include emergency mode, forced mode and normal competition mode; The competition logic processing module is adapted to select a competition mode according to the relationship between the midpoint voltage fluctuation and the zero-sequence circulating current and the corresponding set thresholds, thereby determining the allocation weights of the first zero-sequence component and the second zero-sequence component in the final zero-sequence component; Final zero sequence component d z The calculation formula is: z =αd z_1 +βd z_2 ; Among them, d z_1 and d z_2 denote the first zero-sequence component and the second zero-sequence component respectively, and α and β denote the weights corresponding to the first zero-sequence component and the second zero-sequence component respectively; When the midpoint voltage fluctuates And the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: ≥V th and|i z |≥I th When , the competition logic processing module is in emergency mode; When the midpoint voltage fluctuates And the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: <V th and|i z |<I th When , the competition logic processing module is in normal competition mode.

2. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: The midpoint balance control loop includes a comparator and a controller; the generation process of the first zero-sequence component is: The lower half bus voltage is multiplied by two and then compared with the bus voltage in a comparator to obtain a midpoint voltage fluctuation; the midpoint voltage fluctuation is input into a controller to output a first zero-sequence component.

3. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 2, characterized in that: The circulating current suppression control loop includes a comparator and a controller; the generation process of the second zero-sequence component is: The three-phase currents on the grid side are summed and divided by three to obtain a zero-sequence circulating current; the zero-sequence circulating current is input into a comparator and compared with zero; the comparison result is input into a controller to output a second zero-sequence component.

4. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: For the threshold value V corresponding to the midpoint voltage fluctuation th The calculation formula is: V th =k1(V max -V bus / 2); Among them, k1 represents the voltage safety factor, V max Indicates the maximum withstand voltage of the bus capacitor, V bus Indicates the bus voltage.

5. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: For the threshold value I corresponding to the zero-sequence circulating current th The calculation formula is: ； Among them, k2 represents the current safety factor, I max Indicates the maximum current allowed by the circuit, i line Indicates the maximum value of the three-phase current on the grid side, i z Indicates zero-sequence circulating current.

6. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: When the competition logic processing module is in normal competition mode, the calculation formulas of weights α and β are as follows: ； 。 7. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: The forcing modes of the competition logic processing module include voltage forcing mode and circulating current forcing mode; When the midpoint voltage fluctuates And the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: ≥V th and|i z |<I th When , the competition logic processing module is in voltage-forcing mode; at this time, the relationship between weights α and β is: α≥2β, α+β=1; When the midpoint voltage fluctuates And the zero-sequence circulating current i z Set the corresponding threshold V th and I th The relationship is: <V th and|i z |≥I th When , the competition logic processing module is in the circulation forced mode; at this time, the relationship between the weights α and β is: β≥2α, α+β=1.

8. The inverter midpoint balancing and circulating current suppression coordinated control method according to claim 1, characterized in that: When the competition logic processing module is in emergency mode, the following hierarchical control strategy is adopted: The first priority is to reduce the midpoint voltage fluctuation by setting α≥2β; The second priority is to reduce the final zero sequence component d in a single switching cycle. z Insert circulating current suppression pulse compensation , and then the final zero sequence component d after compensation z ´=d z + ; Circulating current suppression pulse compensation The calculation formula is as follows: ； Among them, K p represents the compensation coefficient, L represents the inductance value, V bus Indicates bus voltage, i z Indicates zero-sequence circulating current, I th Represents the zero-sequence circulating current i z The corresponding threshold, T sw Indicates the switching cycle.

9. The inverter midpoint balancing and circulating current suppression coordinated control method according to any one of claims 1 to 8, characterized in that: The overmodulation processing of the final zero-sequence component includes the following steps: According to the current modulation wave d x * Determine the final zero-sequence component d z The limit value, including the upper amplitude d zmax and the lower amplitude d zmin ; Upper amplitude d zmax and the lower amplitude d zmin The calculation formula is: d zmax =1-max{d a * ,d b * ,d c * },d zmin =-1-min{d a * ,d b * ,d c * }; When the final zero-sequence component is close to the upper amplitude, the weights α and β are corrected. The calculation formula of the corrected weights α´ and β´ is: α´=α×(d zmax -d z ) / d zmax ,β´=β×(d zmax -d z ) / d zmax ; When the final zero-sequence component is close to the lower amplitude, the weights α and β are corrected. The calculation formula of the corrected weights α" and β" is: α"=α×(d z -d zmin ) / d zmin , β"=β×(d z -d zmin ) / d zmin ; Among them, d a * d b * and d c * Represents a three-phase modulated wave.

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