Multi-phase switching converter communicating faults through power stages

Abstract

The present disclosure discloses a power stage of a multiphase switching converter that reliably detects a fault and includes a high side switch and a low side switch in series between a first power supply terminal and a ground terminal. The gate driver generates a drive signal to the two switches based on a control signal received from the phase controller. The fault logic block is powered by the second power supply terminal, and generates a binary bias signal indicating whether a corresponding fault exists by checking a state inside the power stage. When a control signal is switched between logic levels, ringing may occur at the ground terminal and the power supply terminal. The fault logic block generates a fault signal by sensing the deviation signal according to a delayed version of the control signal. Wherein the time amplitude of the delay is greater than the stable time of the ringing. By such delaying the sensing of the deviation signal, any interference of ringing can be avoided.

Description

[0001] Priority Claims

[0002] This patent application claims priority to the co-pending Indian provisional patent application titled "Noise Gating", application number 202441054695, filed on July 17, 2024, with attorney docket number AURA-359-INPR; and claims priority to the U.S. patent application titled "Communicating Faults by a Power Stage of a Multi-Phase Switching Converter", application number 18 / 957,945, filed on November 25, 2024; the entire contents of the above two priorities are incorporated herein to the extent not inconsistent with this specification. Technical Field

[0003] Embodiments of the present disclosure relate to multi-phase switching converters, and more particularly to a multi-phase switching converter that communicates faults through a power stage. Background Art

[0004] A switching converter is an element that generates a stable direct current (DC) voltage from an input power supply by using one or more switches, which is well-known in the relevant technical field. Switching converters are typically applied to components of regulated power supplies, and these regulated power supplies are widely used in devices such as computers and mobile phones, which is also well-known in the relevant technical field.

[0005] A switching converter typically includes a pair of power switches that drive an inductor. Each power switch is typically implemented by a transistor (e.g., a MOSFET). These switches are connected in series between the input supply voltage and a reference terminal (e.g., a ground terminal). The switch closer to the input voltage (the input power supply of the converter) is called the high-side switch, and the other switch is called the low-side switch. These switches are operated by a control circuit that switches the switches to the on state in consecutive and non-overlapping time periods, causing the currently conducting switch to drive the inductor during the corresponding time period.

[0006] A multi-phase switching converter includes multiple pairs of such switches and the associated circuitry for each pair of switches. Each set of switch pairs typically operates at a corresponding phase in a series of phases. These switch pairs operate together to generate the desired regulated voltage (power rail), which is a design that can support higher load currents with higher efficiency and provide other advantages, which is well-known in the relevant technical field. Each such set of switch pairs and its associated circuitry are referred to as the power stage of the power rail provided by the multi-phase switching converter. A phase controller is used to control the specific time at which each power stage of the power rail generates the desired output voltage.

[0007] The power stage can generate signals for indicating internal component or circuit failures of the power stage and transmit the signals of these failures to the phase controller. A failure refers to a situation where the value of an operating parameter (such as current, temperature, voltage, etc.) exceeds a specified range. Failures can be caused by various reasons, such as component aging, component defects, connection failures (such as open circuits or short circuits), etc. Some examples of failures include the current passing through the inductor exceeding the corresponding allowable range, the temperature of the power stage exceeding the corresponding allowable range, the voltage on the input power supply terminal exceeding the specified range, etc.

[0008] Failures may cause the corresponding power stage to operate abnormally and may damage other components of the multiphase switching converter or the equipment using the converter. To manage these failures, corrective actions (such as temporarily shutting down the power stage) can be taken to manage the failures. Therefore, it is very important to be able to reliably detect failures and take appropriate actions when a failure occurs.

[0009] This disclosure indicates communicating failures through the power stage of a multiphase switching converter. Summary of the Invention

[0010] 1. Overview

[0011] This disclosure reliably detects failures through the power stage of a multiphase switching converter. The power stage includes a high-side switch and a low-side switch connected in series at a switching node, and the high-side switch and the low-side switch are connected in series between a first power supply terminal having a first power supply and a ground terminal providing a constant reference potential. An inductor is connected between the switching node and the output node, and the power stage provides a regulated voltage at the output node. A second power supply terminal provided with a second power supply supplies power to components inside the power stage.

[0012] The gate driver generates corresponding drive signals for the two switches based on control signals received from the phase controller. Among them, when the control signal is at a first logic level and a second logic level, the first drive signal and the second drive signal are respectively triggered. The inventor observed that when the control signal switches between the first logic level and the second logic level, ringing may occur at the ground terminal. Ringing may also occur at the power supply terminal.

[0013] The fault logic block generates a deviation signal for indicating a corresponding deviation by checking the internal state of the power stage. Each deviation signal is a binary logic signal indicating whether there is a corresponding failure. The fault logic block generates a fault signal by sensing the deviation signal based on a delayed version of the control signal. The delayed version of the control signal is generated by delaying the control signal by a first delay time, and the first delay time is greater than the settling time of the ringing. By delaying the sensing of the deviation signal, any interference caused by the ringing can be avoided.

[0014] The control signal periodically switches between a first and a second logic level during a first duration and does not switch during a second duration. In an embodiment, the fault logic block includes a plurality of fault sampling blocks, each of which receives a corresponding deviation signal and generates a corresponding fault signal. Each fault sampling block includes a flip-flop. The flip-flop receives the corresponding deviation signal on a data input and a delayed version on a clock input during the first period, and receives the corresponding deviation signal on a set input during the second duration. The Q output of the flip-flop is the fault signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A block diagram of an example system that can implement several aspects of the present disclosure.

[0016] Figure 2 A detailed block diagram of a Voltage Regulator Module (VRM) according to an embodiment of the present disclosure.

[0017] Figure 3A A flowchart of a power stage transmitting a fault signal to a phase controller according to an embodiment of the present disclosure.

[0018] Figure 3B A block diagram of implementation details of a Smart Power Stage (SPS) according to an embodiment of the present disclosure.

[0019] Figure 4A A schematic diagram of implementation details of a fault logic block according to an embodiment of the present disclosure.

[0020] Figure 4B A schematic diagram of implementation details of a PWM state detector according to an embodiment of the present disclosure.

[0021] Figure 4C A block diagram of implementation details of a fault communication block according to an embodiment of the present disclosure.

[0022] Figure 5A A timing diagram of various signal waveforms inside a power stage in a first scenario according to an embodiment of the present disclosure.

[0023] Figure 5B A timing diagram of various signal waveforms inside a power stage in a second scenario according to an embodiment of the present disclosure.

[0024] In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit in the corresponding reference numeral. DETAILED DESCRIPTION

[0025] The present disclosure will be described by the following reference examples. However, those skilled in the art of the present disclosure will recognize that the present disclosure can be practiced without one or more specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown in detail to avoid obscuring the features of the present disclosure. In addition, the described features / aspects are practiced in various combinations, but for the sake of brevity, only some of these combinations are described herein.

[0026] 2. Example System

[0027] Figure 1 FIG. is a block diagram of an example system for implementing several aspects of the present disclosure. System 100 includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and peripherals 150. In one embodiment, system 100 corresponds to a computer (desktop computer, laptop computer, etc.), and in other embodiments, system 100 may represent other types of systems. It is understood that the structure of system 100 may include more or fewer blocks than Figure 1 shown.

[0028] CPU 120 is typically represented as a processor or a system-on-chip (SoC), and receives a pair of supply voltages (Va and Vb) from power supply 110 through corresponding paths 112A and 112B. In the example, supply voltage Va is lower than supply voltage Vb and is used to power the core part of the CPU. CPU 120 includes an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Supply voltage Vb is used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, chip peripherals, etc. CPU 120 provides various signals (all signals are included in path 121) to power supply 110, including its power demand for power supply 110. Examples of such signals may be signals specifying specific operating modes (in terms of power consumption), such as signals PS1, PS2, PS3, etc., and these operating modes are related to "improving the efficiency of power-saving states".

[0029] Memory 130 also includes volatile and non-volatile memories. As in a personal computer, the memory may include magnetic memory (such as a hard disk) and solid-state memory (such as RAM, flash memory, etc.). Memory 130 receives a supply voltage through path 113 to power various internal circuits and blocks.

[0030] The network interface 140 is used to provide two-way communication between the system 100 and a computer network or the Internet. The network interface 140 implements the electronic circuits required to communicate using specific physical layer and data link layer standards, such as Ethernet or Wi-FiTM. The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN) and large-scale network communication through routable protocols, such as the Internet Protocol (IP). The network interface 140 receives power through path 114 to power its internal circuits and blocks. The network interface 140 receives signals from or transmits signals to the external system and the CPU 120 through paths 141 and 124 respectively. Then, the network interface 140 communicates with the external system through path 141 and communicates with the CPU 120 through path 124.

[0031] The peripheral device 150 represents one or more peripheral circuits, such as speakers, microphones, user interface devices, etc. The peripheral device 150 receives power through path 115 and communicates with external devices through path 151.

[0032] The power supply 110 receives power from one or more power sources (such as batteries) through path 101 and operates to provide the required supply voltages on paths 112A, 112B, 113, 114, and 115. The power supply 110 is designed to include one or more multi-phase DC-DC converters to generate the required supply voltages. The power supply 110 responds to signals received from the CPU 120 on path 121 to control the multi-phase converter to reduce / increase the current output according to specific signals.

[0033] In this embodiment, the power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more buck switch converters to generate several lower voltages from a higher voltage power source. However, in other embodiments, other types of DC-DC converters can also be implemented, such as boost, buck-boost, hysteretic converters, etc., to replace the buck switch converters. Using a VRM allows multiple devices or ICs that require different supply voltages to be installed on the same platform, such as the motherboard of a personal computer (PC). Here, the description of the Figure 2 shown VRM continues.

[0034] 3. Voltage Regulator Module (VRM)

[0035] Figure 2This is a detailed block diagram of the VRM according to an embodiment of the present disclosure. Figure 1 The power supply 110 is a voltage regulator module (VRM) and is implemented as a multi-phase switching converter that generates two regulated voltages Va(240) and Vb(250).

[0036] The VRM 110 includes a phase controller 210, smart power stages (SPS(Smart Power Stage) / power stage) SPSA-1(220-1) to SPSA-6(220-6) and smart power stages (SPS / power stage) SPSB-1(230-1) to SPSB-3(230-3), inductors 225A-1 to 225A-6 and inductors 27B-1 to 227B-3, output capacitors 226A-1 to 226A-6 and output capacitors 228B-1 to 228B-3, bootstrap capacitors 224A-1 to 224A-6 and bootstrap capacitors 224B-1 to 224B-3. Each bootstrap capacitor associated with an SPS is connected between the respective nodes SW and BOOT of the corresponding SPS. Then, the bootstrap capacitor 224A-1 is connected between the switching node SWA-1(221-1) and BOOTA-1(215-1). Although the bootstrap capacitors shown in the figure are connected outside each SPS, in an alternative embodiment, the bootstrap capacitors can be located inside the SPS. It should be noted here that, generally speaking, the term "voltage regulator" refers to an independent regulator, such as an independent switching converter, or a part of an independent regulator, such as the smart power stage of an independent regulator.

[0037] The voltage Va(240) (Rail-A) is generated by a 6-phase buck converter (a total of 6 SPSs - 220-1 to 220-6), and the voltage Vb(250) (Rail-B) is generated by a 3-phase buck converter (a total of 3 SPSs - 230-1 to 230-3). The nodes / paths 240 and 250 can correspond to Figure 1 the paths 112A and 112B of Figure 2 The switching nodes 221-1 to 221-6 of the corresponding power stages are also shown. For the sake of brevity, Figure 2 not shown in Figure 1 other power supply circuits that generate power supply on the paths 113, 114, and 115. It can be clearly seen from the context that the smart power stages will be referred to individually or collectively by the reference numbers 220 / 230. In addition, it can also be seen from the context that the inductors 225A-1 to 225A-3 and 227B-1 to 227B-4 can be collectively or individually referred to as the corresponding numbered digits 225 and 227. Other blocks / components / signals throughout the disclosure follow a similar convention.

[0038] In embodiments of the present disclosure, each power stage and phase controller are implemented as separate integrated circuits (ICs). However, in other embodiments, the implementation of the power stage and phase controller may vary.

[0039] The phase controller 210 operates in conjunction with one or more power stages of a rail to generate a regulated voltage as an output. Figure 2 In an example, the phase controller 210 operates with one or more power stages of rail A (i.e., SPSA-1 to SPSA-6) to generate a regulated voltage Va (240). Similarly, the phase controller 210 operates with one or more power stages of rail B (i.e., SPSB-1 to SPSB-3) to generate a regulated voltage Vb (250). Thus, Va (240) and Vb (250) are provided as inputs to the phase controller 210 to enable one or more feedback loops within the phase controller 210 to operate, thereby regulating the voltages Va and Vb. The phase controller 210 also receives inductor current information (regarding the current IL 290 flowing through each inductor 225) from each SPS to implement various operations such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the currents generated by each SPS of the same converter (or “rail”) such that the magnitudes of the currents from each SPS of the converter are substantially equal. Furthermore, other signals flowing between the phase controller 210 and the SPSs will be described below.

[0040] The corresponding circuitry within the phase controller 210, a combination of an SPS with the corresponding inductor and capacitor form one “phase” of a rail. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and the corresponding circuitry within the phase controller 210 form a single buck converter, which is one of the phases in a 6-phase buck converter. It should be noted here that although each phase is shown with its own separate capacitor (such as 226A-1), in another implementation, a single larger capacitor (with a larger capacitance value) may be used only at node 240 (and 250). In other implementations, multiple capacitors are placed near the load powered by the corresponding supply voltage.

[0041] The phase controller 210 can be designed to implement automatic phase management (APM). Herein, the number of power stages (or phases) that the phase controller 210 operates on varies depending on the circumstances, such as the magnitude of the load current drawn from the rail (such as Va 240). Generally, the smaller the load current, the fewer the number of power stages used / operated, and conversely, the larger the load current, the more the number of power stages used / operated.

[0042] Each SPS (or what is generally referred to as a "power stage") may include a high-side switch, a low-side switch, gate drive circuits for the two switches, a temperature monitoring circuit, and an inductor current sensing circuit / block for providing information indicating the magnitude of the inductor current IL(290) to the phase controller 210. Although the high-side switch and the low-side switch of the SPS can be regarded as being used to "drive" the inductor, however, the current provided by the SPS and the corresponding inductor current generally depend on the load current drawn from the supply voltage. Each SPS receives a power supply (which can be the same power supply) as an input, and this input is connected to the high-side switch (which will be explained in detail below). In Figure 2 it, the power supply is numbered 201 and has a voltage Vin. The value of Vin in the embodiment of the VRM 110 is approximately 21 volts (V). Figure 2 It is also shown in it that the SPS220 receives the voltage Vcc at the power supply terminal 202.

[0043] Each SPS communicates with the phase controller 210 through the corresponding signals PWM, SYNC, CS, and TEMP. The SPSA-1 is connected to the phase controller 210 through the signals / paths PWMA-1(211), SYNC-A(212), CSA-1(213), and TEMPA(214). Although in Figure 2 the corresponding connections of the signals PWMA-6, SYNC-A, and CSA-6 to the phase controller 210 are not shown, however, the SPSA-6 communicates with the phase controller 210 through the signals PWMA-6, SYNC-A, CSA-6, and TEMP(214). Similarly, the SPSB-1 is connected to the phase controller 210 through the signals / paths PWMB-1(216), SYNC-B(217), CSB-1(218), and TEMPB(219). Although in Figure 2 it, the corresponding connections of the signals PWMB-3, SYNC-A, and CSB-3 to the phase controller 210 are not shown, however, the SPSB-3 communicates with the phase controller 210 through the signals PWMB-3, SYNC-B, CSB-3, and TEMPB(219). Furthermore, other SPSs have similar connections to the phase controller 210.

[0044] The PWM signal is an input from the phase controller 210 to the SPS and can be regarded as a "phase control signal" for controlling the power switch operations (such as ON and OFF states) in the SPS of the corresponding phase. In the embodiments of the present disclosure, the signal PWM is a pulse-width modulated signal. In such an embodiment, the signal PWM is a signal with a fixed frequency and a variable duty cycle. The duty cycle of the PWM signal is set by the phase controller 210 for the purpose of generating the required supply voltage and / or controlling / changing the current provided by the phase (SPS). For example, PWMA-1 (211) will have the magnitude of Va (240) and the duty cycle required for the current provided by SPSA-1 (220-1). For example, the duty cycle of PWMA-1 (211) is set according to the magnitude of Va (240) and the current that SPSA-1 (220-1) needs to provide. However, generally, the PWM signal may have other characteristics depending on the specific implementation details of the power supply 110.

[0045] For example, in another embodiment, the phase controller 210 may adopt a constant on-time control technique to generate Va. Therefore, in such an embodiment, the signal PWM is a variable frequency, fixed pulse width (constant on-time) signal (i.e., a pulse frequency modulation signal. Nevertheless, for the sake of convenience of reference, the abbreviation PWM is still used in this article to refer to such a signal). The frequency of the signal is generally proportional to the desired regulated voltage (Va) and the load current. In yet another embodiment, the signal PWM can switch between a variable frequency signal with a constant on-time and a pulse width modulated signal with a fixed frequency according to the load current requirements, the desired efficiency of the power supply 110, and other considerations, which are obvious to those skilled in the relevant art.

[0046] The signal PWM can also have a logic high level state, a logic low level state, or a high impedance state (Hi-Z). Generally, the logic high level state and the logic low level state of the signal PWM correspond to the positive rail and negative rail voltages of the power supply circuit that generates the signal PWM (within the allowed phase / noise range), respectively, while the high impedance state (Hi-Z) corresponds to the middle rail voltage of the power supply (or a voltage range close to the middle rail voltage), which is well known in the relevant art. However, other conventions can be adopted for the three states of the signal PWM, which are obvious to those skilled in the relevant field. Generally, in order for the power stage to correctly recognize the high impedance state (Hi-Z), the signal PWM needs to maintain a predetermined minimum duration within the above voltage range.

[0047] The signal PWM controls the conduction and turn-off of the high-side switch and the low-side switch of the phase / power stage through a logic high state and a logic low state. In an embodiment, the logic high state of PWMA-1 turns off and conducts the high-side switch and the low-side switch in SPSA-1, respectively. The logic low state of PWMA-1 conducts and turns off the high-side switch and the low-side switch in SPSA-1, respectively. The time interval during which the high-side switch (HS) conducts can be regarded as the "first stage" (or called the "high-side stage"), and the time interval during which the low-side switch (LS) conducts can be regarded as the "second stage" (or called the "low-side stage"). The first stage and the second stage are repeated periodically. The high-side switch and the low-side switch "drive" the inductor periodically in each first stage and second stage. It should be noted that the terms "first stage" and "second stage" should not be confused with the phases of a multiphase converter (as described above).

[0048] A PWM signal in a high impedance state (Hi-Z) will indicate to the power stage that the power stage does not generate an output voltage, that is, it is in an "inactive" state. Then, when the PWM is in the high impedance state (Hi-Z), the high-side and low-side switches of the power stage are both turned off, and the power stage enters a low power / depowered mode. Generally, the phase controller 210 is designed to be able to generate a PWM signal with three states, and one of the states indicates that the corresponding power stage should be in an inactive state. Those skilled in the relevant art will be aware that the functions of these three states can be implemented in other ways. For example, the phase controller 210 is designed to generate a traditional binary PWM signal, and the power stage is designed to recognize a high impedance state (Hi-Z) when the PWM signal is turned off (i.e., not generated at all).

[0049] As is well known in the relevant field, the PWM signals of each SPS of the same converter may be interleaved, that is, delayed in phase with respect to each other, to ensure that two high-side switches on the same rail (i.e., located in different SPSs respectively) do not conduct simultaneously. The reasons for adopting this technique include, for example, ensuring that the peak instantaneous current drawn from Vin is relatively low at any time.

[0050] The signal TEMP is an output (such as voltage) from the SPS to the phase controller 210 and provides information about the temperature in the SPS. The phase controller 210 can process the TEMP signal or the information contained therein to adjust the current provided by the phase (SPS), or turn off the VRM when a fault indicating an overheating condition occurs. The TEMP outputs of each phase of the converter are connected together, and a single input (such as TEMPA 214) is connected to the phase controller 210. The maximum value of the TEMP output of the phase is driven on the wired connection.

[0051] The signal SYNC is an input to the SPS and can be used by the phase controller 210 to wake up the SPS when the power supply 110 is powered on, while indicating the power mode (e.g., PS2, PS3) of the multiphase converter, i.e., the output current demand. Typically, all SPSs of the same converter share a single SYNC signal (e.g., SYNC-A 212). The signal SYNC is set to the high impedance state (Hi-Z), which indicates that the SPS will be turned off, i.e., all SPSs become inactive and no corresponding power will be generated. In one embodiment, the high impedance state (Hi-Z) is a voltage level / band between the logical high and logical low levels of the SYNC signal. When "SYNC = Hi-Z" occurs, the state machine (not shown) inside the power stage treats it as a "chip disable" signal and turns off all other internal blocks in the power stage.

[0052] The signal CS (current sensing) comes from the SPS / phase and is an input signal to the phase controller 210, which contains information about the instantaneous magnitude of the inductor current of that phase (SPS). This information can be in the form of current, voltage, digital value, etc., depending on the implementation of the power stage and the phase controller 210. The CS block in the SPS performs the current sensing operation and sends the signal CS to the phase controller 210.

[0053] In one embodiment of the present disclosure, the current sensing block of the power stage sends the sensed inductor current information to the phase controller 210 in the form of a current, which can be the same current as the magnitude of the inductor current or a scaled-down version (in terms of magnitude) of the inductor current. Accordingly, in the embodiment, the phase controller 210 is designed to receive information in the form of a current, and when a scaling factor is used, the phase controller 210 and the corresponding power stage are aware of the scaling factor.

[0054] Typically, during power stage operation, when the PWM signal changes between logic high and logic low, both switches change state, one switch turns on and the other switch turns off. As a result, the change in the inductor current is large. This leads to a relatively large rate of change of current (dI / dt) flowing through the switch (about tens / hundreds of amperes per nanosecond). Although the power stage devices are packaged with very low resistance and inductance, they may still have a parasitic inductance of about several tens of pH (pico Henry). The combination of these two factors, i.e., L*dI / dt, can generate a voltage bounce of several volts. The voltage bounce causes ringing (i.e., oscillation around the constant potential of the ground node and the power supply node) between the ground node and the power supply node / package pin of the power supply stage, and couples a large amount of unnecessary noise and interference to each power stage circuit through these nodes. This may cause the power stage to falsely indicate faults that did not actually occur and / or fail to indicate faults that actually occurred. More specifically, capturing and storing fault indications in clock-controlled digital circuits (such as flip-flops) may become unreliable. Similar problems may occur when the PWM signal transitions to the high impedance state (Hi-Z) or transitions from the high impedance state (hi-Z). For the sake of brevity, the following description only addresses the issues when the PWM signal changes between logic high and logic low.

[0055] The power stage may use an internally generated clock (hereinafter referred to as the "reference clock") to sample and time the logic / digital circuits within the power stage. The reference clock is not related to the PWM transitions that cause the above-mentioned power supply noise / ringing. Therefore, when the edges of the reference clock coincide (or align) with the switching events, it may cause the power stage to generate fault indications unreliably.

[0056] Specifically, due to the above-mentioned ringing phenomenon, when the binary signal sampled by the reference clock is stored in the internal circuits / components of the power stage, it may exhibit a logical state that is not expected or desired in the design. For example, when the sampling of the binary signal occurs simultaneously with the PWM transition, the local ground potential may not be zero volts, so the voltage level of the binary signal relative to the local ground potential may be in an intermediate unstable range, resulting in a logic high level being stored as a logic low level, and vice versa.

[0057] In addition, ringing may manifest as glitches on the signals generated by the power stage. Glitches generally refer to the unexpected transition of a signal to the wrong logic level. Usually, the duration of a glitch is very short, or may be much smaller than the normal duration of the signal. If the sampling edge of the reference clock occurs approximately simultaneously with the PWM transition that causes the glitch, the glitch may be stored as a fault within the power stage.

[0058] When such a fault signal is transmitted to the phase controller 210, the phase controller 210 may take corrective actions after receiving the fault signal. For example, for a fault that requires shutting down the power stage, the phase controller 210 may send a signal through a corresponding path to shut down the power stage, which may have a negative impact on the reliability of the power stage. Conversely, the phase controller 210 may fail to take corrective actions when they are actually needed.

[0059] Accordingly, it is desirable to be able to capture and / or store faults within the power stage in a reliable manner. Several aspects of the present disclosure are directed to minimizing or completely eliminating the above-described false fault indications so as to convey valid / actual faults to the phase controller, which will be described in detail hereinafter.

[0060] 4. Flow Chart

[0061] Figure 3A is a flow chart that illustrates how to generate a fault signal and transmit the fault signal to the phase controller with minimal or no error in one embodiment of the present disclosure. Although specific examples are provided in the description and reference is made to the components in Figure 2 , the features of the present disclosure can be applied to corresponding circuits / subsystems in other components and environments without departing from the scope and spirit of the various aspects of the present disclosure, as will be appreciated by those skilled in the relevant art by reading the disclosure provided herein.

[0062] In addition, depending on the needs of the specific environment, certain steps may be performed in a different order than described below, as will be appreciated by those skilled in the relevant art. Many such implementations are covered by various aspects of the present disclosure. The flow chart begins at step 301, where control immediately transfers to step 302.

[0063] In step 302, the SPS 220 drives the high-side switch and the low-side switch in the SPS based on the PWM signal 211 received from the phase controller 210. The SPS 220 uses corresponding first and second drive signals to drive the high-side switch and the low-side switch. As described above, the PWM signal 211 cyclically transitions (switches) between a first logic level (such as a logic high level) and a second logic level (such as a logic low level). When the PWM signal does not cyclically switch between logic levels (i.e., the PWM signal remains at a logic high level, a logic low level, or a high impedance state), the PWM signal is referred to as "not switched". The first drive signal and the second drive signal are respectively enabled to drive corresponding currents through the inductor 225 in the high-side phase and the low-side phase of the SPS 220. Thus, when the PWM signal is at a logic high level (high-side phase), the high-side switch conducts, and when the PWM signal is at a logic low level (low-side phase), the low-side switch conducts.

[0064] As described above, when the PWM signal switches between two logic levels, ringing (unwanted oscillation / voltage bounce) occurs at the ground terminal (i.e., node 299) and stabilizes after a settling time. Ringing may also occur at the power supply terminals Vin(201) and Vcc(202) of the SPS220 and stabilizes after a corresponding settling time of a corresponding amplitude. The term "settling time" as used herein refers to the time from the start of ringing until the oscillation amplitude becomes (and remains within) an acceptable error range (e.g., less than 10% of the peak-to-peak oscillation).

[0065] In step 304, the SPS220 forms a delayed version of the PWM signal. This delayed version is formed by delaying the edges of the corresponding PWM signal by an amount greater than the maximum settling time of the ringing at the above-mentioned terminals. In other words, assuming that the ringing at the ground terminal, the power supply terminal Vin, and the power supply terminal Vcc stabilizes within their respective settling times, the maximum settling time is selected to form the delayed version of the PWM signal. However, due to the characteristics of the ringing phenomenon (affected by the inductance of the IC package leads, for a given IC package, the ringing amplitude at each lead terminal may be approximately similar), the combination of ringing at each terminal may stabilize within the corresponding settling time. Generally, the selected delay time should ensure that such ringing at all terminals stabilizes, and then the control proceeds to step 305.

[0066] In step 305, the SPS220 captures faults (such as overheating, overcurrent, etc.) as corresponding deviation signals. The deviation signal is a binary signal, which is sensed (sampled and / or latched) in the SPS220 by a corresponding latch circuit (such as a flip-flop controlled by a clock generated internally by the SPS220). As described above, ringing may manifest as an unexpected device state and / or glitches on the binary signal.

[0067] In step 306, the SPS220 generates a fault signal by sensing each deviation signal according to the delayed version of the PWM signal. It can be understood that ringing occurs when the PWM signal transitions between logic levels. Sensing the deviation signal according to the delayed version of the PWM signal allows sufficient time for the ringing to stabilize and for the ground potential to stabilize, thereby minimizing or significantly reducing false alarms of faults. Then, the control transfers to step 307.

[0068] In step 307, the SPS220 transmits the fault signal to the phase controller 210. It can be understood that the fault signal generated in step 306 can reliably indicate the occurrence of a fault condition. The phase controller 210 may take any necessary corrective measures after receiving the fault signal. For example, for a fault that requires shutting down the SPS220, the phase controller 210 may send an appropriate signal to the SPS220 to shut down the SPS. The flowchart ends at step 309.

[0069] Next, a power stage implemented according to aspects of the present disclosure will be described. The power stage is capable of reliably sensing faults while taking into account the above ringing effect.

[0070] 5. Smart Power Stage (SPS)

[0071] Figure 3B A block diagram of the SPS implementation details of an embodiment of the present disclosure. SPSA-1 (220-1) is disclosed in detail in Figure 3B . Other SPSs can also be implemented in a manner similar to SPSA-1. SPSA-1 includes a gate driver 310, a high-side (HS) switch 320, a low-side (LS) switch 330, a temperature sensing block 340, a current sensing block 350, and a fault logic block 360. Figure 3B An inductor 225A-1 and an output capacitor 226A-1 are further disclosed. Node 240 provides a supply voltage Va. It should be noted here that Figure 3B only the relevant components for understanding the present disclosure are depicted. It can be understood that SPS220-1 may include more or fewer blocks than Figure 3B shown.

[0072] The gate driver 310 receives a PWM signal, such as PWMA-1 (211-1) from the phase controller 210, and generates an appropriate voltage in response to the logic level of the PWM signal, so as to turn on and off the HS switch 320 and the LS switch 330 at the corresponding intervals according to the logic level of the PWM signal. Both the HS switch 320 and the LS switch 330 are implemented with N-channel MOSFETs (metal oxide semiconductor field effect transistors), and the gate driver 310 drives the gate terminals of the MOSFETs. Although MOSFETs are taken as an example here, other switch implementation methods with similar characteristics can also benefit from the features described herein.

[0073] Figure 3BIn the example, when PWMA-1 is at a logic high level, the gate driver 310 generates respective appropriate voltages on paths 312 (en-HS) and 313 (en-LS) to turn on the MOSFET 320 and turn off and disconnect the MOSFET 330. When PWMA-1 is at a logic low level, the gate driver 310 generates respective appropriate voltages on paths 312 (en-HS) and 313 (en-LS) to turn off the MOSFET 320 and turn off and turn on the MOSFET 330. When PWMA-1 is in the Hi-Z (high impedance or intermediate rail) state, the gate driver 310 generates respective appropriate voltages on paths 312 and 313 to turn off the MOSFETs 320 and 330. It should be noted here that in addition to the single gate driver 310, two separate gate drivers can also be employed, where one gate driver is used to drive the gate of the HS switch to turn on or off, and the other gate driver is used to drive the gate of the LS switch to turn on or off. The gate driver 310 is implemented in a known manner.

[0074] The temperature sensing block 340 is used to measure the magnitude of the junction temperature and provide information via path 214, such as information on the magnitude of the junction temperature in the form of a voltage. The temperature sensing block 340 is implemented in a known manner.

[0075] The current sensing block 350 is used to determine the magnitude (such as the instantaneous magnitude) of the inductor current flowing through the inductor 225A-1 and provide information on the magnitude of the inductor current via path 213. The current sensing block 350 can determine the magnitude of the inductor current by one of several known methods. For example Figure 3B the current sensing block 350 in [example] can receive inputs 325 and 335 from the HS switch 320 and the LS switch 330 respectively. In one embodiment, the signals 325 and 335 respectively represent the corresponding voltage drops across the HS switch and the LS switch when the corresponding switch is turned on and current flows through the turned-on switch and the inductor 225A-1. The current sensing block 350 obtains the instantaneous magnitude (or a scaled-down version thereof) of the inductor current based on the voltage drop. In one embodiment, the current sensing block 350 provides or reports the inductor current information in the form of a (replicated) current (sensing current), the magnitude of which is scaled down relative to the instantaneous inductor current magnitude. In an alternative embodiment, the current sensing block 350 provides information in the form of a voltage or a digital value. The current sensing block 350 is implemented in a known manner.

[0076] The fault logic block 360 is used to detect faults based on the internal state of the power stage 220 and transfer such faults to the phase controller 210. The fault logic block 360 receives the PWMA-1 signal on path 211-1, the temperature sensing information (TEMPA) on path 214, the current sensing information (CSA-1) on path 213-1, the voltage BOOTA-1 on path 215-1, and the voltage Vin on path 201, and generates a fault-output signal on path 362. The lower and upper limits of the startup voltage and the supply voltage, the upper limit of the inductor current, and the upper limit of the temperature can be configured in a known manner at the time of design (hard-wired in the IC). The information received on paths 214, 213, 215, and 201 is used to represent the internal state of the SPS 220.

[0077] The fault logic block 360 internally generates signals indicating the deviation of parameters (such as the above-mentioned temperature, inductor current, etc.) from the corresponding limit values. The fault logic block 360 senses (samples) these deviation signals based on a delayed version of the signal PWMA-1 (211-1). In one embodiment, the fault logic block 360 transfers the fault-output signal to the phase controller 210 through the CSA path / pin 213.

[0078] The implementation details of the fault logic block of the embodiment of the present invention will be further described below.

[0079] 6. Fault Logic Block 360

[0080] Figure 4A is a schematic diagram of the fault logic block of the embodiment of the present disclosure. The fault logic block 360 includes a fault detector 410, a PWM delay block 420, a PWM state detector 430, a fault sampling block 450, and a fault communication block 460. The fault sampling block 450 includes an inverter 448, a flip-flop 455, and AND gates 440, 445. The fault communication block 460 is timed by a reference clock (osc-clk) 453. It should be noted here that Figure 4A only the relevant components for understanding the present disclosure are depicted. It can be understood that the fault logic block may include more or fewer blocks than Figure 4A shown.

[0081] As described above, when the signal PWMA-1 periodically switches (transitions) between logic high and logic low levels, ringing may occur at the ground terminal (299), resulting in false fault indications. The fault logic block implemented according to various aspects of the present invention can eliminate or significantly reduce such false fault indications, thereby transmitting effective fault information to the phase controller 210.

[0082] According to one aspect of the present disclosure, the fault logic block 360 senses (samples) a fault (deviation signal) based on a delayed version of the PWMA-1 signal. By using a sampling edge that is delayed relative to the edge of the PWMA-1 signal to sample the deviation signal, it can be ensured that no incorrect logic states are captured / stored during ringing. In addition, signal glitches in the fault signal path caused by ringing are not stored / captured either. In other words, the sensitivity of the fault signal to ringing can be avoided. This method can avoid or significantly reduce false fault indications, thereby generating a fault signal that reliably indicates a fault condition. The individual sub-blocks of the fault logic block 360 will be described in more detail below.

[0083] The fault detector 410 generates a deviation-occurred signal on path 412 to indicate whether a corresponding fault exists by checking the internal state of the SPS220. The fault detector 410 receives temperature sensing information (TEMPA) on path 214, inductor current information (CSA-1) on path 213-1, and voltages BOOTA-1 and Vin that represent the internal state of the SPS220. The lower and upper limits of the startup voltage and supply voltage, the upper limit of the inductor current, and the upper limit of the temperature can be configured in a known manner at design time (hard-wired in the IC) or specified by the user through corresponding means not shown.

[0084] In one embodiment, for each fault, when a deviation beyond a specified limit is detected, the fault detector 410 sets the corresponding deviation-occurred signal to an enabled state (logic high), otherwise it holds the corresponding deviation-occurred signal in a disabled state (logic low). The fault detector 410 may internally include an overcurrent detector, a comparator circuit, etc. to detect whether the temperature, voltage, and current exceed the corresponding limits. The specific circuits for detecting such faults are not shown in Figure 4A but can be implemented in a known manner. Although the illustrative embodiment describes checking for deviations in the inductor current, temperature, startup voltage, and Vin, alternative embodiments may check fewer or more parameters to detect the corresponding deviations, as will be understood by those skilled in the relevant art by reading the present disclosure. Due to ground bounce, glitches may occur on path / signal 412.

[0085] The PWM delay block 420 generates a delayed version of the signal PWMA-1 on path 422. In one embodiment, the rising edge of signal 422 is delayed by a predetermined time magnitude relative to the corresponding falling edge of the PWMA-1 signal, the predetermined time magnitude being sufficient to allow the propagation time from the transition of the PWMA-1 signal to the start of the change in the voltage magnitude at the SW node (221-1) and to stabilize the ringing. Thus, taking into account the design margin specific to the environment, the delayed time magnitude is equal to the sum of (i) plus (ii), where (i) is the propagation time from the transition of the PWMA-1 signal to the start of the change in the SW node voltage magnitude, and (ii) is the maximum stabilization time among the stabilization times of the ringing at the terminals of ground (299), Vin (201), and Vcc (202). The circuits in the power stage can be simulated (in a known manner) using suitable simulation tools, and / or the power stage itself can be circuit tested and the time required for the ringing to stabilize and the propagation time can be estimated based on the results. The delayed time magnitude can be configured in a known manner at design time (hard-wired in the IC). In this embodiment, for a power stage with an input voltage of 12V and providing an output current of several tens of amperes, the delayed time magnitude is 50 nanoseconds (ns). Generally, the delayed time magnitude depends on factors such as package parasitic values (such as inductance, series resistance, and capacitance), the supported input voltage, and the output load current, etc. In this embodiment, the falling edge of the signal pwm-delayed is synchronized with the rising edge of the signal PWMA-1. When the signal PWMA-1 does not switch, the signal pwm-delayed remains at logic low. Further, although this illustrative embodiment describes the generation of the rising edge of the signal pwm-delayed being delayed relative to the falling edge of the signal PWMA-1, those skilled in the relevant art will understand, upon reading the present disclosure, that the various aspects of the present disclosure are equally applicable to the case where the falling edge of the signal pwm-delayed is delayed. The PWM delay block 420 is implemented in a known manner.

[0086] The PWM status detector 430 generates a signal pwm-not-alive on path 432, which is timed by the reference clock osc-clk (453). The signal pwm-not-alive is used to indicate whether the signal PWMA-1 (the input signal received on path 211-1) is switching. In an embodiment, when the signal PWMA-1 is not switching (i.e., PWMA-1 remains at a logic high level, a logic low level, or a high impedance state), the PWM status detector 430 sets the signal pwm-not-alive to the enabled state (logic high level), otherwise keeps the signal pwm-not-alive in the disabled state (logic low level). Thus, when the signal PWMA-1 switches (transitions between a logic high level and a logic low level according to the frequency determined by the phase controller 210), the signal pwm-not-alive is at a logic low level. In one embodiment, the PWM status detector may be implemented in accordance with Figure 4B as described.

[0087] The fault sampling block 450 senses (samples) each deviation-occurred signal based on the rising edge of the signal pwm-delayed (422) and generates a corresponding fault-clean signal on path 452. The fault-clean signal is a reliable signal indicating the corresponding fault condition. For the sake of brevity, Figure 4A only one instance of the fault sampling block 450 is shown herein, but it is noted that for each deviation-occurred signal, a corresponding fault sampling block 450 is implemented to sense the deviation-occurred signal and generate a corresponding fault-clean signal.

[0088] The inverter 448 receives the deviation-occurred signal on path 412 and generates the logical inversion of the deviation-occurred signal on path 412'. The AND gate 440 receives the signal (pwm-not-alive) on path 432 and the deviation-occurred signal on path 412 and generates an AND output on path 442. The AND gate 445 receives the signal (pwm-not-alive) on path 432 and the logical inversion of the deviation-occurred signal on path 412' and generates an AND output on path 447.

[0089] The flip-flop 455 is timed by the signal pwm-delayed(422). The flip-flop 455 receives the deviation-occurred signal through the D input and generates a corresponding fault-clean signal on path 452 on the output (Q) path. In one embodiment, the flip-flop 455 is a positive edge-triggered flip-flop. Herein, the flip-flop 455 stores the signal 412 synchronized with the rising edge of the signal pwm-delayed(422). Additionally, when asynchronous set / reset inputs are received at the S and R inputs of the flip-flop 455 through paths 442 and 447 respectively, the flip-flop 455 functions as an SR latch. In an alternative embodiment, the flip-flop 455 can be a negative edge-triggered flip-flop when the PWM delay block 420 generates the sampling edge as a falling edge, which will be apparent to a person skilled in the art reading the present disclosure.

[0090] In operation, when the signal PWMA-1 toggles, the signal pwm-delayed also transitions between corresponding logic levels, i.e., after the corresponding falling edge of PWMA-1, according to the timing of the specified delay, the signal pwm-delayed contains a rising edge. Thus, if the deviation-occurred signal is valid, the flip-flop 455 will synchronously transfer the logic level of the deviation-occurred signal on path 452 immediately when the pwm-delayed rising edge occurs after the deviation-occurred signal becomes valid. Additionally, when the signal PWMA-1 toggles, the signal pwm-not-alive is at logic low level. Thus, both the S and R inputs of the flip-flop 455 are at logic low level.

[0091] When the signal PWMA-1 is not toggling, the signal pwm-delayed is at logic low level. If the deviation-occurred signal is valid, the set-input of the flip-flop 455 is asynchronously enabled through the operation of the OR gate 440, and the logic level (logic high level) of the signal deviation-occurred is output on path 452. Thus, faults can be reliably captured in both cases when PWMA-1 toggles and when PWMA-1 is not toggling.

[0092] The fault communication block 460 receives a fault-clean signal on path 452 and generates a fault-output signal on path 362. The fault communication block 460 is timed by osc-clk 453. In one embodiment, the fault communication block 460 serializes a plurality of fault-clean signals received on path 452 and generates a fault-output signal on path 362. In one embodiment, the fault communication block 460 can be implemented in the manner described in Figure 4C the manner described.

[0093] Next, implementation details of the PWM state detector implemented according to various aspects of the present disclosure will be described.

[0094] 7. PWM State Detector

[0095] Figure 4B FIG. is a schematic diagram of implementation details of the PWM state detector of an embodiment of the present disclosure. The PWM state detector 430 includes a level shifter 432, a delay block 435, an exclusive OR (XOR) gate 437, and a counter 439.

[0096] In an illustrative embodiment, the PWM state detector uses the counter 439 to detect whether the signal PWMA-1 is switching. Whenever the signal PWMA-1 makes a transition (i.e., PWMA-1 is switching), the counter will be reset. If the duration that the PWMA-1 signal does not switch (i.e., remains at a logic low / high / high impedance state) exceeds a predetermined duration corresponding to the maximum count value of the counter 439, the signal pwm-not-alive is enabled to indicate that PWMA-1 has not switched.

[0097] The level shifter 432 receives the three-state signal PWMA-1 on path 211 to generate a binary signal on path 433. In one embodiment, when the logic level of the signal PWMA-1 is logic high, the signal on path 433 is logic high, otherwise it is logic low. The level shifter 432 is implemented in a known manner.

[0098] The delay block 435 generates a signal 436 based on the input signal received on path 433. The signal 436 is a delayed version of the signal on path 433. In one embodiment, the minimum pulse width required to reliably reset the above counter is the delay generated by the delay block 435. The time amplitude of the delay can be fixed and can be configured in the SPS220 at design time. In an illustrative embodiment, the time amplitude of the delay is equal to 5 nanoseconds. The exclusive OR gate 437 receives the signals on paths 433 and 436 and generates a signal "reset" on path 438.

[0099] The counter 439 receives the signal "reset" on path 438 and is clocked by osc-clk (453). In one embodiment, the counter 439 is a synchronous up-counter with a maximum count value corresponding to a time length of 8 microseconds. When the signal'reset' is logic high, the counter 439 is reset (the count value is set to zero). When the count value reaches the maximum count, the counter 439 enables the signal pwm-not-alive. The counter 439 can be designed to count for a time length sufficient to reliably determine that the signal PWMA-1 has not switched. Furthermore, the specific time length depends on the specific implementation of the SPS220, which will be understood by those skilled in the art by reading this disclosure. The counter 439 is implemented in a known manner.

[0100] Although the illustrative embodiment describes a particular technique (a technique using a reset signal and a counter) for determining whether PWMA-1 has switched, aspects of the present disclosure can equally employ alternative techniques (techniques with corresponding signals) to generate the pwm-not-alive condition, as will be understood by those skilled in the relevant art by reading the disclosure herein.

[0101] Next, the implementation details of the fault communication block of aspects of the present disclosure will be described.

[0102] 8. Fault Communication Block

[0103] Figure 4C is a block diagram of the implementation details of the fault communication block of an embodiment of the present disclosure. The fault communication block 460 includes a debounce block 465 and an output interface 475. It should be noted herein that Figure 4C only the elements relevant to understanding the present disclosure are depicted. It can be understood that the fault communication block 460 may include more or fewer blocks than Figure 4C shown.

[0104] The fault communication block 460 is used to remove the glitches in the fault information received on path 452 (path 452 represents the respective path for each fault-clean signal) and record the debounced fault signal in an internal memory, which may include volatile and non-volatile memories. The fault communication block 460 transfers the recorded fault information on path 362 to the phase controller 210 through the output interface 475.

[0105] In addition to the delayed sampling of faults implemented by the fault sampling block 450, the debounce block 465 provides additional reliability before passing the faults to the phase controller 210. The debounce block 465 receives an input signal (including multiple fault-clean signals) on path 452 and generates a corresponding fault-deglitched signal on path 467. The debounce block 465 is timed by osc-clk (453).

[0106] In one embodiment, the debounce block 465 includes two Flip-Flop (FF) circuits for processing each fault-clean signal. The FF circuits are used to latch each fault-clean signal at corresponding edges of the osc-clk spaced one or more cycles apart. The output of the first FF circuit serves as the input to the second FF circuit. The first FF samples the corresponding fault-clean signal, and after one or more osc-clk clock cycles (such as 2 to 3 clock cycles), the output of the first FF circuit will be latched in the second FF circuit, and then the first FF circuit will sample the corresponding fault-clean signal again. If the two sampled values are the same, the fault-deglitched is set to the logic level of the corresponding fault-clean signal. Conversely, if the two sampled values are different, the fault-clean signal is considered unreliable and is ignored. Therefore, even if one sampled value is logic high, each fault-deglitched corresponding to the fault-clean signal is set to logic low. The debounce block 465 is implemented in a known manner. Although the illustrative embodiment describes the debounce block 465 as part of the fault communication block 460, in an alternative embodiment, the debounce block 465 can be located outside the fault communication block 460 (and before the fault communication block 460) and implemented in the transmission path 452 of the fault-clean signals between the fault sampling block 450 and the fault communication block 460.

[0107] The output interface 475 is used to store the fault information and transmit the fault information to the phase controller 210. In one embodiment, the output interface 475 records the fault-deglitched signal in an internal memory, which is designed as / includes a sticky bit register, and the sticky bit register is designed to store only the first change in the bit element and disable any subsequent changes to the bit element. Some or all of the fault-deglitched signals can be recorded in the sticky bit register. In an alternative embodiment, the memory is implemented in a different way.

[0108] In one embodiment, the output interface 475 transmits fault information (fault-output, 362) to the phase controller 210 via path 213 (CSA-1). When the output interface 475 is to transmit fault information on path 362, the output of the current sensing block 350 is disconnected from path 213. Similarly, when the current sensing block 350 is to transmit sensed inductor current information via path 213, the output of the output interface 475 is electrically disconnected from path 362, such as the output of the output interface 475 electrically disconnecting path 362 via an internal switch of the output interface 475. Such disconnections are performed in a known manner, and for the sake of brevity, the mechanisms and commands for such disconnections are not shown or described herein. Although the illustrative embodiment describes fault communication on path 213 (CS path / pin), in alternative embodiments, different pins / paths (e.g., path 214) may be employed to appropriately communicate fault information (fault-output) to the phase controller 210, and corresponding changes to the circuit are made, which will be apparent to those skilled in the art of the present disclosure by reading the present disclosure.

[0109] It can be understood that there is only one data path / line (CSA-1) for serially transmitting fault information in the form of binary values and for synchronous communication between the SPS 220 and the phase controller 210 without a common clock as a reference. In one embodiment, the output interface 475 uses osc-clk (453) as the transmission clock to send fault information (fault-output) to the phase controller 210. In this embodiment, if any of the fault-deglitched signals is logic high, the output interface 475 transmits the fault information (fault-output) to the phase controller 210. In an alternative embodiment, the output interface 475 may transmit the fault information (fault-output) to the phase controller 210 only when a pre-configured fault condition occurs. In another alternative embodiment, after receiving a logic high on path 467, the output interface 475 may wait for a predetermined period before transmitting the corresponding fault information (fault-output) to the phase controller 210. Generally speaking, depending on the type of fault, the time and manner of transmitting the fault information (fault-output) to the phase controller 210 may vary.

[0110] Next, continue to describe the manner in which various aspects of the present disclosure reliably capture faults to transmit them to the phase controller 210.

[0111] 9. Reliability Detection of Faults

[0112] Figure 5Ais a timing diagram (not drawn to scale) that shows example waveforms of the signals of each node of SPS220 in the first scenario in an embodiment of the present disclosure. The first scenario describes a situation where ringing may cause the device state to be incorrect in the absence of a fault sampling block.

[0113] Figure 5A shows example waveforms of signals such as osc-clk (453), PWMA-1 (211-1), reset (438), pwm-not-alive (432), pwm-delayed (422), deviation-occurred (412), and fault-clean (452). The duration 'Δt1' represents the amount of delay generated by the delay block 435, which is also equal to the pulse width of the signal "reset" (438). The duration 'Δt2' represents the duration during which the falling edge of the PWM is delayed until the corresponding rising edge of the pwm-delayed signal is generated.

[0114] The PWMA-1 signal switches within the time interval t501 to t512. The time interval t501 to t502 represents the high-side phase (HS switch 320 is on, LS switch 330 is off), while the time interval t502 to t504 represents the low-side phase (HS switch 320 is off, LS switch 330 is on). Through the operation of the PWM state detector 430, the pulse'reset' (438) is synchronously generated at each rising edge and falling edge of the PWMA-1 signal, and its pulse width is equal to the duration 'Δt1'. The counter 439 is reset at time points such as t501, t502, t504, etc. Within the time interval t501 to t512, the signal pwm-not-alive remains at logic low (LOW).

[0115] Each falling edge of the PWMA-1 signal is delayed for a duration of 'Δt2' to generate the corresponding rising edge in the pwm-delayed signal (e.g., at t503, t506, t509). In the illustrative embodiment, the falling edge of pwm-delayed (e.g., at t504) is shown to be generated synchronously with the rising edge of PWMA-1.

[0116] Assume that no fault occurs during the time interval t501 - t507. Then, during the time interval t501 - t507, the signal deviation - occurred(412) shows a logic low level. This article points out that in the absence of the fault sampling block 450, during the time interval t504 - t505, the signal deviation - occurred is at logic low level (LOW), but due to the ringing effect, there is a non - zero probability that this logic low level may be misjudged as logic high level (HIGH). If this happens, this error state may be stored in the fault communication block when the rising edge of osc - clk occurs at time t505. At time t505, the rising edge of osc - clk occurs very close to the transition of the logic level of the PWMA - 1 signal from low to high at time t504, and this transition of the logic level causes the ringing effect. However, since the fault sampling block 450 samples the signal deviation - occurred only after the ringing stabilizes, no false fault indication is sent to the phase controller 210.

[0117] At time t507, a fault confirmation occurs, and the corresponding signal deviation - occurred is set to valid (and remains valid) to indicate the occurrence of a fault. At time t509, when the rising edge of the pwm - delayed signal occurs (i.e., the first pwm - delayed rising edge after deviation - occurred is set to valid), a valid signal deviation - occurred is output on the Q output of the flip - flop 455. Therefore, the signal fault - clean is considered valid starting from time t509.

[0118] Before t517, the PWMA - 1 signal stops switching and remains unchanged until t520. In this exemplary embodiment, when the PWMA - 1 signal stops switching, it is held at logic low level (LOW), however, it can also be held at logic high level (HIGH or high - impedance state (hi - Z)). Since the PWMA - 1 signal does not switch, under the operation of the PWM state detector 430, the signal'reset' remains at logic low level (LOW). When the counter reaches the maximum count at time t517, the pwm - not - alive signal is considered valid and remains in the valid state until the PWMA - 1 signal resumes switching at time t520. During the time interval from t517 to t521, the pwm - delayed signal remains at logic low level (LOW).

[0119] At time t518, a fault is confirmed to occur, and the corresponding deviation-occurred signal is considered valid (and remains valid). The flip-flop 455 operates as an SR-latch, and since its set-input becomes HIGH at time t518, the fault-clean signal is considered valid at time t518.

[0120] Next, continue to describe how to prevent (or at least reduce) the glitches in the deviation-occurred signal from being mis-indicated as corresponding faults.

[0121] Figure 5B FIG. is a timing diagram (not drawn to scale), which shows the example waveforms of the signals of each node of the SPS220 in the second scenario according to the embodiments of the present disclosure. The second scenario describes that ringing may generate glitches on the signal deviation-occurred, and without a fault sampling block, these glitches may be misjudged as faults. Figure 5B The waveform of Figure 5A corresponds to Figure 5A For the sake of brevity, only the differences from the

[0122] In the time interval from t534 to t535, a glitch is shown on the signal deviation-occurred. This glitch is caused by the ringing effect, and the ringing is caused by the switching event when the level of the PWMA-1 signal changes from low to high at time t534. Without the fault sampling block 450, this glitch would be stored as a valid fault at the rising edge of osc-clk at time t535. Such an invalid fault would be transmitted to the phase controller 210 as the corresponding fault information.

[0123] At time t536, the deviation-occurred signal is at logic LOW. Since the deviation-occurred signal is sensed (sampled) at the rising edge of the pwm-delayed signal (occurring at time t536), and the ringing has stabilized at this time, the glitch on the deviation-occurred signal is not captured as a fault (the fault-clean signal remains at logic LOW at time t536). In the time interval from t536 to t547, no deviation occurs, so the signals deviation-occurred and fault-clean both remain at logic LOW in this interval.

[0124] In this way, according to the aspects of the present disclosure, the power stage of the multiphase switching converter reliably captures and communicates faults.

[0125] 10. Conclusion

[0126] As used herein, the terms "one embodiment", "an embodiment", or similar language refer to a particular feature, structure, or characteristic described in connection with an embodiment and included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment", "in an embodiment", and similar language in the specification are not necessarily all referring to the same embodiment.

[0127] Although in Figure 1 、 2 、the diagrams of 3B and 4A - 4C show the terminals / nodes directly connected to various other terminals, it should be understood that there may be other components suitable for the particular environment in the path, and thus these connections can be considered "electrically coupled" to the same connection terminals.

[0128] In the present application, the power supply terminal and the ground terminal are referred to as terminals having a constant reference potential.

[0129] Although various embodiments of the present disclosure have been described above, it should be understood that these embodiments are presented by way of example and not limitation. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A power stage of a multiphase switching converter, characterized in that, Comprising: A high-side switch and a low-side switch are connected in series at a switching node, and the high-side switch and the low-side switch are connected in series between a first power supply terminal provided with a first power supply and a ground terminal provided with a constant reference potential. An inductor is coupled between the switching node and an output node, and the power stage provides a regulated voltage at the output node. Wherein, the high-side switch and the low-side switch are respectively operated by a first driving signal and a second driving signal, and the first driving signal and the second driving signal are respectively triggered to drive corresponding currents through the inductor in a high-side phase and a low-side phase. A gate driver for generating the first driving signal and the second driving signal according to a control signal received from a phase controller; wherein, the first driving signal is triggered when the control signal is at a first logic level, and the second driving signal is triggered when the control signal is at a second logic level. Wherein, when the control signal switches between the first logic level and the second logic level, ringing occurs at the ground terminal, and the ringing stabilizes after a stabilization time. A fault logic block for generating a plurality of deviation signals by checking the internal state of the power stage to indicate corresponding deviations; wherein each of the plurality of deviation signals is a binary logic signal indicating the existence of a corresponding fault. The fault logic block generates the plurality of fault signals by sensing the plurality of deviation signals according to a delayed version of the control signal; wherein, the delayed version is generated by delaying the control signal by a first delay, and the time magnitude of the first delay is greater than the stabilization time of the ringing. The fault logic block transmits the fault signals to the phase controller to take any necessary corrective measures.

2. The power stage of the multiphase switching converter according to claim 1, wherein Wherein the fault logic block is powered by a second power supply at a second power supply terminal, and the ringing also occurs at the first power supply terminal and the second power supply terminal and stabilizes through the stabilization time of a corresponding amplitude.

3. The power stage of the multiphase switching converter according to claim 1, characterized in that, Wherein the control signal periodically switches between the first logic level and the second logic level within a first duration, and the control signal does not switch logic levels within a second duration. Wherein the fault logic block comprises: A plurality of fault sampling blocks, each of the plurality of fault sampling blocks is coupled to receive a corresponding deviation signal among the plurality of deviation signals and generate a corresponding fault signal among the plurality of fault signals. Wherein each of the plurality of fault sampling blocks comprises: A flip-flop is coupled to receive a corresponding deviation signal on a data input and a delayed version of the deviation signal on a clock input within a first duration. Wherein, the flip-flop is coupled to receive a corresponding deviation signal on a set input within a second duration. Wherein, the Q output of the flip-flop is the corresponding fault signal among the plurality of fault signals.

4. The power stage of the multiphase switching converter according to claim 3, wherein Wherein the fault logic block comprises: A first delay block is coupled to receive the control signal and generate the delayed version, wherein, the first delay block generates the rising edge of the delayed version by delaying the corresponding falling edge of the control signal by the time magnitude of the first delay. wherein the time magnitude of the first delay is equal to the sum of (i) and (ii), where (i) is the duration from the transition of the control signal between the second logic level and the first logic level to the start of the change in voltage at the switching node in response to the transition, and (ii) is the stabilization time.

5. The power stage of the multiphase switching converter according to claim 3, characterized in that, wherein the fault logic block includes: a fault detector block, coupled to receive temperature information indicating the temperature of the power stage, current information indicating the scaled magnitude of the instantaneous current flowing through the inductor, and voltage information indicating the voltage magnitude at the first power supply terminal, and generating the plurality of deviation signals, wherein when a fault condition is determined based on the temperature information, the current information, and the voltage information, the corresponding deviation signal among the plurality of deviation signals is valid; a control signal state detector block, receiving the control signal and generating a PWM switching signal, wherein the PWM switching signal has a first logic level during a first duration and a second logic level during a second duration; and a fault communication block, coupled to receive the plurality of fault signals and generate a fault output, wherein the fault communication block transmits the fault output to the phase controller, wherein each of the plurality of fault sampling blocks includes: a first inverter, coupled to receive the corresponding deviation signal and generate the logical inversion of the corresponding deviation signal; a first AND gate, for receiving the deviation signal and the PWM switching signal and generating a first AND output; and a second AND gate, for receiving the logical inversion and the PWM switching signal and generating a second AND output, wherein the flip-flop receives the first AND output at the set input and the second AND output at the reset input.

6. The power stage of the multiphase switching converter as claimed in claim 5, wherein, wherein the control signal state detector block includes: a level converter, for receiving the control signal and generating a converter output of a binary signal, wherein when the control signal is at the first logic level, the converter output is generated as a logic high level, otherwise it is generated as a logic low level; a second delay block, coupled to receive the converter output and delay the converter output by a time magnitude of a second delay to generate a second delay signal; an exclusive OR gate, coupled to receive the converter output and the second delay signal and generate a reset signal, wherein during the first duration, the pulse width of the reset signal is equal to the time magnitude of the second delay and is synchronized with the transition of the control signal, and wherein during the second duration, the reset signal is a logic low level; and a counter, for counting from a zero value to a maximum count, wherein the counter is timed by a reference clock, wherein when the reset signal is a logic high level, the count of the counter is set to the zero value, and wherein when the count of the counter reaches the maximum count, the counter enables the PWM switching signal.

7. The power stage of the multiphase switching converter according to claim 6, wherein, The fault communication block includes: A deburring block is coupled to receive the plurality of fault signals and generate a plurality of fault deburring signals corresponding to the plurality of fault signals. The deburring block is timed by the reference clock. The deburring block latches each of the plurality of fault signals at a first time point to generate a first latched value and generates a second latched value at a second time point after the first time point, and checks whether the first latched value and the second latched value are the same. If it is determined that the first latched value and the second latched value are the same, a fault deburring signal corresponding to each fault signal is generated, and the logic level of the fault deburring signal is the same as the logic level of each fault signal. If it is determined that the first latched value and the second latched value are different, a fault deburring signal corresponding to each of the fault signals and having a logic low level is generated. And An output interface block is coupled to receive the plurality of fault deburring signals and store the plurality of fault deburring signals in a register, and serialize the plurality of fault deburring signals according to the reference clock to generate the fault output.

8. The power stage of the multiphase switching converter according to claim 7, characterized in that, Wherein the plurality of fault signals indicate the occurrence of corresponding faults, including: The amount of current flowing through the inductor exceeds a corresponding limit value; The temperature of the power stage exceeds a corresponding limit value; and A short circuit occurs between the first power supply terminal and the ground terminal.

9. A voltage regulation block, characterized in that, Comprising: A phase controller that provides a regulated supply voltage at a supply node based on an input voltage received at an input node; and A power stage, comprising: A high-side switch and a low-side switch are connected in series at a switching node. The high-side switch and the low-side switch are connected in series between the input node and a ground terminal provided with a constant reference potential. An inductor is coupled between the switching node and the supply node. Wherein the high-side switch and the low-side switch are respectively operated by a first drive signal and a second drive signal, and the first drive signal and the second drive signal are respectively triggered to drive corresponding currents through the inductor in a high-side phase and a low-side phase. A gate driver generates the first drive signal and the second drive signal based on a control signal received from the phase controller; wherein, when the control signal is at a first logic level and a second logic level, the first drive signal and the second drive signal are respectively triggered. Wherein, when the control signal switches between the first logic level and the second logic level, ringing occurs at the ground terminal, and the ringing stabilizes after a stabilization time. A fault logic block is used to generate a plurality of deviation signals by checking the internal state of the power stage to indicate corresponding deviations; wherein each of the plurality of deviation signals is a binary logic signal indicating whether a corresponding fault exists. The fault logic block generates the plurality of fault signals by sensing the plurality of deviation signals according to a delayed version of the control signal; wherein the delayed version is generated by delaying the control signal by a first delay, and the time magnitude of the first delay is greater than the stabilization time of the ringing. The fault logic block transmits the plurality of fault signals to the phase controller to take any necessary corrective measures.

10. The voltage regulating block according to claim 9, characterized in that, The fault logic block is powered by a second power supply at a second power supply terminal, and the ringing also occurs at the input node and the power supply terminal and is stabilized by the stabilization time of a corresponding amplitude.

11. The voltage regulation block according to claim 9, characterized in that, The control signal periodically switches between the first logic level and the second logic level within a first duration, and the control signal does not switch logic levels within a second duration; The fault logic block includes: A plurality of fault sampling blocks, each of the plurality of fault sampling blocks being coupled to receive a corresponding one of the plurality of deviation signals and generate a corresponding one of the plurality of fault signals; Each of the plurality of fault sampling blocks includes: A flip-flop is coupled to receive a corresponding deviation signal on a data input and a delayed version of the deviation signal on a clock input within a first duration, wherein the flip-flop is coupled to receive a corresponding deviation signal on a set input within a second duration, wherein the Q output of the flip-flop is the corresponding fault signal among the plurality of fault signals.

12. The voltage regulation block according to claim 11, characterized in that, The fault logic block includes: A first delay block is coupled to receive the control signal and generate the delayed version, wherein the first delay block generates a rising edge of the delayed version by delaying a corresponding falling edge of the control signal by a time amplitude of the first delay, wherein the time amplitude of the first delay is equal to the sum of (i) and (ii), wherein (i) is the duration from the transition of the control signal between the second logic level and the first logic level to the start of the change in voltage at the switching node in response to the transition, and (ii) is the stabilization time.

13. The voltage regulation block according to claim 11, wherein The fault logic block includes: A fault detector block, coupled to receive temperature information indicating the temperature of the power stage, current information indicating a scaled magnitude of an instantaneous current flowing through the inductor, and voltage information indicating a voltage amplitude at the input node, and generate the plurality of deviation signals, wherein when a fault condition is determined based on the temperature information, the current information, and the voltage information, a corresponding one of the plurality of deviation signals is valid; A control signal state detector block, receiving the control signal and generating a PWM switching signal, wherein the PWM switching signal has a first logic level within a first duration and a second logic level within a second duration; and A fault communication block, coupled to receive the plurality of fault signals and generate a fault output, wherein the fault communication block transmits the fault output to the phase controller, Each of the plurality of fault sampling blocks includes: A first inverter, coupled to receive the corresponding deviation signal and generate a logical inversion of the corresponding deviation signal; A first AND gate for receiving the deviation signal and the PWM switching signal and generating a first AND output; and A second AND gate for receiving the logical inversion and the PWM switching signal and generating a second AND output, wherein the flip-flop receives the first AND output at the set input and the second AND output at the reset input.

14. The voltage regulation block according to claim 13, wherein The control signal state detector block includes: A level converter for receiving the control signal and generating a converter output of a binary signal, wherein when the control signal is at the first logic level, the converter output is generated as a logic high level, otherwise it is generated as a logic low level; A second delay block coupled to receive the converter output and delay the converter output by a time amplitude of a second delay to generate a second delay signal; An exclusive-OR gate coupled to receive the converter output and the second delay signal and generate a reset signal, wherein within the first duration, the pulse width of the reset signal is equal to the time amplitude of the second delay and is synchronized with the transition of the control signal, and wherein within the second duration, the reset signal is at a logic low level; and A counter for counting from a zero value to a maximum count, wherein the counter is timed by a reference clock, wherein when the reset signal is at a logic high level, the count of the counter is set to the zero value, and wherein when the count of the counter reaches the maximum count, the counter enables the PWM switching signal.

15. The voltage regulating block according to claim 14, characterized in that The fault communication block includes: A debounce block coupled to receive the plurality of fault signals and generate a plurality of fault debounced signals corresponding to the plurality of fault signals, the debounce block being timed by the reference clock, wherein the debounce block latches each of the plurality of fault signals at a first time point to generate a first latched value and generates a second latched value at a second time point after the first time point, and checks whether the first latched value and the second latched value are the same; If it is determined that the first latched value and the second latched value are the same, a fault debounced signal corresponding to each fault signal is generated, and the logic level of the fault debounced signal is the same as the logic level of each fault signal; If it is determined that the first latched value and the second latched value are different, a fault debounced signal corresponding to each of the fault signals and having a logic low level is generated; And An output interface block coupled to receive the plurality of fault debounced signals and store the plurality of fault debounced signals in a register, and serialize the plurality of fault debounced signals according to the reference clock to generate the fault output.

16. The voltage regulation block according to claim 15, characterized in that, Wherein the plurality of fault signals indicate the occurrence of corresponding faults, including: The amount of current flowing through the inductor exceeds a corresponding limit; The temperature of the power stage exceeds a corresponding limit; and A short circuit occurs between the first power supply terminal and the ground terminal.

17. A method performed in a power stage of a multiphase switching converter, characterized in that, The multiphase switching converter provides a regulated supply voltage at a supply node based on an input voltage received at an input node, the method comprising: Driving a high-side switch and a low-side switch of the power stage based on a control signal received from a phase controller, the high-side switch and the low-side switch being in series at a switching node, the high-side switch and the low-side switch being serially connected between the input node and a ground terminal provided with a constant reference potential, wherein an inductor is coupled between the switching node and the supply node; Wherein when the control signal switches between the first logic level and the second logic level, ringing occurs at the ground terminal and the ringing stabilizes after a stabilization time; and Form a delayed version of the control signal, where the delayed version is generated by delaying the control signal by a first delay, and the time magnitude of the first delay is greater than the stabilization time of the ringing; Capture multiple faults as corresponding multiple deviation signals; Sense the multiple deviation signals according to the delayed version of the control signal to generate the multiple fault signals; and Transmit the multiple fault signals to the phase controller to take any necessary corrective measures.

18. The method according to claim 17, wherein Where the ringing also occurs at the input node and is stabilized by the stabilization time of the corresponding amplitude.

19. The method according to claim 17, wherein Where the time magnitude of the first delay is equal to the sum of (i) and (ii), where (i) is the duration from the transition of the control signal between the second logic level and the first logic level to the start of the change in voltage at the switching node in response to the transition, and (ii) is the stabilization time.

20. The method according to claim 19, wherein Where the control signal periodically switches between the first logic level and the second logic level within a first duration, and the control signal does not switch logic levels within a second duration, Where, within the first duration, the step of sensing the multiple deviation signals to generate the multiple fault signals includes synchronously storing the multiple fault signals along with the corresponding sampling of the delayed version in a storage element, Where, within the second duration, the step of sensing the multiple deviation signals to generate the multiple fault signals includes asynchronously storing the multiple fault signals in the storage element, The method further includes: Debounce the multiple fault signals to generate corresponding multiple debounced fault signals, Where the debouncing includes: Latch each fault signal in the multiple fault signals at a first time point to generate a first latched value and latch each fault signal in the multiple fault signals at a second time point after the first time instance to generate a second latched value; Check whether the first latched value is the same as the second latched value; If it is determined that the first latched value is the same as the second latched value, generate a debounced fault signal corresponding to each fault signal, and the logic level of the debounced fault signal is the same as the logic level of each fault signal, If it is determined that the first latched value is different from the second latched value, generate a debounced fault signal corresponding to each fault signal and having a logic low level; and Serialize the multiple debounced fault signals for transmission.

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