Low current stress and global soft switching operation control method of direct current interconnection device

Abstract

The invention discloses a low-current stress and global soft switching operation control method for a direct-current interconnection device. The method comprises the following steps of: respectively dividing a front half period and a rear half period of a switching period into a first interval, a second interval, a third interval and a fourth interval; when the direct current interconnection device performs forward transmission, a first switch working mode is operated, so that the current of the inductor L is kept in a first state in a first interval, is kept in a second state in a third interval, and is kept at 0 in a second interval and a fourth interval; when the direct-current interconnection device reversely transmits, a second switch working mode is operated, and the current of the inductor L is kept in a second state in the first interval, kept in the first state in the third interval and kept at 0 in the second interval and the fourth interval; each of the first state and the second state divides an interval into three sub-intervals to form an isosceles trapezoid wave; and in the first switch working mode and the second switch working mode, the turn-off and turn-on of the IGBT tube and the turn-on of the MOSFET tube are completed in the second interval or the fourth interval.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic conversion, and particularly to a control method for low current stress and full-range soft-switching operation of a DC interconnection device. Background Art

[0002] With the wide access of DC power sources and loads such as distributed photovoltaic power generation and electric vehicles to the distribution network, the energy transmission efficiency between DCs in the power system has gradually become a research hotspot. As the bearer of electrical isolation and DC voltage conversion functions, the isolated bidirectional DC interconnection device plays an irreplaceable role in the AC-DC hybrid distribution network.

[0003] On the one hand, under the traditional single-phase-shift control method, the DC interconnection device has problems such as a narrow soft-switching range and high current stress, making it difficult to achieve efficient power transmission within the full load range. In response to the above problems, extended phase-shift control methods, dual moving control methods, triple phase-shift control methods, and hybrid multiple control methods have emerged in existing research. In the extended phase-shift control method and the dual moving control method, the working modes of the DC interconnection device are mainly analyzed, and an attempt is made to reduce the current stress by finding a suitable phase-shift ratio to improve the transmission efficiency. However, the method of finding a suitable phase-shift ratio to reduce the current stress will bring difficulties in realizing full-range soft switching. In the triple phase-shift control method and the hybrid multiple control method, by introducing multiple control variables to generate more working modes, the purpose of reducing the current stress and broadening the soft-switching range is achieved. However, too many control variables greatly increase the control difficulty and require more stringent controller performance. On the other hand, when facing application scenarios with large input voltage fluctuations such as photovoltaic power generation and underground operations, it is also necessary to focus on allowing the input voltage to fluctuate within a certain range while maintaining the original performance of the DC interconnection device.

[0004] Therefore, there is an urgent need for a new technical solution to solve the technical problem of how to control the DC interconnection device to achieve efficient DC transmission with full-range soft switching and low current stress. Summary of the Invention

[0005] The present invention provides a control method for low current stress and full-range soft-switching operation of a DC interconnection device to solve the technical problem of how to control the DC interconnection device to achieve efficient DC transmission with full-range soft switching and low current stress.

[0006] To achieve the above object, the present invention provides a control method for low current stress and full-range soft-switching operation of a DC interconnection device, including: Dividing the first half cycle and the second half cycle of a switching period into a first interval, a second interval, a third interval, and a fourth interval respectively; When the DC interconnection device transmits in the forward direction, operate the first switch mode, so that the current of the inductor L remains in the first state in the first interval, in the second state in the third interval, and remains 0 in the second and fourth intervals; when the DC interconnection device transmits in the reverse direction, operate the second switch mode, so that the current of the inductor L remains in the second state in the first interval, in the first state in the third interval, and remains 0 in the second and fourth intervals; Both the first state and the second state divide the corresponding interval into a first sub-interval, a second sub-interval, and a third sub-interval to form an isosceles trapezoidal wave; in the first state, the isosceles trapezoidal wave sequentially maintains an increase starting from 0, being stable, and gradually decreasing to 0 in the first sub-interval, the second sub-interval, and the third sub-interval; in the second state, the isosceles trapezoidal wave sequentially maintains a decrease starting from 0, being stable, and gradually increasing to 0 in the first sub-interval, the second sub-interval, and the third sub-interval; In the first switch mode and the second switch mode, all the switching tubes and IGBT switching tubes of the output side bridge arm Q 1 and Q 2 are turned off and on, and the MOSFET switching tubes Q 3, Q 4, Q 5 and Q 6 are all turned on within the second interval or the fourth interval.

[0007] Preferably, it further includes: In the first switch mode and the second switch mode, by controlling the turn-on and turn-off moments of the switching tubes Q 3, Q 4, Q 5 and Q 6, the duration division of the first sub-interval, the second sub-interval, and the third sub-interval is further controlled; Controlling the turn-on and turn-off moments of the switching tubes Q 3, Q 4, Q 5 and Q 6 includes: When the DC interconnection device operates in the first switch mode, obtain the output voltage of the DC interconnection device V o ; after subtracting the output voltage V o from the preset output voltage reference value and passing it through a PI regulator to obtain the duty cycle D 1; generate the drive signals D 1 according to the duty cycle T 15 and T 16 , and according to the drive signals T 15 and T16 Drive the switching tubes separately Q 5 and Q 6; Delay the driving signals T 15 and T 16 by 180° respectively to obtain the driving signals T 13 and T 14 . Drive the switching tubes T 13 and T 14 separately according to the driving signals Q 3 and Q 4; When the DC interconnection device operates in the second switching mode, obtain the input voltage of the DC interconnection device V in ; Subtract the preset input voltage reference value from the input voltage V in and pass it through a PI regulator to obtain the duty cycle D 2; Generate driving signals D 2 according to the duty cycle T 23 and T 24 . Drive the switching tubes T 23 and T 24 separately according to the driving signals Q 3 and Q 4; Delay the driving signals T 23 and T 24 by 180° respectively to obtain the driving signals T 25 and T 26 . Drive the switching tubes T 25 and T 26 separately according to the driving signals Q 5 and Q 6.

[0008] Preferably, the first switching mode includes: The switching tube Q 1 is turned on at the beginning of the first interval and turned off at the end of the second interval; The switching tube Q 2 is turned on at the beginning of the third interval and turned off at the end of the fourth interval; The switching tube Q 6 is turned on at the beginning of the first sub-interval of the first interval and turned off at the end; The switching tubeQ turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; switching transistor Q turns on at the start of the first sub - interval of the third interval and turns off at the end; switching transistor Q turns on at the start of the first sub - interval of the third interval and turns off at the end of the second sub - interval of the third interval; During the entire switching cycle, the IGBT switching transistor S 5 remains on, and the IGBT switching transistor S 1 , S 2 , S 3 and S 4 all remain off.

[0009] Preferably, the second switching operation mode includes: switching transistor Q 1, S 1 and S 4 turn on at the start of the first interval and turn off at the end of the second interval; switching transistor Q 2, S 2 and S 3 turn on at the start of the third interval and turn off at the end of the fourth interval; switching transistor Q 3 turns on at the start of the first sub - interval of the first interval and turns off at the end; switching transistor Q 4 turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; switching transistor Q 6 turns on at the start of the first sub - interval of the third interval and turns off at the end; switching transistor Q 5 turns on at the start of the first sub - interval of the third interval and turns off at the end of the second sub - interval of the third interval; During the entire switching cycle, the switching transistor S 5 remains off.

[0010] Preferably, it further includes: When the DC interconnection device operates in the first switch working mode or the second switch working mode, by controlling the on or off of the switching tubes in the DC interconnection device, the voltage change of the inductor L is controlled, so that the voltage of the inductor L remains at a first positive value, 0, and a first negative value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the first state, and remains at a first negative value, 0, and a first positive value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the second state, thereby controlling the current of the inductor L to form an isosceles trapezoidal wave in the first state and the second state.

[0011] Preferably, it further includes: The first positive value The calculation formula can be expressed as: ; Then, in the first sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Represents the input voltage of the DC interconnection device; Represents the output voltage of the DC interconnection device; Represents the main transformer turns ratio; Represents the auxiliary transformer turns ratio; Represents the inductance value; Represents the real-time time; Represents the start time of the first sub-interval; When the voltage of the inductor L is 0, the voltage of the inductor L The calculation formula can be expressed as: ; Then, in the second sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Represents the start time of the second sub-interval; Represents the current of the inductor L at the start time of the second sub-interval; The first negative value The calculation formula can be expressed as: ; Then, in the third sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Represents the start time of the third sub-interval; Represents the current of inductor L at the start time of the third sub-interval.

[0012] Preferably, it further includes: The waveform of the current of inductor L changing with time in the first sub-interval divided in the second state Is expressed as: ; Wherein, Represents the current value of the waveform Within the waveform The current value is stable and unchanged; The waveform of the current of inductor L changing with time in the second sub-interval divided in the second state Is expressed as: ; The waveform of the current of inductor L changing with time in the third sub-interval divided in the second state Is expressed as: .

[0013] Preferably, it further includes: In the DC interconnection device, the opposite ends of the secondary side of the main transformer are connected to the same ends of the secondary side of the auxiliary transformer, then there is a proportional relationship between the current of inductor L and the input current of the auxiliary transformer; The proportional relationship is determined by the turns ratio of the main transformer and the auxiliary transformer, including: If the turns ratios of the main transformer and the auxiliary transformer are 1: N 1 and 1: N 2, then the current of inductor L And the input current of the auxiliary transformer The proportional relationship existing between them is: ; That is, the current i 2 transmitted by the auxiliary transformer forms an isosceles trapezoidal wave proportional to the isosceles trapezoidal wave of the current of inductor L in the first interval and the third interval.

[0014] Preferably, it further includes: When the input voltage transmitted in the forward direction of the DC interconnection device exceeds the preset range, control the switching tubes Q 5 and Q 6 to start and turn off simultaneously, and the switching tubes Q 3 and QStart and turn off simultaneously, so that the current of inductor L remains in the third state in the first interval, in the fourth state in the third interval, and is 0 in the second and fourth intervals; both the third state and the fourth state divide the corresponding interval into a fourth sub-interval and a fifth sub-interval to form a triangular wave; in the third state, the triangular wave successively increases from 0 and then gradually decreases to 0 in the fourth sub-interval and the fifth sub-interval; in the fourth state, the triangular wave successively decreases from 0 and then gradually increases to 0 in the fourth sub-interval and the fifth sub-interval.

[0015] The present invention has the following beneficial effects: For the low current stress and full-range soft-switching operation control method of the DC interconnection device of the present invention, by dividing a switching period into a first interval and a second interval and a third interval and a fourth interval for the first and second half-cycles respectively, and forming an isosceles trapezoidal wave of inductor current in the first and third intervals. By optimizing the current waveform into an isosceles trapezoidal wave, the method of the present invention can greatly reduce the current stress, thereby improving the transmission efficiency of the DC interconnection device. By keeping the inductor current at 0 in the second and fourth intervals, and controlling the turning-off and turning-on of all switching tubes and IGBT switching tubes Q 1 and Q 2, and the turning-on of MOSFET switching tubes Q 3, Q 4, Q 5 and Q 6 are all completed in the second interval or the fourth interval, so that the method of the present invention realizes full-range soft-switching, eliminates the switching loss during the operation of the DC interconnection device, and further improves the transmission efficiency of the DC interconnection device.

[0016] In addition to the purposes, features and advantages described above, the present invention has other purposes, features and advantages. The following will refer to the accompanying drawings to further elaborate on the present invention in detail. Description of the Drawings

[0017] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings: Figure 1 is a schematic diagram of the DC interconnection device of the preferred embodiment of the present invention.

[0018] Figure 2 is a schematic diagram of the method flow of the preferred embodiment of the present invention.

[0019] Figure 3 is a schematic diagram of the positive half-cycle working mode path when the DC interconnection device of the preferred embodiment of the present invention is transmitting in the forward direction.

[0020] Figure 4 It is the current flow diagram of working modes 1 to 4 in the forward transmission of the preferred embodiment of the present invention. Figure 4 (a) is the current flow diagram of working mode 1 in the forward transmission; Figure 4 (b) is the current flow diagram of working mode 2 in the forward transmission; Figure 4 (c) is the current flow diagram of working mode 3 in the forward transmission; Figure 4 (d) is the current flow diagram of working mode 4 in the forward transmission.

[0021] Figure 5 It is the schematic diagram of the working mode path in the positive half cycle during the reverse transmission of the DC interconnection device in the preferred embodiment of the present invention.

[0022] Figure 6 It is the schematic diagram of the current flow diagram of working modes 1 to 4 in the reverse transmission of the preferred embodiment of the present invention. Figure 6 (a) is the current flow diagram of working mode 1 in the reverse transmission; Figure 6 (b) is the current flow diagram of working mode 2 in the reverse transmission; Figure 6 (c) is the current flow diagram of working mode 3 in the reverse transmission; Figure 6 (d) is the current flow diagram of working mode 4 in the reverse transmission.

[0023] Figure 7 It is the schematic diagram of the simulation results of the forward transmission of the preferred embodiment of the present invention and the voltage and current waveforms of each device. Figure 7 (a) is the waveform diagram of the controlled output voltage in the forward transmission; Figure 7 (b) is the waveform diagram of the input current of the main transformer in the forward transmission; Figure 7 (c) is the waveform diagram of the input current of the auxiliary transformer in the forward transmission; Figure 7 (d) is the switching transistor in the forward transmission Q The voltage and current waveform diagram between the collector and emitter of 1; Figure 7 (e) is the switching transistor in the forward transmission Q The voltage and current waveform diagram of the drain-source of 5; Figure 7 (f) is the switching transistor in the forward transmission Q The voltage and current waveform diagram of the drain-source of 6; Figure 7 (g) is the switching transistor in the forward transmission S The voltage and current waveform diagram across the anti-parallel diode of 1.

[0024] Figure 8 It is the schematic diagram of the simulation results of the reverse transmission of the preferred embodiment of the present invention and the voltage and current waveforms of each device. Figure 8 (a) is the waveform diagram of the controlled output voltage in the reverse transmission; Figure 8 (b) is the waveform diagram of the input current of the main transformer in the reverse transmission; Figure 8(c) is the waveform diagram of the input current of the auxiliary transformer in the reverse transmission; Figure 8 (d) is the switch tube in the reverse transmission Q The voltage and current waveform diagram between the collector and emitter of 1; Figure 8 (e) is the switch tube in the reverse transmission Q The voltage and current waveform diagram of the drain-source of 3; Figure 8 (f) is the switch tube in the reverse transmission Q The voltage and current waveform diagram of the drain-source of 4; Figure 8 (g) is the switch tube in the reverse transmission S The voltage and current waveform diagram between the collector and emitter of 1. Specific embodiments

[0025] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways defined and covered by the claims.

[0026] See Figure 1 , the DC interconnection device of the present invention includes an input-side bridge arm, a transformer bank, and an output-side bridge arm.

[0027] The input-side bridge arm includes: Input capacitor C The negative electrode of 1 is connected to the C The positive node of 2 is connected to the diode D r1 , D r2 Node; input capacitor C The positive electrode of 1 is connected to the collector node of the main power bridge arm IGBT Q 1 is connected to the drain of the MOSFET Q 3, the negative electrode of the input capacitor C 2 is connected to the emitter node of the main power bridge arm IGBT Q 2 is connected to the source of the MOSFET Q 6; capacitor C The positive electrode of 3 is connected to the diode D r1 The cathode node is connected to the MOSFET Q 4 drain, capacitor C The negative electrode of 3 is connected to the diode D r2 The anode node is connected to the MOSFET Q 6 drain; the emitter of the IGBT Q 1 is connected to the collector node of the IGBT Q 2 ( Figure 1 Point A in) is connected to the auxiliary transformer T r2 Homonymous end, diode D r1 The anode is connected toD r2 The cathode node ( Figure 1 point B) is connected to the primary side of the main transformer T r1 at the opposite-named terminal, and the source electrode of MOSFET Q 4 is connected to the drain electrode of MOSFET Q 5 at the opposite-named terminal of the auxiliary transformer T r2 at the opposite-named terminal; the MOSFETs of the auxiliary power bridge arm Q 3, Q 4, Q 5, Q 6 are connected in sequence between the source and drain electrodes.

[0028] The transformer bank includes: The main transformer T r1 at the same-named terminal of the primary side is connected to one end of the inductor L ; T r1 at the opposite-named terminal of the primary side is connected to the negative electrode of the input capacitor C 1 and C the positive electrode node of 2; the primary side of the auxiliary transformer T r2 at the same-named terminal is connected to L the other end and is connected to the emitter of the main power bridge arm Q 1 and Q the collector node of 2; the source electrode of the auxiliary power bridge arm Q 4 is connected to Q the drain node of 5 ( Figure 1 point C) T r2 at the opposite-named terminal of the primary side; T r1 at the opposite-named terminal of the secondary side is connected to T r2 the same-named terminal of the secondary side. The turns ratios of the main transformer and the auxiliary transformer are 1: N 1 and 1: N 2 respectively.

[0029] The output side bridge arm includes: The output side bridge arm adopts an H5 inverter bridge structure and a diode full bridge structure, specifically including: the switch tube S 1's emitter and the switch tube S 2's collector node are connected to the T r1 same-named terminal of the secondary side of the main transformer through an inductor, and the switch tube S 3's emitter and the switch tube S 4's collector node are connected to the T r2 opposite-named terminal of the secondary side of the auxiliary transformer through an inductor; the diode Dr3 Anode and diode D r4 Cathode node and main transformer T r1 The same-named ends of the secondary sides are connected, and the diode D r5 Anode and diode D r6 Cathode node and auxiliary transformer T r2 The different-named ends of the secondary sides are connected; the switching tube S 1, S The collector node of 3 and the diode D r3 , D r5 The cathode nodes are all connected to S The collector of 5, S The emitter of 5 is connected to the positive electrode of the output capacitor C o The switching tube S 2, S The emitter node of 4 and the diode D r4 , D r6 The anode nodes are all connected to the negative electrode of the output capacitor C o The switching tube S 1 , S 2 , S 3 , S 4 And S 5 Are all IGBT switching tubes.

[0030] In Figure 1 , V in Represents the input voltage; i in Represents the input current; i 1 represents the current of the inductor L ; i 2 represents the current of the auxiliary transformer; i o Represents the output current; V o Represents the output voltage.

[0031] Embodiment 1: Refer to Figure 2 , in the preferred embodiment of the present invention, a low current stress and full-range soft-switching operation control method for a DC interconnection device is provided, including: Divide the first and second half-cycles of a switching period into a first interval, a second interval, a third interval, and a fourth interval respectively; When the DC interconnection device transmits in the forward direction, operate the first switching mode, so that the current of inductor L maintains the first state in the first interval, the second state in the third interval, and is 0 in the second and fourth intervals; when the DC interconnection device transmits in the reverse direction, operate the second switching mode, so that the current of inductor L maintains the second state in the first interval, the first state in the third interval, and is 0 in the second and fourth intervals; Both the first state and the second state divide the corresponding interval into a first sub-interval, a second sub-interval, and a third sub-interval to form an isosceles trapezoidal wave; in the first state, the isosceles trapezoidal wave sequentially maintains increasing from 0, being stable, and gradually decreasing to 0 in the first sub-interval, the second sub-interval, and the third sub-interval; in the second state, the isosceles trapezoidal wave sequentially maintains decreasing from 0, being stable, and gradually increasing to 0 in the first sub-interval, the second sub-interval, and the third sub-interval; In the first switching mode and the second switching mode, all the switching tubes and IGBT switching tubes of the output side bridge arm Q 1 and Q 2 are turned off and on, and the MOSFET switching tubes Q 3, Q 4, Q 5 and Q 6 are turned on within the second interval or the fourth interval.

[0032] In a preferred embodiment of the present invention, it further includes a method for determining the duty ratios of the switching tubes Q 3, Q 4, Q 5 and Q 6: In the first switching mode and the second switching mode, by controlling the turn-on and turn-off moments of the switching tubes Q 3, Q 4, Q 5 and Q 6, the duration division of the first sub-interval, the second sub-interval, and the third sub-interval is further controlled; Controlling the turn-on and turn-off moments of the switching tubes Q 3, Q 4, Q 5 and Q 6 includes: When the DC interconnection device operates in the first switching mode, obtain the output voltage of the DC interconnection device V o ; after subtracting the output voltage V o from the preset output voltage reference value and passing it through a PI regulator to obtain the duty ratio D1; Generate a drive signal according to the duty cycle D 1 T 15 and T 16 , and drive the switching transistors T 15 and T 16 respectively according to the drive signals Q 5 and Q 6; Lag the drive signals T 15 and T 16 by 180° respectively to obtain drive signals T 13 and T 14 , and drive the switching transistors T 13 and T 14 respectively according to the drive signals Q 3 and Q 4; When the DC interconnection device operates in the second switching mode, obtain the input voltage of the DC interconnection device V in ; Subtract the preset input voltage reference value from the input voltage V in and pass the result through a PI regulator to obtain the duty cycle D 2; Generate a drive signal according to the duty cycle D 2 T 23 and T 24 , and drive the switching transistors T 23 and T 24 respectively according to the drive signals Q 3 and Q 4; Lag the drive signals T 23 and T 24 by 180° respectively to obtain drive signals T 25 and T 26 , and drive the switching transistors T 25 and T 26 respectively according to the drive signals Q 5 and Q 6.

[0033] In a preferred embodiment of the present invention, the first switching mode includes: Switching transistor Q 1 turns on at the start of the first interval and turns off at the end of the second interval; the switching transistor Q 2 turns on at the start of the third interval and turns off at the end of the fourth interval; Switching transistor Q 6 turns on at the start of the first sub - interval of the first interval and turns off at the end; the switching transistor Q 5 turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; Switching transistor Q 3 turns on at the start of the first sub - interval of the third interval and turns off at the end; the switching transistor Q 4 turns on at the start of the first sub - interval of the third interval and turns off at the end of the second sub - interval of the third interval; During the entire switching cycle, the IGBT switching transistor S 5 remains on, and the IGBT switching transistors S 1 , S 2 , S 3 and S 4 all remain off.

[0034] In the preferred embodiment of the present invention, the second switching mode includes: Switching transistors Q 1, S 1 and S 4 turn on at the start of the first interval and turn off at the end of the second interval; switching transistors Q 2, S 2 and S 3 turn on at the start of the third interval and turn off at the end of the fourth interval; Switching transistor Q 3 turns on at the start of the first sub - interval of the first interval and turns off at the end; switching transistor Q 4 turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; Switching transistor Q 6 turns on at the start of the first sub - interval of the third interval and turns off at the end; switching transistor Q 5 turns on at the start of the first sub - interval of the third interval and turns off at the end of the second sub - interval of the third interval; During the entire switching cycle, the switching transistor S 5 remains off.

[0035] In a preferred embodiment of the present invention, it further includes: When the DC interconnection device operates in the first switch operating mode or the second switch operating mode, by controlling the on or off of the switching tubes in the DC interconnection device, the voltage change of the inductor L is controlled, so that the voltage of the inductor L sequentially maintains a first positive value, 0, and a first negative value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the first state, and sequentially maintains a first negative value, 0, and a first positive value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the second state, thereby controlling the current of the inductor L to form an isosceles trapezoidal wave in the first state and the second state.

[0036] In a preferred embodiment of the present invention, it further includes: The first positive value The calculation formula can be expressed as: ; Then, in the first sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Represents the input voltage of the DC interconnection device; Represents the output voltage of the DC interconnection device; Represents the main transformer turns ratio; Represents the auxiliary transformer turns ratio; Represents the inductance value; Represents the real-time time; Represents the start time of the first sub-interval; When the voltage of the inductor L is 0, the voltage of the inductor L The calculation formula can be expressed as: ; Then, in the second sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Represents the start moment of the second sub-interval; Represents the current of the inductor L at the start moment of the second sub-interval; The first negative value The calculation formula can be expressed as: ; Then, in the third sub-interval divided by the first state, the waveform of the current of the inductor L changing with time Is expressed as: ; Wherein, Indicates the start time of the third sub-interval; Indicates the current of inductor L at the start time of the third sub-interval.

[0037] In a preferred embodiment of the present invention, it further includes: The waveform of the current of inductor L changing with time in the first sub-interval divided in the second state Is expressed as: ; Wherein, M Indicates the current value of the waveform Within the waveform The current value is stable and unchanged; The waveform of the current of inductor L changing with time in the second sub-interval divided in the second state Is expressed as: ; The waveform of the current of inductor L changing with time in the third sub-interval divided in the second state Is expressed as: ; In a preferred embodiment of the present invention, it further includes: In the DC interconnection device, if the opposite ends of the secondary side of the main transformer are connected to the same ends of the secondary side of the auxiliary transformer, there is a proportional relationship between the current of inductor L and the input current of the auxiliary transformer; The proportional relationship is determined by the turns ratio of the main transformer and the auxiliary transformer, including: If the turns ratios of the main transformer and the auxiliary transformer are 1: N 1 and 1: N 2, then the current of inductor L And the input current of the auxiliary transformer The proportional relationship existing between them is: ; That is, the current Transmitted by the auxiliary transformer forms an isosceles trapezoidal wave proportional to the isosceles trapezoidal wave of the current of inductor L in the first interval and the third interval.

[0038] In a preferred embodiment of the present invention, it further includes: When the input voltage transmitted in the forward direction of the DC interconnection device exceeds the preset range, control the switching tubes Q 5 and Q 6 to start and turn off simultaneously, and the switching tubes Q 3 and QStart and turn off simultaneously, so that the current of inductor L remains in the third state in the first interval, in the fourth state in the third interval, and is 0 in the second and fourth intervals; both the third state and the fourth state divide the corresponding interval into a fourth sub-interval and a fifth sub-interval to form a triangular wave; in the third state, the triangular wave increases from 0 and then gradually decreases to 0 in the fourth sub-interval and the fifth sub-interval in sequence; in the fourth state, the triangular wave decreases from 0 and then gradually increases to 0 in the fourth sub-interval and the fifth sub-interval in sequence.

[0039] The low-current stress and full-range soft-switching operation control method of the DC interconnection device of the present invention divides the front and back half-cycles of a switching period into a first interval and a second interval and a third interval and a fourth interval respectively, and forms an isosceles trapezoidal wave of inductor current in the first and third intervals. By optimizing the current waveform into an isosceles trapezoidal wave, the method of the present invention can greatly reduce the current stress, thereby improving the transmission efficiency of the DC interconnection device. By keeping the inductor current at 0 in the second and fourth intervals and controlling all the switching tubes and IGBT switching tubes of the output side bridge arm Q 1 and Q 2 to turn off and on, and the MOSFET switching tubes Q 3, Q 4, Q 5 and Q 6 are all turned on within the second interval or the fourth interval, so that the method of the present invention realizes full-range soft switching, completely eliminates the switching loss during the operation of the DC interconnection device, and further improves the transmission efficiency of the DC interconnection device.

[0040] Embodiment 2: In a preferred embodiment of the present invention, the DC interconnection device controlled based on the method of the present invention is analyzed: 1. When the DC interconnection device performs forward energy transmission: When the energy flows forward, the primary switching tubes Q 1, Q 2 are alternately turned on with a duty cycle of 50% respectively, Q 3 to Q 6 are alternately turned on according to the duty cycles of the switching tubes Q 3, Q 4, Q 5 and Q 6 determined above. The secondary switching tube S 5 is always in the on state, and the switching tubes S 1 to S 4 are all in the off state, and their anti-parallel diodes and the full-bridge diodes jointly transmit energy.

[0041] Considering that the operation modes of the DC interconnection device have high symmetry, seeFigure 3 , taking the positive half-cycle working mode path as an example for analysis, and the negative half-cycle is the same.

[0042] (1) Working mode 1 t 0, t 1]: t At 0 moment, as the starting point of a switching cycle, the switch Q 2 turns off, Q 1, Q 5, Q 6 turn on. From the Figure 3 given current waveform, it can be seen that t no current flows before 0 moment. The switches Q 1, Q 5, Q 6 achieve zero-current (Zero-Current-Switching, ZCS) turn-on, Q 2 achieves ZCS turn-off.

[0043] The current flow diagram of working mode 1 is as shown in Figure 4 (a). The inductor current increases linearly from zero and reaches the steady-state value at t 1 moment. At the same time, the secondary-side switch S 1, S 4 anti-parallel diodes and the diode D r3 , D r6 turn on. The turns ratios of the main and auxiliary transformers are 1: N 1 and 1: N 2 respectively. The output voltage is V o . The primary voltage of the main transformer is V AB = V in / 2, and the primary voltage of the auxiliary transformer is V BC = V in . Its corresponding secondary voltage is N 2 V in . Therefore, the secondary voltage of the main transformer is V o - N 2 V in .

[0044] (2) Working mode 2 t 1, t 2]: At t 1 moment, the switch Q 6 turns off, and the current i2 is Q 6 drain-source capacitance is charged. When Q 6 drain-source capacitance is charged to V in / 2, the charging process ends, and the current i 2 passes through the switching transistor Q 5 and the diode D r2 for freewheeling. Since Q 6 turns off at the peak of the current i 2, the process time for charging the drain-source capacitance of Q 6 can be ignored. Because the capacitance voltage cannot change abruptly, the switching transistor Q 6 can achieve zero-voltage (Zero-Voltage -Switching, ZVS) turn-off.

[0045] The current flow diagram of operating mode 2 is as shown in Figure 4 (b). The primary voltage of the main transformer is V in / 2, and the primary voltage of the auxiliary transformer is V in / 2, and its corresponding secondary voltage is N 2 V in / 2. Therefore, the secondary voltage of the main transformer is V o - N 2 V in / 2.

[0046] (3) Operating mode 3 t 2,[[]] t 3]: At t 2 time, the switching transistor Q 5 turns off, and the current i 2 is Q charging the drain-source capacitance of Q 5. When V in the drain-source capacitance of 5 is charged to i / 2, the charging process ends, and the current Q 2 passes through the diodes connected in anti-parallel of the switching transistors Q 3 and Q 4 to conduct freewheeling. Since i 5 turns off at the peak of the current Q 2, the process time for charging the drain-source capacitance of Q 5 can be ignored. Because the capacitance voltage cannot change abruptly, the switching transistor

[0047] The current flow diagram of operating mode 3 is as shown in Figure 4 (c), and the primary voltage of the main transformer isV in / 2, the primary voltage of the auxiliary transformer is 0, so the secondary voltage of the main transformer is V o .

[0048] (4) Operating mode 4 t 3, t 4]: The current path in operating mode 4 is as shown in Figure 4 (d). At t time 3, the inductor current drops to zero, S 1, S 4 anti-parallel diodes and diode D r3 , D r6 naturally turn off. From t time 3 to t time 4, only switch Q 1 and S 5 are conducting. t At Q time 4, switches Q 2, Q 3, Q 4 turn on, switch t 1 turns off. Since the circuit current is zero before Q time 4, switch Q 1 also achieves ZCS turn-off, Q 2, Q 3,

[0049] II. When the DC interconnection device performs energy reverse transmission: When the energy flows reversely, the primary Q 1, Q 2 conduct alternately with a duty cycle of 50%. From Q time 3 to Q time 6, switches Q 3, Q 4, Q 5 and Q 6 conduct alternately according to the duty cycles of switches Q 6 determined above. Different from when the forward current starts, when the reverse current starts, Q 3 conducts first. The secondary S 5 switch is always in the off state. Switches S 1, S 4, S 2, S 3 are respectively in the same switch state as switches Q 1, Q 2 and conduct alternately with a duty cycle of 50%.

[0050] Considering that the operation modes of the DC interconnection device have a high degree of symmetry, refer to Figure 5 , and take the positive half-cycle operation mode path as an example for analysis. The negative half-cycle is the same.

[0051] (1) Operation mode 1 t 0, t 1]: t At the moment of 0, as the starting point of a switching cycle, the switch Q 2 is turned off, Q 1, Q 3, Q 4 are turned on. From the current waveform given by Figure 5 , it can be seen that there is no current flowing before the moment of 0. The switches t 0, Q 1, Q 3, Q 4 achieve ZCS turn-on, Q 2 achieves ZCS turn-off.

[0052] The current flow diagram of operation mode 1 is as shown in Figure 6 (a). The inductor current linearly decreases from zero and reaches the steady-state value at t 1. At the same time, the secondary-side switch S 1, S 4 are turned on. The primary-side voltage of the main transformer V AB = V in / 2, and the primary-side voltage of the auxiliary transformer V BC = 0. Therefore, the secondary-side voltage of the main transformer is V o .

[0053] (2) Operation mode 2 t 1, t 2]: At t 1, the switch Q 3 is turned off, and the current i 2 charges the drain-source capacitance of Q 3. When the drain-source capacitance of Q 3 is charged to V in / 2, the charging process ends, and the current i 2 continues to flow through the switch Q 4 and the diode D r1 . Since Q 3 is turned off at the peak value of the current i 2, the process time for charging the drain-source capacitance of Q 3 can be ignored. Because the capacitance voltage cannot change suddenly, the switchQ ZVS turn-off can be achieved.

[0054] The current flow diagram of operating mode 2 is as shown in Figure 6 (b). The primary voltage of the main transformer is V in / 2, and the primary voltage of the auxiliary transformer is V in / 2. The corresponding secondary voltage is N 2 V in / 2. Therefore, the secondary voltage of the main transformer is V o - N 2 V in / 2.

[0055] (3) Operating mode 3 t 2, t 3]: At t time 2, the switch Q 4 turns off, and the current i 2 charges the drain-source capacitance of Q 4. When the drain-source capacitance of Q 4 is charged to V in / 2, the charging process ends, and the current i 2 continues to flow through the diode anti-parallel to the switch Q 5, Q 6. Since Q 4 turns off at the peak of the current i 2, the charging time of the drain-source capacitance of Q 4 can be ignored. Due to the fact that the capacitance voltage cannot change suddenly, the switch Q 4 can achieve ZVS turn-off.

[0056] The current flow diagram of operating mode 3 is as shown in Figure 6 (c). The primary voltage of the main transformer is V in / 2, and the primary voltage of the auxiliary transformer is V in , so the secondary voltage of the main transformer is V o - N 2 V in .

[0057] (4) Operating mode 4 t 3, t 4]: The current path in operating mode 4 is as shown in Figure 6 (d). At t time 3, the inductor current rises to zero, and at this time the switchQ 3. Q The anti-parallel diodes of 4 can all achieve natural turn-off. t From 3 to t 4, only Q 1 and S 1, S 4 switch tubes are conducting. t At 4, the primary-side switch tubes Q 2, Q 5, Q 6 turn on, the switch tube Q 1 turns off, and the secondary-side switch tubes S 2, S 3 turn on. S 1, S 4 turn off. Since t the circuit current is zero before 4, the switch tubes Q 1, S 1, S 4 also achieve ZCS turn-off. Q 2, Q 5, Q 6, S 2, S 3 achieve ZCS turn-on.

[0058] In forward and reverse transmissions, the output current has the following expression: ; where represents the real-time current of inductor L.

[0059] In summary, in forward and reverse transmissions, Q 1, Q 2, S 1, S 2, S 3, S 4 can all achieve ZCS turn-on and turn-off. Q 3, Q 4 , Q 5, Q 6 can achieve ZVS and ZCS turn-on, and ZVS turn-off. In the energy forward flow mode, S 5 always remains on, and there is no current flowing through its anti-parallel diode; in the energy reverse flow mode, S 5 always remains off, and its anti-parallel diode can achieve natural turn-on and turn-off.

[0060] Verification part: To better prove the effectiveness of the method of the present invention, the following is verified in combination with simulation examples. According to Figure 1The topology of the DC interconnection device shown is used to build a simulation platform in MATLAB / Simulink, and the simulation parameters are shown in Table 1: ; I. Simulation Results of Forward Energy Transmission Figure 7 The simulation results of the forward energy transmission of the DC interconnection device and the voltage and current waveforms of each device are shown. The voltage-type control strategy is adopted in the simulation model of the DC interconnection device, and the output voltage is controlled by a closed loop. Among them, Figure 7 (a) shows the waveform of the controlled output voltage, Figure 7 (b) shows the waveform of the input current of the main transformer, Figure 7 (c) shows the waveform of the input current of the auxiliary transformer. From Figure 7 (a), it can be seen that the output voltage is well controlled, and the voltage magnitude fluctuates around 2000V, and the fluctuation amplitude does not exceed 20V; from Figure 7 (b), Figure 7 (c), it can be seen that the input currents of the main transformer and the auxiliary transformer show an intermittent state. It is the same as the theoretical analysis result, verifying the correctness of the theoretical analysis. At the same time, the magnitude of the input current of the auxiliary transformer is much smaller than that of the main transformer, which also verifies the design result that the main transformer transmits most of the power and the auxiliary transformer transmits a small part of the power.

[0061] Figure 7 (d), Figure 7 (e), Figure 7 (f), Figure 7 (g) show the voltage and current waveforms across each switch of the DC interconnection device in the forward energy flow mode. Among them, Figure 7 (d) shows the voltage and current between the collector and emitter of switch Q 1, Figure 7 (e), Figure 7 (f) respectively show the voltage and current of the drain-source of switches Q 5, Q 6, Figure 7 (g) shows the voltage and current of the anti-parallel diode of switch S 1.

[0062] From Figure 7 (d), it can be seen that before switch Q 1 conducts, the current flowing through it is zero, so switch Q 1 can achieve ZCS conduction. From Figure 7 (e), Figure 7 (f), it can be seen that before switches Q 5, Q 6 conduct, the current flowing through them is zero, so switchesQ 5、 Q 6 can achieve zero-current switching (ZCS) turn-on. As can be seen from Figure 7 (g), before the anti-parallel diode of switch S 1 turns on and off, the current flowing through it is zero, and there is no switching loss.

[0063] II. Simulation Results of Energy Reverse Transmission Figure 8 The simulation results showing the energy reverse transmission of the DC interconnection device are presented. In this simulation model, the voltage-source control strategy is also adopted, and the input voltage is controlled in a closed loop. Figure 8 (a) shows the waveform of the controlled input voltage. Figure 8 (b) shows the waveform of the input current of the main transformer. Figure 8 (c) shows the waveform of the input current of the auxiliary transformer. As can be seen from Figure 8 (a), the input voltage is well controlled, and its magnitude fluctuates around 800 V, with the fluctuation amplitude not exceeding 4 V. As can be seen from Figure 8 (b) and Figure 8 (c), the input currents of the main transformer and the auxiliary transformer are in a discontinuous state, which is consistent with the theoretical analysis results, verifying the correctness of the theoretical analysis.

[0064] Figure 8 The voltage and current waveforms across each switch of the DC interconnection device in the energy forward flow mode are shown. Among them, Figure 8 (d) shows the voltage and current between the collector and emitter of switch Q 1. Figure 8 (e) and Figure 8 (f) respectively show the voltage and current of the drain-source of switches Q 3 and Q 4. Figure 8 (g) shows the voltage and current between the collector and emitter of switch S 1.

[0065] As can be seen from Figure 8 (d), Figure 8 (e), Figure 8 (f), and Figure 8 (g), before switches Q 1, Q 3, Q 4, and S 1 turn on, the current flowing through them is zero. Therefore, switches Q 1, Q 3, Q 4, and S 1 can all achieve ZCS turn-on.

[0066] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A control method for low current stress and global soft-switching operation of a DC interconnection device, characterized in that Including: Dividing the first half cycle and the second half cycle of a switching period into a first interval, a second interval, a third interval, and a fourth interval respectively; When the DC interconnection device transmits in the forward direction, operate the first switch operating mode, so that the current of the inductor L remains in the first state in the first interval, remains in the second state in the third interval, and remains 0 in the second interval and the fourth interval; when the DC interconnection device transmits in the reverse direction, operate the second switch operating mode, so that the current of the inductor L remains in the second state in the first interval, remains in the first state in the third interval, and remains 0 in the second interval and the fourth interval; Both the first state and the second state divide the corresponding interval into a first sub-interval, a second sub-interval, and a third sub-interval to form an isosceles trapezoidal wave; in the first state, the isosceles trapezoidal wave increases from 0, remains stable, and gradually decreases to 0 in the first sub-interval, the second sub-interval, and the third sub-interval in sequence; in the second state, the isosceles trapezoidal wave decreases from 0, remains stable, and gradually increases to 0 in the first sub-interval, the second sub-interval, and the third sub-interval in sequence; In the first switch operating mode and the second switch operating mode, all the switching tubes and IGBT switching tubes of the output side bridge arm Q 1 and Q 2 are turned off and on, and the MOSFET switching tubes Q 3, Q 4, Q 5 and Q 6 are turned on within the second interval or the fourth interval.

2. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 1, characterized in that, Further including: In the first switch operating mode and the second switch operating mode, by controlling the switching tubes Q 3, Q 4, Q 5 and Q 6 to turn on and off, the duration division of the first sub-interval, the second sub-interval, and the third sub-interval is further controlled; The control switch tube Q 3、 Q 4、 Q 5 and Q the on and off times of 6 Including: When the DC interconnection device operates in the first switch working mode, obtain the output voltage of the DC interconnection device V o ; Subtract the output voltage V o from the preset output voltage reference value, and then obtain the duty cycle through a PI regulator D 1; According to the duty cycle D 1, generate drive signals T 15 and T 16 . According to the drive signals T 15 and T 16 , drive switch tubes Q 5 and Q 6 respectively; Delay the drive signals T 15 and T 16 by 180° respectively to obtain drive signals T 13 and T 14 . According to the drive signals T 13 and T 14 , drive switch tubes Q 3 and Q 4 respectively; When the DC interconnection device operates in the second switch working mode, obtain the input voltage of the DC interconnection device V in ; Subtract the preset input voltage reference value from the input voltage V in and then obtain the duty cycle through a PI regulator D 2; Generate drive signals D 2 according to the duty cycle T 23 and T 24 , and drive switch transistors T 23 and T 24 respectively according to the drive signals Q 3 and Q 4; Lag the drive signals T 23 and T 24 by 180° respectively to obtain drive signals T 25 and T 26 , and drive switch transistors T 25 and T 26 respectively according to the drive signals Q 5 and Q 6.

3. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 2, characterized in that, The first switch operating mode includes: Switching transistor Q 1 turns on at the start of the first interval and turns off at the end of the second interval; Switching transistor Q 2 turns on at the start of the third interval and turns off at the end of the fourth interval; Switching transistor Q 6 turns on at the start of the first sub - interval of the first interval and turns off at the end; Switching transistor Q 5 turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; Switching transistor Q 3 is turned on at the start and turned off at the end of the first sub-interval of the third interval; the switching transistor Q 4 is turned on at the start of the first sub-interval of the third interval and turned off at the end of the second sub-interval of the third interval; During the entire switching cycle, the IGBT switch S 5 remains on, and the IGBT switches S 1 , S 2 , S 3 and S 4 all remain off.

4. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 3, characterized in that The second switch operating mode includes: Switching transistor Q 1、 S 1 and S 4 Turn on at the start of the first interval and turn off at the end of the second interval; Switching transistor Q 2、 S 2 and S 3 Turn on at the start of the third interval and turn off at the end of the fourth interval; Switching transistor Q 3 turns on at the start and turns off at the end of the first sub - interval of the first interval; The switching transistor Q 4 turns on at the start of the first sub - interval of the first interval and turns off at the end of the second sub - interval of the first interval; Switching transistor Q 6 turns on at the start and turns off at the end of the first sub-interval of the third interval; Switching transistor Q 5 turns on at the start of the first sub-interval of the third interval and turns off at the end of the second sub-interval of the third interval; During the entire switching cycle, the switching device S 5 remains off.

5. The low-current stress and global soft-switching operation control method of the DC interconnection device according to claim 4, characterized in that Further including: When the DC interconnection device operates the first switch operating mode or the second switch operating mode, by controlling the on or off of the switch tube in the DC interconnection device, the voltage change of the inductor L is controlled, so that the voltage of the inductor L remains a first positive value, 0, and a first negative value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the first state in sequence, and remains a first negative value, 0, and a first positive value in the first sub-interval, the second sub-interval, and the third sub-interval divided by the second state in sequence, thereby controlling the current of the inductor L to form an isosceles trapezoidal wave in the first state and the second state.

6. The low-current stress and global soft-switching operation control method of the DC interconnection device according to claim 5, characterized in that, Further including: The first positive value can be expressed by the formula: ； Then, within the first sub-interval divided by the first state, the waveform of the current of the inductor L changing with time is expressed as: ； Among them, represents the input voltage of the DC interconnection device; represents the output voltage of the DC interconnection device; represents the turns ratio of the main transformer; represents the turns ratio of the auxiliary transformer; represents the inductance value; represents the real-time; represents the start time of the first sub-interval; When the voltage across the inductor L is 0, the voltage across the inductor L can be expressed by the following equation: ； Then, the waveform of the current of the inductor L changing with time within the second sub-interval divided by the first state is expressed as: ； Among them, represents the start time of the second sub-interval; represents the current of the inductor L at the start time of the second sub-interval; The first negative value can be expressed by the formula: ； Then, the waveform of the current of the inductor L changing with time within the third sub-interval divided by the first state is expressed as: ； Among them, represents the start time of the third sub-interval; represents the current of the inductor L at the start time of the third sub-interval.

7. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 6, characterized in that, Further including: Waveform of the current of inductor L varying with time in the first sub-interval divided in the second state It is expressed as: ； Among them, represents the current value of the waveform Within the waveform the current value remains stable and unchanged. The waveform of the current of inductor L changing with time in the second sub-interval divided in the second state It is expressed as: ； The waveform of the current of the inductor L changing with time in the third sub-interval divided in the second state It is expressed as: 。 8. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 7, characterized in that Further including: In the DC interconnection device, the opposite ends of the secondary side of the main transformer are connected to the same ends of the secondary side of the auxiliary transformer, then there is a proportional relationship between the current of the inductor L and the input current of the auxiliary transformer; The proportional relationship is determined by the turns ratio of the main transformer and the auxiliary transformer, including: If the turns ratios of the main transformer and the auxiliary transformer are 1: N 1 and 1: N 2 respectively, then the ratio between the current of the inductor L and the input current of the auxiliary transformer is as follows: ； That is, the current transmitted by the auxiliary transformer In the first interval and the third interval, an isosceles trapezoidal wave proportional to the isosceles trapezoidal wave of the current of the inductor L is formed.

9. The low current stress and global soft-switching operation control method of the DC interconnection device according to claim 8, characterized in that, Further including: When the input voltage transmitted in the forward direction by the DC interconnection device exceeds the preset range, control the switching tubes in the operating mode of the first switch Q 5 and Q 6 to start and turn off simultaneously, and control the switching tubes Q 3 and Q 4 to start and turn off simultaneously, so that the current of the inductor L maintains a third state in the first interval, a fourth state in the third interval, and remains 0 in the second interval and the fourth interval; both the third state and the fourth state divide the corresponding interval into a fourth sub-interval and a fifth sub-interval to form a triangular wave; in the third state, the triangular wave sequentially maintains increasing from 0 and then gradually decreasing to 0 in the fourth sub-interval and the fifth sub-interval; in the fourth state, the triangular wave sequentially maintains decreasing from 0 and then gradually increasing to 0 in the fourth sub-interval and the fifth sub-interval.

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