A multi-phase clock circuit and a multi-phase clock signal generating method

Abstract

The present disclosure provides a multi-phase clock circuit and a multi-phase clock signal generation method, which are applied to the field of integrated circuit technology. The multi-phase clock circuit includes: an injection switch control module configured to obtain an injection mode control signal representing a frequency injection ratio; an injection switch selection module configured to determine the injection phase of a four-phase injection clock signal according to the injection mode control signal; a buffer configured to input the four-phase injection clock signal into a ring oscillator according to the injection phase; the ring oscillator configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into a phase detector; the phase detector configured to extract phase deviation information from the N phase clock signals; and a frequency matching control module configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information. According to embodiments of the present disclosure, the frequency range of the clock signal can be widened.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a multi-phase clock circuit and a method for generating a multi-phase clock signal. Background Art

[0002] Injection-locked ring oscillators offer the advantage of multiple phases when generating clock signals. However, as the number of phases increases, the number of stages in the ring oscillator limits the clock frequency and performance, resulting in a smaller frequency range for the clock signal generated by the ring oscillator. Summary of the Invention

[0003] The present disclosure provides a multi-phase clock circuit and a multi-phase clock signal generating method.

[0004] In a first aspect, an embodiment of the present disclosure provides a multi-phase clock circuit, comprising: an injection switch control module, an injection switch selection module, a buffer, a four-phase injection N-stage output ring oscillator, a phase detector, and a frequency matching control module;

[0005] The injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal represents a frequency injection ratio of a four-phase injection clock signal;

[0006] The injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal;

[0007] a buffer configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase;

[0008] The ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal, and input the N phase clock signals into the phase detector;

[0009] The phase detector is configured to extract phase deviation information from the N phase clock signals;

[0010] The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal and the phase deviation information.

[0011] In a possible implementation manner, the value of the injection mode control signal is a positive odd number.

[0012] In a possible implementation, the frequency matching control module is configured to:

[0013] Before the buffer inputs the four-phase injection clock signal into the ring oscillator, the self-oscillation frequency of the ring oscillator is adjusted to a target frequency; the target frequency = the frequency of the four-phase injection clock signal / the value of the injection mode control signal;

[0014] After the buffer inputs the four-phase injection clock signal into the ring oscillator, negative feedback is used to eliminate the phase deviation information.

[0015] In a possible implementation, the phase detector is configured as follows:

[0016] Determine the phase detection sign bit according to the injection mode control signal;

[0017] determining a frequency deviation based on the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal, and the injection mode control signal;

[0018] The phase deviation information is determined according to the phase detection sign bit and the frequency deviation.

[0019] In a possible implementation, the value of the injection mode control signal is 2k-1; wherein k is a positive integer;

[0020] The last two bits of the binary code of k are a mode control word; the phase detection sign bit is determined according to the mode control word.

[0021] In a possible implementation, the four-phase injection clock signal includes a clock signal of a first phase, a clock signal of a second phase, a clock signal of a third phase, and a clock signal of a fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are in opposite phases, and the third phase and the fourth phase are in opposite phases; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0022] A first end of the first switch is used to access the clock signal of the first phase, and a second end is connected to the first injection node of the ring oscillator via a buffer;

[0023] A first end of the second switch is used to access the clock signal of the first phase, and a second end is connected to the second injection node of the ring oscillator via a buffer;

[0024] A first end of the third switch is used to access the second-phase clock signal, and a second end is connected to the first injection node of the ring oscillator via a buffer;

[0025] A first end of the fourth switch is used to access the second-phase clock signal, and a second end is connected to the second injection node of the ring oscillator via a buffer;

[0026] A first end of the fifth switch is used to access the clock signal of the third phase, and a second end is connected to the third injection node of the ring oscillator via a buffer;

[0027] A first end of the sixth switch is used to access the clock signal of the third phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0028] A first end of the seventh switch is used to receive the clock signal of the fourth phase, and a second end is connected to the third injection node of the ring oscillator via a buffer;

[0029] A first end of the eighth switch is used to access the clock signal of the fourth phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0030] The first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

[0031] In a possible implementation, the first switch and the fourth switch are configured to be in the same state;

[0032] The second switch and the third switch are configured to be in states opposite to the states of the first switch and the fourth switch;

[0033] The fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal;

[0034] The sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

[0035] In a possible implementation, the value of the injection mode control signal is 2k-1; wherein k is a positive integer;

[0036] The last two bits of the binary code of k are a mode control word; the first control signal and the second control signal are determined according to the second bit of the mode control word.

[0037] In a second aspect, an embodiment of the present disclosure provides a method for generating a multi-phase clock signal, the method being applied to the multi-phase clock circuit described in the first aspect, the method comprising:

[0038] Get injection mode control signal;

[0039] Determining the injection phase of the four-phase injection clock signal according to the injection mode control signal;

[0040] inputting the four-phase injection clock signal into a ring oscillator according to the injection phase;

[0041] N phase clock signals are generated by the ring oscillator.

[0042] In a possible implementation, obtaining the injection mode control signal includes:

[0043] The injection mode control signal is determined according to the frequency of the four-phase injection clock signal.

[0044] In a possible implementation, determining the injection mode control signal according to the frequency of the four-phase injection clock signal includes:

[0045] In response to a frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determining that the mode control signal is a first value;

[0046] In response to the frequency of the four-phase injection clock signal being less than the frequency threshold, the mode control signal is determined to be a second value smaller than the first value.

[0047] In the disclosed embodiment, an injection switch control module is used to obtain an injection mode control signal and an injection switch selection module is used to determine the injection phase of a four-phase injection clock signal, so that the four-phase injection clock signal can be switched to a variety of frequency injection ratios and injection phases when injected into a ring oscillator. A phase detector and a frequency matching control module are used to tune the ring oscillator so that the four-phase injection clock signal can generate a clock signal with good performance when injected into the ring oscillator according to different frequency injection ratios and injection phases. This allows the multi-phase clock circuit to operate normally at different clock frequencies, thereby significantly broadening the frequency range of the clock signal generated by the multi-phase clock circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the accompanying drawings of the embodiments of the present disclosure:

[0049] Figure 1 A block diagram of a multi-phase clock circuit according to an embodiment of the present disclosure;

[0050] Figure 2 A schematic structural diagram of an injection switch selection module provided in an embodiment of the present disclosure;

[0051] Figure 3 A schematic structural diagram of a ring oscillator provided in an embodiment of the present disclosure;

[0052] Figure 4 A schematic diagram of generating a switch control signal provided by an embodiment of the present disclosure;

[0053] Figure 5 A schematic diagram of the correspondence between a mode control word, a switch control signal, and an injection node provided in an embodiment of the present disclosure;

[0054] Figure 6 A schematic diagram of phase detection sign bit control provided in an embodiment of the present disclosure;

[0055] Figure 7 A schematic diagram of generating a switch control signal provided by an embodiment of the present disclosure;

[0056] Figure 8 A schematic diagram of the correspondence between a mode control word, a switch control signal, and a phase detection sign bit provided in an embodiment of the present disclosure;

[0057] Figure 9 A schematic diagram of the operation of a frequency matching control module provided in an embodiment of the present disclosure;

[0058] Figure 10 A flowchart of a method for generating a multi-phase clock signal provided by an embodiment of the present disclosure;

[0059] Figure 11 A block diagram of another multi-phase clock circuit provided by an embodiment of the present disclosure;

[0060] Figure 12 A schematic diagram of the relationship between the frequency and phase of an output clock signal provided by an embodiment of the present disclosure;

[0061] Figure 13 A schematic diagram of an arrangement sequence of output clock signals provided by an embodiment of the present disclosure;

[0062] Figure 14 A schematic diagram of the relationship between frequency and phase of another output clock signal provided by an embodiment of the present disclosure;

[0063] Figure 15 A schematic diagram of another output clock signal arrangement sequence provided by an embodiment of the present disclosure;

[0064] Figure 16 A schematic diagram of the relationship between an injection mode control signal, a mode control word, a control signal, and a frequency provided in an embodiment of the present disclosure;

[0065] Figure 17 A schematic diagram of the clock jitter effect of a switching injection mode control signal provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0068] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0069] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0070] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0071] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0073] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0074] In scenarios such as data centers, cloud computing, and 5G networks, data throughput is rapidly increasing, driving the need for higher data rates. Polyphase sampling is a key technology for achieving high receiver throughput by interleaving multiple channels while maintaining the data rate per channel.

[0075] Multiphase clocks play a crucial role in high-speed communication systems. The clock frequency of a multiphase clock determines the sampling rate of the system, while its clock jitter and other performance characteristics determine the sampling quality. Together, these two factors determine the communication quality of the system. Improving the clock frequency and performance of multiphase clocks is a key technology for improving system performance and reliability.

[0076] In some related technologies, multi-phase clocks can be implemented using ring oscillators, typically using the injection locking principle to keep the ring oscillator operating at the desired frequency. While multi-phase clocks based on ring oscillators offer the advantage of multiple phases, the number of stages in the ring oscillator limits its clock frequency as the number of phases increases, resulting in a narrow frequency range for the clock signal generated by the ring oscillator.

[0077] In the disclosed embodiment, an injection switch control module is used to obtain an injection mode control signal and an injection switch selection module is used to determine the injection phase of a four-phase injection clock signal, so that the four-phase injection clock signal can be switched to a variety of frequency injection ratios and injection phases when injected into a ring oscillator. A phase detector and a frequency matching control module are used to tune the ring oscillator so that the four-phase injection clock signal can generate a clock signal with good performance when injected into the ring oscillator according to different frequency injection ratios and injection phases. This allows the multi-phase clock circuit to output a multi-phase clock signal with accurate edges when operating at different clock frequencies, thereby significantly broadening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0078] In a first aspect, an embodiment of the present disclosure provides a multi-phase clock circuit.

[0079] Reference Figure 1The multi-phase clock circuit of the embodiment of the present disclosure includes an injection switch control module, an injection switch selection module, a buffer, a four-phase injection N-stage output ring oscillator, a phase detector and a frequency matching control module; the injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal represents the frequency injection ratio of the four-phase injection clock signal; the injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal; the buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase; the ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase detector; the phase detector is configured to extract phase deviation information from the N phase clock signals; the frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal and the phase deviation information.

[0080] In the embodiment of the present disclosure, a four-phase injection N-stage output ring oscillator refers to a ring oscillator in which the injected clock signal includes a clock signal of four phases and the output clock signal includes a clock signal of N phases. m , m is a positive integer, and N can be 8, 16, 32, etc. In the disclosed embodiment, there is no restriction on the number of stages (ie, the value of N) of the four-phase injection N-stage output ring oscillator (referred to as the ring oscillator).

[0081] Reference Figure 1 The first end of the injection switch selection module is connected to the four-phase injection clock signal, the second end thereof is connected to the injection switch control module, and the third end thereof is connected to the buffer.

[0082] The injected clock signal may represent a clock signal injected into the ring oscillator for injection locking of the ring oscillator. In the disclosed embodiment, the injected clock signal includes a clock signal with four phases, and is therefore referred to as a four-phase injected clock signal. In one example, the four-phase injected clock signal may be an orthogonal four-phase clock signal, for example, the four-phase injected clock signal may include a clock signal with a phase of 0°, a clock signal with a phase of 180°, a clock signal with a phase of 90°, and a clock signal with a phase of 270°. The four-phase injected clock signal is injected into the ring oscillator via the injection switch selection module and the buffer.

[0083] The injection mode control signal can represent the frequency injection ratio of the four-phase injection clock signal. In the embodiment of the present disclosure, the four-phase injection clock signal can inject its frequency into the ring oscillator according to different frequency injection ratios. For example, the four-phase injection clock signal can inject its frequency into the ring oscillator at a ratio of 1 / 3. In this case, the frequency of the clock signal injected into the ring oscillator is 1 / 3 of the frequency of the four-phase injection clock signal. In this way, the effect of injecting multiple frequencies into the ring oscillator is achieved while the frequency of the four-phase injection clock signal remains unchanged.

[0084] The injection switch control module is configured to obtain an injection mode control signal. After obtaining the injection mode control signal, the injection switch control module may send the injection mode control signal to the injection switch selection module.

[0085] The injection switch selection module is configured to determine the injection phase of the four-phase injected clock signal based on the injection mode control signal. In the disclosed embodiment, under different injection mode control signals, the frequency injection ratios of the four-phase injected clock signal vary, and the corresponding injection phases of the four-phase clock signals may also vary. The injection switch selection module can adjust the injection phases of the four-phase injected clock signal based on the injection mode control signal so that the frequency and phase of the four-phase injected clock signal match when injected into the ring oscillator, thereby improving the performance of the clock signal generated by the ring oscillator.

[0086] After receiving the four-phase injection clock signal and the injection mode control signal, the injection switch selection module can determine the injection phase of each phase clock signal of the four-phase injection clock signal according to the injection mode control signal. It should be understood that by switching the mode control signal, the injection phase of each phase clock signal can be switched.

[0087] In the embodiment of the present disclosure, the frequency injection ratio of the four-phase injection clock signal and the injection phase of each phase clock signal can be determined by the injection mode control signal, ensuring the successful injection of the four-phase injection clock signal and the stable oscillation of the ring oscillator.

[0088] Afterwards, the injection switch selection module may send the four-phase injection clock signals and the injection phase of each phase clock signal to the buffer.

[0089] Reference Figure 1 The first end of the buffer is connected to the injection switch selection module, and the second end is connected to the ring oscillator. The buffer can be used to enhance clock driving capability. The buffer is configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase. The buffer can enhance the four-phase injection clock signal and inject the enhanced four-phase injection clock signal into the ring oscillator according to the injection phase of each phase clock signal.

[0090] It should be understood that the injection phases corresponding to the injection nodes in the ring oscillator are different. Therefore, the buffer can inject each phase clock signal of the four-phase injection clock signal into the injection node corresponding to the injection phase.

[0091] Reference Figure 1 A first terminal of the ring oscillator is connected to the buffer, and a second terminal thereof is connected to the phase detector. The ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into the phase detector.

[0092] It should be understood that the N phase clock signals output by the ring oscillator to the phase detector are N phase clock signals with phase deviation. Based on this, the phase detector is configured to receive the N phase clock signals, extract phase deviation information from the N phase clock signals, and input the phase deviation information to the frequency matching control module to facilitate phase deviation elimination.

[0093] In one example, the phase detector can select a portion of the N phase clock signals as phase detection clock signals and extract phase deviation information from the phase detection clock signals. For example, the phase detector can select the clock signal output at the injection node of the ring oscillator as the phase detection clock signal, thereby improving the accuracy of the phase deviation information.

[0094] Reference Figure 1 The first end of the frequency matching control module is connected to the phase detector, and the second end thereof is connected to the ring oscillator.

[0095] The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information.

[0096] In the embodiment of the present disclosure, when tuning the ring oscillator, the frequency matching control module first adjusts the self-oscillation frequency of the ring oscillator according to the frequency injection ratio represented by the injection mode control signal and the frequency of the four-phase injection clock signal; then, the phase information of the ring oscillator is adjusted according to the phase deviation information, thereby completing the tuning of the ring oscillator.

[0097] In the disclosed embodiment, an injection switch control module is used to obtain an injection mode control signal and an injection switch selection module is used to determine the injection phase of a four-phase injection clock signal, so that the four-phase injection clock signal can be switched to a variety of frequency injection ratios and injection phases when injected into a ring oscillator. A phase detector and a frequency matching control module are used to tune the ring oscillator so that the four-phase injection clock signal can generate a clock signal with good performance when injected into the ring oscillator according to different frequency injection ratios and injection phases. This allows the multi-phase clock circuit to output a multi-phase clock signal with accurate edges when operating at different clock frequencies, thereby significantly broadening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0098] In some embodiments, the injection mode control signal is a positive odd number. In this embodiment, the injection mode control signal is represented by INJ_MODE, where INJ_MODE = 2k-1, where k is an integer greater than 0. For example, k can be 1, 2, or 3, and the corresponding INJ_MODE can be 1, 3, or 5, for example.

[0099] The injection mode control signal represents the frequency injection ratio of the four-phase injection clock signal. For example, if the injection mode control signal value is 3, it means that 1 / 3 of the frequency of the four-phase injection clock signal is injected into the ring oscillator; if the injection mode control signal value is 5, it means that 1 / 5 of the frequency of the four-phase injection clock signal is injected into the ring oscillator.

[0100] As one approach in the disclosed embodiments, setting the value of the injection mode control signal to a positive odd number can achieve matching with the universal pattern set, facilitating signal control. It should be noted that in the disclosed embodiments, the injection mode control signal can be used to determine the first control signal, the second control signal, and the like, as will be described in detail later and will not be repeated here.

[0101] In some embodiments, the four-phase injection clock signal includes a clock signal of a first phase, a clock signal of a second phase, a clock signal of a third phase, and a clock signal of a fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are in opposite phases, and the third phase and the fourth phase are in opposite phases; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch;

[0102] A first end of the first switch is used to access the clock signal of the first phase, and a second end is connected to the first injection node of the ring oscillator via a buffer;

[0103] A first end of the second switch is used to access the clock signal of the first phase, and a second end is connected to the second injection node of the ring oscillator via a buffer;

[0104] A first end of the third switch is used to access the second-phase clock signal, and a second end is connected to the first injection node of the ring oscillator via a buffer;

[0105] A first end of the fourth switch is used to access the second-phase clock signal, and a second end is connected to the second injection node of the ring oscillator via a buffer;

[0106] A first end of the fifth switch is used to access the clock signal of the third phase, and a second end is connected to the third injection node of the ring oscillator via a buffer;

[0107] A first end of the sixth switch is used to access the clock signal of the third phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0108] A first end of the seventh switch is used to receive the clock signal of the fourth phase, and a second end is connected to the third injection node of the ring oscillator via a buffer;

[0109] A first end of the eighth switch is used to access the clock signal of the fourth phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer;

[0110] The first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

[0111] In the disclosed embodiments, a clock signal with a phase of 0° is used as the first phase clock signal (denoted as CLK_0°), a clock signal with a phase of 180° is used as the second phase clock signal (denoted as CLK_180°), a clock signal with a phase of 90° is used as the third phase clock signal (denoted as CLK_90°), and a clock signal with a phase of 270° is used as the fourth phase clock signal (denoted as CLK_270°). In this case, the first phase (0°), the second phase (180°), the third phase (90°), and the fourth phase (270°) are differentially distributed, and the first phase (0°) and the second phase (180°) are in opposite phases, while the third phase (90°) and the fourth phase (270°) are in opposite phases. It should be understood that the above is merely an exemplary description of the first, second, third, and fourth phases and is not intended to be limiting. For example, the first phase, the second phase, the third phase, and the fourth phase can be 45°, 225°, 135°, and 315°, respectively.

[0112] In the embodiment of the present disclosure, the clock signal injected into the first injection node is recorded as CKI_A, the clock signal injected into the second injection node is recorded as CKI_B, the clock signal injected into the third injection node is recorded as CKI_C, and the clock signal injected into the fourth injection node is recorded as CKI_D.

[0113] Figure 2 This is a structural diagram of an injection switch selection module provided by an embodiment of the present disclosure. Figure 2The first end of the first switch S1 is connected to the first-phase clock signal CLK_0°, and the second end is connected to the first injection node of the ring oscillator via a buffer for injecting (also called inputting) the clock signal CKI_A. The first end of the second switch S2 is connected to the first-phase clock signal CLK_0°, and the second end is connected to the second injection node of the ring oscillator via a buffer for injecting the clock signal CKI_B. The first end of the third switch S3 is connected to the second-phase clock signal CLK_180°, and the second end is connected to the first injection node of the ring oscillator via a buffer for injecting the clock signal CKI_A. The first end of the fourth switch S4 is connected to the second-phase clock signal CLK_180°, and the second end is connected to the second injection node of the ring oscillator via a buffer for injecting the clock signal CKI_B. The first end of the fifth switch S5 is connected to the third-phase clock signal CLK_90°, and the second end is connected to the third injection node of the ring oscillator via a buffer for injecting the clock signal CKI_C. The first end of the sixth switch S6 is used to receive the third-phase clock signal CLK_90°, and the second end is connected to the fourth injection node of the ring oscillator via a buffer for injecting the clock signal CKI_D. The first end of the seventh switch S7 is used to receive the fourth-phase clock signal CLK_270°, and the second end is connected to the third injection node of the ring oscillator via a buffer for injecting the clock signal CKI_C. The first end of the eighth switch S8 is used to receive the fourth-phase clock signal CLK_270°, and the second end is connected to the fourth injection node of the ring oscillator via a buffer for injecting the clock signal CKI_D.

[0114] Reference Figure 2 It can be seen that the first phase clock signal CLK_0° can be used as the clock signal CKI_A or CKI_B, the second phase clock signal CLK_180° can be used as the clock signal CKI_A or CKI_B, the third phase clock signal CLK_90° can be used as the clock signal CKI_C or CKI_D, and the fourth phase clock signal CLK_270° can be used as the clock signal CKI_C or CKI_D.

[0115] Figure 3 This is a schematic diagram of the structure of a ring oscillator provided by an embodiment of the present disclosure. Figure 3 The four-phase injection N-stage output ring oscillator includes N inverters cascaded into a ring, that is, the N inverters are connected end to end in sequence, and the output end of each inverter is an output node for outputting a clock signal generated by the ring oscillator. The N output nodes included in the ring oscillator can be expressed as CKO<N-1,0> , the i-th output node of the ring oscillator can be expressed as , 0≤i≤N-1, i is an integer.

[0116] In the disclosed embodiment, the ring oscillator has four injection nodes: a first injection node, a second injection node, a third injection node, and a fourth injection node. These four injection nodes are output nodes of the ring oscillator spaced N / 4 apart. Furthermore, the spacing between the first and second injection nodes is greater than the spacing between the first and third injection nodes. Therefore, the third injection node is located between the first and second injection nodes. In other words, the first, third, second, and fourth injection nodes are arranged in sequence.

[0117] Reference Figure 3 The first injection node of the clock signal CKI_A is the output node CKO of the ring oscillator. <0> The second injection node for the clock signal CKI_B is the output node CKO of the ring oscillator. <n 2>The third injection node into which the clock signal CKI_C is injected is the output node CKO of the ring oscillator. <n 4>The fourth injection node, into which the clock signal CKI_D is injected, is the ring oscillator's output node CKO<3N / 4>. As can be seen, the distance between the first and third injection nodes, between the third and second injection nodes, between the fourth and second injection nodes, and between the first and fourth injection nodes is N / 4 output nodes on the ring oscillator. The distance between the first and second injection nodes is greater than the distance between the first and third injection nodes.

[0118] As one method of an embodiment of the present disclosure, by setting an injection switch selection module between the four-phase injection clock signal and the injection node, clock signals of different phases in the four-phase injection clock signal can be input to different injection nodes through the switching switch, thereby adjusting the phase of the four-phase injection clock signal and widening the frequency of the injection clock signal.

[0119] In some embodiments, the first switch and the fourth switch are configured to be in the same state; the second switch and the third switch are configured to be in states opposite to those of the first switch and the fourth switch; the fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal; and the sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

[0120] The first switch and the fourth switch being configured in the same state means that the first switch and the fourth switch are both in the closed state, or the first switch and the fourth switch are both in the open state. The second switch and the third switch being configured in states opposite to the first switch and the fourth switch means that when the first switch and the fourth switch are both in the closed state, the second switch and the third switch are both in the open state; and when the first switch and the fourth switch are both in the open state, the second switch and the third switch are both in the closed state.

[0121] Reference Figure 2 The first switch S1 is configured to be closed (i.e., on), the second switch S2 is configured to be open (i.e., off), and the first-phase clock signal CLK_0° is used as the clock signal CKI_A input to the first injection node; the third switch S3 is configured to be open, and the fourth switch S4 is configured to be closed, and the second-phase clock signal CLK_180° is used as the clock signal CKI_B input to the second injection node.

[0122] The fifth and eighth switches are controlled by a first control signal. The sixth and seventh switches are controlled by a second control signal. The second control signal is the opposite of the first control signal. That is, when the first control signal controls the fifth and eighth switches to be open, the second control signal controls the sixth and seventh switches to be closed; when the first control signal controls the fifth and eighth switches to be closed, the second control signal controls the sixth and seventh switches to be open.

[0123] Reference Figure 2 , the first control signal MC1 controls the fifth switch S5 and the eighth switch S8 to be closed, and the second control signal MC2 controls the sixth switch S6 and the seventh switch S7 to be open. At this time, the third-phase clock signal CLK_90° serves as the clock signal CKI_C input to the third injection node, and the fourth-phase clock signal CLK_270° serves as the clock signal CKI_D input to the fourth injection node. Accordingly, the first control signal MC1 controls the fifth switch S5 and the eighth switch S8 to be open, and the second control signal MC2 controls the sixth switch S6 and the seventh switch S7 to be closed. At this time, the third-phase clock signal CLK_90° serves as the clock signal CKI_D input to the fourth injection node, and the fourth-phase clock signal CLK_270° serves as the clock signal CKI_C input to the third injection node.

[0124] The first control signal is determined according to the injection mode control signal, and the second control signal is opposite to the first control signal, which means that the second control signal is also determined according to the injection mode control signal.

[0125] As one embodiment of the present disclosure, the first control signal and the second control signal are determined by an injection mode control signal, thereby controlling the states of the fifth switch, the sixth switch, the seventh switch, and the eighth switch, and further realizing the switching of the injection nodes corresponding to the third phase clock signal and the fourth phase clock signal through the injection mode control signal.

[0126] In some embodiments, the value of the injection mode control signal is 2k-1; wherein k is a positive integer; the last two bits of the binary code of k are the mode control word; and the first control signal and the second control signal are determined according to the second bit of the mode control word.

[0127] In the disclosed embodiment, the last two bits of the binary code for k can be represented by b1 and b0, and the mode control word can be represented by (b1, b0), with the first bit of the mode control word being b1 and the second bit being b0. The switch control signal can be represented by (MC2, MC1), where MC1 represents the first control signal and MC2 represents the second control signal.

[0128] Figure 4 A schematic diagram of generating a switch control signal provided by an embodiment of the present disclosure. Figure 4 The second bit b0 of the mode control word is connected to the first control signal MC1 and the second control signal MC2. The second bit b0 of the mode control word is connected to the second control signal MC2 via an inverter, and the two have opposite values. The second bit b0 of the mode control word is connected to the first control signal MC1 via two inverters, and the two have the same value. When the second control signal MC2 has a value of 1, the connected switches (the sixth and seventh switches) are closed (i.e., on); when the second control signal MC2 has a value of 0, the connected switches are opened (i.e., off). The first control signal MC1 can refer to the second control signal MC2 and will not be further described here.

[0129] Figure 5 Schematic diagram of the correspondence between a mode control word, a switch control signal, and an injection node according to an embodiment of the present disclosure.

[0130] Reference Figure 5 When the mode control word (b1, b0) takes the value (x, 0), the second control signal MC2 takes the value 1, closing the sixth switch S6 and the seventh switch S7. The first control signal MC1 takes the value 0, opening the fifth switch S5 and the eighth switch S8. At this time, the third injection node CKI_C injects the fourth-phase clock signal CLK_270°, and the fourth injection node CKI_D injects the third-phase clock signal CLK_90°. It should be understood that the mode control word (b1, b0) taking the value (x, 0) means that the first bit of the mode control word can be 0 or 1, and the second bit is 0.

[0131] Reference Figure 5 When the mode control word (b1, b0) takes the value (x, 1), the second control signal MC2 takes the value 0, opening the sixth and seventh switches S6 and S7. The first control signal MC1 takes the value 1, closing the fifth and eighth switches S5 and S8. At this time, the third injection node CKI_C injects the third-phase clock signal CLK_90°, and the fourth injection node CKI_D injects the fourth-phase clock signal CLK_270°. It should be understood that the mode control word (b1, b0) taking the value (x, 1) means that the first bit of the mode control word can be either 0 or 1, and the second bit is 1.

[0132] As one embodiment of the present disclosure, the first control signal and the second control signal are determined by a mode control word, thereby controlling the closing and opening of the switch, thereby achieving switching of the injection phase by the injection mode control signal.

[0133] In some embodiments, the frequency matching control module is configured to: before the buffer inputs the four-phase injection clock signal into the ring oscillator, adjust the self-oscillation frequency of the ring oscillator toward a target frequency; the target frequency = the frequency of the four-phase injection clock signal / the value of the injection mode control signal; after the buffer inputs the four-phase injection clock signal into the ring oscillator, use negative feedback to eliminate the phase deviation information.

[0134] In the embodiment of the present disclosure, the self-oscillation frequency of the ring oscillator is denoted as f osc , the target frequency is recorded as f d The frequency of the four-phase injected clock signal is recorded as f INJ , the injection mode control signal is recorded as INJ_MODE. Among them, f d =f INJ / INJ_MODE. In one example, INJ_MODE=1, then f d =fI NJ ;INJ_MODE=3, then f d =f INJ / 3; INJ_MODE=5, then f d =f INJ / 5.

[0135] Before the buffer injects the four-phase clock signal into the ring oscillator, the frequency matching control module adjusts the self-oscillation frequency f of the ring oscillator to osc Towards the target frequency f d adjust.

[0136] In one example, when the ring oscillator's self-oscillation frequency f osc Less than the target frequency f d When f osc When the natural frequency of the ring oscillator f osc Greater than the target frequency f d When f osc The value of is adjusted until the self-oscillation frequency of the ring oscillator matches the target frequency. osc The adjustment step size (increasing the step size or decreasing the step size) can be set as needed, and this embodiment of the present disclosure does not limit this.

[0137] In one example, when the ring oscillator's self-oscillation frequency f osc With the target frequency f d When the difference between the self-oscillation frequency of the ring oscillator and the target frequency is less than the first preset value, it can be confirmed that the self-oscillation frequency of the ring oscillator matches the target frequency. The first preset value can be set as needed, and the embodiment of the present disclosure does not limit it. In another example, when the self-oscillation frequency f of the ring oscillator is osc With the target frequency f d When the difference is less than the second preset value and the number of adjustments to the ring oscillator's self-oscillation frequency fosc is greater than the third preset value, it can be determined that the ring oscillator's self-oscillation frequency matches the target frequency. The second preset value and the third preset value can be set as needed and are not limited in the present embodiment.

[0138] It should be noted that the above is only the natural frequency f of the ring oscillator osc The adjustment method and the natural frequency f of the ring oscillator osc With the target frequency f d The exemplary description of the matching confirmation method is not intended to limit the embodiments of the present disclosure. Other methods in the relevant technology can also be used to adjust the self-oscillation frequency fosc of the ring oscillator and confirm that the self-oscillation frequency of the ring oscillator matches the target frequency.

[0139] After the frequency matching control module completes adjusting the self-oscillation frequency of the ring oscillator, the buffer may start injecting the four-phase injection clock signal.

[0140] After the buffer inputs the four-phase injection clock signal into the ring oscillator, the frequency matching control module uses negative feedback to eliminate the phase deviation information.

[0141] As one method of an embodiment of the present disclosure, by adjusting the self-oscillation frequency of the ring oscillator before the four-phase injection clock signal is input into the ring oscillator, and eliminating the phase deviation of the ring oscillator after the four-phase injection clock signal is input into the ring oscillator, the phase deviation of the ring oscillator at multiple self-oscillation frequencies is effectively eliminated, so that the ring oscillator can generate accurate clock signals when operating at multiple self-oscillation frequencies, thereby improving the frequency coverage range of the clock signal output by the ring oscillator.

[0142] In some embodiments, the phase detector is configured to: determine a phase detection sign bit according to an injection mode control signal; determine a frequency deviation according to the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal and the injection mode control signal; and determine the phase deviation information according to the phase detection sign bit and the frequency deviation.

[0143] The phase detection sign bit is used to maintain or flip the phase. When the phase detection sign bit is 1, the phase can be maintained; when the phase detection sign bit is 2, the phase can be flipped.

[0144] In one example, the injection mode control signal has a value of 2k-1, where k is a positive integer. The last two digits of the binary code of k constitute the mode control word. The phase detection sign bit is determined based on the mode control word. Assuming the last two digits of the binary code of k are b1 and b0, the mode control word can be expressed as (b1, b0).

[0145] Figure 6 A schematic diagram of phase detection sign bit control provided by an embodiment of the present disclosure. Figure 6 The frequency matching control module may include a ninth switch S9 and a tenth switch S10. When the ninth switch S9 is closed and the tenth switch S10 is open, the phase detection sign bit takes a value of -1; when the ninth switch S9 is open and the tenth switch S10 is closed, the phase detection sign bit takes a value of 1. The closing or opening of the ninth switch may be controlled by a third control signal MC3, and the closing or opening of the tenth switch may be controlled by a fourth control signal MC4. It should be understood that the third control signal MC3 and the fourth control signal MC4 are opposite, and the states of the ninth switch S9 and the tenth switch S10 are opposite.

[0146] In the disclosed embodiment, the third control signal MC3 and the fourth control signal MC4 can be first determined based on the mode control word (b1, b0), and then the phase detection sign bit can be determined based on the third control signal MC3 and the fourth control signal MC4. In one example, the third control signal and the fourth control signal can determine whether the phase detection sign bit is 1 or -1 by controlling the opening or closing of the ninth switch and the tenth switch.

[0147] Figure 7 A schematic diagram of generating a switch control signal provided by an embodiment of the present disclosure. Figure 7 The first bit b1 and second bit b0 of the mode control word serve as inputs to an XOR gate. The output of the XOR gate is connected to the fourth control signal MC4, and the output of the XOR gate has the same value as the fourth control signal MC4. The first bit b1 and second bit b0 of the mode control word serve as inputs to an XOR gate. The output of the XOR gate is connected to the third control signal MC3 through an inverter, and the output of the XOR gate has the opposite value to the third control signal MC3. When the fourth control signal MC4 takes the value of 1, the tenth switch S10 connected to it is closed (i.e., on); when the fourth control signal MC4 takes the value of 0, the tenth switch S10 connected to it is opened (i.e., off). When the third control signal MC3 takes the value of 1, the ninth switch S9 connected to it is closed; when the third control signal MC3 takes the value of 0, the ninth switch S9 connected to it is opened.

[0148] Figure 8 A schematic diagram of the correspondence between a mode control word, a switch control signal, and a phase detection sign bit provided in an embodiment of the present disclosure.

[0149] Reference Figure 8 When the mode control word (b1, b0) takes the value (0, 0), the fourth control signal MC4 takes the value 0, the third control signal MC3 takes the value 1, and the tenth switch S10 is controlled to be open and the ninth switch S9 is controlled to be closed. At this time, the phase detection sign bit takes the value -1.

[0150] Reference Figure 8 When the mode control word (b1, b0) takes the value (0, 1), the fourth control signal MC4 takes the value 1, the third control signal MC3 takes the value 0, and the tenth switch S10 is controlled to be closed and the ninth switch S9 is controlled to be open. At this time, the phase detection sign bit takes the value 1.

[0151] Reference Figure 8 When the mode control word (b1, b0) takes the value (1, 0), the fourth control signal MC4 takes the value 1, the third control signal MC3 takes the value 0, and the tenth switch S10 is controlled to be closed and the ninth switch S9 is controlled to be open. At this time, the phase detection sign bit takes the value 1.

[0152] Reference Figure 8 When the mode control word (b1, b0) takes the value (1, 1), the fourth control signal MC4 takes the value 0, the third control signal MC3 takes the value 1, and the tenth switch S10 is controlled to be open and the ninth switch S9 is controlled to be closed. At this time, the phase detection sign bit takes the value -1.

[0153] Figure 9 This is a working diagram of a frequency matching control module provided by an embodiment of the present disclosure. Figure 9 The frequency matching control module of the disclosed embodiment includes a coarse tuning loop and a fine tuning loop. Before the buffer operates (i.e., injects the four-phase injection clock signal into the buffer), the frequency matching control module uses the coarse tuning loop to coarsely tune the ring oscillator's self-oscillation frequency.

[0154] Reference Figure 9 The coarse tuning process includes: when the frequency of the four-phase injected clock signal is f INJ When the injection mode control signal is INJ_MODE, the coarse adjustment loop obtains and measures the natural frequency f of the ring oscillator. osc , fI NJ / INJ_MODE and f osc For comparison, the difference between the two is Δf=f INJ / INJ_MODE -f osc , and then tune the ring oscillator's self-oscillation frequency according to Δf. If Δf>0, increase f osc , if Δf<0, then reduce f osc After the buffer works (ie, the four-phase injection clock signal is injected into the buffer), the frequency matching control module performs fine tuning through the fine tuning loop.

[0155] Reference Figure 9 The fine tuning process includes: the phase detector first determines the phase detection symbol bit sign according to the injection mode control signal; then, according to the phase detection symbol bit sign and the frequency deviation Δf, the phase deviation information V is determined. pd Then, the frequency matching control module is based on V pd If it is greater than 0, negative feedback is used to eliminate the phase deviation signal to obtain a multi-phase clock signal with accurate edges.

[0156] In one example, the phase deviation information V pd ≈sign×K pd ×Δf.

[0157] The value of the phase detection sign bit sign is determined by the third control signal MC3 and the fourth control signal MC4. When (MC4, MC3) = (0, 1), sign = -1, and when (MC4, MC3) = (1, 0), sign = 1. (MC4, MC3) under different mode control words (b1, b0) can refer to Figure 8 .

[0158] Among them, the phase deviation K pd It can be determined based on the selected phase-locked clock signal. For example, the selected phase-locked clock signal can be the clock signal output at each injection node. Figure 9 , N to 4 MUX represents a four-phase injection N-level output ring oscillator, and its output clock signal is CKO<N-1,0> , where CKO_A, B, C, D represent the four selected phase-locked clock signals CKO_A, CKO_B, CKO_C and CKO_D. CKO_A represents the clock signal output at the first injection node, CKO_B represents the clock signal output at the second injection node, CKO_C represents the clock signal output at the third injection node, and CKO_D represents the clock signal output at the fourth injection node. Figure 9 The phase detection clock signals CKO_A and CKO_B are processed by the multiplier and adder to obtain the first output result, and the phase detection clock signals CKO_C and CKO_D are processed by the multiplier and adder to obtain the second output result. The first output result and the second output result are input into the adder to obtain the phase deviation K. pd .

[0159] The frequency deviation Δf refers to the coarse tuning process and will not be described in detail here.

[0160] As one method of an embodiment of the present disclosure, by combining a coarse adjustment loop and a fine adjustment loop, the self-oscillation frequency of the ring oscillator can be tuned to different clock frequencies, and the ring oscillator can output edge-accurate multi-phase clock signals when operating at different clock frequencies, thereby greatly broadening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0161] In a second aspect, an embodiment of the present disclosure provides a method for generating a multi-phase clock signal, which can be applied to the phase clock circuit provided in the first aspect. Figure 10 , the method may include:

[0162] S1001, obtaining an injection mode control signal.

[0163] Among them, the injection mode control signal can refer to the first aspect and will not be repeated here.

[0164] S1002: Determine the injection phase of the four-phase injection clock signal according to the injection mode control signal.

[0165] The process of determining the injection phase may refer to the first aspect and will not be described in detail here.

[0166] S1003 : Input the four-phase injection clock signal into a ring oscillator according to the injection phase.

[0167] S1004: Generate N phase clock signals through the ring oscillator.

[0168] In the disclosed embodiment, the injection mode control signal controls the four-phase injection clock signal so that it can switch to a variety of frequency injection ratios and injection phases when injected into the ring oscillator. At the same time, the four-phase injection clock signal can generate a clock signal with better performance when injected into the ring oscillator according to different frequency injection ratios and injection phases, so that the multi-phase clock circuit can output a multi-phase clock signal with accurate edges when operating at different clock frequencies, thereby greatly broadening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0169] In some embodiments, acquiring the injection mode control signal includes: determining the injection mode control signal according to a frequency of the four-phase injection clock signal.

[0170] The natural frequency of the ring oscillator is denoted as f osc The frequency of the four-phase injected clock signal is recorded as f INJ , the injection mode control signal is recorded as INJ_MODE, then f osc =f INJ / INJ_MODE.

[0171] As one embodiment of the present disclosure, the injection mode control signal switches the injection frequency when the four-phase injection clock signal is injected into the ring oscillator, thereby significantly widening the frequency range of the clock signal generated by the multi-phase clock circuit.

[0172] In some embodiments, determining the injection mode control signal based on the frequency of the four-phase injection clock signal includes: in response to the frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determining the mode control signal to be a first value; in response to the frequency of the four-phase injection clock signal being less than the frequency threshold, determining the mode control signal to be a second value smaller than the first value.

[0173] The preset frequency threshold can be used to evaluate whether the frequency of the Dixiang injected clock signal is large or small. The preset frequency threshold can be set as needed and is not limited in the present embodiment. When the frequency of the four-phase injected clock signal is greater than or equal to the preset frequency threshold, it indicates that the frequency of the four-phase injected clock signal is large; when the frequency of the four-phase injected clock signal is less than the preset frequency threshold, it indicates that the frequency of the four-phase injected clock signal is small.

[0174] Because the jitter performance of the output clock signal deteriorates when the ring oscillator's self-oscillation frequency is low, and improves when the ring oscillator's self-oscillation frequency is high, the jitter performance of the output clock signal improves. Therefore, when the frequency of the four-phase injected clock signal is greater than or equal to a preset frequency threshold, a larger first value can be used as the value of the mode control signal, thereby increasing the self-oscillation frequency of the ring oscillator and improving the jitter performance of the output clock signal. When the frequency of the four-phase injected clock signal is greater than the preset frequency threshold, a smaller second value can be used as the value of the mode control signal, thereby reducing the self-oscillation frequency of the ring oscillator and expanding the frequency range.

[0175] As a method of an embodiment of the present disclosure, by adjusting the value of the mode control signal according to the frequency of the four-phase injected clock signal, the switching of the ring oscillator's self-oscillation frequency is achieved, the generation of a multi-phase clock signal in a large frequency band is achieved, and the good jitter performance of the clock in a large range is ensured.

[0176] Reference Figure 11 The multi-phase clock circuit of the embodiment of the present disclosure includes a four-phase injection clock, an injection switch selection module, a buffer, a ring oscillator, a phase detector, a frequency matching control module and an injection switch control module. The connection relationship and functions thereof are as follows: the four-phase injection clock signal generates a frequency of fI NJ An accurate four-phase injection clock signal is used for injection locking. The four-phase injection clock signal is sent to the injection switch selection module, which selects the correct injection phase under different injection mode control signals to ensure successful injection and stable oscillation. The four-phase injection clock signal is sent to the buffer to enhance the clock drive capability. The buffer is connected to the corresponding injection nodes of the N ring oscillators, and the corresponding frequency and four phase relationships are injected from the injection nodes. The ring oscillator generates N phase clock signals with phase deviations based on the injected information. The N phase clock signals containing phase deviation information are sent to the phase detector for extraction to obtain phase deviation information. The obtained phase deviation information is sent to the frequency matching control module, which tunes the ring oscillator according to the frequency matching requirements under the current injection mode control signal to eliminate phase deviation and ultimately generate a set of N phase clocks with accurate phases. Under the control of the injection mode control signal, this multi-phase clock circuit generation module can cover a wider frequency range and achieve better clock jitter performance.

[0177] Reference Figure 11 The four-phase injected clock signal includes clock signals with phases of 0°, 180°, 90°, and 270°. The clock signals injected into the ring oscillator are CKI_A, CKI_B, CKI_C, and CKI_D. The frequency matching control module tunes the ring oscillator through a coarse tuning loop and a fine tuning loop.

[0178] Figure 12 Taking N=16 as an example, the frequency and phase relationship of the final output N-phase clock signal when the injection mode control signal is 1 is shown. Figure 12 , the mode control signal INK_MODE = 1, so the frequency of the clock signal output by the ring oscillator is f CKO , the frequency f of the four-phase injected clock signal INJ and the ring oscillator's natural frequency f osc The frequency relationship is f CKO =f INJ =f osc . Figure 13 Taking N=16 as an example, the following diagram shows the phase sequence of the output clock signal when the injection mode control signal is 1. Figure 13 , arrange the output clock signals in phase order, CKO <0> , CKO <9> , CKO <2> , CKO <11> , CKO <4> , CKO <13> , CKO <6> and CKO <15> , CKO <8> , CKO <1> , CKO <10> and CKO <3> , CKO <12> , CKO <5> , CKO <14> and CKO <7> . Reference Figure 12 , input phase adjacent output clock signal CKO <0> , CKO <9> , CKO <2> and CKO <11> There is a phase difference of 1.

[0179] Figure 14 Taking N=16 as an example, the frequency and phase relationship of the final output N-phase clock signal when the injection mode control signal is 3 is shown. Figure 14 , the mode control signal INK_MODE = 3, so the frequency of the clock signal output by the ring oscillator is f CKO , the frequency f of the four-phase injected clock signal INJ and the ring oscillator's natural frequency f osc The frequency relationship is f CKO =f INJ =3f osc . Figure 15 Taking N=16 as an example, the following diagram shows the phase sequence of the output clock signal when the injection mode control signal is 3. Figure 15 , arrange the output clock signals in phase order, CKO <0> , CKO <3> , CKO <6> , CKO <9> , CKO <12> , CKO <15> , CKO <2> and CKO <5> , CKO <8> , CKO <11> , CKO <14> and CKO <1> , CKO <4> , CKO <7> , CKO <10> and CKO <3> . Reference Figure 14 , input phase adjacent output clock signal CKO <0> and CKO <9> There is a phase difference of 3 between them, and the output clock signal CKO <9> and CKO <6> There is a phase difference of 2 between them, and the output clock signal CKO <0> and CKO <3> There is a phase difference of 1.

[0180] Figure 16 A schematic diagram of the relationship between an injection mode control signal, a mode control word, a control signal, and a frequency is provided in an embodiment of the present disclosure.

[0181] Reference Figure 17 , showing the schematic diagram of the effect of achieving low clock jitter by switching the injection mode control signal in the embodiment of the present disclosure. Assuming that the tuning range of the designed ring oscillator is f osc =(f min ,f max ), where f osc Indicates the natural frequency, f min , represents the minimum frequency, f max Indicates the maximum frequency. Since the edge of the ring oscillator clock signal slows down at low frequencies, the multi-phase clock will have a low-frequency interval (f min ,f Jitter,limit ), when f osc >f Jitter,limit When the injection mode control signal INJ_MODE=5, the frequency variation range of the multi-phase clock circuit is (5f min ~5f max ), however, in (5f min ,5f Jitter,limit ) frequency range, its clock jitter performance is poor, which greatly reduces the frequency band range available for high-order injection in a single mode. In the embodiment of the present disclosure, the injection mode control signal can be switched, such as in (5f min ,3f Jitter,limit ) frequency range and switches to 1 injection (ie, switches the injection mode control signal to 1, (3f Jitter,limit ,5f Jitter,limit ) frequency range (i.e., the injection mode control signal is switched to three injections (i.e., the injection mode control signal is switched to five), thus ensuring good clock jitter performance. Thus, by switching the injection mode control signal, segmented processing is performed between low-frequency performance degradation ranges and high-frequency performance improvement ranges. This not only enables the generation of multi-phase clocks across a wide frequency band, but also ensures good clock jitter performance across a wide range, improving design and application flexibility.

[0182] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.< / n> < / n>

Claims

1. A multi-phase clock circuit, characterized in that: include: Injection switch control module, injection switch selection module, buffer, four-phase injection N-level output ring oscillator, phase detector and frequency matching control module; The injection switch control module is configured to obtain an injection mode control signal; the injection mode control signal represents a frequency injection ratio of a four-phase injection clock signal; The injection switch selection module is configured to determine the injection phase of the four-phase injection clock signal according to the injection mode control signal; a buffer configured to input the four-phase injection clock signal into the ring oscillator according to the injection phase; The ring oscillator is configured to generate N phase clock signals based on the four-phase injection clock signal, and input the N phase clock signals into the phase detector; The phase detector is configured to extract phase deviation information from the N phase clock signals; The frequency matching control module is configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal and the phase deviation information.

2. The multi-phase clock circuit according to claim 1, wherein: The value of the injection mode control signal is a positive odd number.

3. The multi-phase clock circuit according to claim 1, wherein: The frequency matching control module is configured to: Before the buffer inputs the four-phase injection clock signal into the ring oscillator, adjusting the self-oscillation frequency of the ring oscillator toward a target frequency; The target frequency=the frequency of the four-phase injection clock signal / the value of the injection mode control signal; After the buffer inputs the four-phase injection clock signal into the ring oscillator, negative feedback is used to eliminate the phase deviation information.

4. The multi-phase clock circuit according to claim 1, wherein: The phase detector is configured as follows: Determining a phase detection sign bit according to the injection mode control signal; determining a frequency deviation based on the self-oscillation frequency of the ring oscillator, the frequency of the injection clock signal, and the injection mode control signal; The phase deviation information is determined according to the phase detection sign bit and the frequency deviation.

5. The multi-phase clock circuit according to claim 4, wherein: The value of the injection mode control signal is 2k-1; wherein k is a positive integer; The last two bits of the binary code of k are a mode control word; the phase detection sign bit is determined according to the mode control word.

6. The multi-phase clock circuit according to claim 1, wherein: The four-phase injection clock signal includes a clock signal of a first phase, a clock signal of a second phase, a clock signal of a third phase, and a clock signal of a fourth phase; the first phase, the second phase, the third phase, and the fourth phase are differentially distributed, and the first phase and the second phase are in opposite phases, and the third phase and the fourth phase are in opposite phases; the injection switch selection module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; A first end of the first switch is used to access the clock signal of the first phase, and a second end is connected to the first injection node of the ring oscillator via a buffer; A first end of the second switch is used to access the clock signal of the first phase, and a second end is connected to the second injection node of the ring oscillator via a buffer; A first end of the third switch is used to access the second-phase clock signal, and a second end is connected to the first injection node of the ring oscillator via a buffer; A first end of the fourth switch is used to access the second-phase clock signal, and a second end is connected to the second injection node of the ring oscillator via a buffer; A first end of the fifth switch is used to access the clock signal of the third phase, and a second end is connected to the third injection node of the ring oscillator via a buffer; A first end of the sixth switch is used to access the clock signal of the third phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer; A first end of the seventh switch is used to receive the clock signal of the fourth phase, and a second end is connected to the third injection node of the ring oscillator via a buffer; A first end of the eighth switch is used to access the clock signal of the fourth phase, and a second end is connected to the fourth injection node of the ring oscillator via a buffer; The first injection node, the second injection node, the third injection node and the fourth injection node are output nodes on the ring oscillator with an interval of N / 4, and the interval between the first injection node and the second injection node is greater than the interval between the first injection node and the third injection node.

7. The multi-phase clock circuit according to claim 6, wherein: The first switch and the fourth switch are configured to be in the same state; The second switch and the third switch are configured to be in states opposite to the states of the first switch and the fourth switch; The fifth switch and the eighth switch are controlled by a first control signal determined according to the injection mode control signal; The sixth switch and the seventh switch are controlled by a second control signal opposite to the first control signal.

8. The multi-phase clock circuit according to claim 7, wherein: The value of the injection mode control signal is 2k-1; wherein k is a positive integer; The last two bits of the binary code of k are a mode control word; the first control signal and the second control signal are determined according to the second bit of the mode control word.

9. A method for generating a multi-phase clock signal, characterized in that: The method is applied to the multi-phase clock circuit according to any one of claims 1 to 8, and the method includes: Get injection mode control signal; Determining the injection phase of the four-phase injection clock signal according to the injection mode control signal; inputting the four-phase injection clock signal into a ring oscillator according to the injection phase; N phase clock signals are generated by the ring oscillator.

10. The method according to claim 9, characterized in that The obtaining of the injection mode control signal comprises: The injection mode control signal is determined according to the frequency of the four-phase injection clock signal.

11. The method according to claim 10, characterized in that Determining the injection mode control signal according to the frequency of the four-phase injection clock signal includes: In response to a frequency of the four-phase injection clock signal being greater than or equal to a preset frequency threshold, determining that the mode control signal is a first value; In response to the frequency of the four-phase injection clock signal being less than the frequency threshold, the mode control signal is determined to be a second value smaller than the first value.

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