A primary-secondary delay phase-locked loop with dual delay lines

Abstract

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

Description

Technical Field

[0001] The present invention belongs to the field of digital clock generation technology in the integrated circuit field, and more particularly, relates to a primary and secondary delay phase-locked loop with dual delay lines. Background Art

[0002] With the advancement of semiconductor technology and its continuous improvement, intelligent electronic devices have long become an integral part of our daily lives. These electronic devices rely on power supplies, which are widely used in all aspects of life. Clock generation circuits, as a crucial component of integrated circuit (IC) systems, have a direct impact on overall system performance. As chip operating frequencies increase, the requirements for clock signals are also increasing. Digital switching power supplies are a key trend. Digital pulse width modulation (DPWM) is a crucial component of digitally controlled switching power supplies.

[0003] The hybrid DPWM circuit combines a counter-compare structure and a delay line structure. The front stage uses the counter-compare structure for coarse adjustment to generate the set and reset signals for controlling the RS flip-flop. The back stage uses the delay line structure for fine adjustment to perform corresponding phase shift on the reset signal.

[0004] The two-stage delay line structure reduces the number of delay cells. A delay-locked loop (DLL) provides control voltage for the delay cells, minimizing external influences. Two DLL modules control the coarse and fine delay lines, respectively. However, the voltage-controlled delay line within the DLL controlling the fine delay line has more delay cells and occupies a larger layout area. Summary of the Invention

[0005] In order to overcome the problems in the prior art, the purpose of this application is to provide a primary and secondary delay phase-locked loop with dual delay lines, which avoids the use of long delay lines when controlling the coarse and fine delay lines of DPWM, ensuring that the secondary phase-locked loop is locked after the primary delay phase-locked loop is locked.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] A primary-secondary delay phase-locked loop with dual delay lines, comprising:

[0008] Power-on reset module POR, primary delay locked loop DLL1, secondary delay locked loop DLL2 and lock indication module LI; wherein,

[0009] The power-on reset module and the external reset signal are used to generate a system operation control signal;

[0010] The primary delay phase-locked loop includes a phase frequency detector module PFD1, a charge pump module CP1, a reset control module SC, a filter module Filter1 and a primary voltage-controlled delay line module VCDL1;

[0011] The secondary delay phase-locked loop includes a phase frequency detector module PFD2, a charge pump module CP2, a filter module Filter2 and a dual-chain voltage-controlled delay line module VCDL2;

[0012] The locking indication module is used to determine whether the two phase-locked loops have completed locking;

[0013] The power-on reset module is connected to the reset control module of the primary delay-locked loop, the output voltage signal V1 of the primary delay-locked loop is connected to the short link of the secondary dual-chain voltage-controlled delay line, the external input clock signal CLK is connected to the primary delay-locked loop and the secondary delay-locked loop, the total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector module PFD1 and the phase frequency detector module PFD2 are respectively connected to the lock indication module.

[0014] The voltage-controlled delay line in the secondary delay-locked loop is a double chain, and the delay unit in the first delay chain is the same as the delay unit in the primary delay line.

[0015] The reset signal of the power-on reset circuit is a ramp signal during the power-on process of the circuit power supply, which is used to prevent the phase-locked loop from incorrectly locking when powered on.

[0016] The lock indication module performs an exclusive OR operation on the two output signals of the phase frequency detector in the primary delay locked loop, and then performs an AND operation on the obtained signal after a short delay. The secondary delay locked loop performs the same operation, and the two signals finally obtained are subjected to an OR operation.

[0017] The delay time of the delay unit of the second delay chain of the secondary dual-chain voltage-controlled delay line is the accuracy of the digital pulse width modulator, and the total delay time of the delay chain is the delay time after the main delay unit is locked.

[0018] In the secondary delay-locked loop dual-chain structure, when the primary delay-locked loop is locked, the total time of the first chain of the secondary delay-locked loop is determined, the frequency detector input reference signal of the secondary delay line is determined, and its output signal controls the charging and discharging of the capacitor by the charge pump to lock the secondary delay-locked loop, thereby obtaining the locking voltage V2.

[0019] The delay time and number of delay units in the primary delay line are determined according to the period of the input clock signal, and the number and delay time of delay units in the secondary delay line are determined according to the delay accuracy and the number of delay units in the primary delay line.

[0020] The phase frequency detector modules PFD1 and PFD2 are provided with parasitic capacitance to precharge the circuit before the rising edge of the input signal, thereby increasing the circuit's operating rate. The circuit uses a smaller channel length and a larger width-to-length ratio to reduce the phase frequency detector conduction time.

[0021] The charge pump module CP1 and the charge pump module CP2 have charge and discharge switches located at the source end to reduce charge sharing.

[0022] Both the main-stage voltage-controlled delay line module VCDL1 and the dual-chain voltage-controlled delay line module VCDL2 are provided with delay units, which adopt a pseudo-differential structure to achieve voltage-controlled adjustment characteristics of the delay time by controlling the RC time constant of the output node. Increasing the control voltage increases the delay time.

[0023] Beneficial effects of the present invention:

[0024] The present invention adopts a primary and secondary delay phase-locked loop with dual delay lines. For a higher-precision digital pulse width modulation system, a hybrid DPWM structure is adopted. Without considering the delay units that maintain consistency in each delay line, if a single delay line structure is adopted for the fine adjustment part, there will be 2*(T / d2) delay units; if a primary and secondary DLL structure is adopted, there will be T / d2+2(T / d1)+d1 / d2 delay units; the structure proposed by the present invention requires 2(d1 / d2+T / d1)+4 delay units, where T is the clock period, d1 is the coarse delay unit delay time, and d2 is the fine delay unit delay time, that is, the precision. When higher precision is required, T / d2 is large, but the structure proposed by the present invention effectively avoids this problem, achieving the effect of reducing the number of delay units, thereby reducing the area of ​​the delay units in the layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a structural block diagram of a digital pulse width modulator provided in an example of the present invention.

[0026] Figure 2 This is a structural block diagram of the main-stage delay-locked loop and reset signal provided in an example of the present invention.

[0027] Figure 3 This is a structural block diagram of a secondary delay-locked loop provided in an example of the present invention.

[0028] Figure 4 This is a structural block diagram of a secondary delay-locked loop dual-chain delay line provided in an example of the present invention.

[0029] Figure 5 This is a general structural block diagram of a primary and secondary delay locked loop with dual delay lines provided in an example of the present invention.

[0030] Figure 6 This is a waveform diagram provided in an example of the present invention.

[0031] Figure 7 This is a structural block diagram of the system lock indication module provided in an example of the present invention.

[0032] Figure 1 In the figure, counter 101, comparator 102, coarse voltage-controlled delay line 103, fine voltage-controlled delay line 104, frequency divider 105, RS latch 106, data selector 1 (MUX1) 107, data selector 2 (MUX2) 108, primary and secondary delay-locked loop with dual delay lines 109;

[0033] Figure 2 In the embodiment, a phase frequency detector (PFD1) 201, a charge pump (CP1) 202, a filter (Filter1) 203, a main voltage controlled delay line (VCDL1) 204, a power-on reset circuit (POR) 205, and a reset circuit (SC) 206 are provided.

[0034] Figure 3 In the embodiment, a phase frequency detector (PFD2) 301, a charge pump (CP2) 302, a filter (Filter2) 303, and a dual-chain voltage-controlled delay line (VCDL2) 304 are provided;

[0035] Figure 4 In the middle, there are coarse delay units M1X and fine delay units M2X. DETAILED DESCRIPTION

[0036] In order to help those skilled in the art better understand the present invention, the following will clearly describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0037] The hybrid digital pulse-width modulation system consists of a counter-comparator for coarse modulation, with a clock period as the modulation precision. After the coarse modulation, the system enters a voltage-controlled delay line for fine modulation, with a minimum delay time as the modulation precision. The voltage-controlled delay line, with multiple delay units, generates multiple delayed clock signals, each delayed by a fixed time interval, based on the clock signal CLK. More specifically, the clock signal CLK is decomposed into a set of delayed clock signals with different phases or sequentially delayed by a time interval t, referred to as delayed clock signals. The output tap voltage of the voltage-controlled delay line is connected to a data selector to adjust the output delay time, thereby performing digital pulse-width modulation.

[0038] The delay-locked loop is composed of a phase frequency detector (PFD), a charge pump (CP), and a voltage-controlled delay line (VCDL). The PFD receives the reference clock from the system clock source and the clock fed back by the voltage-controlled delay chain, and compares the two clocks. According to the phase difference between the two clocks, if the reference clock signal is ahead of the feedback clock signal, an UP signal is generated. If the reference clock lags behind the feedback clock signal, a DN signal is generated. The corresponding UP and DN signals are transmitted to the charge pump to control the opening and closing of the charge pump current source and current sink, thereby charging and discharging the capacitor and generating the corresponding control voltage V ctrl , V ctrl The delay time of the delay unit in the VCDL is controlled and fed back to the phase frequency detector to adjust the phase of the feedback clock, which then enters the PFD again. This process is repeated to eventually generate a stable voltage output.

[0039] like Figure 1 The figure shows the principle diagram of the hybrid digital pulse width modulation structure. The hybrid DPWM structure includes a counter circuit 101, a comparator circuit 102, a coarse voltage-controlled delay line 103, a fine voltage-controlled delay line 104, a frequency divider 105, an RS latch 106, a data selector 107 and a data selector 2 108, and a primary and secondary delay locked loop (DLL circuit) 109. The counter 101 inputs a signal CLK.

[0040] CLK is a high-frequency clock. The clock passes through counter 101 and comparator 102 to obtain a low-frequency clock. The low-frequency clock enters coarse voltage-controlled delay line 103. The tap of the delay unit of coarse voltage-controlled delay line 103 is connected to data selector 107. The input signal of data selector 1 is the high-order signal of the delay control code. The output signal enters fine delay line 104. The tap of the delay unit of fine delay line 104 is connected to data selector 2 108. The input signal of data selector 2 is the low-order signal of the delay control code. The delayed output signal and the high-frequency clock signal divided by the divider enter the latch together, and finally the DPWM signal is obtained.

[0041] In this embodiment, if Figure 1As shown, the primary voltage-controlled delay line 103 can be divided into 8 delay units M11-M18, and the secondary voltage-controlled delay line 104 can be divided into 8 delay units M21-M28. Each unit of the output 8 delayed clock signals M1 is delayed by 1 / 8 of the clock cycle, and the output 8 delayed clock signals clk <0> , clk <1> … clk <7> , represented as clk<7:0>; M2 can be divided into 1 / 64 clock cycles, and the output of 8 delayed clock signals clk <8> , clk <9> … clk <15> , represented as clk<15:8>. For example, if the input clock frequency is 80MHz and the period is 12.5ns, then the delay after a coarse delay unit is 1.56ns, and the delay after a fine delay unit is 195ps. By analogy, the clock signal CLK after passing through the delay circuit is obtained as follows Figure 1 A set of delayed clock signals clk<15:0> is shown.

[0042] A primary and secondary delay-locked loop (109) with dual delay lines includes a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module, the primary delay-locked loop (DLL), and the secondary delay-locked loop (DLL) are sequentially connected to obtain control voltages V1 and V2 of two delay chain delay cells. The control voltages are connected to the delay chain of a DPWM system to ultimately generate an analog duty cycle signal.

[0043] When the main delay-locked loop is working, the input clock signal passes through the frequency detector, the charge pump, and the voltage-controlled delay chain to obtain the signal F1. div , F1 div The input is sent to another port of the phase frequency detector. The phase frequency detector determines the phase difference between the two signals and outputs UP and DN signals. The UP and DN signals are input to the charge pump to control the charge pump to charge and discharge the capacitor, and the voltage V1 on the capacitor is obtained. V1 is input to the voltage-controlled delay unit to change the output signal F1. div After this feedback process, DLL1 reaches the locked state and locks the voltage V1;

[0044] like Figure 2As shown, the main-stage delay-locked loop (DLL) DLL1 circuit includes a phase frequency detector (PFD1) 201, a charge pump (CP1) 202, a filter (Filter1) 203, a main-stage voltage-controlled delay line (VCDL1) 204, and a reset circuit (SC) 205. The voltage-controlled delay line is composed of a voltage-controlled delay unit M1. The clock signal CLK provides a reference clock with a period of T for the entire digital pulse width modulation circuit. The input end of the phase frequency detector is connected to the clock signal CLK. The reference clock passes through the phase frequency detector 201 to generate two signals, UP1 and DN1, which are connected to the charge pump 202 to control the charge pump switch. The charge pump 202 controls the charging and discharging of the capacitor in the filter circuit 203 to generate V1. V1 is connected to the voltage-controlled delay line 204. The clock signal of the voltage-controlled delay line is the system clock CLK, and the control voltage is the filter output voltage V1. The signal passes through the voltage-controlled delay line 204 to output the signal F1. div , F1 div Feedback is sent to another input port of the frequency detector and phase detector, and so on. After the feedback loop reaches stability, CLK and F1 div The difference is one cycle, that is, a rising edge of CLK is obtained after a series of delays F1 div , at this time F1 div It coincides with CLK, but F1 div Lagging behind CLK by one cycle.

[0045] The secondary delay-locked loop (DLL) consists of a phase frequency detector (PFD) module, a charge pump module, and a dual-chain voltage-controlled delay line (VCD) module. The dual-chain VCD consists of delay cells M1X from the primary VCD and M2X from the secondary VCD. The primary DLL (VCDL1) has eight delay cells M1X, while the secondary VCDL2 has both M1X and M2X delay cells. The total delay time of the secondary delay cells M2X equals the delay time of a single M1X module in the primary VCDL1. The lock state of the secondary DLL2 is determined by the lock voltage V1 of the primary DLL1 and its own feedback, ensuring that the DLL2 circuit locks after the DLL1 circuit locks.

[0046] like Figure 3 The structure of the secondary delay locked loop (DLL2) is shown in FIG. 3 . The input signal of the frequency detector 301 is the output signal F of the dual-chain voltage-controlled delay line 304. ref and F div The output signal of the phase frequency detector 301 is connected to the charge pump 302. The charge pump 302 controls the charging and discharging of the capacitor in the filter 303 to obtain a voltage V2. V2 is connected to the dual-chain voltage-controlled delay line 304.

[0047] The first delay chain of the dual-chain voltage-controlled delay line is a coarse delay chain, whose delay unit is the delay unit M1X of the main delay phase-locked loop. The second delay chain is a fine delay chain, whose delay unit is M2X. When the phase-locked loop is locked, the total delay time of the two chains is the same. The signal returned by the input clock through the first delay chain is F ref As the first input signal of the frequency detector, the signal returned by the input clock through the second delay chain is F div As the second input signal of the phase frequency detector.

[0048] like Figure 4 The figure shows the structure of the double-chain delay locked loop 304 of the secondary delay locked loop DLL2. The CLK input is connected to the delay line 401 and the delay line 402 respectively after passing through a buffer delay unit M11. The output signal of CLK after the delay line 401 is F ref , the output signal after delay line 402 is F div The input signal V1 is the output voltage of the main stage voltage-controlled delay line.

[0049] Figure 4 The total delay time of 8 M2X is the delay time of 1 M1X, and the delay time of M21-M28 is equal to the delay time of M12, that is,

[0050] M11+M21+⋯+M28+M15=M11+M12+M13

[0051] M21+⋯+M29=M12.

[0052] F ref When the primary delay-locked loop is not locked, the phase of the signal is unstable, so the secondary delay-locked loop is also in an unlocked state. When the primary delay-locked loop is not locked, the delay time of each delay unit in the low-precision delay chain is not fixed, so the high-precision delay chain cannot be locked either. This ensures that DLL2 is locked after DLL1. After the primary delay-locked loop is locked, F ref The phase is stable, the frequency detector, charge pump and second delay chain of the secondary delay phase-locked loop start to work in phase lock, and finally F ref With F div The same phase is reached, and the secondary delay locked loop is locked, with the locking voltage being V2.

[0053] In this example, V1 is the control voltage of the voltage-controlled delay line 401, and CLK outputs the signal F through the voltage-controlled delay line 401. ref , CLK outputs signal F through voltage-controlled delay line 402 div , when the main delay-locked loop is stable, F ref The phase of the secondary delay phase-locked loop no longer changes, and the system feedback loop of the secondary delay phase-locked loop can reach stability. At this time, F refWith F div To ensure consistency with the DPWM circuit, each delay unit in 109 is followed by a load identical to the MUX input stage.

[0054] like Figure 6 As shown in this example, T=12.5ns, assuming d1=1.56ns, d2=195ps, that is, after the delay phase-locked loop is locked, the delay time of each M1 is 1.56ns, and the delay time of each M2 is 195ps, then n=T / d1=8, m=d1 / d2=8, if a single delay line structure is used, 2mn=128 delay units are required, and the primary and secondary delay phase-locked loop structure requires mn+2n+m=88 delay units. The structure of the invention requires 2(m+n)+4=36 delay units, which can effectively reduce the number of delay units.

[0055] The POR (Power On Reset) circuit 206 uses a ramp signal as the power-on voltage to prevent the delayed phase-locked loop from locking when the system operating voltage is not reached. The power-on reset signal and the external reset signal together constitute the input signal of the reset module. The POR circuit ensures that there will be no false lock during the power-on process. In addition, an off-chip reset signal and reset circuit 205 are added to the circuit, which together with the external Reset_in signal form the reset signal Reset.

[0056] like Figure 2 201 and 301 in FIG3 are pre-charged phase frequency detectors. Before the rising edge of the input signal arrives, the circuit will be pre-charged due to the presence of parasitic capacitance to increase the operating rate of the circuit. The circuit adopts a smaller channel length and a larger width-to-length ratio to reduce the PFD conduction time.

[0057] like Figure 2 The 205 circuit in the circuit is based on the D flip-flop. When the system starts normally, the Start signal is low, which resets the D flip-flop and generates a Reset signal to make the initial values ​​of the control voltages V1 and V2 zero.

[0058] like Figure 5 The figure shows the overall structure of 109 , where the input signal is the high-frequency clock CLK, and the output signal is the voltage V1 of the voltage-controlled delay line 103 and the voltage V2 of the voltage-controlled delay line 104 .

[0059] like Figure 7 The lock indication module 501 (LI) shown is composed of an exclusive-OR operation, an AND operation, an OR operation, and a delay module. It performs an exclusive-OR operation on the output signal of the phase frequency detector in the primary delay-locked phase-locked loop to obtain signal D11; and performs an exclusive-OR operation on the output signal of the phase frequency detector in the secondary delay-locked phase-locked loop to obtain signal D21.

[0060] The D11 signal passes through the delay module to obtain signal D12. The AND operation of D12 and D11 obtains signal S1. When the S1 signal is low and remains unchanged, it means that the primary delay-locked loop is locked. The D21 signal passes through the delay module to obtain signal D22. The AND operation of D22 and D21 obtains signal S2. When the S2 signal is low and remains unchanged, it means that the secondary delay-locked loop is locked. The S1 and S2 signals are ORed to obtain signal LI. When LI is low and remains unchanged, it means that the entire system is locked.

[0061] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A primary and secondary delay locked loop with dual delay lines, characterized in that: include: Power-on reset module POR, primary delay locked loop DLL1, secondary delay locked loop DLL2 and lock indication module LI; wherein, The power-on reset module and the external reset signal are used to generate a system operation control signal; The primary delay phase-locked loop includes a phase frequency detector module PFD1, a charge pump module CP1, a reset circuit SC, a filter module Filter1 and a primary voltage-controlled delay line module VCDL1; The secondary delay phase-locked loop includes a phase frequency detector module PFD2, a charge pump module CP2, a filter module Filter2 and a dual-chain voltage-controlled delay line module VCDL2; The locking indication module is used to determine whether the two phase-locked loops have completed locking; The power-on reset module is connected to the reset control module of the primary delay-locked loop, the output voltage signal V1 of the primary delay-locked loop is connected to the short link of the secondary dual-chain voltage-controlled delay line, the external input clock signal CLK is connected to the primary delay-locked loop and the secondary delay-locked loop, the total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector module PFD1 and the phase frequency detector module PFD2 are respectively connected to the lock indication module.

2. A primary and secondary delay locked loop with dual delay lines according to claim 1, characterized in that: The voltage-controlled delay line in the secondary delay-locked loop is a double chain, and the delay unit in the first delay chain is the same as the delay unit in the primary delay line.

3. The primary and secondary delay locked loop with dual delay lines according to claim 1, wherein: The reset signal of the circuit of the power-on reset module is a ramp signal during the power-on process of the circuit power supply, which is used to prevent the phase-locked loop from incorrectly locking when powered on.

4. The primary and secondary delay locked loop with dual delay lines according to claim 1, wherein: The lock indication module performs an exclusive OR operation on the two output signals of the phase frequency detector in the primary delay locked loop, and then performs an AND operation on the obtained signal after a short delay. The secondary delay locked loop performs the same operation, and the two signals finally obtained are subjected to an OR operation.

5. The primary and secondary delay locked loop with dual delay lines according to claim 2, characterized in that: In the secondary delay-locked loop dual-chain structure, when the primary delay-locked loop is locked, the total time of the first chain of the secondary delay-locked loop is determined, the frequency detector input reference signal of the secondary delay line is determined, and its output signal controls the charging and discharging of the capacitor by the charge pump to lock the secondary delay-locked loop, thereby obtaining the locking voltage V2.

6. A primary-secondary delay phase-locked loop with dual delay lines according to any one of claims 1 to 5, characterized in that: The delay time and number of delay units in the primary delay line are determined according to the period of the input clock signal, and the number and delay time of delay units in the secondary delay line are determined according to the delay accuracy and the number of delay units in the primary delay line.

7. The primary and secondary delay locked loop with dual delay lines according to claim 1, characterized in that: The phase frequency detector modules PFD1 and PFD2 are provided with parasitic capacitance to precharge the circuit before the rising edge of the input signal, thereby increasing the circuit's operating rate. The circuit uses a smaller channel length and a larger width-to-length ratio to reduce the phase frequency detector conduction time.

8. The primary and secondary delay locked loop with dual delay lines according to claim 1, characterized in that: The charge pump module CP1 and the charge pump module CP2 have charge and discharge switches located at the source end to reduce charge sharing.

9. The primary and secondary delay locked loop with dual delay lines according to claim 1, wherein: Both the main-stage voltage-controlled delay line module VCDL1 and the dual-chain voltage-controlled delay line module VCDL2 are provided with delay units, which adopt a pseudo-differential structure to achieve voltage-controlled adjustment characteristics of the delay time by controlling the RC time constant of the output node. Increasing the control voltage increases the delay time.

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