Circuit and chip for preventing false triggering

Abstract

The application discloses a circuit and a chip for preventing mis-triggering, which comprises a first power regulator, a main circuit load, a second power regulator, a static load and a control circuit. The first power regulator and the second power regulator are connected with a power-on reset circuit; the static load is connected with the power-on reset circuit; and the control circuit is connected with the power-on reset circuit, the first power regulator and the main circuit load. The circuit for preventing mis-triggering of the application adopts the mode of copying the first power regulator to obtain the second power regulator and the static load without jump, and the power-on reset circuit switches from monitoring the first output voltage and the second output voltage simultaneously to monitoring only the second output voltage from the power-on process to the completion of the power-on, which effectively reflects the power voltage change of the main circuit load and avoids the mis-triggering problem of the power-on reset circuit caused by the glitch of the main circuit load jump.

Claims

1. A circuit for preventing false triggering, comprising: A first power regulator, a main circuit load, and a power-on reset circuit are interconnected, wherein the first power regulator outputs a first output voltage to the main circuit load based on a first input voltage, characterized in that the circuit further includes: The second power regulator is connected to the power-on reset circuit. The second power regulator outputs a second output voltage based on the second input voltage. The first input voltage and the second input voltage are the same, and the first output voltage and the second output voltage are the same. The static load is connected to the second power regulator and the power-on reset circuit; and The control circuit, connected to the power-on reset circuit, the first power regulator, and the main circuit load, is used to control the connection and disconnection between the main circuit load and the node connected to the first power regulator and the power-on reset circuit; The power-on reset circuit is used to monitor the first output voltage of the first power regulator and the second output voltage of the second power regulator during the power-on process, and output a valid control signal when the first output voltage and the second output voltage exceed a threshold. The control circuit is used to control the connection between the node of the main circuit load connected to the first power regulator and the power-on reset circuit to be disconnected based on the valid control signal after power-on, so that the power-on reset circuit only monitors the second output voltage of the second power regulator.

2. The circuit for preventing false triggering as described in claim 1, characterized in that, The circuit also includes several reference sources. If there is one reference source, it is connected to both the first power regulator and the second power regulator to provide a first input voltage and a second input voltage. If there are two reference sources with the same structure, they are connected to the first power regulator and the second power regulator respectively to provide a first input voltage and a second input voltage respectively.

3. The circuit for preventing false triggering as described in claim 1, characterized in that, The static load is a device or circuit that generates a fixed current under a fixed voltage or does not generate a jump current or voltage under a fixed voltage.

4. The circuit for preventing false triggering as described in claim 2, characterized in that, The static load includes a resistor, a MOSFET used as a diode, and / or a current mirror.

5. The circuit for preventing false triggering as described in claim 1, characterized in that, The second power regulator provides a fixed voltage or current within a preset load range.

6. The circuit for preventing false triggering as described in claim 1, characterized in that, The first power regulator includes a first amplifier, a first MOSFET, and a first resistor. The first input terminal of the first amplifier is used to receive a first input voltage. The output terminal of the first amplifier is connected to the gate of the first MOSFET. The source of the first MOSFET is connected to the power supply voltage. The drain of the first MOSFET is connected to the first terminal of the first resistor, the second input terminal of the first amplifier, and the main circuit load. The second terminal of the first resistor is connected to the ground voltage.

7. The circuit for preventing false triggering as described in claim 1, characterized in that, The second power regulator includes a second amplifier, a second MOSFET, and a second resistor. The first input terminal of the second amplifier is used to receive a second input voltage. The output terminal of the second amplifier is connected to the gate of the second MOSFET. The source of the second MOSFET is connected to the power supply voltage. The drain of the second MOSFET is connected to the first terminal of the second resistor, the second input terminal of the second amplifier, and the static load. The second terminal of the second resistor is connected to the ground voltage.

8. The circuit for preventing false triggering as described in claim 6, characterized in that, The second power regulator includes a third MOSFET and a third resistor. The gate of the third MOSFET is connected to the output terminal of the first amplifier, the source of the third MOSFET is connected to the power supply voltage, the drain of the third MOSFET is connected to the first terminal of the third resistor and the static load, and the second terminal of the third resistor is connected to the ground voltage.

9. The circuit for preventing false triggering as described in claim 1, characterized in that, The control circuit includes a first switch and a drive circuit. The first end of the first switch is connected to the main circuit load and the first power regulator, and the second end of the first switch is connected to the power-on reset circuit. The drive circuit is connected to the power-on reset circuit and the first switch to control the closing and opening of the first switch.

10. A chip, characterized in that, Includes the circuit for preventing false triggering as described in any one of claims 1 to 9.

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