Phase-locked loop circuit based on PID control

Abstract

The invention discloses a phase-locked loop circuit based on PID control, and relates to the technical field of integrated circuits, and the main points of the technical scheme are that the phase-locked loop circuit comprises a phase frequency detector, a PID gain module, an oscillator, a self-adaptive PID controller and a frequency divider; the PID gain module comprises three gain paths, and the three gain paths respectively carry out proportional, integral and differential control on the received clock error signals and superpose and output the signals to the oscillator; the oscillator generates an oscillation signal, the frequency divider outputs a feedback clock signal after carrying out frequency division on the oscillation signal, and the adaptive PID controller is provided with a plurality of gain control ends corresponding to gain paths; in the self-adaptive PID controller, phase detection is carried out on a feedback clock signal, a feedback phase signal is generated, combinational logic processing is carried out on the feedback phase signal, a gain control signal corresponding to the gain path is generated, and therefore the oscillation signal is adjusted. The method has the characteristics of reducing overshoot, improving the stability of the system and being flexible in control.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a phase-locked loop circuit based on PID control. Background Art

[0002] Phase-locked loops play a key role in modern electronic and communication systems, and their functions and performances directly affect the stability, reliability, and efficiency of the systems. In wireless communication, phase-locked loops are required to have low phase noise and reference spurs. Since wireless communication requires frequent frequency hopping operations, phase-locked loops need a fast locking speed. In wired communication, with the development of high-speed serial links and chiplet technology, different protocol standards have different requirements for line rates, so phase-locked loops with specific output frequency ranges and clock jitters are required for different protocol standards. With the increasing demand for physical layers compatible with different protocol standards, higher requirements are put forward for the on-chip integration ability of phase-locked loops and the reconfigurability of loop parameters.

[0003] To reduce the locking time of the phase-locked loop, the traditional solution is to increase its loop bandwidth. When the loop bandwidth increases, the locking time decreases. However, the increase in bandwidth leads to an increase in the phase noise and reference spurs of the phase-locked loop. This is because the phase-locked loop system is equivalent to a low-pass filter for the output noise of the reference clock and charge pump, and a larger loop bandwidth results in a greater contribution of the noise of these two to the total output noise. Therefore, simply increasing the loop bandwidth of the phase-locked loop to obtain fast locking is not a feasible solution.

[0004] In addition, traditional proportional-integral phase-locked loops have some limitations, especially in terms of flexibility and adaptability. Proportional-integral phase-locked loops usually only contain proportional and integral parts, which limits their adjustment ability in the face of complex system dynamics. The proportional control part can quickly respond to changes in the input signal, while the integral part helps to eliminate the steady-state error, but this combination may not be sufficient to cope with all types of system disturbances and uncertainties. Summary of the Invention

[0005] Aiming at the problems existing in the prior art, the first object of the present invention is to provide a phase-locked loop circuit based on PID control, which is characterized by being able to predict the change trend of the error, so as to make adjustments in advance to reduce overshoot and improve the stability of the system.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A phase-locked loop circuit based on PID control includes a frequency discriminator / phase discriminator, a PID gain module, an oscillator, an adaptive PID controller, and a frequency divider; wherein,

[0008] The two input terminals of the frequency discriminator and phase detector are respectively connected to the reference clock source and the frequency divider, receive the reference clock signal output by the reference clock source and the feedback clock signal output by the frequency divider, and generate a clock error signal representing the phase difference;

[0009] The PID gain module includes three gain paths, namely the proportional gain path, the integral gain path, and the differential gain path. The three gain paths are respectively connected to the output terminal of the frequency discriminator and phase detector to receive the clock error signal; the three gain paths respectively perform proportional, integral, and differential control on the received clock error signal, and respectively output a proportional gain signal, an integral gain signal, and a differential gain signal. The proportional gain signal, the integral gain signal, and the differential gain signal are superimposed to form the input signal of the oscillator and output to the oscillator;

[0010] The output terminal of the oscillator is connected to the input terminal of the frequency divider. The oscillator generates an oscillation signal based on the input signal of the oscillator, and the frequency divider divides the oscillation signal and outputs the feedback clock signal;

[0011] The output terminal of the frequency divider is connected to the input terminal of the adaptive PID controller;

[0012] The adaptive PID controller is provided with a plurality of gain control terminals corresponding to the gain paths, including a proportional gain control terminal, an integral gain control terminal, and a differential gain control terminal; the proportional gain control terminal, the integral gain control terminal, and the differential gain control terminal are respectively connected to the corresponding gain paths in the PID gain module; in the adaptive PID controller, the phase of the feedback clock signal is detected to generate a feedback phase signal, and the feedback phase signal is subjected to combinational logic processing to generate a gain control signal corresponding to the gain path. The gain control signal includes a proportional gain control signal, an integral gain control signal, and a differential gain control signal. The gain control signal is sent to the corresponding gain path through the gain control terminal to adjust the magnitudes of the proportional gain signal, the integral gain signal, and the differential gain signal, thereby adjusting the oscillation signal.

[0013] Furthermore, the adaptive PID controller includes a phase detector, a combinational logic module, and a gain control terminal; wherein, the phase detector is used to detect the phase of the feedback clock signal to generate a feedback phase signal; the combinational logic module is used to perform combinational logic processing on the feedback phase signal to generate a gain control signal; the gain control terminal is used to send the gain control signal to the corresponding gain path to adjust the magnitudes of the proportional gain signal, the integral gain signal, and the differential gain signal.

[0014] Further, a proportional path switch, an integral path switch, and a differential path switch are respectively arranged on the three gain paths, which are used to independently control the on / off of the proportional gain path, the integral gain path, and the differential gain path. The proportional path switch, the integral path switch, and the differential path switch are arranged between the output end of the corresponding gain path and the oscillator.

[0015] Further, the proportional gain path, the integral gain path, and the differential gain path all respectively include a phase difference pulse conversion module and a corresponding filter; in any gain path, the input end of the phase difference pulse conversion module is connected to the output end of the frequency discriminator and phase detector, and the output end of the phase difference pulse conversion module is connected to the input end of the filter; among them, the proportional gain path includes a phase difference pulse conversion module and a proportional gain filter; the integral gain path includes a phase difference pulse conversion module and an integral gain filter; the differential gain path includes a phase difference pulse conversion module and a differential gain filter.

[0016] Further, the phase difference pulse conversion modules in the proportional gain path, the integral gain path, and the differential gain path are respectively independently arranged.

[0017] Further, the phase difference pulse conversion module is used to convert the clock error signal into a current pulse signal; the phase difference pulse conversion module includes one or more current units. The current units receive a reference current and a clock error signal, and convert the clock error signal into a current pulse sub-signal. The current pulse signal is the superposition of all current pulse sub-signals; the current pulse signal output by the phase difference pulse conversion module is the superposition of the current pulse sub-signals output by all current units.

[0018] Further, the phase difference pulse conversion module further includes a current mirror for providing a reference current, and the current mirror is used to copy the reference current to the current unit.

[0019] Further, the phase difference pulse conversion module includes a plurality of current units. The current of the current pulse sub-signal output by each current unit increases according to the binary multiple relationship of the reference current. Each current unit is provided with an EN switch, and whether the current unit outputs a current pulse sub-signal is controlled by the EN switch; by setting the switch state of the EN switch of each current unit, the current regulation of the current pulse signal is realized.

[0020] Preferably, the gain control terminal includes a proportional gain control terminal, an integral gain control terminal, and a differential gain control terminal; among them,

[0021] The proportional gain control terminal includes a proportional gain amount control terminal and a proportional gain enable control terminal. Among them, the proportional gain amount control terminal is connected to the EN switch in the proportional gain path, and the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path;

[0022] The integral gain control terminal includes an integral gain amount control terminal and an integral gain enable control terminal. Among them, the integral gain amount control terminal is connected to the EN switch in the integral gain path, and the integral gain enable control terminal is connected to the integral path switch in the integral gain path;

[0023] The differential gain control terminal includes a differential gain amount control terminal and a differential gain enable control terminal. Among them, the differential gain amount control terminal is connected to the EN switch in the differential gain path, and the differential gain enable control terminal is connected to the differential path switch in the differential gain path.

[0024] Preferably, the gain control terminal includes a proportional gain control terminal, an integral gain control terminal, and a differential gain control terminal; among them,

[0025] The proportional gain control terminal includes a proportional gain enable control terminal, and the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path;

[0026] The integral gain control terminal includes an integral gain enable control terminal, and the integral gain enable control terminal is connected to the integral path switch in the integral gain path;

[0027] The differential gain control terminal includes a differential gain enable control terminal, and the differential gain enable control terminal is connected to the differential path switch in the differential gain path.

[0028] The beneficial effects of the present invention are as follows: The PLL combined architecture based on PID control provided by the present invention adds a differential part on the basis of the proportional-integral control strategy compared with the traditional PLL, which can predict the change trend of the error, so as to make adjustments in advance to reduce overshoot and improve the stability of the system. The three parameters (proportional, integral, differential) of PID control can be adjusted independently, and the locking time can be improved without increasing the bandwidth and sacrificing the phase noise performance, realizing the decoupling of the loop bandwidth and the locking time. In addition, the three parameters of the PID controller can be arbitrarily combined and adjusted according to needs to adapt to different control requirements. Description of the Drawings

[0029] Figure 1 It is a schematic diagram of the PLL circuit structure of the present invention;

[0030] Figure 2 It is a schematic diagram of the PLL circuit structure of the embodiment;

[0031] Figure 3 It is a schematic diagram of the phase difference pulse conversion module structure of the embodiment;

[0032] Figure 4 It is a schematic diagram of the active inductor circuit structure of the embodiment;

[0033] Figure 5 Schematic diagram of the adaptive PID controller of the embodiment.

[0034] Reference numerals: 10, phase frequency detector; 11, proportional gain path; 12, integral gain path; 13, derivative gain path; 14, oscillator; 15, adaptive PID controller; 16, frequency divider; 101, first D flip-flop; 102, second D flip-flop; 103, AND logic gate; 104, delay unit; 2, phase difference pulse conversion module; 20, current mirror; 21, PMOS current source; 22, PMOS transistor assembly; 23, PMOS switch transistor assembly; 24, NMOS current source; 25, NMOS transistor assembly; 26, NMOS switch transistor assembly; 27, operational amplifier; 201, reference current source; 202, first NMOS transistor; 203, second NMOS transistor; 204, first PMOS transistor; 231, second PMOS transistor, 232, third PMOS transistor; 261, third NMOS transistor, 262, fourth NMOS transistor; 30, phase detector; 31, combinational logic module; 32, gain control terminal; 321, proportional gain control terminal; 322, integral gain control terminal; 323, derivative gain control terminal; 33, proportional gain filter; 34, integral gain filter; 35, derivative gain filter; 41, first transconductance amplifier; 42, second transconductance amplifier; 43, load capacitor. Detailed implementation manners

[0035] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0037] It should be noted that: like reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It should be noted that the terms "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to the directions in the drawings, and the terms "bottom surface" and "top surface", "inner" and "outer" refer to the directions towards or away from the geometric center of a specific component, respectively.

[0038] The existing phase-locked loops mainly have the following problems: 1. The trade-off contradiction between the loop bandwidth and the locking time of the phase-locked loop; 2. The lack of flexibility and adaptability of the traditional proportional-integral phase-locked loop.

[0039] To solve the problems existing in the prior art, the present invention provides a phase-locked loop circuit based on PID control, including a frequency discriminator and phase detector, a PID gain module, an oscillator, an adaptive PID controller, and a frequency divider. Among them, the frequency discriminator and phase detector is used to receive a reference clock signal and a feedback clock signal and generate a clock error signal.

[0040] The PID gain module is used to receive the clock error signal, generate proportional, integral, and differential control quantities, and output an oscillator control signal.

[0041] The PID gain module includes a parallel proportional gain path, an integral gain path, and a differential gain path; among them,

[0042] The proportional gain path includes a phase difference pulse conversion module and a proportional gain filter, and is used to perform proportional control on the received clock error signal and output a proportional gain signal;

[0043] The integral gain path includes a phase difference pulse conversion module and an integral gain filter, and is used to perform integral control on the clock error signal and output an integral gain signal;

[0044] The differential gain path includes a phase difference pulse conversion module and a differential gain filter, and is used to perform differential control on the clock error signal and output a differential gain signal.

[0045] The above-mentioned proportional gain signal, integral gain signal, and differential gain signal are superimposed and output to the input end of the oscillator.

[0046] The oscillator is used to receive the proportional gain signal, integral gain signal, and differential gain signal output by the superimposed PID gain module and generate an oscillation signal.

[0047] The adaptive PID controller is used to receive the feedback clock signal and generate a gain control signal. The gain control signal includes a proportional gain control signal, an integral gain control signal, and a differential gain control signal.

[0048] Among them,

[0049] The proportional gain control signal is used to adjust the magnitude of the proportional gain signal output by the proportional gain path;

[0050] The integral gain control signal is used to adjust the magnitude of the integral gain signal output by the integral gain path;

[0051] The differential gain control signal is used to adjust the magnitude of the differential gain signal output by the differential gain path. The adaptive PID controller outputs the proportional gain control signal, the integral gain control signal, and the differential gain control signal to the proportional gain path, the integral gain path, and the differential gain path of the PID gain module respectively.

[0052] The frequency divider is used to receive the oscillation signal, generate a feedback clock signal, and output the feedback clock signal to the input end of the adaptive PID controller and the input end of the frequency discriminator and phase detector.

[0053] As Figure 1 shown, the two input ends of the frequency discriminator and phase detector 10 are respectively connected to the reference clock source and the frequency divider 16, and receive the reference clock signal ref_clk output by the reference clock source and the feedback clock signal fb_clk output by the frequency divider 16. The proportional gain path 11, the integral gain path 12, and the differential gain path 13 in the PID gain module are connected in parallel and connected to the output end of the frequency discriminator and phase detector 10 to receive the clock error signal. The output ends of the proportional gain path 11, the integral gain path 12, and the differential gain path 13 of the PID gain module are respectively connected to the input end of the adder, and the output end of the adder is connected to the input end of the oscillator 14. In some embodiments, since the proportional gain signal, the integral gain signal, and the differential gain signal output by the PID gain module are all current signals, and based on the characteristics of the parallel circuit, there is no need to use an adder. After the proportional gain path, the integral gain path, and the differential gain path are connected in parallel, the output end is directly connected to the input end of the oscillator.

[0054] The output end of the oscillator 14 is connected to the input end of the frequency divider 16. The input signal of the oscillator generates an oscillation signal through the oscillator, and the frequency divider divides the oscillation signal and outputs a feedback clock signal.

[0055] The output end of the frequency divider 16 is connected to the input end of the adaptive PID controller 15. The adaptive PID controller is provided with a plurality of gain control ends, including a proportional gain control end 321, an integral gain control end 322, and a differential gain control end 323; the proportional gain control end 321, the integral gain control end 322, and the differential gain control end 323 are respectively connected to the control input ends of the proportional gain path 11, the integral gain path 12, and the differential gain path 13 of the PID gain module. In the adaptive PID controller, after the feedback clock signal is detected by the phase detector, a feedback phase signal is generated. After the feedback phase signal is processed by the combinational logic module, a gain control signal is generated, and the gain control signal respectively adjusts the magnitudes of the gain signals output by the proportional gain path, the integral gain path, and the differential gain path.

[0056] The proportional gain control of the present invention associates the control quantity with the current error proportionally. The greater the error, the stronger the control action. The integral control can eliminate the steady-state error. It integrates the error, that is, accumulates it over time. This can ensure that the error accumulated over a long time is eliminated, enabling the system to finally reach the set value. The derivative control is based on the rate of change of the error, that is, predicting the trend of the error. By adjusting the control quantity to counteract the change of the error, the oscillation and overshoot of the system can be reduced.

[0057] Compared with the traditional phase-locked loop, the loop filter composed of proportional, integral, and derivative gains (PID) adds derivative gain to the traditional proportional-integral filter, making the loop dynamic performance of the phase-locked loop more sensitive. Through the adaptive PID controller, independent adjustment of the proportional, integral, and derivative gains can be achieved. At the same time, the adaptive PID controller can also achieve different filter gain combinations of the phase-locked loop at different locking stages to adapt to different control requirements.

[0058] The above is the core idea of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by this application. Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0059] Embodiment: A phase-locked loop circuit based on PID control, as Figure 2 shown, includes a frequency discriminator and phase detector 10, a PID gain module, an oscillator 14, an adaptive PID controller 15, and a frequency divider 16.

[0060] Specifically, the frequency discriminator and phase detector 10 includes two D flip-flops with asynchronous set, an AND logic gate for feedback clearing, and a delay unit. For ease of explanation, the above two D flip-flops are respectively denoted as the first D flip-flop 101 and the second D flip-flop 102. The D terminals of the first D flip-flop 101 and the second D flip-flop 102 are both connected to a high level, and they share an asynchronous set terminal. The first D flip-flop 101 and the second D flip-flop 102 respond to different clock signals respectively. The Clk terminal of the first D flip-flop 101 is connected to a reference clock source, and the reference clock source provides a reference clock signal for the first D flip-flop, that is, the input clock signal of the first D flip-flop is the reference clock signal; the Clk terminal of the second D flip-flop 102 is connected to a frequency divider 16, and the frequency divider 16 provides a feedback clock signal for the second D flip-flop, that is, the input clock signal of the second D flip-flop is the feedback clock signal. The Q terminal of the first D flip-flop 101 is connected to one input terminal of the AND logic gate 103 and is used to output the UP signal; the Q terminal of the second D flip-flop 102 is connected to the other input terminal of the AND logic gate 103 and is used to output the DN signal. The output terminal of the AND logic gate 103 is connected to the input terminal of the delay unit 104, and the output terminal of the delay unit 104 is connected to the asynchronous set terminal shared by the first D flip-flop 101 and the second D flip-flop 102. The function of the delay unit is that when the two input signals of the frequency discriminator and phase detector are of the same frequency and in phase, the output pulse has sufficient width (delay time) to turn on or off the switching transistor used as the charge and discharge switch in the charge pump, thereby avoiding the occurrence of dead zone effect. The frequency discriminator and phase detector arranged in this way can receive the reference clock signal and the feedback clock signal and generate a clock error signal. Since the D flip-flop responds quickly, the frequency discriminator and phase detector can detect the phase difference between the reference clock signal and the feedback clock signal without dead zone, and also has a self-resetting function to avoid the situation where the UP and DN signals are both valid at the same time.

[0061] The operation of the frequency discriminator and phase detector is as follows: When the reference clock signal and the feedback clock signal arrive simultaneously, the two D flip-flops almost simultaneously output a high level, immediately triggering a reset, generating a very narrow reset pulse, and the output UP signal and DN signal are almost zero; When the reference clock signal arrives before the feedback clock signal, the Q terminal of the first D flip-flop is first set high. Until the feedback clock signal arrives, the Q terminal of the second D flip-flop is set high, triggering a reset, and then a UP pulse signal proportional to the phase difference is generated; When the reference clock signal arrives after the feedback clock signal, the Q terminal of the second D flip-flop is first set high. Until the reference clock signal arrives, the Q terminal of the first D flip-flop is set high, triggering a reset, and then a DN pulse signal proportional to the phase difference is generated; When the frequencies of the reference clock signal and the feedback clock signal are different, the greater the frequency difference, the longer the duration of the UP or DN pulse signal, thereby providing frequency adjustment information to the subsequent circuit. The above UP signal and DN signal are the output signals of the frequency discriminator and phase detector, that is, the above clock error signals. The pulse widths of the UP signal and DN signal can represent the phase difference between the reference clock signal and the feedback clock signal.

[0062] Specifically, the PID gain module includes a proportional gain path, an integral gain path, and a derivative gain path.

[0063] The proportional gain path, the integral gain path, and the derivative gain path each include a phase difference pulse conversion module and a corresponding filter; The input end of the phase difference pulse conversion module is connected to the output end of the frequency discriminator and phase detector, and the output end of the phase difference pulse conversion module is connected to the input end of the filter. Among them,

[0064] The proportional gain path includes a phase difference pulse conversion module and a proportional gain filter;

[0065] The integral gain path includes a phase difference pulse conversion module and an integral gain filter;

[0066] The derivative gain path includes a phase difference pulse conversion module and a derivative gain filter.

[0067] Preferably, the phase difference pulse conversion modules in the proportional gain path, the integral gain path, and the derivative gain path are independently set respectively to achieve independent adjustment of proportional, integral, and derivative gains.

[0068] Specifically, the phase difference pulse conversion module is used to convert a clock error signal representing a phase difference into a current pulse signal. The phase difference pulse conversion module includes one or more current units. Among them, one current unit includes a PMOS current source and an NMOS current source, and the PMOS current source and the NMOS current source are connected in one-to-one correspondence. Among them, the pulse width control terminal of the PMOS current source is connected to the Q terminal of the first D flip-flop, and the pulse width control terminal of the NMOS current source is connected to the Q terminal of the second D flip-flop. The current unit receives a reference current signal and a clock error signal, and converts the clock error signal into a current pulse sub-signal. The pulse width of the current pulse sub-signal is proportional to the pulse width of the clock error signal, and the current magnitude of the current pulse sub-signal has a multiple relationship with the current magnitude of the reference current signal. The current pulse signal output by the phase difference pulse conversion module is the superposition of the current pulse sub-signals output by all current units, that is, the current of the current pulse signal is the sum of the currents of all current pulse sub-signals.

[0069] Preferably, an independent EN switch is provided in each current unit to control the number of current units turned on, so that the current magnitude of the current pulse signal output by the phase difference pulse conversion module can be digitally adjusted by the EN switch.

[0070] In a specific embodiment, as Figure 3 shown, the phase difference pulse conversion module 2 includes a current mirror 20 for providing a reference current, and the current mirror 20 is used to copy the reference current to the charge pump.

[0071] The current mirror 20 includes a reference current source 201, a first PMOS transistor 204, a first NMOS transistor 202, and a second NMOS transistor 203. Among them, the reference current source 201 is used to provide a reference current. One end of the reference current source 201 is connected to a high level, and the other end is connected to the drain of the first NMOS transistor 202. The first NMOS transistor 202 and the second NMOS transistor 203 share the same gate and are connected to the second output terminal of the current mirror. The drain and gate of the first NMOS transistor 202 are short-circuited, and the source of the first NMOS transistor 202 is grounded. The sources of the second NMOS transistors 203 are all grounded, and the gates of the second NMOS transistors 203 are connected to the drain of the first PMOS transistor 204. The gate and drain of the first PMOS transistor 204 are short-circuited, and the source of the first PMOS transistor 204 is connected to a high level. The gate of the first PMOS transistor 204 is also connected to the first output terminal of the current mirror.

[0072] The charge pump includes a plurality of current units connected in parallel. Each current unit includes a PMOS current source 21 and an NMOS current source 22, and the PMOS current source 21 and the NMOS current source 22 are connected in one-to-one correspondence. The first output terminal and the second output terminal of the current mirror are respectively connected to the PMOS current source 21 and the NMOS current source 22 of the current unit and provide a reference current.

[0073] The PMOS current source 21 includes a PMOS transistor assembly 22 and a PMOS switch transistor assembly 23. Among them, the PMOS transistor assembly 22 is used to provide a stable bias current, and the PMOS switch transistor assembly 23 has a common source and is used to output a current under the control of the DN signal. The PMOS transistor assembly 22 includes one or more PMOS transistors. When the PMOS transistor assembly 22 includes one PMOS transistor, the gate of this PMOS transistor is connected to the first output terminal of the current mirror, so as to replicate the reference current by a certain multiple as the bias current; the source of this PMOS transistor is connected to a high level, and the drain is connected to the common source of the PMOS switch transistor assembly 23. When the PMOS transistor assembly 22 includes multiple PMOS transistors, the above-mentioned multiple PMOS transistors all have a common gate and the gate is connected to the first output terminal of the current mirror, so as to replicate the reference current by a certain multiple as the bias current; and the source and drain of each pair of adjacent PMOS transistors are connected, the source of the first PMOS transistor is connected to a high level, and the drain of the last PMOS transistor is connected to the common source of the PMOS switch transistor assembly 23.

[0074] The PMOS switch transistor assembly 23 includes two PMOS switch transistors with a common source. For the convenience of description, the above two series-connected PMOS transistors are respectively defined as the second PMOS transistor 231 and the third PMOS transistor 232. The sources of the second PMOS transistor 231 and the third PMOS transistor 232 are connected, and the drains of the second PMOS transistor 231 and the third PMOS transistor 232 are both connected to the NMOS current source. The gate of the second PMOS transistor 231 is connected to the Q terminal of the second D flip-flop 102 for receiving the DN signal, and the gate of the third PMOS transistor 232 is connected to the Q terminal of the second D flip-flop 102 through an inverter for receiving the inverted signal of the DN signal.

[0075] Preferably, the PMOS transistor assembly 22 is controlled by an EN switch, so that the magnitude of whether the PMOS switch transistor assembly 23 outputs a current can be adjusted by the EN switch. If the PMOS transistor assembly 22 includes one PMOS transistor, the gate of this PMOS transistor is connected to the first output terminal of the current mirror through the EN switch, and whether it replicates the reference current by a certain multiple is controlled by the EN switch; if the PMOS transistor assembly 22 includes multiple PMOS transistors, the above-mentioned multiple PMOS transistors all have a common gate, and the gate is connected to the first output terminal of the current mirror through the EN switch, and whether it replicates the reference current by a certain multiple is controlled by the EN switch.

[0076] The NMOS current source 24 includes an NMOS transistor component 25 and an NMOS switch transistor component 26. Among them, the NMOS transistor component 25 is used to provide a stable bias current, and the NMOS switch transistor component 26 is common-source and is used to output a current under the control of the UP signal. The NMOS transistor component 25 includes one or more NMOS transistors. When the NMOS transistor component 25 includes one NMOS transistor, the gate of this NMOS transistor is connected to the first output terminal of the current mirror, so as to replicate the reference current by a certain multiple as the bias current; the source of this NMOS transistor is grounded, and the drain is connected to the common source of the NMOS switch transistor component 26. When the NMOS transistor component 25 includes multiple NMOS transistors, the above-mentioned multiple NMOS transistors are all common-gate and the gates are connected to the first output terminal of the current mirror, so as to replicate the reference current by a certain multiple as the bias current; and the source and drain of each pair of adjacent NMOS transistors are connected, the source of the first NMOS transistor is grounded, and the drain of the last NMOS transistor is connected to the common source of the NMOS switch transistor component 26.

[0077] The NMOS switch transistor component 26 includes two common-source NMOS switch transistors. For convenience of description, the above two series-connected NMOS transistors are respectively defined as the third NMOS transistor 261 and the fourth NMOS transistor 262. The sources of the third NMOS transistor 261 and the fourth NMOS transistor 262 are connected. The gate of the third NMOS transistor 261 is connected to the Q terminal of the first D flip-flop 101 for receiving the UP signal, and the gate of the fourth NMOS transistor 262 is connected to the Q terminal of the first D flip-flop 101 through an inverter for receiving the inverted signal of the UP signal. The drain of the fourth NMOS transistor 262 is connected to the drain of the second PMOS transistor, and the drain of the third NMOS transistor 261 is connected to the drain of the third PMOS transistor 232. The output terminal of the current unit is led out from the common drain of the third NMOS transistor 261 and the third PMOS transistor 232 for outputting the signal of this current unit. The output terminals of multiple parallel-connected current units are all connected to the output terminal of the charge pump to output a current pulse signal.

[0078] Preferably, the NMOS transistor component 25 is controlled by an EN switch, so that whether the NMOS switch transistor component 26 outputs a current can be adjusted by the EN switch. If the NMOS transistor component 25 includes one NMOS transistor, the gate of this NMOS transistor is connected to the first output terminal of the current mirror through the EN switch, and whether it replicates the reference current by a certain multiple is controlled by the EN switch; if the NMOS transistor component 25 includes multiple NMOS transistors, the above-mentioned multiple NMOS transistors are all common-gate, and the gates are connected to the first output terminal of the current mirror through the EN switch, and whether it replicates the reference current by a certain multiple is controlled by the EN switch.

[0079] When multiple groups of parallel current units are set, by setting the multiples of the replicated reference current of the PMOS transistor components in the PMOS current sources and the NMOS transistor components 25 in the NMOS current source 24 in different current units, the magnitudes of the current pulse signals output by different current units can be made different. Thus, by setting the switching states of the EN switches of each current unit, the amplitude adjustment of the current pulse signal can be achieved. It is easy for those skilled in the art to think that the different magnitudes of the current pulse signals output by different current units can be achieved by common technical means in the art. For example, different aspect ratios can be set for the PMOS transistor components and the NMOS transistor components 25 in different current units; or, for example, different numbers of parallel MOS transistors / series MOS transistors can be set in the PMOS transistor components and the NMOS transistor components 25 in different current units, so as to achieve different magnitudes of the current pulse signals output by different current units.

[0080] In a specific embodiment, the multiples of the replicated reference current of the PMOS current source and the NMOS current source in each current unit are set to the same multiple of the reference current. By setting the switching states of the EN switches of each current unit, the amplitude adjustment of the current pulse signal is achieved.

[0081] In this embodiment, the bias currents of the PMOS current source 21 and the NMOS current source 24 in each current unit are set to increase in accordance with the binary multiple relationship of the reference current. Ignoring the on-resistance of the switching transistors, the current pulse sub-signals output by the current units also increase in accordance with the binary multiple relationship of the reference current, so that by setting the switching states of the EN switches of each current unit, the output current pulse signal is in binary weighted configuration. For example, there are N current units, and the current output by each current unit is a binary multiple of the reference current, that is, from 1 times to 2^N times. Let the control signals of all EN switches be encoded as N-bit binary control signals EN<1:N> according to the binary multiples of the current units corresponding to each switch. At this time, by configuring the EN control signals, the amplitude adjustment of the current pulse signal can be achieved, and the current pulse signal corresponding to the multiple of the EN control signal is output, so as to realize the digital adjustment of the current pulse signal through the EN control signal, making the charge pump in this embodiment programmable.

[0082] Preferably, as Figure 3 shown, the charge pump further includes an operational amplifier 27. The positive input terminal of the operational amplifier 27 is connected to the output terminal of the current unit, the negative input terminal is connected to the drains of the second PMOS transistor and the fourth NMOS transistor in the current unit, the positive output terminal is connected to the second output terminal of the current mirror, and the negative output terminal is connected to the first output terminal of the current mirror. The operational amplifier 27 is used to reduce the mismatch error of the charge pump current and improve the output accuracy of the charge pump.

[0083] It should be noted that the conduction resistance of the switching transistor is ignored in the above statements about the current multiple relationship of each part of the charge pump. In fact, the conduction resistance of the switching transistor will affect the amplitude of the current pulse signal. Therefore, in practical applications, it is necessary to calibrate the amplitude of the current pulse signal according to the specific application scenario.

[0084] In a specific embodiment, the proportional gain filter 33 is used to filter the current pulse signal and output a proportional gain signal. The proportional gain filter 33 includes a resistor unit. One end of the resistor unit is connected to the output end of the charge pump, and the other end is grounded. The output end of the proportional gain path is led out from the connection between the resistor unit and the output end of the charge pump for outputting the proportional gain signal. Preferably, a proportional path switch is arranged between the output end of the proportional gain path and the input end of the oscillator. By closing / opening the proportional path switch, it can be controlled whether to enable the proportional gain path. Specifically, the resistor unit may include one or more resistors, and the resistance value of the resistor can be adjusted according to the specific application scenario. The control signal of the proportional path switch is the proportional path switch control signal. For example, when the proportional path switch control signal is at a high level, the proportional path switch is closed to enable the proportional gain path; when the proportional path switch control signal is at a low level, the proportional path switch is opened to disable the proportional gain path.

[0085] In a specific embodiment, the integral gain filter 34 is used to integrally filter the current pulse signal and output an integral gain signal. The integral gain filter 34 includes a capacitor unit. One end of the capacitor unit is connected to the output end of the charge pump, and the other end is grounded. The output end of the integral gain path is led out from the connection between the capacitor unit and the output end of the charge pump for outputting the integral gain signal. Preferably, an integral path switch is arranged between the output end of the integral gain path and the input end of the oscillator. By closing / opening the integral path switch, it can be controlled whether to enable the integral gain path. Specifically, the capacitor unit may include one or more capacitors, and the capacitance value of the capacitor can be adjusted according to the specific application scenario. The control signal of the integral path switch is the integral path switch control signal. For example, when the integral path switch control signal is at a high level, the integral path switch is closed to enable the integral gain path; when the integral path switch control signal is at a low level, the integral path switch is opened to disable the integral gain path.

[0086] In a specific embodiment, a differential gain filter is used to perform differential filtering on a current pulse signal and output a differential gain signal. The differential gain filter 35 includes an inductor unit. One end of the inductor unit is connected to the output end of the charge pump, and the other end is grounded. The output end of the differential gain path is led out from the connection point between the inductor unit and the output end of the charge pump for outputting the differential gain signal. Preferably, a differential path switch is provided between the output end of the differential gain path and the input end of the oscillator. By closing / opening the differential path switch, it is possible to control whether the differential gain path is enabled or not. Specifically, the inductor unit may include one or more inductors, and the inductance value of the inductor can be adjusted according to the specific application scenario. The inductor can be implemented by including but not limited to passive inductors, active inductors, and digital filters. The control signal of the differential path switch is the differential path switch control signal. For example, when the differential path switch control signal is at a high level, the differential path switch is closed to enable the differential gain path; when the differential path switch control signal is at a low level, the differential path switch is opened to disable the differential gain path.

[0087] The active inductor circuit provided in this embodiment is as Figure 4 shown, and includes two transconductance amplifiers connected in a negative feedback form, and a load capacitor 43. The output end of the charge pump is connected to one end of the negative feedback loop of the two transconductance amplifiers, and the other end of the negative feedback loop of the two transconductance amplifiers is grounded through the load capacitor 43. For the convenience of description, the above two transconductance amplifiers are respectively named the first transconductance amplifier 41 and the second transconductance amplifier 42. The positive input end of the first transconductance amplifier 41 is connected to the output end of the second transconductance amplifier 42 and is commonly connected to the output end of the charge pump. The negative input end of the first transconductance amplifier 41 and the positive input end of the second transconductance amplifier 42 are grounded. The output end of the first transconductance amplifier 41 is connected to the negative input end of the second transconductance amplifier 42 and is commonly connected to one end of the load capacitor 43, and the other end of the load capacitor 43 is grounded. It is easy for those skilled in the art to think that the transconductance amplifier can be implemented by one or more transistors; the load capacitor 43 can be the inherent equivalent parasitic capacitance of the transistor at this node or a passive capacitor. The input impedance of this circuit is:

[0088]

[0089] where C is the capacitance value of the load capacitor, s represents the complex frequency in Laplace, g m1 and g m2 represent the transconductance values of the first transconductance amplifier and the second transconductance amplifier respectively. It should be noted that the signs of g m1 and g m2 are negative. The first transconductance amplifier and the second transconductance amplifier are also called gyrators, which convert the impedance of the load capacitor by 90°, from capacitive to inductive.

[0090] The specific implementation of the active inductor circuit can be adjusted according to the specific application scenario.

[0091] In a specific embodiment, the PID gain module further includes an adder, which is used to receive the proportional gain signal, the integral gain signal, and the differential gain signal, superimpose them, and output the superimposed signal to the oscillator. The adder is respectively connected to the output ends of the proportional gain path, the integral gain path, and the differential gain path, receives the proportional gain signal, the integral gain signal, and the differential gain signal, superimposes the three, and then outputs the result to the oscillator. The adder can be implemented by the circuit structure of a current adder, and the specific implementation can be adjusted according to the specific application scenario. The oscillator is the controlled object of the phase-locked loop, and together with the phase-locked loop, it constitutes a frequency synthesizer. In a specific embodiment, the oscillator uses a voltage-controlled oscillator.

[0092] By adopting the above solution, the proportional gain, integral gain, and differential gain provided by the proportional, integral, and differential gain paths including resistors, capacitors, and inductors can be respectively controlled by the output currents of three groups of programmable charge pumps, without adjusting the parameters of the resistors, capacitors, and inductors.

[0093] The PID gain module uses a loop filter composed of proportional, integral, and differential gains (PID). The three independent control gains in the PID gain module are: the proportional gain path with a gain of Kp, the integral gain path with a gain of Ki, and the differential gain path with a gain of Kd. Among them, the proportional gain path proportionally associates the proportional gain control amount with the current clock error signal. The larger the error, the stronger the control effect. The integral control provided by the integral gain path can eliminate the steady-state error. By integrating the error, that is, accumulating over time, it ensures that the error accumulated over a long time is eliminated, so that the system can finally reach the set value. The differential control provided by the differential gain path can predict the trend of the error. By adjusting the control amount to counteract the change of the error, the oscillation and overshoot of the system can be reduced.

[0094] The loop filter of the PID gain module of the present invention consists of three independent control gains: a proportional gain path with a gain of Kp, an integral gain path with a gain of Ki, and a derivative gain path with a gain of Kd. Proportional gain control correlates the control quantity proportionally with the current error. The larger the error, the stronger the control action. In an actual charge pump phase-locked loop, in each reference clock cycle, the charge pump current through the resistor generates an instantaneous voltage, whose pulse width is proportional to the phase error, forming a proportional gain path. Integral control can eliminate the steady-state error. It integrates the error, that is, accumulates it over time. This ensures that the error accumulated over a long time is eliminated, enabling the system to ultimately reach the set value. In an actual charge pump phase-locked loop, according to the polarity of the phase error, positive or negative charges accumulate in the loop capacitor, forming an integral gain path of frequency. Derivative control is based on the rate of change of the error, that is, predicting the trend of the error. By adjusting the control quantity to counteract the change of the error, the oscillation and overshoot of the system are reduced. In an actual charge pump phase-locked loop, according to the rate of change of the phase error, the charge pump current through the inductor generates an instantaneous voltage, whose pulse width is proportional to the rate of change of the phase error, forming a derivative gain path.

[0095] As Figure 2 , 3 shown, the closed-loop transfer function of the phase-locked loop circuit based on PID control is:

[0096]

[0097] where the damping ratio is:

[0098]

[0099] The natural frequency is:

[0100]

[0101] K d is the gain of the phase frequency detector and charge pump in the phase-locked loop, and K v is the gain of the voltage-controlled oscillator. It can be seen from Formulas 2 and 3 that the differential gain generated by the inductor is added to the damping ratio and natural frequency. Therefore, it provides more flexible loop dynamic characteristics compared with the traditional proportional integral (PI) phase-locked loop. In addition, the currents flowing through the resistor R, capacitor C, and inductor L are independently controlled to achieve independent adjustment of the proportional, integral, and derivative gains. Among them, the resistor R, capacitor C, and inductor L are the equivalent resistor of the proportional gain filter, the equivalent capacitor of the integral gain filter, and the equivalent inductor of the derivative gain filter, respectively.

[0102] The closed-loop transfer function of the traditional PI control-based phase-locked loop is:

[0103]

[0104] where the damping ratio is:

[0105]

[0106] and the natural frequency is:

[0107]

[0108] Define the system settling time as the time when the error between the system output and the specified output is 1%, and the formula is as follows:

[0109]

[0110] Obviously, the ζω of PID control n is much greater than that of PI control n , so, under the same loop parameters, the system settling time of PID control is much less than that of PI control.

[0111] In this embodiment, as Figure 1 , 2 shown, since the proportional gain path 11, the integral gain path 12, and the derivative gain path 13 are in parallel, the output ends of the proportional gain path 11, the integral gain path 12, and the derivative gain path 13 can be directly connected to the input end of the oscillator 14. At this time, the input current signal received by the oscillator is the superposition of the proportional gain signal, the integral gain signal, and the derivative gain signal. The oscillator 14 converts the received input current signal into an oscillation signal vco - clk and outputs it. The output end of the oscillator 14 is also connected to the input end of the frequency divider 16, and outputs the oscillation signal to the frequency divider 16. The output end of the frequency divider 16 is respectively connected to the input end of the adaptive PID controller 15 and the input end of the frequency discriminator and phase discriminator 10. The frequency divider 16 receives the oscillation signal and generates a feedback clock signal. In a specific embodiment, the frequency divider is a programmable frequency divider, and its division factor can be adjusted by an external control signal. In practical applications, the implementation manner of the frequency divider can be the same as the prior art, and the division multiple of the frequency divider can be adjusted according to specific application scenarios. The programmable frequency divider constitutes the feedback loop of the PID control phase - locked loop of the present invention, and its function is to divide the high - frequency signal of the oscillator by a specified division multiple to a lower frequency for comparison with the reference clock.

[0112] The adaptive PID controller is used to receive the feedback clock signal and adaptively adjust the proportional, integral, and derivative gains of the PID gain module according to the change trend of the feedback clock signal. Specifically, as Figure 2 , 5As shown, the adaptive PID controller 15 includes a phase detector 30, a combinational logic module 31, and a plurality of gain control terminals 32. The input terminal of the phase detector 30 is connected to the output terminal of the frequency divider 16. The output terminal of the phase detector 30 is connected to the input terminal of the combinational logic module 31. The output terminal of the combinational logic module 31 is the gain control terminal 32. The gain control terminal 32 is respectively connected to the proportional gain path 11, the integral gain path 12, and the derivative gain path 13 in the PID gain module. Among them, the phase detector is used to detect the phase of the feedback clock signal and generate a feedback phase signal. The combinational logic module is used to receive the feedback phase signal, perform combinational logic processing on the feedback phase signal, generate a gain control signal, and send the gain control signal to the corresponding gain path through the gain control terminal. The gain control signal includes a proportional gain control signal, an integral gain control signal, and a derivative gain control signal. During operation, the adaptive PID controller receives the feedback clock signal. The phase detector detects the phase of the feedback clock signal. The combinational logic module adaptively combines different gains according to the phase locking state of the feedback phase signal and generates a gain control signal. The gain control signal adjusts the proportional, integral, and derivative gains of the PID gain module through the gain control terminal, realizing the fast locking and noise suppression of the phase-locked loop.

[0113] The gain control terminal 32 includes a proportional gain control terminal 321, an integral gain control terminal 322, and a derivative gain control terminal 323.

[0114] In this embodiment, the proportional gain control terminal includes a proportional gain amount control terminal and a proportional gain enable control terminal. Among them, the proportional gain amount control terminal is connected to the EN switch in the proportional gain path, and the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path. The proportional gain control signal includes a proportional gain amount control signal and a proportional gain enable control signal. The proportional gain amount control signal is the above-mentioned EN control signal, which can digitally adjust the magnitude of the proportional gain. The proportional gain enable signal is the proportional path switch control signal.

[0115] In this embodiment, the integral gain control terminal includes an integral gain amount control terminal and an integral gain enable control terminal. Among them, the integral gain amount control terminal is connected to the EN switch in the integral gain path, and the integral gain enable control terminal is connected to the integral path switch in the integral gain path. The integral gain control signal includes an integral gain amount control signal and an integral gain enable control signal. The integral gain amount control signal is the above-mentioned EN control signal, which can digitally adjust the magnitude of the integral gain. The integral gain enable signal is the above-mentioned integral path switch control signal.

[0116] In this embodiment, the differential gain control terminal includes a differential gain amount control terminal and a differential gain enable control terminal. Among them, the differential gain amount control terminal is connected to the EN switch in the differential gain path, and the differential gain enable control terminal is connected to the differential path switch in the differential gain path. The differential gain control signal includes a differential gain amount control signal and a differential gain enable control signal. The differential gain amount control signal is the above-mentioned EN control signal, which can digitally adjust the magnitude of the differential gain. The differential gain enable signal is the differential path switch control signal.

[0117] In another embodiment, the proportional gain control terminal includes a proportional gain enable control terminal. Among them, the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path. The proportional gain control signal is the proportional path switch control signal. In this embodiment, the magnitude of the proportional gain is digitally adjusted by the host computer sending an EN control signal to the programmable charge pump. The integral gain control terminal and the differential gain control terminal are the same.

[0118] By adopting the above solution, an adaptive PID controller can be used. By detecting the phase-locked state of the feedback clock signal, in the frequency acquisition stage, the full function of PID is used to achieve fast locking. In the phase-locked state, the traditional proportional-integral (PI) gain combination is used to achieve phase-locked loop stability and noise suppression. Those skilled in the art can also customize the logic function of the combinational logic module according to the specific application scenario to achieve different PID gain combinations.

[0119] According to the above description, those skilled in the art can easily think of using the prior art to implement the phase detector and combinational logic module of this embodiment, and the specific implementation method can be adjusted according to the specific application scenario.

[0120] In summary, the phase-locked loop combination architecture based on PID control provided by the present invention, compared with the traditional phase-locked loop, adds a differential part on the basis of the proportional-integral control strategy, can predict the change trend of the error, and thus make adjustments in advance to reduce overshoot and improve the stability of the system. The three parameters (proportional, integral, differential) of the PID control can be adjusted independently, and the lock-in time can be improved without increasing the bandwidth loss of the phase noise performance, realizing the decoupling of the loop bandwidth and the lock-in time. In addition, the three parameters of the PID controller can be arbitrarily combined and adjusted according to needs to adapt to different control requirements.

[0121] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the invention can be modified or equivalently replaced without departing from the scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A phase-locked loop circuit based on PID control, characterized in that: It includes a phase frequency detector, a PID gain module, an oscillator, an adaptive PID controller, and a frequency divider; among them, Two input terminals of the phase frequency detector are respectively connected to a reference clock source and the frequency divider, receive a reference clock signal output by the reference clock source and a feedback clock signal output by the frequency divider, and generate a clock error signal representing the phase difference; The PID gain module includes three gain paths, namely a proportional gain path, an integral gain path, and a differential gain path. The three gain paths are respectively connected to the output terminal of the phase frequency detector to receive the clock error signal; the three gain paths respectively perform proportional, integral, and differential control on the received clock error signal, and respectively output a proportional gain signal, an integral gain signal, and a differential gain signal. The proportional gain signal, the integral gain signal, and the differential gain signal are superimposed to form an input signal of the oscillator and output to the oscillator; The output terminal of the oscillator is connected to the input terminal of the frequency divider. The oscillator generates an oscillation signal based on the input signal of the oscillator, and the frequency divider divides the oscillation signal and outputs a feedback clock signal; The output terminal of the frequency divider is connected to the input terminal of the adaptive PID controller; The adaptive PID controller is provided with a plurality of gain control terminals corresponding to the gain paths, including a proportional gain control terminal, an integral gain control terminal, and a differential gain control terminal; the proportional gain control terminal, the integral gain control terminal, and the differential gain control terminal are respectively connected to the corresponding gain paths in the PID gain module; in the adaptive PID controller, phase detection is performed on the feedback clock signal to generate a feedback phase signal, and combinational logic processing is performed on the feedback phase signal to generate a gain control signal corresponding to the gain path. The gain control signal includes a proportional gain control signal, an integral gain control signal, and a differential gain control signal. The gain control signal is sent to the corresponding gain path through the gain control terminal to adjust the magnitudes of the proportional gain signal, the integral gain signal, and the differential gain signal, thereby adjusting the oscillation signal.

2. The phase-locked loop circuit according to claim 1, wherein: The adaptive PID controller includes a phase detector, a combinational logic module, and a gain control terminal; among them, the phase detector is used to perform phase detection on the feedback clock signal to generate a feedback phase signal; the combinational logic module is used to perform combinational logic processing on the feedback phase signal to generate a gain control signal; the gain control terminal is used to send the gain control signal to the corresponding gain path to adjust the magnitudes of the proportional gain signal, the integral gain signal, and the differential gain signal.

3. The phase-locked loop circuit according to claim 2, wherein: A proportional path switch, an integral path switch, and a differential path switch are respectively arranged on the three gain paths, and are used to independently control the on / off of the proportional gain path, the integral gain path, and the differential gain path. The proportional path switch, the integral path switch, and the differential path switch are arranged between the output terminal of the corresponding gain path and the oscillator.

4. The phase-locked loop circuit according to any one of claims 1-3, characterized in that: The proportional gain path, integral gain path, and derivative gain path each include a phase difference pulse conversion module and a corresponding filter; in any gain path, the input end of the phase difference pulse conversion module is connected to the output end of the frequency discriminator and phase detector, and the output end of the phase difference pulse conversion module is connected to the input end of the filter; among them, the proportional gain path includes a phase difference pulse conversion module and a proportional gain filter; the integral gain path includes a phase difference pulse conversion module and an integral gain filter; the derivative gain path includes a phase difference pulse conversion module and a derivative gain filter.

5. The phase-locked loop circuit according to claim 4, wherein: The phase difference pulse conversion modules in the proportional gain path, integral gain path, and derivative gain path are independently provided respectively.

6. The phase-locked loop circuit according to claim 5, wherein: The phase difference pulse conversion module is used to convert the clock error signal into a current pulse signal; The phase difference pulse conversion module includes one or more current units. The current units receive a reference current and a clock error signal, and convert the clock error signal into current pulse sub-signals. The current pulse signal is the superposition of all current pulse sub-signals; the current pulse signal output by the phase difference pulse conversion module is the superposition of the current pulse sub-signals output by all current units.

7. The phase-locked loop circuit according to claim 5, wherein: The phase difference pulse conversion module further includes a current mirror for providing the reference current, and the current mirror is used to copy the reference current to the current units.

8. The phase-locked loop circuit according to claim 7, wherein: The phase difference pulse conversion module includes a plurality of current units. The current of the current pulse sub-signal output by each current unit increases according to the binary multiple relationship of the reference current. Each current unit is provided with an EN switch, and whether the current unit outputs a current pulse sub-signal is controlled by the EN switch; By setting the switch states of the EN switches of each current unit, the current regulation of the current pulse signal is realized.

9. The phase-locked loop circuit according to claim 8, wherein: The gain control terminal includes a proportional gain control terminal, an integral gain control terminal, and a derivative gain control terminal; among them, The proportional gain control terminal includes a proportional gain amount control terminal and a proportional gain enable control terminal. Among them, the proportional gain amount control terminal is connected to the EN switch in the proportional gain path, and the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path; the integral gain control terminal includes an integral gain amount control terminal and an integral gain enable control terminal. Among them, the integral gain amount control terminal is connected to the EN switch in the integral gain path, and the integral gain enable control terminal is connected to the integral path switch in the integral gain path; The derivative gain control terminal includes a derivative gain amount control terminal and a derivative gain enable control terminal. Among them, the derivative gain amount control terminal is connected to the EN switch in the derivative gain path, and the derivative gain enable control terminal is connected to the derivative path switch in the derivative gain path.

10. The phase-locked loop circuit according to claim 3, wherein: The gain control terminal includes a proportional gain control terminal, an integral gain control terminal, and a derivative gain control terminal; among them, The proportional gain control terminal includes a proportional gain enable control terminal, and the proportional gain enable control terminal is connected to the proportional path switch in the proportional gain path; The integral gain control terminal includes an integral gain enable control terminal, and the integral gain enable control terminal is connected to the integral path switch in the integral gain path; The differential gain control terminal includes a differential gain enable control terminal, and the differential gain enable control terminal is connected to a differential path switch in the differential gain path.

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