Charge pump for fractional-N frequency synthesizer

Abstract

The invention relates to a charge pump for a fractional-N frequency synthesizer. The charge pump includes: a digital-to-analog converter configured to draw a first current and a second current from a first node and a second node, respectively, according to a first logic signal, a second logic signal, and a B-bit control command; a common-gate amplifier configured to provide a path for charge transfer between the second node and a third node according to a third logic signal; the integrating capacitor is connected with the second node and is configured to be discharged by the digital-to-analog converter or charged by the common-gate amplifier according to a fourth logic signal; and the low-impedance active load is connected with the first node.

Description

Technical Field

[0001] The present disclosure relates to a charge pump for a fractional-N frequency synthesizer, and more particularly to a charge pump with low noise and low non-linearity characteristics for a frequency synthesizer. Background Art

[0002] Those skilled in the art can understand the terms and basic concepts related to microelectronic technology used herein, such as "voltage", "current", "signal", "local signal", "clock", "phase", "(clock) edge", "capacitance", "transistor", "n-channel metal-oxide semiconductor transistor (NMOST)", "source", "gate", "drain", "node", "ground node", "power supply node", "inverter", "data flip-flop (DFF)", "common-gate amplifier", "load", "impedance", "noise", and "non-linearity characteristics". Terms and related concepts such as these are obvious to those skilled in the art, and thus will not be explained in detail herein.

[0003] Those skilled in the art can recognize resistor symbols, capacitor symbols, and n-channel metal-oxide semiconductor transistor (NMOST) symbols, and can identify the "source" terminal, "gate" terminal, "drain" terminal, and "base" terminal of an NMOST. For the sake of brevity, when referring to an NMOST herein, the "source terminal" is abbreviated as "source", the "gate terminal" is abbreviated as "gate", and the "drain terminal" is abbreviated as "drain". An NMOST has a threshold voltage and is turned on when the gate-source voltage is greater than the threshold voltage.

[0004] Those skilled in the art can read a schematic diagram of a circuit including components such as resistors, capacitors, NMOSTs, inverters, and DFFs, and there is no need for a redundant description of how one component in the schematic diagram is connected to another component.

[0005] As Figure 1As shown, a phase lock loop (PLL) 100 includes a phase / frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LP) 130, a voltage-controlled oscillator (VCO) 140, and a multi-modulus divider 150. The phase / frequency detector 110 detects the timing (the time when the rising edge appears) difference between the reference clock and the divided clock, and outputs two logic signals, UP (representing "up") and DN (representing "down"), to represent the timing difference. Whenever the phase / frequency detector 110 performs detection, if the reference clock leads the divided clock in timing, a pulse of the logic signal UP will be generated, and if the divided clock leads the reference clock in timing, a pulse of the logic signal DN will be generated, where the width of the pulse of the logic signal UP or the pulse of the logic signal DN is proportional to the detected timing difference. The charge pump 120 receives the logic signals UP and DN and outputs an error current to represent the timing difference. Thus, if the reference clock leads the divided clock in timing, the error current is positive; if the divided clock leads the reference clock in timing, the error current is negative; and the net charge of the error current, that is, the integral value of the error current, is proportional to the timing difference. The loop filter 130 receives the error current and establishes a control voltage to control the voltage-controlled oscillator 140, which outputs a voltage-controlled oscillator clock. The multi-modulus divider 150 receives the voltage-controlled oscillator clock and outputs a divided clock according to the division value N. Thus, a pulse of the divided clock will be generated every N cycles of the voltage-controlled oscillator clock. A closed-loop control system can be established to adjust the frequency / phase of the voltage-controlled oscillator clock and track the frequency / phase of the reference clock, and the frequency of the voltage-controlled oscillator clock will be N times the frequency of the reference clock. The phase lock loop 100 is well known in the prior art and will not be described in detail herein.

[0006] In practice, the charge pump 120 is affected by the non-linear characteristics caused by the "P-N mismatch" problem, where the magnitude of the error current in response to the pulse of the logic signal UP is different from the magnitude of the error current in response to the pulse of the logic signal DN. To avoid this problem, a fixed current of positive polarity is input to the loop filter 130 to pull up the timing of the voltage controlled oscillator clock ahead, so that the timing of the divided clock in the steady state is always ahead of the timing of the reference clock. Thus, the phase / frequency detector 110 will specifically output pulses of the logic signal DN, and the error current will always be of negative polarity. (Due to the circuit implementation limitations of the phase / frequency detector circuit, pulses of the logic signal UP with zero width are not allowed, so there may be pulses of the logic signal UP that are extremely short, but the impact of the extremely short pulses of the logic signal UP is negligible and thus is ignored in this article.) The remainder of this article assumes the following scenario, where the divided clock is always ahead of the reference clock in timing, does not have (apparent) pulses of the logic signal UP, but has pulses of the logic signal DN, the width of which represents the timing difference of the divided clock relative to the reference clock.

[0007] When the division value N is a fixed integer and in the steady state, except for a fixed offset, the timing (e.g., rising edge) of the divided clock will be well aligned with the timing of the reference clock. Therefore, the width of the pulses of the logic signal DN will be nearly fixed. However, in the application of a "fractional-N frequency synthesizer", the division value N is not a fixed integer but jitters dynamically. In the case where the target frequency of the voltage controlled oscillator clock is N0 + α times the frequency of the reference clock, where N0 is a non-zero integer and α is a small value greater than 0 but less than 1, at this time the division value N jitters dynamically and is equal to N0 plus the carry bit generated by the accumulator 160. The accumulator 160 performs the cumulative sum operation of α according to the divided clock, outputs a carry bit to indicate the occurrence of a carry event when the cumulative sum value is greater than or equal to 1, subtracts 1 from the cumulative sum value when the carry event occurs, and can also output a residual value equal to the subtracted cumulative sum value if applicable. The division value N is equal to N0 plus the carry bit, so it is equal to N0 or N0 + 1. The probability that the division value N is N0 + 1 is α, so the frequency of the voltage controlled oscillator clock will be N0 + α times the frequency of the reference clock, because the average timing of the divided clock will still be aligned with the timing of the reference clock. However, relative to the reference clock, the instantaneous timing (time point) of the divided clock may have a large variation, up to the period of the voltage controlled oscillator clock, resulting in instantaneous noise introduced into the error current due to the periodic variation of the width of the pulses of the logic signal DN. However, the instantaneous noise is deterministic and can be predicted by the residual value generated by the accumulator 160.

[0008] In the paper titled "Fractional-N Frequency Synthesizer Architecture with Mismatch-Compensated PFD / DAC Structure for Reducing Phase Noise due to Quantization" in the November 2003 issue, Volume 50, Number 11 of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Menninger et al. proposed a noise compensation scheme that can effectively suppress the instantaneous noise generated by the jitter of the division value N. As Figure 2 shown, the divided clock is re-timed by the shift register 220 according to the voltage-controlled oscillator clock. The shift register 220 includes a first unit period delay (denoted by "z -1 ", which is a symbol widely used in the field of discrete-time signal processing) 221 and a second unit period delay 222 following it to generate a first re-timed clock FB0 and a second re-timed clock FB1. It can be understood that except for the time delay of T vco , the second re-timed clock FB1 will be the same as the first re-timed clock FB0, where T vco represents the period of the voltage-controlled oscillator clock. The timing difference between the reference clock and the first re-timed clock FB0 is detected by the first phase / frequency detector 211 and represented by the first pulse DN0 of the logic signal DN, while the timing difference between the reference clock and the second re-timed clock FB1 is detected by the second phase / frequency detector 212 and represented by the second pulse DN1 of the logic signal DN. The first digital-analog converter (DAC) 231 is controlled by (1 - ε) and configured to output a first current I c , which is equal to I cp (1 - ε). Among them, I cp is a fixed current, ε is a B-bit digital word that quantizes the residue of the accumulator 160, and its value is between 0 and 1 (including 0 and 1), where B is an integer greater than 1.

[0009] The second digital-analog converter (DAC) 232 is controlled by ε and configured to output a second current I e , which is equal to I cp ε. The first current I c and the second current I e are combined through the first switch 241 and the second switch 242 controlled by the first pulse DN0 and the second pulse DN1 respectively. As explained by Menninger et al., ε represents the residue of the accumulator 160, so it is determined by T vcoThe predicted value of the width of the normalized second pulse DN1 (subtracting the previously known fixed offset if there is an introduced fixed offset), and although the width of the second pulse DN1 varies, the total net charge (which is equal to the integral value of the error current) will be I cp T vco , regardless of the value of ε. However, the compensation scheme is based on using a current pulse with a fixed width (equal to one period of the voltage controlled oscillator clock) and a variable height (equal to I cp (1 - ε)) to compensate for a current pulse with a fixed height (equal to I cp ) and a variable width (equal to ε times the period of the voltage controlled oscillator clock), so that the total net charge of the current pulse is equal to I cp T vco regardless of ε. However, the time domain waveforms are different, so the compensation is not perfect, and due to the difference in the time domain waveforms, time domain noise still exists.

[0010] In U.S. Patent Publication No. 7,629,854, Lin et al. disclose a switched-capacitor loop filter that integrates an error current by using a capacitor that stores the net charge of the error current; samples the net charge according to the timing of a reference clock after the end of the second pulse DN1; and transfers the sampled net charge to the loop filter to eliminate time domain noise. Thus, the loop filter does not see the time domain noise, making the time domain noise insignificant. However, the disclosed switched-capacitor loop filter requires an operational amplifier to transfer the sampled net charge to the loop filter; this consumes additional power and causes additional circuit noise.

[0011] What is desired by those skilled in the art is a switched-capacitor loop filter that does not require an operational amplifier and has low random noise and low deterministic noise. SUMMARY OF THE INVENTION

[0012] An object of the present disclosure is to compensate for the noise of a fractional-N frequency synthesizer in an energy-saving manner.

[0013] Another object of the present disclosure is to compensate for the noise of a fractional-N frequency synthesizer but avoid generating random noise.

[0014] Another object of the present disclosure is to compensate for the noise of a fractional-N frequency synthesizer but avoid generating deterministic noise.

[0015] In one embodiment, a charge pump includes: a digital-to-analog converter configured to draw a first current and a second current from a first node and a second node respectively according to a first logic signal, a second logic signal, and a B-bit control word, where B is an integer greater than 1; a common-gate amplifier configured to provide a path for charge transfer between the second node and a third node according to a third logic signal; an integrating capacitor connected to the second node and configured to be discharged by the digital-to-analog converter or charged by the common-gate amplifier according to a fourth logic signal; and a low-impedance active load connected to the first node. Wherein: the first logic signal includes a first pulse that starts at a second time instant and ends at a fourth time instant, and the second time instant lags behind the first time instant but leads the third time instant, and the fourth time instant lags behind the third time instant; the second logic signal includes a second pulse that starts at the third time instant and ends at the fourth time instant; the fourth logic signal includes a fourth pulse that starts at the first time instant and ends no earlier than the fourth time instant; the third logic signal is the inverse of the fourth logic signal; and within the time window of the fourth pulse, the value of the B-bit control word remains fixed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a functional block diagram of an existing phase lock loop (PLL).

[0017] Figure 2 is a functional block diagram of a circuit of an existing phase / frequency detector / digital-to-analog converter (PFD / DAC), and the circuit of the PFD / DAC can be used to compensate for the noise of a fractional-N frequency synthesizer.

[0018] Figure 3 is a functional block diagram of a fractional-N frequency synthesizer according to an embodiment of the present disclosure.

[0019] Figure 4A is a schematic diagram of a phase detector according to an embodiment of the present disclosure, and the phase detector can be used for Figure 3 the fractional-N frequency synthesizer.

[0020] Figure 4B is Figure 4A the timing diagram of the phase detector.

[0021] Figure 5A is a schematic diagram of a charge pump according to an embodiment of the present disclosure, and the charge pump can be used for Figure 3 the fractional-N frequency synthesizer.

[0022] Figure 5B is a schematic diagram of a current steering network according to an embodiment of the present disclosure, and the current steering network can be used forFigure 5A Charge pump

[0023] Symbol Explanation

[0024] 100: Phase-locked loop

[0025] 110: Phase / frequency detector

[0026] 120: Charge pump

[0027] 130: Loop filter

[0028] 140: Voltage-controlled oscillator

[0029] 150: Multimodulus divider

[0030] 160: Accumulator

[0031] UP: Logic signal

[0032] DN: Logic signal

[0033] α: Fractional value

[0034] N0: Integer

[0035] N: Division value

[0036] 211: First phase / frequency detector

[0037] 212: Second phase / frequency detector

[0038] 220: Shift register

[0039] 221: First unit-delay (z -1 )

[0040] 222: Second unit-delay (z -1 )

[0041] 231: First digital-to-analog converter (DAC)

[0042] 232: Second digital-to-analog converter (DAC)

[0043] 241: First switch

[0044] 242: Second switch

[0045] FB0: First time-reset clock

[0046] DN0: First pulse

[0047] I c : First current

[0048] FB1: Second time-reset clock

[0049] DN1: Second Pulse

[0050] I e : Second Current

[0051] ε: B-bit Digital Command

[0052] 300: Fraction-N Frequency Synthesizer

[0053] 310: Phase Detector

[0054] 320: Charge Pump

[0055] 330: Loop Filter

[0056] 340: Voltage Controlled Oscillator

[0057] 350: Multi-Modulus Divider 360: Accumulator

[0058] C: Carry Bit

[0059] E[B-1:0]: B-bit Control Command C REF : Reference Clock

[0060] C VCO : Voltage Controlled Oscillator Clock C DIV : Divided Clock

[0061] S1: Logic Signal

[0062] S2: Logic Signal

[0063] S3: Logic Signal

[0064] S4: Logic Signal

[0065] I ER : Error Current

[0066] V CTL : Control Voltage

[0067] 400: Phase Detector

[0068] 410: Shift Register

[0069] 411: Unit Delay (z -1 )

[0070] 412: Unit Delay (z -1 )

[0071] 421: First Phase / Frequency Detector

[0072] 422: Second Phase / Frequency Detector

[0073] 430: Charge transfer control signal generator 431: Data flip-flop

[0074] 432: Inverter

[0075] CK1: Time reset clock

[0076] CK2: Time reset clock

[0077] t1: First time point

[0078] t2: Second time point

[0079] t3: Third time point

[0080] t4: Fourth time point

[0081] T VCO : Period

[0082] T REF : Period

[0083] 500: Charge pump

[0084] 501: First node

[0085] 502: Second node

[0086] 503: Third node

[0087] 510: Digital-to-analog converter

[0088] 540: Common-gate amplifier

[0089] 541: First N-channel metal-oxide-semiconductor transistor

[0090] 550: Low-impedance active load

[0091] 551: Second N-channel metal-oxide-semiconductor transistor

[0092] 560: Loop filter

[0093] E[0]: Corresponding bit

[0094] E[1]: Corresponding bit

[0095] E[2]: Corresponding bit

[0096] CDN0: Current steering network

[0097] CDN1: Current steering network

[0098] CDN2: Current steering network

[0099] CS0: Current source

[0100] CS1: Current source

[0101] CS2: Current source

[0102] I0: Tail current

[0103] I1: Tail current

[0104] I2: Tail current

[0105] I 00 : Current

[0106] I 01 : Current

[0107] I 10 : Current

[0108] I 11 : Current

[0109] I 20 : Current

[0110] I 21 : Current

[0111] I S0 : First current

[0112] I S1 : Second current

[0113] V1: Voltage

[0114] V G : Gate voltage

[0115] V D : Drain voltage

[0116] V2: Voltage

[0117] C I : Integral capacitor

[0118] I CH : Charging current

[0119] C P : Parallel capacitor

[0120] R S : Series resistor

[0121] C S : Series capacitor

[0122] INV1: Inverter

[0123] INV2: Inverter

[0124] INV3: Inverter

[0125] SW1: Switch

[0126] SW2: Switch

[0127] SW3: Switch

[0128] SW4: Switch

[0129] SW5: Switch

[0130] SW6: Switch

[0131] E’[0]: Logic inverse value

[0132] S1’: Logic inverse signal

[0133] S2’: Logic inverse signal Detailed implementation manners

[0134] The present disclosure relates to a charge pump in a fractional-N frequency synthesizer. Although the specification describes several embodiments of the present disclosure, and these embodiments are considered to be preferred ways to implement the present invention. However, it should be understood that the present invention can be implemented in various ways, not limited to the specific exemplary embodiments described below, or not limited to the specific ways of implementing any features of these exemplary embodiments. In other cases, well-known details are not shown or described to avoid obscuring aspects of the present disclosure.

[0135] The common-gate amplifier is implemented by a MOST, configured to receive an input current at its source and output an output current through its drain, wherein its gate is connected to a bias node, and the voltage of the bias node is equal to the bias voltage, which is nearly in a steady state within the time window of concern to those skilled in the art.

[0136] A circuit is a collection of transistors, capacitors, inductors, resistors, and / or other electronic devices interconnected in a specific manner to achieve a specific function. A network is a circuit or a collection of circuits configured to achieve a specific function.

[0137] In this text, "circuit node" is simply referred to as "node" because its meaning can be clearly understood from the field of microelectronics without causing confusion.

[0138] In this text, a signal is a voltage with a variable level, and the variable level can change over time. The (voltage) level of a signal at a moment represents the state of the signal at this moment.

[0139] A logic signal is a signal with two states, namely a low level state and a high level state. The low level state is also referred to as the "0" state, while the high level state is also referred to as the "1" state. Regarding the logic signal Q, when we say "Q is at a high level" or "Q is at a low level", it means "Q is in the high level state" or "Q is in the low level state". Similarly, when we say "Q is 1" or "Q is 0", it means "Q is in the 1 state" or "Q is in the 0 state".

[0140] When a logic signal switches from a low level to a high level, the logic signal undergoes a transition from a low level to a high level and a rising edge appears. When a logic signal switches from a high level to a low level, the logic signal undergoes a transition from a high level to a low level and a falling edge appears. The pulse of a logic signal starts from the rising edge and ends at the subsequent falling edge.

[0141] If the first logic signal and the second logic signal are always in opposite states, it means the first logic signal is the logical inversion of the second logic signal. That is, when the first logic signal is 0 (low level), the second logic signal is 1 (high level); when the first logic signal is 1 (high level), the second logic signal is 0 (low level). When the first logic signal is the logical inversion of the second logic signal, it means the first logic signal and the second logic signal are complementary.

[0142] A clock is a logic signal that periodically switches back and forth between a low level state and a high level state.

[0143] Figure 3 FIG. 300 is a functional block diagram of a fractional-N frequency synthesizer (FNFS) 300 according to an embodiment of the present disclosure. The fractional-N frequency synthesizer 300 includes: a phase detector (PD) 310 configured to receive a reference clock C REF 、a divided clock C DIV and a voltage controlled oscillator clock C VCO , and output four logic signals S1, S2, S3 and S4; a charge pump (CP) 320 configured to receive the four logic signals S1, S2, S3 and S4 and a B-bit control command E[B-1:0], and establish an error current I ER ; a loop filter (LP) 330 configured to output a control voltage V ER in response to the error current I CTL ; a voltage controlled oscillator (VCO) 340 configured to output a voltage controlled oscillator clock C CTL in response to the control voltage VVCO ; a multi-modulus divider (MMD) 350 configured to receive a voltage controlled oscillator clock C VCO and output a divided clock C according to a division value N DIV , where the division value N is equal to a fixed integer N0 plus a carry bit C; and an accumulator 360 configured to receive a fractional value α and output a carry bit C and a B-bit control command E[B-1:0] according to the divided clock, where the B-bit control command E[B-1:0] is a quantization value of the residue of the cumulative sum value of the fractional value α.

[0144] An example schematic diagram of a phase detector (PD) 400 is shown in Figure 4A , and the phase detector 400 can be used to implement the phase detector 310. The phase detector 400 includes: a shift register 410 including two cascaded unit period delays 411, 412 and configured to receive the divided clock C DIV and respectively output two time reset clocks CK1 and CK2 according to the timing of the voltage controlled oscillator clock C VCO ; a first phase / frequency detector (PFD) 421 configured to output a logic signal S1 to represent the time difference (timing difference) between the reference clock C REF and the time reset clock CK1; a second phase / frequency detector 422 configured to output a logic signal S2 to represent the time difference (timing difference) between the reference clock C REF and the time reset clock CK2; and a charge transfer control signal generator 430 including: a data flipflop (DFF) 431 configured to reset the logic signal S4 to 0 when the reference clock C REF is at a high level and set the logic signal S4 to 1 at the rising edge of the divided clock C DIV ; and an inverter 432 configured to receive the logic signal S4 and output a logic signal S3 such that the logic signal S3 is the logical inversion of the logic signal S4.

[0145] The phase detector 400 operates in a periodic manner according to the reference clock C REF . A timing diagram of the phase detector 400 under the period of the reference clock C REF is shown in Figure 4B . As shown, the voltage controlled oscillator clock C VCO is periodic, with a period of T VCO , and every other period of the reference clock C REF , the voltage controlled oscillator clock C VCO has either N0 or N0+1 pulses. InFigure 4B In the example of FIG. 1 , N0 is 6. The multi-modulus frequency divider 350 generates a voltage controlled oscillator clock C VCO Divide the frequency to generate the divided clock C DIV , thereby generating a frequency-divided clock C at the first time instant t1 DIV The rising edge of the data trigger 431 generates the rising edge of the logic signal S4. Z -1 ”)411 controls the oscillator clock C according to the voltage VCO The frequency division clock C DIV Sampling is performed to generate the time reset clock CK1, so that the rising edge of the time reset clock CK1 is generated at the second time point t2, which is aligned with the voltage controlled oscillator clock C VCO The rising edge of the logic signal S1 is generated by the first phase / frequency detector 421 at the second time point t2. Z -1 ”) 412 controls the oscillator clock C according to the voltage VCO The time reset clock CK1 is sampled to generate the time reset clock CK2, so that the rising edge of the time reset clock CK2 is generated at the third time point t3, which is aligned with the voltage controlled oscillator clock C VCO The rising edge of the reference clock C causes the second phase / frequency detector 422 to generate a rising edge of the logic signal S2 at the third time point t3. REF The rising edge of the pulse of appears at the fourth time point t4, so that the data trigger 431 resets the logic signal S4 and generates the falling edge of the logic signal S4, so that the first phase / frequency detector 421 resets the logic signal S1 and generates the falling edge of the logic signal S1, and the second phase / frequency detector 422 resets the logic signal S2 and generates the falling edge of the logic signal S2, all of which occur at the fourth time point t4. In addition, the logic signal S3 is the logical inversion of the logic signal S4, and thus has a falling edge at the first time point t1 and a rising edge at the fourth time point t4.

[0146] It should be noted that the B-bit control command E[B-1:0] is in the divided clock C DIV The rising edge of the frequency division clock C DIV The rising edge of the logic signal S1 occurs before the pulse of the logic signal S2, and the B-bit control command E[B-1:0] remains unchanged until the frequency division clock C DIV Therefore, in the time window of the pulse of the logic signal S1 and the pulse of the logic signal S2, the value of the B-bit control command E[B-1:0] remains fixed; this condition is important to ensure that noise compensation can be performed correctly.

[0147] As Figure 5A shown, a charge pump (CP) 500 according to an embodiment of the present disclosure can be used to implement the charge pump 320. The charge pump 500 includes: a digital-to-analog converter (DAC) 510 configured to draw a first current I from a first node 501 and a second current I from a second node 502 respectively according to a logic signal S1, a logic signal S2, and a B-bit control command E[B-1:0], S0 and a second current I S1 ; a common-gate amplifier (CGA) 540 configured to provide a charge transfer path between the second node 502 and a third node 503 according to a logic signal S3; an integration capacitor C I configured to be discharged by the digital-to-analog converter 510 through the second current I according to a logic signal S4 S1 or charged by the common-gate amplifier 540 through a charging current I CH ; and a low-impedance active load 550 connected to the first node 501.

[0148] By way of example and not limitation, B is 3, and the digital-to-analog converter 510 includes: three current sources CS0, CS1, and CS2 configured to draw three tail currents I0, I1, and I2 respectively; and three current steering networks CDN0, CDN1, and CDN2, wherein the current steering network CDN0 steers the current I 00 from the first node 501 or the current I 01 from the second node 502 to the tail current I0 according to the corresponding bit E[0] of the logic signal S1, the logic signal S2, and the B-bit control command E[B-1:0], the current steering network CDN1 steers the current I 10 from the first node 501 or the current I 11 from the second node 502 to the tail current I1 according to the corresponding bit E[1] of the logic signal S1, the logic signal S2, and the B-bit control command E[B-1:0], and the current steering network CDN2 steers the current I 20 from the first node 501 or the current I 21 from the second node 502 to the tail current I2 according to the corresponding bit E[2] of the logic signal S1, the logic signal S2, and the B-bit control command E[B-1:0]. The first current I S0 is the sum of the current I 00 , the current I 10 , and the current I 20 , and the second current I S1 is the current I 01 , the current I11 and current I 21 sum.

[0149] As Figure 5B shown, in one embodiment, the current steering network CDN0 includes: three inverters INV1, INV2, and INV3 configured to receive the logic signals S1, S2, and the corresponding bit E[0] of the B-bit control command E[B-1:0] respectively, and output the logical inverse signals S1', S2' of the logic signals S1, S2 respectively, and the logical inverse value E'[0] of the corresponding bit E[0] of the B-bit control command E[B-1:0]; and six switches SW1, SW2, SW3, SW4, SW5, and SW6 controlled by the logical inverse value E'[0], the corresponding bit E[0] of the B-bit control command E[B-1:0], the logical inverse signal S1', the logic signal S1, the logical inverse signal S2', and the logic signal S2 respectively. At any moment, current I 00 and current I 01 one of them is steered to the tail current I0 through two switches: when both the logical inverse signal S1' and the logical inverse value E'[0] are high, current I 00 is steered to the tail current I0 through switch SW3 and switch SW1, or when both the logical inverse signal S2' and the corresponding bit E[0] of the B-bit control command E[B-1:0] are high, current I 00 is steered to the tail current I0 through switch SW5 and switch SW2; and when both the logic signal S1 and the logical inverse value E'[0] are high, current I 01 is steered to the tail current I0 through switch SW4 and switch SW1, or when both the logic signal S2 and the corresponding bit E[0] of the B-bit control command E[B-1:0] are high, current I 01 is steered to the tail current I0 through switch SW6 and switch SW2. By respectively changing the corresponding bit E[0] of the B-bit control command E[B-1:0], the logical inverse value E'[0], the tail current I0, current I 00 and current I 01 to the corresponding bit E[1](E[2]) of the B-bit control command E[B-1:0], the logical inverse value E'[1](E'[2]), the tail current I1(I2), current I 10 (I 20 ) and current I 11 (I 21 ), the same circuit of the current steering network CDN0 can be used to implement the current steering network CDN1(CND2).

[0150] The four logic signals S1, S2, S3, and S4 are all based on the reference clock C REF repeatedly occur periodically, and Figure 4B shown are the time-domain waveforms of the four logic signals S1, S2, S3, and S4 within the current cycle starting from time point t = 0 to time point t = T REF , where T REF is the period of the reference clock C REF . In the current cycle, the pulse of logic signal S1 starts at the second time point t2 and ends at the fourth time point t4, the pulse of logic signal S2 starts at the third time point t3 and ends at the fourth time point t4, and the pulse of logic signal S4 starts at the first time point t1 and ends at the fourth time point t4, while logic signal S3 is the logical inversion of logic signal S4. It should be noted that the first time point t1, the second time point t2, the third time point t3, and the fourth time point t4 are successive in time. When logic signal S4 is at a high level (and logic signal S3 is at a low level), the charge pump 500 is in the discharging stage, where the common-gate amplifier 540 is turned off, the top plate of the integrating capacitor C I is pulled up by logic signal S4, and when both logic signal S1 and logic signal S2 are at a high level or when logic signal S1 is at a high level but logic signal S2 is at a low level, the integrating capacitor C I is discharged by the second current I S1 drawn by the digital-to-analog converter 510. When logic signal S4 is at a low level (and logic signal S3 is at a high level), the charge pump 500 is in the transfer stage, where the common-gate amplifier 540 is turned on, the top plate of the integrating capacitor C I is pulled down by logic signal S4, and the integrating capacitor C I is charged by the charging current I CH from the common-gate amplifier 540. The charging current I CH comes from the error current I ER , which draws charge from the loop filter 560. The loop filter 560 is an embodiment of the loop filter 330 and includes a series resistor R S and a series capacitor C S connected in series and a shunt capacitor C S connected in parallel with the series-connected series resistor R S and series capacitor C P . Furthermore, it should be noted that between time point 0 and the first time point t1, the charge pump 500 is in the transfer stage and continues from the previous cycle, and between the fourth time point t4 and the period T REF , the charge pump 500 is in the transfer stage and will continue to the subsequent cycle. In the transfer stage, both logic signal S1 and logic signal S2 are at a low level, and the second current IS1 is zero, the first current I S0 is the sum of the tail current I0, the tail current I1, and the tail current I2.

[0151] The common-gate amplifier 540 includes a first N-channel metal-oxide semiconductor transistor 541, whose gate is controlled by a logic signal S3, whose source is connected to the second node 502, and whose drain is connected to the third node 503. The low-impedance active load 550 includes a second N-channel metal-oxide semiconductor transistor 551, whose gate is controlled by a gate voltage V G control, whose source is connected to the first node 501, and whose drain is connected to a drain voltage V D . The low-impedance active load 550 is used to provide a low impedance at the first node 501 so that the voltage V1 at the first node 501 can maintain a stable level during the transfer phase; this ensures that the initial conditions of the charge pump 500 are consistent and independent of the signals (i.e., independent of the logic signal S1, the logic signal S2, the logic signal S3, the logic signal S4, and the B-bit control command E[B-1:0]). It should be noted that the gate voltage V G needs to be high enough to turn on the second N-channel metal-oxide semiconductor transistor 551, and the drain voltage V D needs not to be lower than the gate voltage V G by more than the threshold voltage of the second N-channel metal-oxide semiconductor transistor 551; thus, the second N-channel metal-oxide semiconductor transistor 551 can be maintained in the saturation region and effectively provide a low impedance.

[0152] The combination of the phase detector 310 (implemented by the phase detector 400, for example) and the charge pump 320 (implemented by the charge pump 500, for example) provides certain advantages. First, as in the case of U.S. Patent Publication No. 7,629,854, since the charge transfer of the error current I ER is synchronized to the loop filter 330 using a two-phase scheme (according to the logic signal S4 and the logic signal S3), the time-domain noise generated when compensating a pulse with a fixed height and variable width with a pulse having a fixed width and variable height is not visible to the loop filter 330, and thus the time-domain noise becomes insignificant. Thus, the purpose of eliminating the time-domain instantaneous noise (which is deterministic) can be achieved. Second, different from the case of U.S. Patent Publication No. 7,629,854, no operational amplifier is required; thus, it helps to avoid the additional random noise and power consumption brought about by using an operational amplifier. Third, since a noise compensation scheme is used (using the digital-to-analog converter 510 according to the B-bit control command B[B-1:0], and the B-bit control command E[B-1:0] is the quantization value of the predicted timing of the divided clock C DIV ), the second current I S1 drawn by the integrating capacitor C during the discharge phaseI The total charge is compensated, so as long as the quantization value of the compensation (i.e., the value of B) is fine enough, the total charge is nearly fixed and has small variation between periods. Thus, the voltage V2 of the second node 502 has small variation between periods at the end of the discharge phase. During the transfer phase, charge will be drawn from the loop filter 330 through the error current I ER and generate a charging current I CH until the voltage V2 rises to a level that causes the first N-channel metal-oxide-semiconductor transistor 541 to turn off. At the end of the transfer phase, the voltage V2 will be approximately the voltage level of the logic signal S3 minus the threshold voltage of the first N-channel metal-oxide-semiconductor transistor 541, and its value is also nearly fixed and has very small variation between periods. Since the voltage V2 has small variation between periods, the adverse effects of the circuit non-linear characteristics associated with the digital-to-analog converter 510 and the common-gate amplifier 540 are also small. Thus, it helps to reduce the deterministic noise caused by the circuit non-linear characteristics.

[0153] It should be noted that the phase detector 400 is only an exemplary embodiment that generates the logic signals S1, S2, S3, and S4 based on the voltage-controlled oscillator clock C VCO , the reference clock C REF and the divided clock C DIV . Many modifications and variations can be made. Anyway, it is necessary to ensure that the rising edge of the logic signal S4 does not occur later than the rising edge of the logic signal S1, and the falling edge of the logic signal S4 does not occur earlier than the rising edge of the reference clock C REF ; this is the condition that can ensure the normal operation of the charge pump 320.

[0154] Switches, phase / frequency detectors, inverters, accumulators, data flip-flops, unit-period delays (z -1 ) and current sources are all well known in the prior art, so they will not be explained in detail. The circuit designer can freely choose any circuit known in the prior art according to his own judgment.

[0155] Those of ordinary skill in the art will easily observe that many modifications and variations can be made to the apparatus and method while retaining the teachings of the present disclosure. Therefore, the above should not be construed as being defined only by the recitations of the appended claims.

Claims

1. A divide-by-charge pump, comprising: A digital-to-analog converter configured to draw a first current and a second current from a first node and a second node respectively according to a first logic signal, a second logic signal, and a B-bit control command, where B is an integer greater than 1; A common-gate amplifier configured to provide a path for charge transfer between the second node and a third node according to a third logic signal; An integrating capacitor connected to the second node and configured to be discharged by the digital-to-analog converter or charged by the common-gate amplifier according to a fourth logic signal; and A low-impedance active load connected to the first node, where: The first logic signal includes a first pulse that starts at a second time point and ends at a fourth time point, and the second time point lags behind a first time point but leads a third time point, and the fourth time point lags behind the third time point; The second logic signal includes a second pulse that starts at the third time point and ends at the fourth time point; The fourth logic signal includes a fourth pulse that starts at the first time point and ends no earlier than the fourth time point; The third logic signal is the inverse of the fourth logic signal; And During a time window of the fourth pulse, the value of the B-bit control command remains fixed.

2. The divide-by-charge pump according to claim 1, wherein the digital-to-analog converter includes B current sources configured to draw B tail currents guided by B current guiding networks, and each of the current guiding networks is controlled by a corresponding bit of the B-bit control command, the first logic signal, and the second logic signal to determine whether the corresponding tail current is guided out from the first node or the second node.

3. The divide-by-charge pump according to claim 2, wherein when both the first logic signal and the corresponding bit are at a low level or when the second logic signal is at a low level and the corresponding bit is at a high level, the corresponding tail current is guided out from the first node; when both the second logic signal and the corresponding bit are at a high level or when the first logic signal is at a high level and the corresponding bit is at a low level, the corresponding tail current is guided out from the second node.

4. The divide-by-charge pump according to claim 1, wherein the low-impedance active load includes an N-channel metal-oxide-semiconductor transistor, a source of which is connected to the first node, a gate of which is controlled by a gate voltage high enough to turn on the N-channel metal-oxide-semiconductor transistor, a drain of which is connected to a drain voltage, and the drain voltage is not lower than the gate voltage by more than a threshold voltage of the N-channel metal-oxide-semiconductor transistor.

5. The divide-by-charge pump according to claim 1, wherein the common-gate amplifier includes an N-channel metal-oxide-semiconductor transistor, a source of which is connected to the second node, a gate of which is controlled by the third logic signal, and a drain of which is connected to the third node.

6. The divide-ratio charge pump as claimed in claim 1, wherein the first logic signal, the second logic signal, the third logic signal, and the fourth logic signal are generated by a phase detector configured to detect a first timing difference between a reference clock and a first time-reset clock, a second timing difference between the reference clock and a second time-reset clock, the first time-reset clock, and the second time-reset clock, wherein the second time-reset clock is established by performing a timing reset on a divided clock according to a voltage-controlled oscillator clock, and the divided clock is generated by dividing the voltage-controlled oscillator clock by a divide value using a multi-modulus divider.

7. The divide-ratio charge pump as claimed in claim 6, wherein the second time-reset clock is identical to the first time-reset clock except for a delay of one period of the voltage-controlled oscillator clock being removed.

8. The divide-ratio charge pump as claimed in claim 7, wherein the divide ratio is equal to a fixed integer value plus a carry bit generated by an accumulator.

9. The divide-ratio charge pump as claimed in claim 8, wherein the accumulator performs a cumulative sum operation on a fractional value greater than 0 but less than 1 according to the divided clock, outputs the carry bit to indicate the occurrence of a carry event when the cumulative sum value is greater than or equal to 1, subtracts 1 from the cumulative sum value when the carry event occurs, and quantizes the cumulative sum value into the B-bit control command.

10. The divide-ratio charge pump as claimed in claim 9, wherein the first time point is associated with a rising edge of the divided clock, the second time point is associated with a rising edge of the first time-reset clock, the third time point is associated with a rising edge of the second time-reset clock, and the fourth time point is associated with a rising edge of the reference clock.

Images