A two-step ADC circuit based on an auto-corrected DCO, conversion method and applications

Abstract

This invention discloses a two-step ADC circuit, conversion method, and application based on an automatically calibrated DCO. The circuit includes: automatically calibrating the DCO to perform frequency calibration of the coarse and fine quantization clocks; the first step of the ADC is a single-step M-bit SS ADC coarse quantization, and the second step is fine quantization. For fine quantization, the residual time is first extracted by a residual time detection module, and then the DCO is activated to generate a fine quantization clock to perform N-bit time-to-digital quantization on the residual time. Both steps together achieve an ADC with M+N-bit quantization accuracy. The automatic calibration ensures that the output fine quantization clock frequency of the DCO meets the frequency matching requirements of the two-step ADC system for the coarse and fine quantization clock frequencies. This circuit features small area, high sampling rate, high resolution, low power consumption, no need for global high-frequency clock transmission, and limited high-frequency clock duration, making it suitable for high-performance image sensors and infrared focal plane detector readout circuits.

Description

Technical Field

[0001] This invention relates to ADC circuits, specifically to a two-step analog-to-digital converter (ADC) circuit, conversion method, and application based on an automatically calibrated digitally controlled ring oscillator (DCO). Background Technology

[0002] Image sensors typically employ column-level analog-to-digital converters (ADCs) for analog-to-digital quantization. Single-slope ADCs (SS ADCs) are widely used in image sensors. Each column uses a comparator and a counter, and the entire array shares a single ramp signal generation circuit. This design is simple, occupies a small area, and is a suitable ADC architecture for array applications such as image sensors.

[0003] However, high-performance image sensors and infrared detectors typically have high dynamic ranges, requiring their corresponding readout circuits to have ADCs with an accuracy of 14 bits or higher. As the area of ​​image sensor arrays and frame rates continue to increase, the conversion speed requirements for ADCs also continuously rise. The conversion of an SS ADC is essentially a conversion from the voltage domain to the time domain and then to the digital domain. In an SS ADC, one counting clock cycle represents the SS ADC's time resolution. An N-bit SS ADC has a conversion period of 2... N To increase the sampling rate, the counting clock frequency must be increased within one CLK clock cycle, thus increasing the time resolution. Therefore, a high-frequency clock is required for counting. In the column-level digital readout circuit of an image sensor, the SS ADC is arranged on an area array. A high-frequency clock needs to be sent to all column-level SS ADCs in the entire array. High-frequency clocks not only introduce significant power consumption, but also pose a major challenge in ensuring transmission quality. For example, a 14-bit traditional SS ADC with a sampling rate of 100kS / s requires a counting clock signal with a frequency as high as 1.64GHz to meet the requirements. Transmitting a 1.64GHz clock is a huge challenge.

[0004] Because single-step SS ADCs are limited by the counting clock frequency, some studies have proposed a two-step (M+N) bit SS ADC scheme with coarse and fine clocks, such as... Figure 1 The two-step coarse-fine clock shown is used for the coarse clock in the first step of coarse quantization. The low frequency is used to control the high-order MSB counting of the M-bit; it is also used as the fine clock frequency for the second step of fine quantization. The high-order clock is used to control the N-bit low-order LSB counting. The coarse and fine clocks of this two-step ADC must have a strict frequency relationship to meet the system requirements of the two-step ADC, as shown in equation (1):

[0005] (1)

[0006] The quantization results of the two-step coarse-fine clock are then combined as shown in equation (2):

[0007] (2)

[0008] Figure 1 The toggle time of the comparator It can detect the comparison flip time. Until the rising edge of the next coarse quantization clock MSB_CLK The time, the residual time Recorded as Use the refined clock LSB_CLK to store this residual time segment. Count quantization. Due to It is the part included in the multi-count of that MSB, so the counting duration of the MSB can be used. Subtract the remaining time from the middle The final voltage-to-time conversion is represented by equation (3):

[0009] (3)

[0010] Converting the time domain to the digital domain is expressed by equation (4):

[0011] (4)

[0012] By adopting this two-step ADC method, the conversion rate of the ADC can be greatly improved. As can be seen from the above working principle, for a (M+N) bit single-step SS ADC, the quantization time is as shown in equation (5):

[0013] (5)

[0014] For a (M+N) bit two-step coarse-fine clock, the quantization time is only as shown in equation (6):

[0015] (6)

[0016] For example, if M=9, N=5, and the coarse quantization clock MSB_CLK is designed to be 50MHz, then the fine quantization clock LSB_CLK is 1.6GHz. Compared to a single-step SS ADC, the two-step coarse-fine clock ADC significantly improves the sampling rate, and the reduced frequency of the coarse quantization clock MSB_CLK also greatly reduces the power consumption of the counter and transmission lines. However, transmitting such a high-frequency clock as the fine quantization clock LSB_CLK (1.6GHz) to the entire array is very difficult and introduces huge power consumption. Furthermore, the frequency relationship between the coarse quantization clock MSB_CLK and the fine quantization clock LSB_CLK is difficult to match perfectly under the parasitic RC effects introduced by the large array traces. Therefore, this two-step coarse-fine clock ADC is difficult to implement for transmitting the high-frequency fine quantization clock LSB_CLK, and more seriously, it introduces errors in the coarse quantization residual time and the fine quantization process, which will cause problems such as missing or duplicate codes in the ADC, severely affecting the imaging quality of the image sensor. Summary of the Invention

[0017] The purpose of this invention is to overcome the clock matching difficulties of single-step column-level SS ADCs and two-step coarse-fine clock ADCs, while also overcoming their application limitations in area array image sensors. It provides a two-step ADC circuit and conversion method based on an automatically calibrated DCO. This circuit features small area, high sampling rate, high resolution, low power consumption, no need for global high-frequency clock transmission, and limited high-frequency clock duration. The DCO used has an automatic calibration function, the digital calibration scheme has no static power consumption, is non-volatile, calibration parameters can be stored, and it has a small area. Through this DCO calibration, the strict frequency matching requirements of the two-step ADC system can be met, ensuring the linearity of the two-step ADC. It is suitable for application in high-performance image sensors and infrared focal plane detector readout circuits.

[0018] According to the first aspect, the technical solution adopted by the present invention is as follows:

[0019] M-bit ramp generator module, used to generate the ramp voltage required for ADC quantization. ramp voltage The range is [V L V H ],Should The signal is connected to the positive input terminal of the comparator module.

[0020] Comparator module, used to compare analog signals and slope voltage The size of HIT is the output of the comparator;

[0021] The M-bit counter module is used for quantization counting and storage during the first step of M-bit coarse quantization.

[0022] The residual time detection module is used to detect the residual time LSB_EN between the comparator's HIT flip and the rising edge of the next coarse quantization clock MSB_CLK after the comparator's output HIT flips in the first coarse quantization step.

[0023] The N-bit DCO and auto-calibration module includes a ring oscillator consisting of one NAND gate and four NOT gates connected end-to-end, an N-bit ADC counter (used for counting during ADC fine quantization), an N-bit calibration counter (operating in calibration mode), one DFF and one AND gate, one Z-bit calibration counter, and a Z-bit binary weighted switching capacitor connected to them. It is used to fulfill the frequency requirements of the two-step ADC during the auto-calibration phase, completing frequency calibration to ensure the coarse quantization clock frequency meets the requirements. and precise clock frequency Between satisfy The corresponding correction parameters are stored in the register. During the second step of ADC fine-tuning, the residual time LSB_EN effectively turns on the ring oscillator and generates the fine-tuning clock LSB_CLK locally. This eliminates the need to transmit the high-frequency fine-tuning clock LSB_CLK throughout the entire array. Furthermore, the ring oscillator is only turned on during the residual time LSB_EN, and the ring oscillator operates for a very short time, thus greatly saving power consumption.

[0024] The connections and interactions between the various modules are as follows:

[0025] This refers to the input analog voltage, ADC_EN is the ADC quantization enable signal, MSB_CLK is the coarse quantization SS ADC operating clock, and the ramp voltage. From M bits The ramp generator module generates

[0026] The positive input terminal of the comparator module is connected to a ramp voltage. The negative input terminal is connected to the input signal. The comparison output is the HIT signal. When the ramp voltage... Greater than the input signal When the comparator's output HIT signal is 1, the ramp voltage... Less than the input signal At this time, the comparator's output HIT signal is 0. The comparator's output HIT signal and the quantization enable ADC_EN are ANDed together to generate the coarse quantization enable MSB_EN signal. On one hand, the coarse quantization enable MSB_EN is used to control the M-bit counter, which counts according to the clock MSB_CLK and outputs the coarse quantization digital code MSB_DOUT. <m:1>On the other hand, the coarse quantization enable MSB_EN signal is connected to the residual time detection module. The residual time detection module detects the residual time LSB_EN pulse signal from the coarse quantization enable MSB_EN signal to the next coarse quantization clock MSB_CLK. The residual time LSB_EN signal is connected to the N-bit DCO automatic correction module.

[0027] The N-bit DCO and automatic calibration module includes a ring oscillator consisting of one NAND gate and four NOT gates connected end-to-end, an N-bit ADC counter (used for counting during the ADC fine-tuning stage), an N-bit calibration counter (operating in calibration mode), one DFF and one AND gate, one Z-bit calibration counter, and Z-bit binary weighted switching capacitors C0, C1, ..., C1 connected to it. z-1 The switched capacitor array uses a binary weighted capacitor array, meaning that the capacitance value of each bit satisfies C. i =2 i C0,i The Z-position switched capacitor array is connected as follows: the lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off state of switch S0 is controlled by signal CAL_Q. <0> Control; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off state of switch S1 is controlled by signal CAL_Q. <1> Control; and so on, capacitor C z-1 The lower electrode is grounded, and the upper electrode is connected to switch S. z-1 One end, switch S z-1 The on / off state is determined by the signal CAL_Q <z-1>Control; the switches S0, S1, ..., S of the control capacitor array used. z-1 The other end of the capacitor is connected together as the total capacitive load CAP_LOAD, which is connected to the output node of a NOT gate in the ring oscillator circuit. The DCO ring oscillator is turned on by either the correction enable CAL_EN or the residual time LSB_EN. When the correction enable CAL_EN is active, it enters automatic correction mode; when the residual time LSB_EN is active, it enters the quantization mode of the second residual time step of the two-step ADC. Once the ring oscillator is turned on, it generates a fine quantization clock LSB_CLK. This LSB_CLK clock signal is connected to the N-bit ADC counter to generate the fine quantization digital code LSB_DOUT. <n:1>On the other hand, the precision clock LSB_CLK is connected to the N-bit correction counter, which generates an OVER_FLOW signal pulse when it reaches full. The Z-bit correction counter receives the OVER_FLOW signal from the N-bit correction counter as input. This counter counts based on the rising edge of the OVER_FLOW pulse and outputs a count result of CAL_Q. <z-1:0>Z-bit CAL_Q <z:1>The signal feedback is connected to the Z-position capacitor array switches S0, S1, ..., S z-1 This is used to control the connection of the switch array. The frequency of the precision clock LSB_CLK is adjusted by controlling the number of capacitors connected to the ring oscillator, and the correction parameters are stored in CAL_Q after correction is complete. <z-1:0>middle.

[0028] RST is the reset signal, connected to the N-bit ADC counter, the N-bit calibration counter, the Z-bit calibration counter, and DFF, used for global reset.

[0029] The residual time detection module, after coarse quantization, outputs the residual time pulse width (LSB_EN). During the active high level of residual time LSB_EN, a ring oscillator is activated to generate the fine quantization clock LSB_CLK. An N-bit ADC counter is then used to quantize the residual time from time to digital, outputting the fine quantized digital code LSB_DOUT. <n:1>;

[0030] Ultimately, the ADC outputs (M+N) bits of coarse quantization data, MSB_DOUT. <m:1>and refined numeric code LSB_DOUT <n:1>The combined (M+N) bit data DOUT[M+N:1].

[0031] According to the second aspect, the technical solution adopted by the present invention is as follows:

[0032] A two-step analog-to-digital converter (ADC) circuit and conversion method based on an automatically calibrated digitally controlled ring oscillator (DCO) includes the following steps:

[0033] Step 1, DCO begins automatic digital calibration, the method includes:

[0034] Step 1.1: The reset signal RST is invalid, the CAL_FLAG signal is valid, and the coarse quantization clock MSB_CLK is generated by ANDing the DFF and CAL_FLAG signals to produce the calibration enable CAL_EN, which is used to control the automatic calibration mode. The high-level pulse of the calibration enable CAL_EN signal is one clock cycle of the coarse quantization clock MSB_CLK. When the calibration enable CAL_EN is high, the ring oscillator in the DCO module is started to generate the fine quantization clock LSB_CLK, so that the N-bit calibration counter starts counting within one clock cycle of the coarse quantization clock MSB_CLK according to the fine quantization clock LSB_CLK.

[0035] Step 1.2, CAL_Q <z-1:0>The signal is connected to the switched capacitor load at the corresponding Z-position, CAL_Q <0> The signal controls whether the capacitor at bit 0 is connected to the ring oscillator, CAL_Q <1> The signal controls whether the capacitor in position 1 is connected to the load of the ring oscillator, and so on, CAL_Q <z-1>The signal controls whether the capacitor at position Z-1 is connected to the ring oscillator;

[0036] Step 1.3, if In a coarse quantization clock MSB_CLK, when the N-bit correction counter reaches its full count, an overflow signal OVER_FLOW is generated. The rising edge of the OVER_FLOW signal increments the count value of the Z-bit correction counter by 1, and the count result of this counter is CAL_Q. <z-1:0>Increasing by 1 will add one unit of capacitance to the total capacitive load CAP_LOAD node, thereby reducing the ring oscillator's capacitance. Frequency; in the second loop, if In a coarse quantization clock MSB_CLK, an N-bit correction counter will generate an overflow signal OVER_FLOW, and the counting result will be CAL_Q. <z-1:0>Adding 1 will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, further reducing the ring oscillator's capacitance. The frequency repeats in this cycle until the desired frequency is met. Therefore, in a coarse quantization clock MSB_CLK, the N-bit correction counter will no longer generate the overflow signal OVER_FLOW, and thus CAL_Q <z-1:0>The count value remains unchanged, meaning the total capacitive load CAP_LOAD node remains constant;

[0037] Step 1.4: When the CAL_FLAG signal equals 0, the calibration mode ends, satisfying the condition. The correction result CAL_Q <z-1:0>It is stored in the Z-bit correction counter and used during two-step ADC quantization.

[0038] Step 2: The two-step ADC begins quantization, first performing M-bit coarse quantization, the process of which includes:

[0039] Step 2.1: Quantization enable ADC_EN is active, ramp enable RAMP_EN signal is active, ramp generator starts integration, ramp voltage... From high reference voltage V H Discharge, input voltage The range should include the ramp voltage. Voltage range [V] L V H ]middle;

[0040] Step 2.2, when the ramp voltage Compared to the input signal When the output HIT signal of the comparator is high, the generated coarse quantization enable MSB_EN is active, and the M-bit coarse quantization counter starts counting in conjunction with the coarse quantization clock MSB_CLK, generating the coarse quantization digital code MSB_DOUT. <m:1>;

[0041] Step 2.3, when the ramp voltage Compared to input voltage When low, the comparator's output HIT signal toggles from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization counter stops counting, and the count value is the coarse quantization digital code MSB_DOUT. <m:1>;

[0042] Step 3: After the comparator's output HIT signal flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization process, including:

[0043] Step 3.1: The coarse quantization enable signal MSB_EN and the coarse quantization working clock signal MSB_CLK pass through the residual time detection module, and the residual time LSB_EN is output.

[0044] Step 3.2: During the residual time LSB_EN high level, the DCO is enabled. Since the DCO has already coarsely quantized the clock frequency during the calibration phase... and the frequency of the precision clock Correction satisfies Therefore, the precision clock LSB_CLK generated by the DCO meets the system requirements of a two-step ADC. During the high-level residual time, the N-bit ADC counter counts according to the precision clock LSB_CLK. When the residual time LSB_EN becomes 0, the N-bit ADC counter stops counting and outputs the precision digital code LSB_DOUT. <n:1>;

[0045] Step 4, the process of merging coarse and fine quantization, includes:

[0046] The coarse quantization numeric code MSB_DOUT <m:1>With refined numeric code LSB_DOUT <n:1>Combined into the final quantized value DOUT<M+N:1> There are a total of (M+N) bits, of which:

[0047] (7)

[0048] In equation (7): DOUT<M+N:1> This is the final quantization result output by the two-step ADC, totaling (M+N) bits, where the high M bits are the coarse quantization digital code MSB_DOUT. <m:1>The lower N bits are the refined numeric code LSB_DOUT. <n:1>.

[0049] Furthermore, the coarse quantization in step 2 uses an M-bit ramp voltage. When the two-step ADC starts working, the ramp voltage From high reference voltage V H Initially, after 2 M Integrate to the low reference voltage V after one coarse quantization clock cycle MSB_CLK. L After the entire two-step ADC quantization is completed, it is reset to the high reference voltage V. H .

[0050] Furthermore, all two-step ADCs in the entire readout circuit array share a single ramp voltage. It is generated by the M-bit ramp generator module.

[0051] According to a third aspect, the present invention relates to the application of a two-step ADC circuit based on an automatically calibrated DCO in the readout circuit of a high-performance image sensor and an infrared focal plane detector, wherein all two-step ADCs in the entire readout circuit array share a single ramp voltage. It is generated by the M-bit ramp generator module.

[0052] The principle of this invention is as follows:

[0053] The two-step analog-to-digital converter circuit based on an automatically calibrated DCO of this invention adopts a two-step ADC structure. The key feature is the use of a digitally controlled ring oscillator for automatic coarse and fine clock frequency calibration, which addresses the frequency requirements of the two-step ADC. The first step, coarse quantization, uses a single-step SS ADC. The second step, fine quantization, first extracts the residual time LSB_EN through a residual time detection module, then uses the residual time LSB_EN to activate the DCO to generate a fine quantization clock LSB_CLK to count and quantize the residual time. The calibration circuit ensures the frequency of the fine quantization clock LSB_CLK generated by the DCO during the transition from coarse to fine quantization. and the frequency of the externally input coarse quantization clock MSB_CLK It meets the frequency matching requirements of a two-step ADC system.

[0054] The automatically calibrated DCO in this two-step structure is a digitally controlled local ring oscillator. First, it solves the problem of generating a high-frequency, precise clock LSB_CLK to achieve high time resolution, thus addressing the high power consumption and transmission difficulties associated with high-frequency full-array transmission. Second, during a single analog-to-digital conversion, the ring oscillator only activates during the high-level period of the residual time LSB_EN, significantly saving power. Third, and crucially, this automatically calibrated DCO uses digital control to calibrate the ring oscillator, and can perform calibration before each ADC operation, once per frame, or at any time in the background. Its calibration parameters are stored internally in a counter, making it non-volatile. The automatic calibration uses the frequency of the precise clock LSB_CLK generated by the DCO... and the frequency of the coarse quantization clock MSB_CLK The frequency requirements of a two-step ADC system must be met: This ensures the seamless integration of the M-bit coarse quantization SS ADC and the N-bit fine quantization for the residual time in the two-step structure, ultimately achieving the analog-to-digital conversion function with (M+N)-bit quantization accuracy through both steps.

[0055] First, in the coarse quantization stage, the voltage is converted into a counting duration using the principle of the SS ADC, and then coarse quantization counting is performed using the coarse quantization clock MSB_CLK. The first step, coarse quantization, represents the minimum voltage resolution in the SS ADC. As shown in equation (8), the temporal resolution of coarse quantization As shown in equation (9):

[0056] (8)

[0057] (9)

[0058] In the formula:

[0059] It is the high voltage of the reference voltage of the ramp voltage generator. It is the low voltage of the reference voltage of the ramp voltage generator, the ramp voltage. Generated by a ramp generator, ramp voltage The range is [ Therefore, the quantizable input analog voltage V in The range is [ ].

[0060] After the first step of coarse quantization conversion by SS ADC, the first step of time resolution Unquantifiable residual time The second step is quantization. After the comparator flips, the residual time detection module outputs the residual time LSB_EN pulse width, which could not be quantized in the first step. Fine quantization completes the conversion of the residual time to digital code: the residual time LSB_EN pulse width controls the DCO's on / off state. During the high-level period of the residual time LSB_EN, the DCO is on, generating the fine quantization clock LSB_CLK. Within the residual time LSB_EN pulse width, the N-bit ADC counter starts counting according to the fine quantization clock LSB_CLK and outputs LSB_DOUT. <n:1>When the residual time LSB_EN goes low, the N-bit ADC counter stops counting, completing the fine-tuning process. The two conversion steps together complete the (M+N)-bit ADC. for

[0061] (10)

[0062] It is the minimum resolvable voltage in the second-step refinement stage, and the equivalent time resolution of the second step is... Equation (11) is shown

[0063] (11)

[0064] This invention employs a two-step method to digitally quantize the residual time LSB_EN after coarse quantization using a fine quantization clock LSB_CLK generated by a DCO. The DCO of this invention, with automatic correction, locally generates a high-frequency fine quantization clock LSB_CLK, and the frequency of the coarse quantization clock LSB_CLK is... The DCO guarantees that the corrected frequency satisfies equation (12).

[0065] (12)

[0066] During automatic calibration, the frequency of the output fine-tuning clock LSB_CLK is changed by iteratively controlling the capacitor load connected to the DCO. CAL_Q <z-1:0>The signal is connected to the switched capacitor load at the corresponding Z-position, CAL_Q <0> The signal controls whether capacitor C0 at bit 0 is connected to the ring oscillator, CAL_Q <1> The signal controls whether capacitor C1 in position 1 is connected to the load of the ring oscillator, and so on, CAL_Q <z-1>Signal controls capacitor C at position Z-1 Z-1 Whether to connect a ring oscillator.

[0067] like In a coarse quantization clock MSB_CLK, the N-bit correction counter will fill up, generating an overflow signal OVER_FLOW. Each OVER_FLOW pulse edge increments the count value of the Z-bit correction counter by 1, and the count result of this counter is CAL_Q. <z-1:0>Adding 1 will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, thereby reducing the ring oscillator's capacitance. Frequency; in the second loop, if In a coarse quantization clock MSB_CLK, an N-bit counter will generate an overflow signal OVER_FLOW, and the counting result will be CAL_Q. <z-1:0>Adding 1 will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, further reducing the ring oscillator's capacitance. The frequency is repeated until the N-bit counter stops generating the overflow signal OVER_FLOW within one coarse quantization clock cycle (MSB_CLK), then CAL_Q... <z-1:0>The count value remains unchanged, meaning the correction is satisfied. At this point, frequency correction is complete, and the correction parameters are directly stored in CAL_Q. <z-1:0>middle.

[0068] The ring oscillator in the DCO design is affected by process, voltage, and temperature (PVT) conditions. Since the operating temperature of the infrared image sensor is fixed, and the ring array voltage can be provided by a high-precision LDO, and considering factors such as process angles during the design phase, by designing an appropriate ring oscillator size, it is possible to ensure… The determined frequency range.

[0069] In this invention, a local ring oscillator provides the high-frequency clock required for the second step of digital conversion of the residual time, solving the difficulty of high-frequency clock transmission along the array. The key DCO automatic correction scheme of this invention automatically corrects the frequency of the ring oscillator, solving the problem of coarse clock frequency in the two-step coarse clock and coarse quantization process. And precise clock precise clock frequency The matching requirements between them must be met after the correction is completed. It meets the system matching requirements of two-step quantization, and the correction function can be set to automatic background correction or external command correction.

[0070] The beneficial effects of this invention are:

[0071] (1) The digital control automatic correction scheme adopted by the two-step analog-to-digital converter based on automatic correction DCO generates a high-frequency fine-tuning clock LSB_CLK locally, and automatically corrects the frequency of the fine-tuning clock LSB_CLK. Corrected to coarse quantization clock MSB_CLK frequency of times, that is: It automatically performs digital correction internally, fulfilling the frequency requirements of the two-step ADC system. This correction module ensures the normal operation of the two-step ADC and the correct connection between the two steps, controlling the ADC's integral nonlinearity (DNL) within... Within this range, the image quality of the sensor imaging system can be significantly improved. This DCO correction method can be performed in the background, every frame time, or every line time, and the correction parameters are non-volatile and easy to store.

[0072] (2) The DCO in the two-step analog-to-digital converter based on automatic correction DCO generates a high-frequency precision clock LSB_CLK locally, which not only overcomes the high power consumption introduced by high-frequency clock transmission in the full array of image sensors, but also avoids the difficulty of high-speed clock layout and wiring, greatly reducing power consumption, which is beneficial to the low-power application of large array sensors.

[0073] (3) The high-frequency clock LSB_CLK required in the second step of the two-step analog-to-digital converter based on automatic correction DCO is only turned on during the short residual time LSB_EN in a single conversion, which reduces ADC power consumption and greatly reduces power consumption overhead, which is beneficial for low-power applications of large-area array sensors.

[0074] (4) A two-step analog-to-digital converter based on an auto-calibrated DCO adopts a two-step structure, reducing the conversion time of a single-step high-precision SS ADC with the same number of bits, greatly improving the conversion speed and reducing power consumption. This two-step ADC reduces the conversion time of a single-step SS ADC by 2... (M+N) The MSB_CLK clock cycles are reduced to 2. M A single coarse quantization clock cycle (MSB_CLK) can greatly improve conversion speed and reduce power consumption, making it suitable for high-speed sensor applications.

[0075] (5) The two-step analog-to-digital converter based on automatic calibration DCO can achieve high precision (above 14 bits), high sampling rate (100kSps), and low power consumption, making it suitable for large-area image sensors and infrared detectors. It provides flexibility in the selection of the number of bits in the two steps, and by appropriately selecting the coarse quantization bits M and fine quantization bits N, it can meet the needs of different sensor imaging systems. Attached Figure Description

[0076] Figure 1 This describes the principle of a coarse-fine clock two-step SS ADC.

[0077] Figure 2 This is a circuit schematic diagram of the two-step analog-to-digital converter based on automatic correction DCO of the present invention.

[0078] Figure 3 This is a timing diagram of the two-step analog-to-digital converter based on automatic correction DCO of the present invention. Detailed Implementation

[0079] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, but the scope of protection of the present invention is not limited to the following embodiments.

[0080] like Figure 2 As shown, a two-step analog-to-digital converter circuit based on an automatically corrected DCO according to the present invention includes:

[0081] M position The system includes: a ramp generator module; a comparator module; an M-bit counter module; a residual time detection module; and an N-bit DCO and automatic correction module. The components described are: The signal is generated by a ramp generator circuit, and the ramp voltage is... The range is [V L V H The ramp voltage The signal is connected to the positive input terminal of the comparator module. This refers to the input analog voltage, ADC_EN is the enable signal for the ADC to start quantization, MSB_CLK is the coarse quantization clock for the SS ADC, and the ramp voltage... The ramp voltage is generated by the M-bit ramp generator module. and input signal These are connected to the positive and negative terminals of the comparator, respectively. The positive input terminal of the comparator module is connected to... The negative input terminal is connected to the output signal. The comparator outputs a HIT signal. When the ramp voltage... Greater than the input signal When the comparator's output HIT signal is 1, Less than At this time, the comparator module's output HIT signal is 0. The HIT signal and the enable signal ADC_EN generate the coarse quantization enable signal MSB_EN. On one hand, the coarse quantization enable MSB_EN is used to control the M-bit counter, which counts according to the coarse quantization clock MSB_CLK to generate the coarse quantization digital code MSB_DOUT. <m:1>On the other hand, the coarse quantization enable MSB_EN signal is connected to the residual time detection module. The residual time detection module detects the residual time LSB_EN from the coarse quantization enable MSB_EN signal to the coarse quantization clock MSB_CLK. The residual time LSB_EN signal is connected to the N-bit DCO and automatic correction module.

[0082] The N-bit DCO and automatic calibration module includes a ring oscillator consisting of one NAND gate and four NOT gates connected end-to-end, an N-bit ADC counter (used for counting during ADC fine-tuning), an N-bit calibration counter (used in calibration mode), one DFF and one AND gate, one Z-bit calibration counter, and Z-bit binary weighted switched capacitors connected to it. This switched capacitor array is a binary weighted capacitor array C0, C1, ... C1. z-1 That is, the capacitance value of each bit satisfies C i =2 i C0, i The Z-position switched capacitor array is connected as follows: the lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off state of switch S0 is controlled by signal CAL_Q. <0> Control; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off state of switch S1 is controlled by signal CAL_Q. <1> Control; and so on, capacitor C z-1 The lower electrode is grounded, and the upper electrode is connected to switch S. z-1 One end, switch S z-1 The on / off state is determined by the signal CAL_Q <z-1>Control; S 0， S1,.., S z-1 The ends of the circuit without the switch are connected together to serve as the output node of a certain stage of the NOT gate in the CAP_LOAD circuit of the ring oscillator.

[0083] The activation of the DCO ring oscillator is controlled by either the correction enable CAL_EN or the residual time LSB_EN. When the correction enable CAL_EN is active, the ring oscillator is activated, generating a fine-tuning clock LSB_CLK. This LSB_CLK clock signal is then connected to the N-bit ADC counter to generate the fine-tuning digital code LSB_DOUT. <n:1>On the other hand, the precision quantization clock signal LSB_CLK is connected to the N-bit correction counter to generate the overflow signal OVER_FLOW. The input to the Z-bit correction counter is the OVER_FLOW signal; this counter counts based on the rising edge of the OVER_FLOW pulse and outputs the count result as CAL_Q. <z-1:0>Z-bit CAL_Q <z:1>The signal feedback is connected to the Z-position capacitor array switches S0, S1, …, S z-1 The frequency of the precision clock LSB_CLK is adjusted by controlling the number of capacitors connected to the ring oscillator, and the result is stored in CAL_Q after calibration. <z-1:0>middle.

[0084] RST is the reset signal, connected to the N-bit ADC counter, the N-bit calibration counter, the Z-bit calibration counter, and DFF, used for global reset.

[0085] The residual time detection module outputs the residual time pulse width LSB_EN after coarse quantization. During the active high level of residual time LSB_EN, a ring oscillator is activated to generate the fine quantization clock LSB_CLK, which is fed into an N-bit ADC counter for counting, and outputs the fine quantization digital code LSB_DOUT. <n:1>Ultimately, the ADC outputs (M+N) bits of coarse quantization data, MSB_DOUT. <m:1>and refined numeric code LSB_DOUT <n:1>The combined (M+N) bit data DOUT[M+N:1].

[0086] like Figure 3 As shown, the timing diagram of the conversion method of a two-step analog-to-digital converter based on automatic correction DCO of the present invention is as follows:

[0087] (1) The DCO begins automatic digital calibration. The automatic calibration process is as follows:

[0088] a) The RST reset signal is invalid, the CAL_FLAG signal is valid, and the coarse quantization clock MSB_CLK is passed through a DFF and then combined with the CAL_FLAG signal through an AND gate to generate the calibration enable signal CAL_EN, which is used to control the automatic calibration mode. The high-level pulse of the calibration enable signal CAL_EN is one coarse quantization clock MSB_CLK cycle. When the calibration enable signal CAL_EN is high, the ring oscillator in the DCO module is started to generate the fine quantization clock LSB_CLK, so that the N-bit calibration counter starts counting within one coarse quantization clock MSB_CLK cycle according to the fine quantization clock LSB_CLK.

[0089] b) Figure 3 The Z-bit correction counter in the example is 6-bit (Z=6), and its output CAL_Q<5:0> signal is connected to the corresponding 6-bit switched-capacitor load. <0> The signal controls whether the capacitor at bit 0 is connected to the ring oscillator, CAL_Q <1> The signal controls whether capacitor C0 in position 1 is connected to the CAP_LOAD capacitor load of the ring oscillator, and so on, CAL_Q. <5> The signal controls whether capacitor C5 (position 5) is connected to the CAP_LOAD capacitor load of the ring oscillator.

[0090] c) The coarse quantization clock MSB_CLK is fed in externally, with a frequency of... The frequency of the fine-tuned clock LSB_CLK. This is generated by the ring oscillator in the DCO. At the start of calibration, CAL_Q<5:0> is 0, so the CAP_LOAD capacitor load in the connected DCO circuit is 0. If... In a coarse quantization clock MSB_CLK, the N-bit correction counter will generate an overflow signal OVER_FLOW. Each OVER_FLOW pulse edge increments the Z-bit correction counter by 1, i.e., the count result CAL_Q<5:0> is incremented by 1. This increases the total CAP_LOAD capacitor load node by one unit capacitance, thereby reducing the frequency of the fine quantization clock generated by the ring oscillator. In the second cycle, if In a coarse quantization clock MSB_CLK, the N-bit correction counter will generate an overflow signal OVER_FLOW, and the count result CAL_Q<5:0> will increment by 1. This will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, further reducing the ring oscillator's capacitance. The frequency repeats in this cycle until the desired frequency is met. In a coarse quantization clock MSB_CLK, the N-bit correction counter will no longer generate the overflow signal OVER_FLOW, and the CAL_Q<5:0> count value will remain unchanged. The correction result in the figure is CAL_Q<5:0>=001100. This correction parameter is stored in the counter and is used in subsequent two-step ADC quantization.

[0091] (2) The two-step ADC begins quantization, and the process is as follows:

[0092] a) First, perform M-bit coarse quantization. Enable quantization with ADC_EN and RAMP_EN signals. Start the ramp generator integration. Ramp voltage... Signal from V H Discharge, input signal The range should include the ramp voltage. Voltage range [V] L V H ]middle;

[0093] b) Initially, when the ramp voltage Compared to the input signal The high voltage causes the coarse quantization enable MSB_EN to be active (1). The M-bit coarse quantization counter, in conjunction with the coarse quantization clock MSB_CLK, begins counting and generating the coarse quantization digital code MSB_DOUT. <m:1>When the ramp voltage Compared to the input signal When the output HIT signal of the comparator is low, it toggles from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization M-bit counter stops counting, and the coarse quantization digital code MSB_DOUT is displayed. <m:1>The value remains unchanged.

[0094] c) After the comparator's output HIT signal flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization. The coarse quantization enable MSB_EN and the coarse quantization clock MSB_CLK pass through the residual time detection module and output the residual time LSB_EN.

[0095] d) Because the DCO has already coarsely quantized the clock frequency during the calibration phase. and precise clock frequency Adjust to meet The correction parameters CAL_Q<5:0> are stored. The high level of the residual time LSB_EN enables the ring oscillator in the DCO, generating the fine-tuning clock LSB_CLK to meet the system requirements of a two-step ADC. During the residual time LSB_EN high level, the N-bit ADC counter counts according to the fine-tuning clock LSB_CLK, generating the fine-tuning digital code LSB_DOUT. <n:1>After the residual time LSB_EN high level period ends, the DCO ring oscillator turns off, no fine-tuning clock LSB_CLK is generated, the N-bit ADC counter stops counting, and the fine-tuning process ends.

[0096] e) The coarse quantization and fine quantization merging process includes: converting the coarse quantization numeric code MSB_DOUT... <m:1>With refined numeric code LSB_DOUT <n:1>Combined into the final quantized value DOUT<M+N:1> ,in:

[0097] (13)

[0098] DOUT<M+N:1> This is the final quantization result output by the two-step ADC, totaling (M+N) bits, where the high M bits are the coarse quantization digital code MSB_DOUT. <m:1>The lower N bits are the refined numeric code LSB_DOUT. <n:1>.

[0099] Furthermore, the entire readout circuit array shares the same M-bit ramp voltage. It is generated by the ramp generator module.

[0100] The above description is only some specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A two-step ADC circuit based on an automatically calibrated DCO, wherein the DCO is a digitally controlled ring oscillator, characterized in that, The ADC circuit includes: M-bit ramp generator module, used to generate the ramp voltage required for ADC quantization. ; Comparator module, used to compare analog signals and slope voltage The size of the value is determined, and the comparison result HIT is output. The M-bit counter module is used for quantization counting and storage during the first step of M-bit coarse quantization. The residual time detection module is used to detect the residual time LSB_EN between the comparator's flip time and the rising edge of the next coarse quantization clock MSB_CLK after the first coarse quantization SS ADC completes coarse quantization and the comparator output flips. An N-bit DCO and automatic correction module, wherein the N-bit DCO and automatic correction module includes: The system comprises a ring oscillator consisting of one NAND gate and four NOT gates connected end-to-end, an N-bit ADC counter for counting during ADC fine-tuning, an N-bit calibration counter for calibration mode, a DFF and an AND gate, a Z-bit calibration counter, and a matched array of switched capacitors. The Z-bit calibration counter outputs the counting result CAL_Q. <z-1:0> This refers to the switching control signal for the switched capacitor array; The automatic calibration DCO automatically completes the frequency correction of the coarse clock required for coarse quantization and the fine clock required for fine quantization; the first step of the two-step ADC is single-step M-bit SS ADC coarse quantization, and the second step is fine quantization. The fine quantization first extracts the residual time LSB_EN through the residual time detection module, and then uses the residual time LSB_EN to enable the DCO to generate the fine quantization clock LSB_CLK to perform N-bit time-to-digital quantization on the residual time LSB_EN. The two steps together realize the analog-to-digital conversion function with (M+N)-bit quantization accuracy. The transition from coarse to fine quantization is automatically corrected to ensure that the output fine quantization clock LSB_CLK frequency of the DCO meets the frequency matching requirements of the two-step ADC system for the coarse quantization clock MSB_CLK and the fine quantization clock LSB_CLK.

2. The ADC circuit according to claim 1, characterized in that: Automatic calibration of the DCO is performed before each ADC operation, or once per frame, or at any time via a calibration command sent from the background. Calibration parameters are stored internally in a counter. Automatic calibration corrects the output frequency of the ring oscillator DCO to meet the coarse quantization clock frequency of the two-step ADC system through detection. and precise clock frequency Frequency requirements: This is used to meet the carry requirements of the M-bit coarse quantization SS ADC and the N-bit fine quantization of the residual time in a two-step ADC structure.

3. The ADC circuit according to claim 1, characterized in that: The comparison result HIT signal and the quantization enable ADC_EN signal generate a coarse quantization enable MSB_EN signal. The coarse quantization enable MSB_EN signal is used to control the M-bit counter to count according to the coarse quantization clock MSB_CLK and output the coarse quantization digital code MSB_DOUT. <m:1> The coarse quantization enable signal MSB_EN is also used to connect to the residual time detection module, which detects the residual time LSB_EN and connects it to the N-bit DCO and automatic correction module.

4. The ADC circuit according to claim 3, characterized in that: The residual time LSB_EN is valid during its high level and is used to enable the DCO to generate the fine-quantization clock LSB_CLK, which is then fed into the N-bit ADC counter for counting, and outputs the fine-quantization digital code LSB_DOUT. <n:1>Ultimately, the ADC outputs (M+N) bits of coarse quantization data, MSB_DOUT. <m:1>and refined numeric code LSB_DOUT <n:1> The combined (M+N) bit data DOUT[M+N:1].

5. The ADC circuit according to claim 1, characterized in that, The switched capacitor array includes C0, C1, ... C1 z-1 There are Z capacitors in total, and S0, S1, ..., S z-1 There are Z switches in total, and the switched capacitor array is connected as follows: The lower plate of capacitor C0 is grounded, and the upper plate is connected to one end of switch S0. The on / off state of switch S0 is determined by the signal CAL_Q output from the Z-position correction counter. <0> Control; the lower plate of capacitor C1 is grounded, and the upper plate is connected to one end of switch S1. The on / off state of switch S1 is controlled by the signal CAL_Q output by the Z-position correction counter. <1> control; And so on, capacitor C z-1 The lower electrode is grounded, and the upper electrode is connected to switch S. z-1 One end, switch S z-1 The on / off state is determined by the signal CAL_Q output from the Z-bit correction counter. <z-1> control; The switches S0, S1, ..., S z-1 The other ends of the capacitors are all connected together as the total capacitive load CAP_LOAD, which is then connected to the output node of a certain stage of the NOT gate in the ring oscillator circuit. The switched capacitor array is a binary weighted capacitor array C0, C1, ... C1 z-1 Each of its bits has a capacitance value that satisfies C i =2 i C0,i ; The activation of the DCO ring oscillator is controlled by the calibration enable CAL_EN or the residual time LSB_EN. When the calibration enable CAL_EN is valid, it enters the automatic calibration process. When the residual time LSB_EN is valid, it enters the fine quantization process of the two-step ADC formal quantization.

6. The ADC circuit according to claim 2, characterized in that: The coarse quantization clock frequency and frequency during quantization The matching relationship is corrected by DCO, using an N-bit correction counter and a Z-bit correction counter. The overflow signal OVER_FLOW of the N-bit correction counter determines whether more capacitive loads should be connected. The specific correction process is as follows: like In a coarse quantization clock MSB_CLK, the N-bit correction counter will generate an overflow signal OVER_FLOW. Each OVER_FLOW pulse increments the Z-bit correction counter by 1, and the counter's count result is CAL_Q. <z-1:0>Increasing by 1 will add one unit of capacitance to the total capacitive load CAP_LOAD node, thereby reducing the ring oscillator's capacitance. Frequency; in the second loop, if In a coarse quantization clock MSB_CLK, an N-bit correction counter will generate an overflow signal OVER_FLOW, and the counting result will be CAL_Q. <z-1:0>Adding 1 will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, further reducing the ring oscillator's capacitance. Frequency; this cycle continues until the N-bit correction counter stops generating overflow signals OVER_FLOW and CAL_Q within one coarse quantization clock cycle MSB_CLK. <z-1:0>The count value remains unchanged, and the correction is satisfied. Frequency correction is completed in time, and the correction parameters are used for subsequent two-step ADC quantization.

7. A conversion method for a two-step ADC circuit based on an automatically calibrated DCO according to any one of claims 1-6, characterized in that, Includes the following steps: Step 1, DCO begins automatic digital calibration, the method includes: Step 1.1: The reset signal RST is invalid, the CAL_FLAG signal is valid, and the coarse quantization clock MSB_CLK is ANDed with the DFF and CAL_FLAG signals to generate the calibration enable CAL_EN used to control the automatic calibration mode. The high-level pulse of the calibration enable CAL_EN signal is one clock cycle of the coarse quantization clock MSB_CLK. When the calibration enable CAL_EN is high, the ring oscillator in the DCO module is started to generate the fine quantization clock LSB_CLK, so that the N-bit calibration counter starts counting within one clock cycle of the coarse quantization clock MSB_CLK according to the fine quantization clock LSB_CLK. Step 1.2, CAL_Q <z-1:0>The signal is connected to the switched capacitor load at the corresponding Z-position, CAL_Q <0> The signal controls whether the capacitor at bit 0 is connected to the ring oscillator, CAL_Q <1> The signal controls whether the capacitor in position 1 is connected to the load of the ring oscillator, and so on, CAL_Q <z-1> The signal controls whether the capacitor at position Z-1 is connected to the ring oscillator;< / z-1> Step 1.3, if In a coarse quantization clock MSB_CLK, when the N-bit correction counter reaches full speed, an overflow signal OVER_FLOW is generated. The rising edge of the OVER_FLOW signal increments the count value of the Z-bit correction counter by 1, and the count result of this counter is CAL_Q. <z-1:0>Increasing by 1 will add one unit of capacitance to the total capacitive load CAP_LOAD node, thereby reducing the ring oscillator's capacitance. Frequency; in the second loop, if In a coarse quantization clock MSB_CLK, an N-bit correction counter will generate an overflow signal OVER_FLOW, and the counting result will be CAL_Q. <z-1:0>Adding 1 will increase the total capacitive load of the CAP_LOAD node by one unit capacitance, further reducing the ring oscillator's capacitance. The frequency repeats in this cycle until the desired frequency is met. Therefore, in a coarse quantization clock MSB_CLK, the N-bit correction counter will no longer generate the overflow signal OVER_FLOW, and thus CAL_Q <z-1:0> The count value remains unchanged, meaning the total capacitive load CAP_LOAD node remains constant;< / z-1:0> Step 1.4: When the CAL_FLAG signal equals 0, the calibration mode ends, satisfying the condition. The correction result CAL_Q <z-1:0> It is stored in the Z-bit correction counter and used during two-step ADC quantization.< / z-1:0> Step 2: The two-step ADC begins quantization, first performing M-bit coarse quantization, the process of which includes: Step 2.1: Quantization enable ADC_EN is active, ramp enable RAMP_EN signal is active, ramp generator starts integration, ramp voltage... From high reference voltage V H Discharge, input voltage The range should include the ramp voltage. Voltage range [V] L V H ]middle; Step 2.2, when the ramp voltage Compared to input voltage When the output HIT signal of the comparator is high, the generated coarse quantization enable MSB_EN is active, and the M-bit coarse quantization counter starts counting in conjunction with the coarse quantization clock MSB_CLK, generating the coarse quantization digital code MSB_DOUT. <m:1> ；< / m:1> Step 2.3, when the ramp voltage Compared to input voltage When low, the comparator's output HIT signal toggles from 1 to 0, the coarse quantization enable MSB_EN is 0, the coarse quantization counter stops counting, and the count value is the coarse quantization digital code MSB_DOUT. <m:1> ；< / m:1> Step 3: After the comparator's output HIT signal flips from 1 to 0, the M-bit coarse quantization ends, and the ADC enters the N-bit fine quantization process, including: Step 3.1: The coarse quantization enable signal MSB_EN and the coarse quantization working clock signal MSB_CLK pass through the residual time detection module, and the residual time LSB_EN is output. Step 3.2: During the residual time LSB_EN high level, the DCO is enabled. Since the DCO has already coarsely quantized the clock frequency during the calibration phase... and the frequency of the precision clock Correction satisfies Therefore, the precision clock LSB_CLK generated by the DCO meets the system requirements of a two-step ADC. During the high-level residual time, the N-bit ADC counter counts according to the precision clock LSB_CLK. When the residual time LSB_EN becomes 0, the N-bit counter stops counting and outputs the precision digital code LSB_DOUT. <n:1> ；< / n:1> Step 4, the process of merging coarse and fine quantization, includes: The coarse quantization numeric code MSB_DOUT <m:1>With refined numeric code LSB_DOUT <n:1> Combined into the final quantized value DOUT<M+N:1> There are a total of (M+N) bits, of which:< / n:1> （1） In equation (1): DOUT<M+N:1> This is the final quantization result output by the two-step ADC, totaling (M+N) bits, where the high M bits are the coarse quantization digital code MSB_DOUT. <m:1>The lower N bits are the refined numeric code LSB_DOUT. <n:1> 。< / n:1> 8. The conversion method according to claim 7, characterized in that: In the coarse quantization step 2, an M-bit ramp voltage generator is used to generate the ramp voltage. When the two-step ADC starts working, the ramp voltage From high reference voltage V H Initially, after 2 M Integrate to the low reference voltage V after one coarse quantization clock cycle MSB_CLK. L After the entire two-step ADC quantization is completed, it is reset to the high reference voltage V. H .

9. The application of a two-step ADC circuit based on an auto-calibrated DCO as described in any one of claims 1-6 in a high-performance image sensor readout circuit, wherein all two-step ADCs in the entire readout circuit array share the ramp voltage generated by the M-bit ramp generator module. .

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