A time interpolation circuit for synchronous down-sampling and an interpolation time correction method

Abstract

The application provides a time interpolation circuit and an interpolation time correction method. A gate circuit controller in the time interpolation circuit controls a first switch and a second switch to charge a capacitor through an external trigger signal and a comparator circuit output signal trigger, controls a third switch to switch a path to realize voltage sampling, operation and comparison, and realizes time interpolation through a comparator circuit output trigger signal. The interpolation time correction method includes setting a current source current size, starting capacitor charging, then sampling and holding the voltage drop on the capacitor at this time, then constantly changing the voltage source code value, gradually approaching the sampled voltage value size, finally outputting the voltage source code value of the interpolation time, and completing the interpolation time correction. The application reduces the problem that the sampling waveform is not coherent in the time domain and redundant noise is introduced in the frequency domain due to the time error between the external trigger signal and the clock edge trigger when the synchronous down-sampling algorithm is used in AC sampling.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of metrological test instruments, and more particularly, to a time interpolation circuit for synchronous decimation and an interpolation time correction method. BACKGROUND

[0002] In the field of metrological test instruments, especially in the field of AC measurement, the root mean square value of AC voltage is usually calculated by using a thermal AC-DC converter or an analog AC-DC converter. The principle of the thermal AC-DC converter is to apply an AC voltage to the heating wire of a thermal electric converter, and to read the output of the thermocouple coupled with the heating wire by using an instrument. This method is quite accurate and is used by most countries for AC voltage and AC current reference, but due to the limitation of the technical principle, it has the disadvantages of high cost and slow measurement speed, which is not suitable for industrial production.

[0003] The principle of the analog AC-DC converter is to use analog circuits such as adders, inverters, multipliers and integrators to build an AC-DC conversion circuit. The output of the circuit is the effective value of the AC signal to be measured. The existing circuit is directly integrated into a commercial chip and is widely used in various instruments. However, this method is more accurate in the medium frequency range, but in the case of higher frequency, the precision and linearity will decrease due to the limitation of circuit bandwidth. The AC digital sampling method does not have the time constant limitation of the thermal AC-DC converter technology, and the measurement result is more accurate. Compared with the analog AC-DC converter, it can provide better linearity.

[0004] In the AC digital sampling method, in order to further improve the equivalent sampling rate and obtain accurate AC voltage root mean square value and expand the frequency spectrum range, the synchronous decimation technology is often used to increase the number of sampling points in the period. However, the existing time interpolation algorithm, such as the AC synchronous decimation time interpolation algorithm based on clock frequency, may encounter a time error between the external level trigger and the clock edge trigger, resulting in incoherent sampling waveform in the time domain, the clock circuit cannot provide smaller time resolution, and redundant noise is introduced in the frequency domain, which causes inaccurate measurement of the AC voltage root mean square value. Or the time interpolation circuit realized by hardware circuit is not convenient for correcting the interpolation time, which introduces redundant noise and makes it difficult to mass-produce and correct the circuit. SUMMARY

[0005] In view of the above-mentioned problems of the prior art, the present application provides a time interpolation circuit for synchronous decimation and an interpolation time correction method.

[0006] The time interpolation circuit for synchronous decimation in the present application comprises:

[0007] a current source module for providing adjustable charging current according to an external setting value;

[0008] a capacitor module for accumulating electric charge and generating voltage drop;

[0009] a sample-and-hold module for sampling and holding an input voltage signal;

[0010] a voltage source module for providing adjustable reference voltage;

[0011] an operation circuit module for performing operation according to output values of the sample-and-hold module and the voltage source module and outputting a resultant voltage;

[0012] a comparator module for comparing the output voltage of the operation circuit module with the voltage drop on the capacitor module and outputting a comparison result;

[0013] a control module for controlling working states of the current source module, the capacitor module, the voltage source module and the sample-and-hold module according to an external trigger signal and the output signal of the comparator module, so as to realize time interpolation;

[0014] wherein the time interpolation comprises:

[0015] when the external trigger signal arrives, the current source module is started to charge the capacitor module, and the charging time is equal to a time difference between a next clock synchronization edge (rising edge or falling edge) and the external trigger signal plus a fixed charging time;

[0016] the voltage drop on the capacitor module is sampled by the sample-and-hold module;

[0017] the output voltage of the voltage source module is adjusted according to a sequence of samples required by the synchronous down-sampling, so as to realize variation of a position of the time interpolation trigger position in the entire synchronous down-sampling measurement sequence, thereby realizing time interpolation;

[0018] according to the output signal of the comparator module, an external measurement circuit samples a to-be-measured signal according to the signal, and a synchronous down-sampling sequence is generated by combining sample sequences generated by different time interpolation parameters in multiple cycles, thereby realizing synchronous down-sampling.

[0019] An interpolation time correction method for synchronous down-sampling in the present application adopts the above-mentioned circuit and comprises the following steps:

[0020] Step 1. A charging current is started to charge a capacitor, and the charging time is related to an integer multiple of a period of an external clock signal;

[0021] Step 2. After the charging is completed, a voltage value on the capacitor is sampled and held;

[0022] Step 3. Adjusting the output voltage of the reference voltage source to approach the sampled voltage value successively;

[0023] Step 4. Calculating and outputting the corrected interpolation time code value according to the relationship between the output voltage of the reference voltage source and the sampled voltage value;

[0024] Step 5. Adjusting the precision of time interpolation according to the corrected interpolation time code value to reduce the time error caused by circuit parameter variation or external trigger signal error.

[0025] The present application has the following beneficial effects by adopting the above technical solutions:

[0026] (1) The first aspect of the present application provides a circuit structure which can respond to an external trigger signal through a gate circuit controller, control a voltage source current source using a specific control timing, control the opening and closing of a switch, thereby charging and discharging a capacitor, and output a trigger signal through a comparator circuit to realize synchronous downsampling. The structure has the advantages of adjustable and correctable interpolation time. It solves the problem that some existing time interpolation algorithms cannot obtain higher clock resolution. It reduces the problem that when using a synchronous downsampling algorithm in AC sampling, the sampling waveform is not coherent in the time domain and redundant noise is introduced in the frequency domain due to the time error between the external trigger signal and the clock edge trigger.

[0027] (2) The second aspect of the present application is based on the first aspect of the present application and uses the adjustable and correctable interpolation time of the circuit structure of the first aspect to provide an interpolation time correction method. The interpolation time is corrected by the circuit structure itself, replacing manual parameter adjustment due to different circuit parameters. It is suitable for batch production and correction of circuits and solves the problem that some existing time interpolation circuits cannot correct or are inconvenient to correct the interpolation time due to circuit parameter variation. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a schematic structural diagram of a time interpolation circuit for synchronous downsampling.

[0029] Figure 2 It is a schematic flow chart of an interpolation time correction method for a time interpolation circuit for synchronous downsampling.

[0030] Figure 3 It is a schematic control timing diagram of a time interpolation circuit for synchronous downsampling.

[0031] Figure 4 It is a schematic control timing diagram of an interpolation time correction method for a time interpolation circuit for synchronous downsampling.

[0032] Figure 5The output sampling point fitting graph of the clock frequency AC synchronous downsampling provided by the embodiment of the present application.

[0033] Figure 6 The output sampling point (unmodified interpolation time) of the time interpolation circuit based synchronous downsampling provided by the embodiment of the present application.

[0034] Figure 7 The output sampling point (modified interpolation time) of the time interpolation circuit based synchronous downsampling provided by the embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] The embodiment of the present application provides a time interpolation circuit, comprising: a current source, a switch diode, a capacitor, a first switch, a second switch, a third switch, a buffer, a first path, a second path, a sample and hold circuit, a voltage source, an operation circuit, a comparator circuit, a comparator circuit output path, a resistor and a gate circuit controller.

[0037] The specific connection mode is as shown in Figure 1 The current source can change the output current value according to the external setting value, and provide the charging current of the capacitor.

[0038] The switch diode is used for controlling whether the current charges the capacitor, and is connected with the current source and the first switch.

[0039] The capacitor is used for accumulating the charge from the current source to generate a voltage drop, and is connected with the buffer, and the other end is connected with the power supply ground, and the two ends of the capacitor are connected with the two ends of the second switch.

[0040] The first switch is used for controlling whether the current source current flows to the power supply ground, and is connected with the second switch. One end of the first switch is connected with the current source and the switch diode, and the other end is connected with the power supply ground.

[0041] The second switch is used for short-circuiting the capacitor to clear the charge in the capacitor, and is connected with the first switch. The two ends of the second switch are connected with the two ends of the capacitor, and one end is connected with the power supply ground.

[0042] The second switch is used for short-circuiting the capacitor to clear the charge in the capacitor, and is connected with the first switch. The two ends of the second switch are connected with the two ends of the capacitor, and one end is connected with the power supply ground.

[0043] The third switch, used for switching the buffer voltage output channel, is a single-pole double-throw switch, the input port of which is connected with the buffer output, two output channels of which are connected with the first channel and the second channel respectively;

[0044] The buffer, used for outputting the voltage value behind the input voltage, has one end connected with the switch diode and the capacitor and the other end connected with the input end of the third switch;

[0045] The first channel, used for transmitting the voltage signal to be sampled and held, is a signal channel connected with the sampling and holding circuit;

[0046] The second channel, used for transmitting the voltage drop signal of the capacitor current charging, is a signal channel connected with the comparator circuit and the resistor;

[0047] The sampling and holding circuit, used for sampling and holding the input voltage value, has one end connected with the first channel and the other end connected with the operation circuit;

[0048] The voltage source, capable of transforming the output voltage value according to the external setting value, is connected with the input end of the operation circuit;

[0049] The operation circuit, which inputs the output value of the voltage source and the output value of the sampling and holding circuit and outputs a new voltage output value through the operation amplifier circuit, is connected with the sampling and holding circuit and the voltage source and connected with the comparator circuit. out V in1 , V in2 are two inputs respectively, and the weight parameters A and B are as follows:

[0050]

[0051] The comparator circuit, used for comparing the output value of the operation circuit with the voltage drop on the resistor, obtains the high-low level result, and the comparator circuit can output the voltage signal with the amplitude compatible with the digital system level, the output of which is connected with the comparator circuit output channel, and one end of the input is connected with the operation circuit and one end is connected with the second channel and the resistor;

[0052] The comparator circuit output channel, used for transmitting the output signal of the comparator circuit, is connected with the gate circuit controller on one side and connected with the external measurement circuit on the other side;

[0053] The resistor, used for providing a stable potential, has one end connected with the second channel and the comparator circuit and the other end connected with the power supply ground;

[0054] The gate circuit controller is configured to provide control signals to the first switch, the second switch and the third switch, wherein the output control signal is connected to the first switch, the second switch and the third switch, the input signal is connected to an external clock signal, an external trigger signal, a modified start trigger signal and a comparator circuit output signal.

[0055] Based on Figure 1 A time interpolation circuit for synchronous down-sampling is shown in FIG. 1, and a time interpolation control timing diagram thereof is shown in FIG. 2. In the figures: Figure 3

[0056] Figure 3 In FIG. 1, the signal waveform of the external clock corresponds to the level state of the external clock signal. The external clock signal is provided by an external clock source, typically a square wave signal provided by a crystal oscillator, and is represented in the form of a square wave in FIG. 2. Figure 3

[0057] Figure 3 In FIG. 1, the signal waveform of the external trigger corresponds to the level state of the external trigger signal. The external trigger is a trigger signal generated when the amplitude of the sampled signal exceeds the set voltage of the comparator, and is embodied in the form of a pulse in FIG. 2, which is realized by an external circuit. Figure 3

[0058] Figure 3 In FIG. 1, the signal waveforms of the first switch and the second switch correspond to the switch states of the first switch and the second switch. The first switch and the second switch are linked switches, and are embodied as high-level switch closed and low-level switch opened in FIG. 2. Figure 3

[0059] Figure 3 In FIG. 1, the signal waveform of the third switch corresponds to the switch state of the third switch. The third switch is a single-pole double-throw switch, and is embodied as connecting the second path at high level and connecting the first path at low level in FIG. 2. Figure 3

[0060] In FIG. 1, the signal waveform of the time interpolation trigger signal corresponds to the comparator circuit output signal on the comparator circuit output path during synchronous down-sampling. Figure 3

[0061] In FIG. 1, the signal waveform of the capacitor potential corresponds to the size of the potential on the capacitor. Figure 3

[0062] In FIG. 1, the signal waveform of the sample-and-hold circuit output potential corresponds to the size of the potential held by the sample-and-hold circuit. Figure 3 According to

[0063] , the timing logic is as follows: Figure 3

[0064] ​​​​​When the system is reset, the current source does not output current, the first switch and the second switch are closed, and the third switch is connected to the first path. At this time, the capacitor is short-circuited, the voltage drop on the capacitor is the ground potential, and the sampling potential of the sample and hold circuit is the ground potential. The voltage source outputs the set bias voltage, which can enable the time interpolation circuit to start the initial comparator circuit without accidental flipping.

[0065] After the system is reset, the current source outputs a set current value in advance, the first switch and the second switch are closed, the switch diode is not conductive, the third switch is connected to the first path, and the voltage source outputs the set bias voltage.

[0066] When the rising edge of the external trigger signal enters the gate circuit controller, the first switch and the second switch are opened after asynchronous triggering occurs in the gate circuit controller, the switch diode is conductive, the set current generated by the current source flows through the switch diode to charge the capacitor, and the voltage drop on the capacitor is sampled by the sample and hold circuit via the buffer and the third switch to the first path.

[0067] After T0 and T1 time, when the second clock rising edge comes, the first switch and the second switch are closed, the switch diode is opened, the current generated by the current source flows into the power supply ground via the first switch, and the capacitor is short-circuited. The third switch is connected to the second path, and at this time, the output potential of the sample and hold circuit remains the voltage drop before the capacitor is short-circuited. T1 time is fixed, and the purpose is to prevent the first switch and the second switch from being closed too late due to too short T0 time, resulting in time interpolation error.

[0068] After T2 time, when the clock rising edge comes, the first switch and the second switch are opened, the capacitor starts to charge, and the voltage drop on the capacitor is reflected on the resistor via the second path. When the voltage drop on the capacitor exceeds the output voltage drop of the operation circuit, the output level of the comparator circuit flips, at this time, the first switch and the second switch are closed, the capacitor is short-circuited, and the output level of the comparator circuit flips again. The output signal of the comparator circuit is similar to a short pulse signal, and the comparator circuit output signal at this time is used as a time interpolation trigger signal.

[0069] After T3 time, when the clock rising edge comes, the first switch and the second switch are opened, which is consistent with the previous T3, the capacitor is charged again until the time interpolation trigger signal is generated. The setting of T3 time needs to be greater than the sampling period of the sampling circuit.

[0070] After a single sampling sequence is generated in several T3 time, the output voltage of the voltage source is changed, a voltage of an interpolation time is added, and the sampling sequence generation is started again after waiting for an external trigger.

[0071] After multiple external triggers and multiple sampling sequence generations, the data of the multiple sampling sequences are integrated by an external processor to generate a sampling sequence with an equivalent high sampling rate, and an AC synchronous downsampling is completed.

[0072] In order to intuitively compare the effect of the embodiment, taking a 2V peak-to-peak sine wave with a frequency of 1MHz as an example, a 10MHz crystal oscillator is used as the clock signal input of the controller, and the sampling point outputs of the clock frequency-based AC synchronous downsampling, the uncorrected time interpolation circuit-based synchronous downsampling, and the corrected time interpolation circuit-based synchronous downsampling are tested respectively.

[0073] The output sampling point result of the clock frequency-based AC synchronous downsampling is shown in Figure 5 . It can be found that, due to the clock frequency of the circuit itself, the sampled points are less, and spikes appear after fitting. It is considered that the spikes are caused by the low sampling rate and the time difference between the sampling start point and the actual trigger point.

[0074] The output sampling point fitting result of the time interpolation circuit-based synchronous downsampling is shown in Figure 6 , Figure 7 . Figure 6 is the sampling point output fitting image without correction of the interpolation time, and Figure 7 is the sampling point output fitting image obtained after the interpolation time correction method is used. By comparing Figure 5 , Figure 7 , it can be found that, in the time domain, the sampling point fitting result of the time interpolation circuit can be directly observed. Compared with the sampling points of the clock frequency-based AC synchronous downsampling, the output sampling points of the time interpolation circuit-based synchronous downsampling can provide finer time resolution, and the curve is almost smooth, solving the problems of difficult to obtain finer resolution in the traditional method and the time difference between the sampling start point and the actual trigger point.

[0075] The embodiment provides an interpolation time correction method, which is implemented based on the time interpolation circuit of the embodiment. The specific process is shown in Figure 2 . When the gate circuit controller receives a correction start trigger signal, the current source sets the current size according to the capacitor and the voltage range, the voltage source voltage is set to half the range, the first switch and the second switch are disconnected, the third switch is connected to the first path, and the capacitor starts charging.

[0076] When the capacitor begins charging, the gate circuit controller starts timing for N clock cycles, where N is a positive integer. After the timing ends, the first switch and the second switch close, the third switch connects to the second path, the capacitor discharges, the sample-and-hold circuit holds the capacitor potential before the short circuit, and the arithmetic circuit outputs the result of the calculation between the sample-and-hold circuit output potential and the voltage drop across the resistor.

[0077] Based on the high or low output level of the comparator circuit, the voltage source output code value is continuously changed to approximate the sampled voltage value. At this time, the voltage code value of the tracking and holding circuit obtained by the successive approximation is obtained, and finally the voltage source code value of the interpolation time is output according to the formula.

[0078] Its timing control diagram is as follows Figure 4 As shown.

[0079] Figure 4 In the timing diagram, except for Figure 3 In addition to the waveforms with the same name in the text, among them:

[0080] Figure 4 The waveform of the corrected start-up trigger signal corresponds to the level state of the corrected start-up trigger signal. The corrected start-up trigger signal is typically provided by an external processor.

[0081] Figure 4 The waveform of the correction end signal corresponds to the level state of the correction end register inside the gate circuit controller. The high or low level output of the correction end register inside the gate circuit controller is determined by whether the interpolation time correction has ended. When the interpolation time correction is started, the correction end register becomes low; when the interpolation time correction is completed, the correction end register becomes high.

[0082] Figure 4 The signal waveform of the comparator circuit output signal corresponds to the comparator circuit output signal on the comparator circuit output path.

[0083] Figure 4 The signal waveform of the voltage output from the medium voltage source corresponds to the magnitude of the voltage output by the voltage source. The magnitude of the voltage output by the voltage source is provided by the gate circuit controller.

[0084] Figure 4 The reference line output by the sample-and-hold circuit is derived from the arithmetic circuit. The arithmetic circuit uses V... out For the output of the operational circuit, V in1 V in2 The input consists of two paths, with weight parameters A and B, as shown in the formula below:

[0085]

[0086] In actual circuit, let V in1 be the output voltage of the sample-and-hold circuit, V in2 be the output voltage of the voltage source. In case of interpolation time correction initiation, the voltage drop on the input terminal of the comparator circuit connected with the resistor is the reference ground potential, and V in1 will remain unchanged after the sample-and-hold, thus only when V in2 changes will the output of the comparator circuit change, and the voltage value of the output of the voltage source that makes the level of the comparator flip is V ref . Let V out be 0, V in2 be rewritten as V ref , we have:

[0087]

[0088] wherein V ref is the output reference line of the sample-and-hold circuit.

[0089] According to Figure 4 , the timing logic is as follows:

[0090] After the system completes reset, the current source outputs a preset current value, the first switch and the second switch are closed, the switch diode is not conductive, the third switch is connected to the first path, and the voltage source outputs half of the voltage source range.

[0091] When the gate circuit controller captures the correction initiation trigger signal according to the external clock signal, at the next clock rising edge, the first switch and the second switch are opened, the switch diode is conductive, the third switch is connected to the first path, the capacitor starts to charge, and the output of the sample-and-hold circuit is the same as the potential of the capacitor.

[0092] After T4 time, at the clock rising edge, the first switch and the second switch are closed, the switch diode is conductive, the third switch is connected to the second path, the capacitor is short-circuited, and the potential before the capacitor is short-circuited is sampled and held by the sample-and-hold circuit. The output reference line of the sample-and-hold circuit in the figure is sampled and held by the sample-and-hold circuit, and the length of the time held by T4 is the charging time of the capacitor, which is N clock cycles.

[0093] Every T5, the output result of the comparator circuit is judged. The judgment result of the comparator circuit reflects the output voltage of the voltage source and the output reference line of the sample-and-hold circuit. For example, if the voltage source is a 12-bit binary code value control, at the first T5 cycle, the voltage source will first output the following code value voltage: 1000 0000 0000.

[0094] When the comparator circuit result shows that the voltage source output voltage is higher than the sample-and-hold circuit output reference line (at this time, the comparator circuit output is low in this example), the gate circuit controller changes the voltage source code value at the next clock cycle after the judgment (corresponding to the time when the next T5 starts). The first bit from the left is judged as 0, and the second bit is 1 for the next judgment, and at this time, the voltage source output code value is changed to: 0100 0000 0000.

[0095] At the next T5, the comparator circuit compares the voltage source output code value at the previous T5 with the sample-and-hold circuit output reference line (at this time, the comparator circuit output is low in this example). Similarly, the gate circuit controller changes the voltage source code value at the next clock cycle after the judgment (corresponding to the time when the next T5 starts). The second bit from the left is judged as 0, and the third bit is 1 for the next judgment, and at this time, the voltage source output code value is changed to: 0010 0000 0000.

[0096] At the next T5, the comparator circuit compares the voltage source output code value at the previous T5 with the sample-and-hold circuit output reference line (at this time, the comparator circuit output is low in this example). Similarly, the gate circuit controller changes the voltage source code value at the next clock cycle after the judgment (corresponding to the time when the next T5 starts). The second bit from the left is judged as 0, and the third bit is 1 for the next judgment, and at this time, the voltage source output code value is changed to: 0010 0000 0000.

[0097] By analogy, after 12 T5 judgments, the final complete 12-bit code value is obtained, and the interpolation time code value is calculated according to the formula. In the voltage source code value operation formula of the interpolation time, the voltage code value V_CODE hold obtained by successive approximation is obtained by the tracking and holding circuit min , the clock period T CLK , the charging time T CLK is an integer multiple N of the interpolation time T min , and the expected interpolation time T

[0098]

[0099] According to the interpolation time correction method, the interpolation time can be freely set, and the interpolation time code value can be corrected.

[0100] After the end period T6, the self-correction function ends.

[0101] Further, in order to improve the correction accuracy and reduce the time error of the synchronous decimation sequence, the first method is to use a higher bit number digital-to-analog converter (voltage source), and the second method is to reasonably change the A and B weight parameters of the operation circuit, to appropriately amplify the sample-and-hold voltage, or to appropriately reduce the voltage source weight, which can also equivalently improve the resolution of the voltage source relative to the sample-and-hold voltage, thereby improving the correction accuracy and reducing the time error of the synchronous decimation sequence. The principle of the second method is as follows:

[0102] According to the previous derivation, the output reference line voltage formula of the sample-and-hold circuit is as follows:

[0103]

[0104] After the interpolation time correction is completed, the voltage source code value is V_CODE hold , and the ideal output is V ref . Due to the limited resolution of the digital-to-analog converter, the actual output is V ref-dac , the error caused by the resolution is ΔV, the ideal output is V ref , and the following relationship exists:

[0105]

[0106] Substituting V ref into the formula, we get:

[0107]

[0108] The expression of V in1 is obtained:

[0109]

[0110] In the formula, the error term ΔV is scaled by the coefficient of B / A, and the cost is only to set a larger code value of the digital-to-analog converter. Therefore, it can be judged that by selecting appropriate A and B weight parameters, the correction accuracy can be improved, and the time error of the synchronous decimation sequence can be reduced.

[0111] The output result of the uncorrected synchronous decimation sampling point based on the time interpolation circuit is shown in Figure 6 . It can be found that due to the influence of the parasitic parameters of the devices on the circuit, or the non-strict calculation of the parameter configuration, the waveform appears to have a part of the sampling point step. This is a typical uncorrected circuit, which introduces noise and causes a large error in the final calculation of the AC effective value.

[0112] The output result of the corrected synchronous decimation sampling point based on the time interpolation circuit is shown in Figure 7As shown, the time interpolation circuit after the correction program is substantially no "steep" similar to the step waveform, that is, the weakening of the noise component in the frequency domain, the time domain curve is more smooth, greatly improves the accuracy of subsequent calculation of the effective value of alternating current.

[0113] The above-described embodiments are merely preferred modes of the present application and are not intended to limit the scope of the present application, and various modifications and improvements to the technical solutions of the present application made by those skilled in the art without departing from the design spirit of the present application shall fall within the protection scope of the present application.

Claims

1. A time-interpolation circuit for synchronous down-sampling, characterized by, The current source, the switching diode, the capacitor, the first switch, the second switch, the third switch, the buffer, the first path, the second path, the sample and hold circuit, the voltage source, the operation circuit, the comparator circuit, the comparator circuit output path, the resistance and the gate circuit controller; The current source can transform the output current value according to the external setting value, and provide the charging current of the capacitor; The switching diode is used for controlling whether the current charges the capacitor, and is connected with the current source and the first switch; The capacitor is used for accumulating the charge from the current source, generating a voltage drop, and is connected with the buffer at one end and the power supply ground at the other end, and the two ends of the capacitor are connected with the two ends of the second switch; The first switch is used for controlling whether the current source current flows to the power supply ground, and is connected with the second switch, and one end of the first switch is connected with the current source and the switching diode, and the other end is connected with the power supply ground; The second switch is used for short-circuiting the capacitor to clear the charge in the capacitor, and is connected with the first switch, and the two ends of the second switch are connected with the two ends of the capacitor, and one end of the second switch is connected with the power supply ground; The third switch is used for switching the buffer voltage output channel, and is a single-throw double-pole switch, the input port of which is connected with the buffer output, one of the two output channels is connected with the first path, and the other is connected with the second path; The buffer is used for following the input voltage to output to the next stage, and is connected with the switching diode and the capacitor at one end, and is connected with the third switch input at the other end; The first path is used for transmitting the voltage signal to be sampled and held, and is a signal path connected with the third switch and the sample and hold circuit; The second path is used for transmitting the voltage drop signal of the current charging on the capacitor, and is a signal path connected with the third switch, the comparator circuit and the resistance; The sample and hold circuit is used for sampling and holding the input voltage value, and is connected with the first path at one end and the operation circuit at the other end; The voltage source can transform the output voltage value according to the external setting value, and is connected with the input end of the operation circuit; The operation circuit obtains a new voltage output value through the operation and amplification circuit of the output value of the voltage source and the output value of the sample and hold circuit, and is connected with the sample and hold circuit and the voltage source at the input end, and is connected with the comparator circuit at the output end; The comparator circuit is used for comparing the output value of the operation circuit with the voltage drop on the resistance, and obtaining the high-low level result, and the comparator circuit can output the voltage signal compatible with the digital system level, and is connected with the comparator circuit output path at the output end, and is connected with the operation circuit at one end and the second path and the resistance at the other end; The comparator circuit output path is used for transmitting the output signal of the comparator circuit, and is connected with the gate circuit controller at one end and the external measurement circuit at the other end; The resistance is used for providing a stable potential, and is connected with the second path and the comparator circuit at one end and the power supply ground at the other end. The gate circuit controller is configured to provide control signals to the first switch, the second switch, and the third switch, receive an external clock signal, an external trigger signal, a correction start trigger signal, and a comparator circuit output signal, and control the working states of the current source, the capacitor, the voltage source, and the sample-and-hold circuit according to the external trigger signal and the output signal of the comparator circuit to achieve time interpolation. The time interpolation includes: When the external trigger signal arrives, the current source starts to charge the capacitor; The voltage drop on the capacitor is sampled by the sample-and-hold circuit; The output voltage of the voltage source is adjusted according to the sequence of the required samples in the synchronous down-sampling, so that the change of the time interpolation trigger position in the entire synchronous down-sampling sequence is realized, thereby realizing time interpolation; The external measurement circuit samples the to-be-measured signal according to the output signal of the comparator circuit, and generates a synchronous down-sampling sequence by combining a plurality of sample sequences generated by different time interpolation parameters, thereby realizing synchronous down-sampling.

2. The time interpolation circuit for synchronous decimation according to claim 1, characterized in that, The output voltage of the voltage source can be adjusted after each sample sequence is generated in the synchronous down-sampling process, so that the time interpolation trigger position is changed for the generation of the next sample sequence, thereby realizing time interpolation.

3. The time-interpolation circuit for synchronous decimation according to claim 1 or 2, characterized in that, The time interpolation circuit further includes a correction function, which continuously adjusts the output voltage of the voltage source according to the output of the comparator circuit, corrects the interpolation time code value, and reduces the time error caused by the change of the circuit parameters.

4. An interpolation time correction method for synchronous decimation, employing the circuit according to any one of claims 1 to 3, characterized in that, The method includes the following steps: Step 1: Start the charging current to charge the capacitor, and the charging time is related to an integer multiple of the period of the external clock signal; Step 2: After the charging is completed, the voltage value on the capacitor is sampled and held; Step 3: The output voltage of the reference voltage source is adjusted to gradually approach the voltage value sampled and held; Step 4: According to the relationship between the output voltage of the reference voltage source and the voltage value sampled and held, the corrected interpolation time code value is calculated and outputted; Step 5: According to the corrected interpolation time code value, the accuracy of time interpolation is adjusted to reduce the time error caused by the change of the circuit parameters or the error of the external trigger signal.

5. The interpolation time correction method for synchronous decimation according to claim 4, characterized in that, The charging current is provided by a current source, and the current source can dynamically adjust the output current according to the external setting value to adapt to different charging requirements.

6. The interpolation time correction method for synchronous decimation according to claim 5, wherein, The charging time is set as an integer multiple of the period of the external clock signal to ensure that the charging process is synchronized with the external clock.

7. The interpolation time correction method for synchronous decimation according to claim 4, characterized by, The step of adjusting the output voltage of the reference voltage source includes: The output voltage of the reference voltage source is adjusted by the gradual approximation method to gradually approach the voltage value sampled by the sample-and-hold circuit, thereby realizing high-precision correction of the interpolation time.

8. The interpolation time correction method for synchronous decimation according to claim 4 or 7, characterized in that, The step of calculating and outputting the corrected interpolation time code value includes: According to the relationship between the output voltage of the reference voltage source and the voltage value sampled and held, the interpolation time code value is calculated by a formula, and the formula is as follows: T_CODE min T_CODE is the time code value to be interpolated CLK T is the clock period, N is an integer multiple of T min V_CODE is the desired interpolated time hold V_CODE is the sample and hold circuit voltage code value 9. The interpolation time correction method for synchronous decimation according to claim 8, characterized in that, The step of adjusting the accuracy of time interpolation includes: By adjusting the weight parameter of the operation circuit, the correction accuracy is further improved, and the time error of the synchronous down-sampling sequence is reduced.

10. The interpolation time correction method for synchronous decimation according to claim 4, characterized by, The method further includes: After the correction is completed, the corrected interpolation time code value is used for synchronous downsampling, the data of the multiple sampling sequences are integrated by an external processor, a synchronous down-sampling sequence with equivalent high sampling rate is generated, and the measurement precision of the alternating current effective value is improved.

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