Successive approximation analog-to-digital converter, integrated circuit, device and switch switching method

Abstract

The invention provides a successive approximation analog-to-digital converter, an integrated circuit, equipment and a switch switching method, and the converter comprises a capacitor array which comprises a positive capacitor array and a negative capacitor array which are of the same structure; the differential input voltage is respectively connected with the upper polar plates of the positive capacitor array and the negative capacitor array; the in-phase input end of the comparator is connected with the upper pole plate of the upper capacitor array, the inverted input end of the comparator is connected to the upper pole plate of the negative capacitor array, and the comparator is controlled by the first clock signal to compare and output a comparison signal; the logic control circuit is controlled by a second clock signal, and generates a corresponding control signal by taking the comparison signal as input to control switches of the lower polar plates of the positive capacitor array and the negative capacitor array, so that the lower polar plates are switched to positive reference voltage or negative reference voltage; and the decoder is used for converting the digital codes into binary codes and outputting the binary codes. The convergent value of the common mode voltage in the successive approximation algorithm is controlled by alternating up conversion and down conversion, and the conversion speed is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more particularly to a successive approximation analog-to-digital converter, an integrated circuit, a device, and a switching method. Background Art

[0002] In high-speed applications, the most popular CDAC (capacitor array or capacitive digital-to-analog converter) architectures are monotonic switches and split monotonic switches. Monotonic switch CDACs are highly resource-efficient and easy to optimize, but their output common-mode swing is relatively large. Specifically, the common-mode swing of an MSCDAC (high-precision or high-speed CDAC) without parasitic parameters is VDD / 2 (VDD is the supply voltage), which severely degrades the performance of the comparator and forces designers to adopt more complex architectures, which are usually less efficient.

[0003] Split monotonic switch CDACs ensure a constant output common mode, but at the cost of a significant increase in circuit complexity. Although the total capacitance of the array can be kept constant by halving the unit capacitance, split monotonic switch CDACs typically exhibit longer settling times and higher power consumption compared to equivalent monotonic CDACs because the design process becomes more complex and the parasitics associated with routing increase significantly. Additionally, reducing the unit capacitance increases the sensitivity to parasitic effects, which limits the linearity of the CDAC.

[0004] In summary, during analog-to-digital conversion, there is an urgent need for a novel switching strategy to improve the conversion speed of successive approximation analog-to-digital converters. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a successive approximation analog-to-digital converter, an integrated circuit, a device, and a switching method, which are used to solve the problem of low conversion speed in successive approximation analog-to-digital converters in the prior art.

[0006] In a first aspect, the application provides a successive approximation analog-to-digital converter, an integrated circuit, a device, and a switching method, including: a capacitor array including a positive capacitor array and a negative capacitor array with the same structure; a differential input voltage respectively connected to upper plates of the positive capacitor array and the negative capacitor array; a comparator, the non-inverting input terminal of the comparator is connected to the upper plate of the upper capacitor array, the inverting input terminal of the comparator is connected to the upper plate of the negative capacitor array, and the comparator is controlled by a first clock signal to perform comparison and output a comparison signal; a logic control circuit connected to the output terminal of the comparator, controlled by a second clock signal, and using the comparison signal as an input to generate corresponding control signals to control the switching of lower plates of the positive capacitor array and the negative capacitor array, so that the lower plates are switched to a positive reference voltage or a negative reference voltage; the decoder, connected to the output terminal of the logic control circuit, for encoding and converting each digital code into a binary code and outputting it.

[0007] In an embodiment of the present application, the positive capacitor array and the negative capacitor array are respectively composed of N capacitors, and there is a one-to-one correspondence between N - 1 capacitors formed from the most significant bit capacitor to the second least significant bit capacitor and N - 1 lower plate switches, so that each of the N - 1 capacitors is connected to a lower plate switch, where N is a positive integer greater than 1; and the lower plate of the least significant bit capacitor is connected to the negative reference voltage, the lower plate switches in the positive capacitor array are switched between the positive reference voltage and the negative reference voltage under the control of a first control signal output by the logic control circuit, and the lower plate switches in the negative capacitor array are switched between the positive reference voltage and the negative reference voltage under the control of a second control signal output by the logic control circuit.

[0008] In an embodiment of the present application, the differential input voltage includes a positive input terminal voltage and a negative input terminal voltage. The non-inverting input terminal is connected to the positive terminal input voltage through a first sampling switch, and the non-inverting input terminal is connected to the upper plates of the positive capacitor array; the inverting input terminal is connected to the negative terminal input voltage through a second sampling switch, and the inverting input terminal is connected to the upper plates of the negative capacitor array.

[0009] In an embodiment of the present application, the logic control circuit includes: a timing generation unit, which is composed of a plurality of flip-flops connected in series, uses the second clock signal as the reset signal of each flip-flop, and uses the comparison signal as the timing input signal. A reference voltage is connected to the input end of the flip-flop with the highest bit, and a plurality of flip-flops sequentially output timing signals; a logic control unit, which includes a flip-flop. The clock signal of the flip-flop is any one of the timing signals. The input end of the flip-flop samples the first output signal of the comparator, and the output end of the flip-flop is the second output signal of the analog-to-digital converter; any one of the timing signals is processed by a buffer and then subjected to an AND gate operation or a NAND gate operation with the second output signal to generate a third control signal to control the on / off of the positive capacitance array and the negative capacitance array; among them, the third control signal obtained by the AND gate operation resets the positive capacitance array and the negative capacitance array to the positive reference voltage; the third control signal obtained by the NAND gate operation resets the positive capacitance array and the negative capacitance array to the negative reference voltage to change the common-mode voltage of the capacitance array.

[0010] In an embodiment of the present application, the logic control unit further includes a PMOS transistor, an NMOS transistor and a capacitor. The source electrode of the PMOS transistor is connected to the power supply voltage, and the source electrode of the NMOS transistor is grounded; the gates of the PMOS transistor and the NMOS transistor are interconnected and then connected to the third control signal, and the drains of the PMOS transistor and the NMOS transistor are interconnected and then externally connected to the capacitor. Among them, the capacitor is any one of the capacitors switched in the capacitance array.

[0011] In an embodiment of the present application, the circuit structure for determining the common-mode voltage includes: performing an AND gate operation on the timing control signal of the first high bit and the inverted signal of the timing control signal of the second high bit to determine a first logic signal as the weight switching between the (N-2)th capacitor and the (N-3)th capacitor; among them, the output of the (N-2)th capacitor is obtained by an OR gate operation on the first logic signal and the control signal of the (N-2)th capacitor; performing an AND gate operation on the timing control signal of the second high bit and the inverted signal of the timing control signal of the third high bit to determine a second logic signal; performing an OR gate operation on the first logic signal, the second logic signal and the control signal of the (N-3)th capacitor to perform the switching of the connection level of the (N-3)th capacitor.

[0012] In an embodiment of the present application, in the sampling stage, the most significant bit capacitor is reset to the negative reference voltage, and the remaining capacitors among the N-1 capacitors are all reset to the positive reference voltage. According to the received common-mode voltage, the X bits are reset to the negative reference voltage, and the remaining capacitors among the remaining N-X are reset to the positive reference voltage, where N is the resolution of the successive approximation analog-to-digital converter, and the X bits are determined by the optimal common-mode voltage of the actual comparator.

[0013] In a second aspect, the present application provides an integrated circuit including the successive approximation type analog-to-digital converter described above.

[0014] In a third aspect, the present application provides an electronic device including the successive approximation type analog-to-digital converter described above; or, adopting the integrated circuit described above.

[0015] In a fourth aspect, the present application provides a switching method for a successive approximation analog-to-digital converter, including: In the sampling stage: closing the first sampling switch and the second sampling switch, connecting the non-inverting input terminal of the comparator to the positive terminal input voltage, connecting the inverting input terminal of the comparator to the negative terminal input voltage, performing a first comparison, and obtaining a first comparison result output by the comparator through a pre-comparison; after the first comparison is completed, switching the levels connected to the positive capacitance array and the negative capacitance array respectively according to the first comparison result; if the first comparison result is a high level, connecting the lower plate switches corresponding to the lower plates of n-1 capacitors in the positive capacitance array to the reference voltage, and keeping the lower plate of the least significant bit capacitor connected to the negative reference voltage, while connecting the n lower plate switches corresponding to the lower plates of the negative capacitance array to the negative reference voltage; if the first comparison result is a low level, connecting the lower plate switches corresponding to the lower plates of the positive capacitance array to the negative reference voltage, connecting the lower plate switches corresponding to the lower plates of n-1 capacitors in the negative capacitance array to the reference voltage, and keeping the lower plate of the least significant bit capacitor connected to the negative reference voltage; In the conversion stage: after the sampling stage ends, disconnecting the first sampling switch and the second sampling switch, switching the levels connected to the positive capacitance array and the negative capacitance array respectively according to the first comparison result, performing a second comparison, and obtaining a second comparison result, wherein the least significant bit capacitors in the positive capacitance array and the negative capacitance array are both connected to the negative reference voltage; The kth comparison includes: switching the connection levels of the positive capacitance array and the negative capacitance array according to the (k-1)th comparison result; if the (k-1)th comparison result is 1, switching the non-common terminal of the (k-2)th capacitor in the positive capacitance array to the negative reference voltage through the corresponding lower plate switch, and connecting the least significant bit capacitor to the negative reference voltage, while keeping the connections of the other capacitors in the positive capacitance array unchanged; switching the non-common terminal of the (k-2)th capacitor in the negative capacitance array to the reference voltage through the corresponding lower plate switch, and connecting the least significant bit capacitor to the negative reference voltage, while keeping the connections of the other capacitors in the negative capacitance array unchanged; if the (k-1)th comparison result is 0, switching the non-common terminal of the (k-2)th capacitor in the positive capacitance array to the reference voltage through the corresponding lower plate switch, and connecting the least significant bit capacitor to the negative reference voltage, while keeping the connections of the other capacitors in the positive capacitance array unchanged; switching the non-common terminal of the (k-2)th capacitor in the negative capacitance array to the negative reference voltage through the corresponding lower plate switch, and connecting the least significant bit capacitor to the negative reference voltage, while keeping the connections of the other capacitors in the negative capacitance array unchanged; to perform the kth comparison and obtain the kth comparison result of the kth comparison; wherein, 3≤k≤n, and n is the resolution of the successive approximation analog-to-digital converter.

[0016] As described above, the successive approximation analog-to-digital converter, integrated circuit, device and switching method of the present application have the following beneficial effects:

[0017] First, by using the alternation of rising conversion and falling conversion to control the converged value of Vcm (common-mode voltage) in the successive approximation algorithm, the magnitude of Vcm during conversion (especially in the last part for resolving LSBs) is related to the input common mode of the ADC comparator. Therefore, it can be customized and optimized according to the optimal input common mode of the comparator, so as to improve the conversion speed.

[0018] Second, on the above basis, a circuit structure for temporarily changing the common-mode voltage is added, which is implemented through AND gates and OR gates. At an appropriate time, the control signal can control the switching of the third capacitor and the fourth capacitor, temporarily changing the differential output voltage of the capacitor array to reduce the output common-mode swing.

[0019] Third, except for the LSB conversion process in this application, in other conversion processes, the upper negative capacitor array is switched simultaneously, so the common-mode voltage of the capacitor array remains basically unchanged, thereby simplifying the design of the comparator.

[0020] Fourth, this application greatly reduces the switching energy consumption of the capacitor array by optimizing the control logic. Description of the Drawings

[0021] Figure 1 Shows the overall structural schematic diagram of a successive approximation analog-to-digital converter provided by an embodiment of this application

[0022] Figure 2 Shows the overall structural schematic diagram of a 10-bit successive approximation analog-to-digital converter provided by an embodiment of this application;

[0023] Figure 3 Shows the internal timing generation circuit of SARLogic in a successive approximation analog-to-digital converter provided by an embodiment of this application;

[0024] Figure 4 Shows the first circuit diagram of SARLogic in a successive approximation analog-to-digital converter provided by an embodiment of this application;

[0025] Figure 5 Shows the second circuit diagram of SARLogic in a successive approximation analog-to-digital converter provided by an embodiment of this application;

[0026] Figure 6 Shows the comparison chart of the CDAC voltage and the common-mode output voltage of the monotonic switching strategy in a successive approximation analog-to-digital converter provided by an embodiment of this application;

[0027] Figure 7 Shows the circuit structure diagram for temporarily changing the output common-mode voltage provided by an embodiment of this application;

[0028] Figure 8Shown is a circuit structure diagram of temporarily changing the output common-mode voltage in a 10-bit successive approximation analog-to-digital converter provided by an embodiment of the present application;

[0029] Figure 9 Shown is a successive approximation process diagram of a successive approximation analog-to-digital converter with or without a temporarily changing common-mode voltage circuit provided by an embodiment of the present application;

[0030] Figure 10 Shown is a comparison diagram of the common-mode voltage change during the successive approximation process in a successive approximation analog-to-digital converter provided by an embodiment of the present application. Detailed implementation manners

[0031] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0032] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The types, quantities, and ratios of the components during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0033] Please refer to Figure 1 , the present application provides a structure block diagram of a successive approximation analog-to-digital converter shown as provided by an embodiment of the present application, including:

[0034] A capacitor array, including a positive capacitor array and a negative capacitor array with the same structure;

[0035] Among them, the capacitor array is a set composed of multiple capacitor units with the same structure arranged according to a certain rule. Here, the capacitor array is divided into a positive capacitor array and a negative capacitor array. The two have the same structure but are symmetric in function and are used to implement the processing of differential signals; each capacitor unit in the positive capacitor array and the negative capacitor array is designed with an upper plate and a lower plate. The upper plate is used to receive the input signal, and the lower plate is connected to different reference voltages (positive reference voltage or negative reference voltage) through switches to achieve the modulation of the capacitance value. For example, by changing the reference voltage connected to the lower plate of the capacitor, the charging / discharging state of the capacitor can be changed, and thus the total capacitance value of the entire capacitor array can be changed.

[0036] The differential input voltage is respectively connected to the upper plates of the positive capacitor array and the negative capacitor array;

[0037] Among them, the differential input voltage refers to a pair of voltage signals with equal magnitude and opposite polarities, which are respectively applied to the upper plates of the positive capacitor array and the negative capacitor array; Exemplarily, the differential input voltage is provided by an external signal source and is respectively connected to the upper plates of the positive capacitor array and the negative capacitor array to form a differential signal input. The differential signal can suppress common-mode noise and improve the anti-interference ability of the signal, which is a commonly used signal form in analog circuit design.

[0038] A comparator, the non-inverting input terminal of the comparator is connected to the upper plate of the upper capacitor array, the inverting input terminal of the comparator is connected to the upper plate of the negative capacitor array, and the comparator is controlled by a first clock signal to perform comparison and output a comparison signal;

[0039] Among them, a comparator is a circuit used to compare the magnitudes of two input voltages and output a logic level (high or low) as the comparison result; The comparator compares the difference between two input voltages. When the difference exceeds a certain threshold, the output logic level changes; The logic control circuit receives the output signal of the comparator as input and, under the control of a second clock signal, generates corresponding control signals according to the comparison result to control the lower plate switches of the positive capacitor array and the negative capacitor array.

[0040] A logic control circuit, connected to the output terminal of the comparator, is controlled by a second clock signal, uses the comparison signal as input to generate corresponding control signals to control the lower plate switches of the positive capacitor array and the negative capacitor array, so that the lower plates are switched to the positive reference voltage or the negative reference voltage;

[0041] The logic control circuit is a circuit that generates control signals according to input signals and is used to control the working states of other circuit components. The logic control circuit determines when to switch the reference voltage of the capacitor lower plate according to the output signal (high or low) of the comparator and the timing of the clock signal. For example, the logic control circuit receives the output signal of the comparator as input and, under the control of a second clock signal, generates corresponding control signals to control the lower plate switches of the positive capacitor array and the negative capacitor array.

[0042] The decoder, connected to the output terminal of the logic control circuit, is used to encode and convert each digital code into a binary code and output it.

[0043] Among them, a decoder is a circuit that converts an input digital code into a specific output signal (such as a binary code); the output terminal of the comparator is connected to the input terminal of the successive approximation control logic circuit SAR Logic, and the output terminal of the successive approximation control logic circuit SAR Logic is connected to the input terminal of the decoder. The decoder is used to convert the input N+1-bit digital code into an N-bit standard binary code Dout[N].

[0044] In this embodiment, a successive approximation control logic circuit SAR Logic is designed, and its output control terminal is configured to be respectively connected to the switch control terminals of the positive capacitor array and the negative capacitor array. This configuration ensures that the common terminal of the positive capacitor array and the negative capacitor array can be accurately connected to the non-inverting input terminal and the inverting input terminal of the comparator, thereby realizing the precise comparison and processing of signals. In addition, the technical solution of this application embodiment innovatively connects the non-common terminals (capacitor bottom plates) of the capacitors in the positive capacitor array and the negative capacitor array in the capacitive array digital-to-analog converter, cleverly generating a virtual common-mode level. This design completely eliminates the need for an external common-mode level reference source, greatly simplifies the system structure, reduces costs, and improves the stability and reliability of the system.

[0045] In summary, the technical solution provided by the embodiments of this application not only realizes efficient signal processing through an accurate successive approximation control logic circuit and capacitive array configuration, but also avoids the use of an external common-mode level reference source through an innovative virtual common-mode level generation method, demonstrating significant technical advantages and application values.

[0046] Optionally, in one embodiment, the positive capacitor array and the negative capacitor array are respectively composed of N capacitors, and the N-1 capacitors formed from the most significant bit capacitor to the second least significant bit capacitor correspond one-to-one with the N-1 lower plate switches, so that each of the N-1 capacitors is connected to a lower plate switch. N is a positive integer greater than 1; and the lower plate of the least significant bit capacitor is connected to the negative reference voltage. The lower plate switches in the positive capacitor array are switched between the positive reference voltage and the negative reference voltage by the first control signal output by the logic control circuit, and the lower plate switches in the negative capacitor array are switched between the positive reference voltage and the negative reference voltage by the second control signal output by the logic control circuit.

[0047] It should be noted that the levels of the lowest bit capacitors in the positive capacitor array and the negative capacitor array are always connected to the negative reference voltage, that is, the reference ground.

[0048] In the above manner, a higher energy efficiency ratio is achieved by dynamically adjusting the capacitance value.

[0049] Optionally, in one embodiment, the differential input voltage includes a positive input terminal voltage and a negative input terminal voltage. The non-inverting input terminal is connected to the positive terminal input voltage through a first sampling switch, and the non-inverting input terminal is connected to the upper plates of the respective positive capacitor arrays; the inverting input terminal is connected to the negative terminal input voltage through a second sampling switch, and the inverting input terminal is connected to the upper plates of the respective negative capacitor arrays.

[0050] Optionally, in one embodiment, the logic control circuit includes:

[0051] A timing generation unit, composed of a plurality of flip-flops connected in series, uses the second clock signal as the reset signal of each flip-flop, and uses the comparison signal as the timing input signal. A reference voltage is connected to the input terminal of the flip-flop with the highest bit, and a plurality of flip-flops sequentially output timing signals;

[0052] A logic control unit, including a flip-flop, whose clock signal is any one of the timing signals, the input terminal of the flip-flop samples the first output signal of the comparator, and the output terminal of the flip-flop is the second output signal of the analog-to-digital converter; any one of the timing signals is processed by a buffer and then subjected to an AND gate process or a NAND gate process with the second output signal to generate a third control signal to control the on / off of the positive capacitor array and the negative capacitor array;

[0053] Among them, the third control signal obtained through the AND gate process resets the positive capacitor array and the negative capacitor array to the positive reference voltage; the third control signal obtained through the NAND gate process resets the positive capacitor array and the negative capacitor array to the negative reference voltage to change the common-mode voltage of the capacitor array.

[0054] Exemplarily, using the second clock signal as the reset signal of each flip-flop ensures that the flip-flop state is reset at a specific moment; using the comparison signal as the timing input signal triggers the change of the flip-flop state. A reference voltage is connected to the input terminal of the flip-flop with the highest bit as the initial comparison reference of the flip-flop; a plurality of flip-flops are connected in sequence, and each flip-flop outputs a timing signal to form a series of timing signals with different delays; select one timing signal as the clock signal of the flip-flop.

[0055] The first output signal of the comparator is used as the input signal of the flip-flop, and the second output signal of the analog-to-digital converter is generated at the output terminal of the flip-flop; after any timing signal is processed by the buffer, it is subjected to an AND gate process or a NAND gate process with the second output signal; a third control signal is generated according to the processing result. The positive capacitor array and the negative capacitor array are reset to the positive reference voltage through the third control signal processed by the AND gate; the positive capacitor array and the negative capacitor array are reset to the negative reference voltage through the third control signal processed by the NAND gate; the common-mode voltage of the capacitor array is changed to adapt to different application requirements.

[0056] In the above manner, an accurate timing signal is generated by the timing generation unit, realizing accurate control of the on / off of the capacitor array; through the switching of the logic control unit and the third control signal, dynamic adjustment of the common-mode voltage of the capacitor array is realized, so that the capacitance value can be flexibly adjusted. The use of standard circuit elements such as flip-flops, buffers, and logic gates is beneficial to the integration and miniaturization of the circuit. Through accurate timing control and logic processing, the reliability and stability of the circuit are improved.

[0057] Please refer to Figure 2 , which is a schematic diagram of the overall structure of a 10-bit successive approximation analog-to-digital converter provided by an embodiment of the present application, including:

[0058] The present application provides a novel switching strategy for a capacitor array (CDAC) in a successive approximation (SAR) analog-to-digital converter (ADC). The proposed CDAC achieves a smaller CADC output common-mode swing while maintaining the same number of capacitors and switches as a monotonic switched CDAC. This is achieved by appropriately alternating rising and falling transitions in the CDAC and temporarily changing the output common-mode voltage. Therefore, since the switching strategy of the CDAC can be customized according to the optimal input common-mode of the comparator, the performance of the converter is significantly improved. The structure diagram of the SAR ADC adopting the proposed switching strategy is as shown in Figure 2 As shown, for comparison, it is the same as a traditional SAR ADC and does not mean that it is only applicable to a 10-bit SAR ADC. It consists of a sampling switch, a differential CDAC array, a dynamic comparator, digital control logic (SAR Logic), and an output encoder (Encoder).

[0059] The differential input voltage, i.e., the positive terminal input voltage (Vip) and the negative terminal input voltage (Vin), are respectively connected to the top plates of the positive capacitor array and the negative capacitor array through sampling switches; the top plates of the positive capacitor array are connected to the non-inverting input terminal of the comparator, and the top plates of the negative capacitor array are connected to the inverting input terminal of the comparator; the comparison result signal Va controlled by the clock signal Clkc is transmitted to the digital control logic (SAR Logic); SAR Logic generates control signals to control the bottom plates of the positive capacitor array and the negative capacitor array to be connected to the corresponding levels, and the output encoder (Encoder) encodes each digital code output by SAR Logic to generate the converted digital code.

[0060] Specifically, in one embodiment, the logic control unit further includes a PMOS transistor, an NMOS transistor, and a capacitor. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded; the gates of the PMOS transistor and the NMOS transistor are interconnected and then connected to the third control signal, and the drains of the PMOS transistor and the NMOS transistor are interconnected and then externally connected to the capacitor. Among them, the capacitor is any one of the capacitors switched in the capacitor array.

[0061] As Figure 3 shown, the internal timing generation circuit of SAR Logic uses Va as the clock signal; CLKs is the ADC sampling switch control signal, which also serves as the reset signal of the register here. When CLKs is at a high level, CLK0 to CLK9 are all reset to GND. CLK0 to CLK9 are the output signals of this circuit.

[0062] As Figure 4 shown, the Clk generated by the internal timing generation circuit of SAR Logic The digital outputs OUTP or OUTN of the sampling comparator, and serves as the control signal for the capacitor array. The DFF register outputs B is the digital output signal of the ADC, which is associated with Clk The on / off of the switch is controlled by an AND gate (or NAND gate), thereby controlling the capacitor array.

[0063] Circuit a( Figure 4 ) and circuit b( Figure 5 ) differ in that the control signal C of the capacitor control switch Whether it is an AND gate or a NAND gate. The function of Circuit a is to reset to Vref (VDD), while Circuit b resets to GND. By different reset results, it can change whether the successive approximation process is rising or falling. It should be noted that the circuit structure of Logic Circuit is Figure 7 as shown. Therefore, configure the reset result of each switch according to actual needs to improve the common-mode output of the CDAC, which is also the reason why the switch switching strategy in this application is customizable.

[0064] Such as Figure 6 as shown, using an improved version of the monotonic switch successive approximation process allows the common-mode voltage (Vcm) change at the input of the comparator to be reduced by 2 times, while the monotonic switching strategy in this application allows the common-mode change on the top plate of the CDAC to be halved compared to the traditional one without increasing the logic complexity. It is achieved by modifying the reset phase and the first switch step: different from the original monotonic switch strategy, in the sampling stage, the bottom plate of the MSB capacitor is reset to GND instead of being reset to Vref. All the remaining capacitors are reset to Vref.

[0065] For details, see Figure 7 , which shows a circuit structure diagram of a circuit for temporarily changing the output common-mode voltage provided by an embodiment of this application. Among them, the circuit structure for determining the common-mode voltage includes:

[0066] Perform an AND operation on the timing control signal of the first high bit and the inverted signal of the timing control signal of the second high bit to determine the first logic signal as the weight switching between the (N - 2)th capacitor and the (N - 3)th capacitor; among them, the output of the (N - 2)th capacitor is obtained by performing an OR operation on the first logic signal and the control signal of the (N - 2)th capacitor.

[0067] Perform an AND operation on the timing control signal of the second high bit and the inverted signal of the timing control signal of the third high bit to determine the second logic signal;

[0068] Perform an OR operation on the first logic signal, the second logic signal, and the control signal of the (N - 3)th capacitor to perform the switching of the connection level of the (N - 3)th capacitor.

[0069] Specifically, although changing whether the successive approximation process is rising or falling reduces the change range of the CDAC common-mode voltage to a certain extent, since the highest bit and the second highest bit capacitors have the largest weights, when the highest bit capacitor and the second highest bit are switched, the common-mode change is relatively large. To reduce the amplitude of the common-mode voltage, it is necessary to change the common-mode voltage change of the highest bit and the second highest bit. Therefore, Figure 7 a structure that can reduce the common-mode change by simultaneously switching some capacitors of the positive and negative capacitor arrays is used. Assume that the resolution of the ADC is N and the timing control signal of the highest bit is Clk <n>。Clk <n>and Clk <n-1>The inverted signal can control Cd <n-2>, thereby controlling C <n-2>and C <n-3>The switching of the weighting capacitors achieves the effect of reducing the change in the highest-bit common-mode voltage; the timing control signal Clk of the second highest bit <n-1>, Clk <n-1>and Clk <n-2>The anti-phase signal can control Cd <n-3>, thereby controlling C <n-3>By switching the weighting capacitors, the effect of reducing the change in the second-highest common-mode voltage is achieved.

[0070] As Figure 8 shown, the Cd<7> signal should be the logical OR operation of the first logic signal and C<7> (i.e., the third control signal), while the Cd<6> signal is the logical OR operation of the first logic signal, the second logic signal, and C<6> (the third control signal). The high-order logic signal should act together with the low-order logic signal; and so on. If there is a Cd<5> signal, it should be the logical OR operation of the first logic signal, the second logic signal, the third logic signal, and C<5>.

[0071] Specifically, this application reduces the variation range of the CDAC common-mode voltage. However, it can be seen that the common-mode change of the highest bit is the largest. To reduce the amplitude of the common-mode voltage, the common-mode voltage change of the highest bit needs to be changed. Therefore, the Figure 8 structure is used. The anti-phase signals of the timing control signal Clk<9> of the highest bit MSB and the timing control signal Clk<8> of the second-highest bit are used for AND logic control of Cd<7> and Cd<6>, thereby controlling the switching of the third and fourth capacitors. The anti-phase signals of the timing control signal Clk<8> of the second-highest bit MSB and the timing control signal Clk<7> are used for AND logic control of Cd<6>, thereby controlling the switching of the fourth capacitor.

[0072] In this embodiment, the proposed switch switching strategy is verified by simulation in the SAR ADC. For comparison, except for the SAR Logic that needs to be changed, other configurations are the same as those of the traditional monotonic switch switching strategy. The switch strategy proposed in this application is applied to an asynchronous 10-bit, 100MS / s SAR analog-to-digital converter, which is implemented in 40nm CMOS with VDD = 1.1V. In the sampling stage, the bottom plate of the MSB (most significant bit) capacitor is reset to GND (i.e., Figure 2 the V refn ) instead of Vref (i.e., Figure 2 the V refp ), and all the remaining capacitors are reset to Vref.

[0073] As Figure 9 shown, the mVp and mVn curves are the successive approximation processes where only in the sampling stage, the bottom plate of the MSB capacitor is reset to GND, and the remaining capacitors are reset to Vref, without adding a circuit for temporarily changing the common-mode voltage. The Vp and Vn curves are the successive approximation processes with a circuit for temporarily changing the common-mode voltage added.

[0074] After the first comparison in the successive approximation process and before the second comparison, the voltage of mVn without adding the temporary change common-mode voltage circuit is up-converted to VDD / 2, and the voltage of mVp remains unchanged. At the same time, due to the action of the temporary change common-mode voltage circuit, the voltage of Vn is not up-converted to VDD / 2, but VDD / 2 - VDD / 8 - VDD / 16, that is, 5 / 16*VDD, and at the same time, the voltage of Vp is down-converted to VDD / 8 + VDD / 16, that is, 3 / 16*VDD.

[0075] After the second comparison and before the third comparison, mVp is down-converted by VDD / 4, and mVn remains unchanged. However, for the proposed switch switching strategy, Vp is down-converted by VDD / 4 + VDD / 16, that is, 5 / 16*VDD, and at the same time, the voltage of Vn is down-converted by VDD / 16.

[0076] After the third comparison, the voltages of the two successive approximation processes become the same. This is also the core of the temporary change common-mode voltage circuit. Because the common-mode change of the voltages in the first two successive approximation processes is relatively large, the voltages in the first two successive approximation processes are temporarily changed, and changing Vp and Vn has little effect on the linearity. From Figure 9 it can be seen that since the change of the common-mode voltage will cause a certain improvement in the speed of successive approximation, this is beneficial for high-speed ADC applications.

[0077] It should be noted that Figure 9 the voltages of Vp and Vn after the first temporary change in Figure 9 will change back to the voltages before the change before the second switch. The fact that Vp and Vn in

[0078] do not change significantly is due to the limited number of sampling points in the drawing. Figure 10 As shown in

[0079] is the common-mode voltage change of the traditional monotonic switch switching strategy and the proposed switch strategy. In the traditional monotonic switch switching strategy, the common-mode swing is VDD / 2. The different reset voltages proposed in this application reduce the common-mode swing to VDD / 4. On this basis, adding the proposed temporary common-mode voltage change circuit further reduces the common-mode voltage swing to VDD / 16. As can be seen above, the common-mode voltage swing is significantly reduced, and the performance of the comparator during the conversion process will also be significantly improved.

[0080] In a second aspect, the present application provides an integrated circuit including the successive approximation analog-to-digital converter described above.

[0081] In a third aspect, the present application provides an electronic device including the successive approximation analog-to-digital converter described above; or, adopting the integrated circuit described above.

[0082] In a fourth aspect, the present application provides a method for switching switches of a successive approximation analog-to-digital converter, including:

[0083] In the sampling stage: closing the first sampling switch and the second sampling switch, connecting the non-inverting input terminal of the comparator to the positive terminal input voltage, connecting the inverting input terminal of the comparator to the negative terminal input voltage, performing a first comparison, and obtaining a first comparison result output by the comparator through pre-comparison;

[0084] After the first comparison is completed, switching the levels connected to the positive capacitance array and the negative capacitance array respectively according to the first comparison result; if the first comparison result is a high level, connecting the lower plate switches corresponding to the lower plates of n - 1 capacitors in the positive capacitance array to the reference voltage, and keeping the lower plate of the lowest-bit capacitor connected to the negative reference voltage, while connecting the n lower plate switches corresponding to the lower plates of the negative capacitance array to the negative reference voltage; if the first comparison result is a low level, connecting the lower plate switches corresponding to the lower plates of the positive capacitance array to the negative reference voltage, connecting the lower plate switches corresponding to the lower plates of n - 1 capacitors in the negative capacitance array to the reference voltage, and keeping the lower plate of the lowest-bit capacitor connected to the negative reference voltage;

[0085] In the conversion stage: after the sampling stage ends, disconnecting the first sampling switch and the second sampling switch, switching the levels connected to the positive capacitance array and the negative capacitance array respectively according to the first comparison result, performing a second comparison, and obtaining a second comparison result, wherein the lowest-bit capacitors in the positive capacitance array and the negative capacitance array are both connected to the negative reference voltage;

[0086] The k-th comparison includes: switching the connection levels of the positive capacitance array and the negative capacitance array according to the (k - 1)-th comparison result; if the (k - 1)-th comparison result is 1, switching the non-common end of the (k - 2)-th capacitor in the positive capacitance array to be connected to the negative reference voltage through the corresponding lower plate switch, and connecting the lowest-bit capacitor to the negative reference voltage, while keeping the connections of other capacitors in the positive capacitance array unchanged; switching the non-common end of the (k - 2)-th capacitor in the negative capacitance array to be connected to the reference voltage through the corresponding lower plate switch, and connecting the lowest-bit capacitor to the negative reference voltage, while keeping the connections of other capacitors in the negative capacitance array unchanged;

[0087] If the result of the (k - 1)-th comparison is 0, then the non-common terminal of the (k - 2)-th capacitor in the positive capacitor array is switched and connected to the reference voltage through the corresponding lower plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the positive capacitor array remain unchanged; the non-common terminal of the (k - 2)-th capacitor in the negative capacitor array is switched and connected to the negative reference voltage through the corresponding lower plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the negative capacitor array remain unchanged;

[0088] to perform the k-th comparison and obtain the result of the k-th comparison; where 3 ≤ k ≤ n, and n is the resolution of the successive approximation analog-to-digital converter.

[0089] Through the above method, the present application provides a switching method for an integrated circuit, an electronic device, and a successive approximation analog-to-digital converter, having the following technical effects:

[0090] First, by using the alternation of the rising conversion and the falling conversion to control the converged value of Vcm (common-mode voltage) in the successive approximation algorithm, the magnitude of Vcm during the conversion (especially in the last part of resolving the LSBs) is related to the input common mode of the ADC comparator. Therefore, it can be customized and optimized according to the best input common mode of the comparator, so that the conversion speed can be improved;

[0091] Second, on the basis of the above, a circuit structure for temporarily changing the common-mode voltage is added, which is implemented through AND gates and OR gates. At an appropriate time, the control signal can control the switching of the third capacitor and the fourth capacitor to temporarily change the differential output voltage of the capacitor array to reduce the output common-mode swing;

[0092] Third, except for the LSB conversion process, in other conversion processes of the present application, the switching of the upper negative capacitor array is performed simultaneously, so the common-mode voltage of the capacitor array remains basically unchanged, thereby simplifying the design of the comparator;

[0093] Fourth, the present application greatly reduces the switching energy consumption of the capacitor array by optimizing the control logic

[0094] The above embodiments are only illustrative of the principles and effects of the present application, and are not used to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present application should still be covered by the claims of the present application. < / n> < / n>

Claims

1. A successive approximation analog-to-digital converter, characterized in that, Comprising: A capacitor array, including a positive capacitor array and a negative capacitor array with the same structure; A differential input voltage, respectively connected to the upper plates of the positive capacitor array and the negative capacitor array; A comparator, the non-inverting input terminal of the comparator is connected to the upper plate of the upper capacitor array, the inverting input terminal of the comparator is connected to the upper plate of the negative capacitor array, and the comparator is controlled by a first clock signal to perform comparison and output a comparison signal; A logic control circuit, connected to the output terminal of the comparator, controlled by a second clock signal, using the comparison signal as an input to generate a corresponding control signal to control the lower plate switches of the positive capacitor array and the negative capacitor array, so that the lower plate switches to a positive reference voltage or a negative reference voltage; The decoder, connected to the output terminal of the logic control circuit, is used to encode and convert each digital code into a binary code and output it.

2. The successive approximation type analog-to-digital converter according to claim 1, wherein The positive capacitor array and the negative capacitor array are respectively composed of N capacitors. The N-1 capacitors formed from the most significant bit capacitor to the second least significant bit capacitor correspond one-to-one with N-1 lower plate switches, so that each of the N-1 capacitors is connected to a lower plate switch. N is a positive integer greater than 1; and the lower plate of the least significant bit capacitor is connected to the negative reference voltage. The lower plate switches in the positive capacitor array are switched between the positive reference voltage and the negative reference voltage under the control of the first control signal output by the logic control circuit, and the lower plate switches in the negative capacitor array are switched between the positive reference voltage and the negative reference voltage under the control of the second control signal output by the logic control circuit.

3. The successive approximation type analog-to-digital converter according to claim 2, wherein The differential input voltage includes a positive input terminal voltage and a negative input terminal voltage. The non-inverting input terminal is connected to the positive terminal input voltage through a first sampling switch, and the non-inverting input terminal is connected to the upper plates of the positive capacitor array; the inverting input terminal is connected to the negative terminal input voltage through a second sampling switch, and the inverting input terminal is connected to the upper plates of the negative capacitor array.

4. The successive approximation type analog-to-digital converter according to claim 1, wherein The logic control circuit includes: A timing generation unit, composed of a plurality of serially connected flip-flops, using the second clock signal as the reset signal of each flip-flop, and using the comparison signal as the timing input signal. A reference voltage is connected to the input terminal of the flip-flop with the highest bit, and a plurality of flip-flops sequentially output timing signals; A logic control unit, including a flip-flop, the clock signal of the flip-flop is any one of the timing signals, the input terminal of the flip-flop samples the first output signal of the comparator, and the output terminal of the flip-flop is the second output signal of the analog-to-digital converter; any one of the timing signals is processed by a buffer and then subjected to an AND gate process or a NAND gate process with the second output signal to generate a third control signal to control the on / off of the positive capacitor array and the negative capacitor array; Wherein, the third control signal obtained through the AND gate process resets the positive capacitor array and the negative capacitor array to the positive reference voltage; the third control signal obtained through the NAND gate process resets the positive capacitor array and the negative capacitor array to the negative reference voltage to change the common-mode voltage of the capacitor array.

5. The successive approximation type analog-to-digital converter according to claim 4, wherein The logic control unit further includes a PMOS transistor, an NMOS transistor, and a capacitor. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded. The gates of the PMOS transistor and the NMOS transistor are interconnected and connected to the third control signal. The drains of the PMOS transistor and the NMOS transistor are interconnected and externally connected to the capacitor. Among them, the capacitor is any one of the capacitors switched in the capacitor array.

6. The successive approximation type analog-to-digital converter according to claim 4, wherein, The circuit structure for determining the common-mode voltage includes: Performing an AND operation on the timing control signal of the first high bit and the inverted signal of the timing control signal of the second high bit to determine a first logic signal for use as the weight switching between the (N - 2)-th capacitor and the (N - 3)-th capacitor. Among them, the output of the (N - 2)-th capacitor is obtained by performing an OR operation on the first logic signal and the control signal of the (N - 2)-th capacitor. Performing an AND operation on the timing control signal of the second high bit and the inverted signal of the timing control signal of the third high bit to determine a second logic signal. Performing an OR operation on the first logic signal, the second logic signal, and the control signal of the (N - 3)-th capacitor to perform the switching of the connection level of the (N - 3)-th capacitor.

7. The successive approximation type analog-to-digital converter according to claim 1, wherein In the sampling stage, the most significant bit capacitor is reset to the negative reference voltage, and the remaining capacitors among the N - 1 capacitors are reset to the positive reference voltage. According to the received common-mode voltage, the X bits are reset to the negative reference voltage, and the remaining capacitors among the remaining N - X are reset to the positive reference voltage, where N is the resolution of the successive approximation analog-to-digital converter, and the X bits are determined by the optimal common-mode voltage of the actual comparator.

8. An integrated circuit, characterized in that, Including the successive approximation analog-to-digital converter according to any one of claims 1 to 7 above.

9. An electronic device, characterized in that, Including the integrated circuit according to any one of claim 8 above, or using the successive approximation analog-to-digital converter according to any one of claims 1 to 7 above.

10. A switching method for a successive approximation analog-to-digital converter, characterized in that, Including: In the sampling stage: Closing the first sampling switch and the second sampling switch, connecting the non-inverting input terminal of the comparator to the positive terminal input voltage, connecting the inverting input terminal of the comparator to the negative terminal input voltage, performing the first comparison, and obtaining the first comparison result output by the comparator through pre-comparison. After the first comparison is completed, switching the connection levels of the positive capacitor array and the negative capacitor array respectively according to the first comparison result. If the first comparison result is a high level, connecting the lower plate switches corresponding to the lower plates of n - 1 capacitors in the positive capacitor array to the reference voltage, and keeping the lower plate of the lowest bit capacitor connected to the negative reference voltage. At the same time, connecting the n lower plate switches corresponding to the lower plates of the negative capacitor array to the negative reference voltage. If the first comparison result is a low level, connecting the lower plate switches corresponding to the lower plates of the positive capacitor array to the negative reference voltage, connecting the lower plate switches corresponding to the lower plates of n - 1 capacitors in the negative capacitor array to the reference voltage, and keeping the lower plate of the lowest bit capacitor connected to the negative reference voltage. During the conversion stage: after the sampling stage ends, disconnect the first sampling switch and the second sampling switch, and switch the levels connected to the positive capacitance array and the negative capacitance array respectively according to the first comparison result, and perform a second comparison to obtain a second comparison result, wherein the lowest-bit capacitors in the positive capacitance array and the negative capacitance array are both connected to a negative reference voltage; The k-th comparison includes: switching the connection levels of the positive capacitance array and the negative capacitance array according to the (k - 1)-th comparison result; if the (k - 1)-th comparison result is 1, switch the non-common terminal of the (k - 2)-th capacitor in the positive capacitance array to be connected to the negative reference voltage through the corresponding lower-plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the positive capacitance array remain unchanged; switch the non-common terminal of the (k - 2)-th capacitor in the negative capacitance array to be connected to the reference voltage through the corresponding lower-plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the negative capacitance array remain unchanged; if the (k - 1)-th comparison result is 0, switch the non-common terminal of the (k - 2)-th capacitor in the positive capacitance array to be connected to the reference voltage through the corresponding lower-plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the positive capacitance array remain unchanged; switch the non-common terminal of the (k - 2)-th capacitor in the negative capacitance array to be connected to the negative reference voltage through the corresponding lower-plate switch, and the lowest-bit capacitor is connected to the negative reference voltage, while the connections of other capacitors in the negative capacitance array remain unchanged; so as to perform the k-th comparison and obtain the k-th comparison result of the k-th comparison; wherein, 3 ≤ k ≤ n, and n is the resolution of the successive approximation analog-to-digital converter.

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