Error correction circuit, memory system and error correction method

Abstract

An error correction device includes: a syndrome generation circuit configured to: output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for data; the error position determination circuit is configured to determine a coefficient of a first error position polynomial based on the first syndrome, the second syndrome and the third syndrome, and determine a coefficient of a second error position polynomial based on the fourth syndrome, the fifth syndrome and the sixth syndrome, and based on the first error position polynomial and the second error position polynomial, obtaining the position of an error included in the data by taking two continuous symbols as a unit, and an error value determination circuit configured to pre-determine a value of an error in units of two consecutive symbols based on the first syndrome and the second syndrome.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0001735, filed with the Korean Intellectual Property Office on January 4, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a storage device, and more particularly, to an error - correction circuit, a memory system, and an error - correction method. Background art

[0004] An error - correction circuit may perform error - correction coding (ECC) to correct error bits in information data.

[0005] As communication speed increases and data throughput increases, the number of error bits in information data may increase. Due to the increase in error bits, the error - correction latency required from when the information data is received by the error - correction decoder until the error - correction decoder outputs corrected data may increase. Summary of the invention

[0006] The present inventive concept provides an error - correction decoder including an error - correction device that corrects errors in units of two consecutive symbols, thereby reducing error - correction latency.

[0007] According to some embodiments of the present inventive concept, there is provided an error - correction device including: a syndrome generation circuit configured to: receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data, the first syndrome, second syndrome, third syndrome, fourth syndrome, fifth syndrome, and sixth syndrome for the data being determined by substituting powers of a primitive element of a Galois field into a received polynomial based on the data. The corresponding exponents of the powers of the primitive element for determining the first syndrome, second syndrome, and third syndrome among the primitive elements increase sequentially, and the corresponding exponents of the powers of the primitive element for determining the fourth syndrome, fifth syndrome, and sixth syndrome among the primitive elements increase sequentially. The error - correction device includes: an error - location determination circuit configured to: determine coefficients of a first error - location polynomial based on the first syndrome, second syndrome, and third syndrome, determine coefficients of a second error - location polynomial based on the fourth syndrome, fifth syndrome, and sixth syndrome, and obtain positions of errors included in the data in units of two consecutive symbols based on the first error - location polynomial and the second error - location polynomial; an error - value determination circuit configured to: pre - determine values of errors in units of two consecutive symbols based on the first syndrome and the second syndrome; and an error - correction circuit configured to: correct errors included in the data based on the positions and values of the errors.

[0008] According to some embodiments of the inventive concept, a memory system is provided, including: a storage device including a plurality of memory cells; and a memory controller configured to: correct data read from the storage device. The memory controller includes an error correction device. The error correction device includes a syndrome generation circuit configured to: receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data, the first syndrome, the second syndrome, the third syndrome, the fourth syndrome, the fifth syndrome, and the sixth syndrome for the data being determined by substituting powers of a primitive element of a Galois field into a received polynomial based on the data. The respective exponents of the powers of the primitive element used to determine the first syndrome, the second syndrome, and the third syndrome among the primitive elements increase sequentially, and the respective exponents of the powers of the primitive element used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome among the primitive elements increase sequentially. The error correction device includes an error location determination circuit configured to: determine coefficients of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine coefficients of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain positions of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial. The error correction device includes: an error value determination circuit configured to: pre-determine values of errors in units of two consecutive symbols based on the first syndrome and the second syndrome; and an error correction circuit configured to: correct errors included in the data based on the positions and the values of the errors.

[0009] According to some embodiments of the inventive concept, there is provided an error correction method, including: receiving data, and outputting a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data, where the first syndrome, the second syndrome, the third syndrome, the fourth syndrome, the fifth syndrome, and the sixth syndrome for the data are determined by substituting powers of a primitive element of a Galois field into a received polynomial based on the data. The corresponding exponents of the powers of the primitive element for determining the first syndrome, the second syndrome, and the third syndrome increase sequentially, and the corresponding exponents of the powers of the primitive element for determining the fourth syndrome, the fifth syndrome, and the sixth syndrome increase sequentially. Determining coefficients of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determining coefficients of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtaining positions of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial. Pre-calculating values of errors in units of two consecutive symbols based on the first syndrome and the second syndrome, and correcting errors included in the data based on the positions of the errors and the values of the errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing a memory system according to some embodiments;

[0012] Figure 2 is a block diagram showing a method of encoding and decoding data performed by a memory system according to the inventive concept;

[0013] Figure 3 shows Figure 2 an example of a decoder shown;

[0014] Figure 4A shows Figure 3 an example of a Reed - Solomon (RS) code decoder shown;

[0015] Figure 4B shows Figure 3 a flowchart of an operation method of the RS code decoder shown;

[0016] Figure 5 shows Figure 3 an example of an error correction device shown;

[0017] Figure 6A shows Figure 5 an example of an error location determination circuit shown;

[0018] Figure 6B shows Figure 6A a block diagram of an example of the sub-error position determination circuit shown;

[0019] Figure 6C shows Figure 6B a block diagram of an example of the error position polynomial generation circuit shown;

[0020] Figure 7A shows Figure 5 a block diagram of an example of the error value determination circuit shown;

[0021] Figure 7B shows Figure 7A a block diagram of an example of the error value determination circuit shown;

[0022] Figure 8 shows Figure 3 a flowchart of an error correction method of the decoder shown;

[0023] Figure 9 shows Figure 2 a block diagram of another example of the decoder shown;

[0024] Figure 10 shows Figure 9 a block diagram of an example of the error correction device shown;

[0025] Figure 11 shows Figure 9 a flowchart of an error correction method of the decoder shown;

[0026] Figure 12 a diagram of a storage device according to some embodiments;

[0027] Figure 13 a diagram of a system applying a storage device according to some embodiments; and

[0028] Figure 14 a block diagram of an example of applying a memory controller to a solid state drive (SSD) system according to some embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, various embodiments of the inventive concept will be described with reference to the drawings.

[0030] Figure 1 a block diagram of a memory system according to some embodiments.

[0031] Refer to Figure 1, the memory system 1 may include a memory controller 10 and a storage device 20. The memory system 1 may also be referred to as a storage device. In addition, the memory system 1 may refer to a computing device, for example, an integrated circuit, an electronic device or system, a smart phone, a tablet PC, a computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), and / or other suitable computers, virtual machines, or their virtual computing devices. The memory system 1 may be a part of components included in a computing system, for example, a graphics card. According to some embodiments, the memory system 1 may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0032] The storage device 20 may include a memory cell array including a plurality of memory cells. The memory cell array may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at points where the word lines and the bit lines cross each other. The memory cells of the memory cell array may be volatile memory cells (e.g., dynamic random access memory (DRAM) cells, static RAM (SRAM) cells), non-volatile memory cells (e.g., flash memory cells, resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, magnetic RAM (MRAM) cells), or any other type of memory cells.

[0033] In some embodiments, the memory system 1 may be implemented as an embedded or removable memory in an electronic device and may be implemented in various forms, for example, an embedded universal flash storage (UFS) device, an embedded multimedia card (eMMC), a solid state drive (SSD), a UFS memory card, a compact flash (CF) memory, a secure digital (SD) memory, a micro secure digital (Micro-SD) memory, a mini secure digital (Mini-SD) memory, an extreme digital (xD) memory, or a memory stick.

[0034] The memory controller 10 may control the storage device 20 to read data stored in the storage device 20 or write data to the storage device 20 in response to a write / read request from a host HOST. Specifically, the memory controller 10 may control write, read, and erase operations on the storage device 20 by providing an address ADDR, a command CMD, and a control signal CTRL to the storage device 20. In addition, data DATA to be stored in the storage device 20 and data DATA read from the storage device 20 may be sent and received between the memory controller 10 and the storage device 20.

[0035] The memory controller 10 may include a decoder 100.

[0036] The decoder 100 can perform decoding on the data read from the storage device 20 using an error correction code (hereinafter referred to as ECC). The decoder 100 can perform decoding to correct errors in the read data.

[0037] That is, the decoder 100 can correct the data read from the memory cell array of the storage device 20.

[0038] According to some embodiments, the decoder 100 includes an error correction device that corrects errors in units of two consecutive symbols in addition to a Reed Solomon (RS) decoder, thereby reducing the time required for RS decoding. Therefore, the read latency can be improved.

[0039] Figure 2 is a block diagram showing a method of encoding and decoding data performed by a memory system according to the inventive concept.

[0040] Refer to Figure 2 , in addition to Figure 1 the storage device 20 and the decoder 100 shown, the memory system 1 may further include an encoder 200. According to some embodiments, the encoder 200 may be included in the memory controller 10 ( Figure 1 ).

[0041] First, when data DATA is input from the host HOST (see Figure 1 ), the input data DATA can be encoded by the encoder 200. At this time, the encoder 200 can perform RS code encoding on the input data DATA. Here, the encoded data may be referred to as an encoded codeword.

[0042] That is, the encoder 200 can perform RS code encoding on the data to generate a codeword of the RS code. In addition, the encoded data (e.g., codewords of multiple RS codes) can be written as write data WD to the storage device 20.

[0043] In addition, when a read command is received, the memory system 1 can read the data stored in the storage device 20 as read data RD. At this time, the read data RD may include an error E that occurs for various reasons. For example, the error E may occur due to a failure during programming of the write data WD or data loss when storing the write data WD in the storage device 20. According to some embodiments, the error E may occur due to a failure during a read operation of reading the read data RD.

[0044] The decoder 100 can perform RS code decoding on the read data RD to eliminate the error E. Here, the read data RD can be referred to as the read codeword. The decoding result can be output as the corrected data DATA'.

[0045] Hereinafter, a method of generating a codeword encoded with an RS code performed by the encoder 200 is described.

[0046] The RS code is a non-binary error correction code, and error correction using the RS code can be performed in units of symbols rather than in units of bits. Here, a symbol can refer to information represented by a predetermined number of bits.

[0047] When a symbol is represented by m bits, the RS code can be defined by GF(2 m ) which is a Galois field of size 2 m . The Galois field is a finite field and has a finite number of elements.

[0048] In the finite field GF(2 m ) of size 2 m , GF(2 m ) = {0, 1, , …, }. That is, GF(2 m ) can include 2 m elements. Here, can be a primitive element of the Galois field GF(2 m ).

[0049] In addition, there can be a one-to-one mapping relationship between the 2 m symbols which are all cases of numbers that can be represented by m bits and all 2 m elements of GF(2 m ).

[0050] To illustrate this, it will be assumed that the RS code has a total of N symbols. At this time, the decoded RS code can include K data symbols and P parity check symbols. The assumed RS code can correct up to P / 2 errors. That is, when N = K + P and a symbol is m bits, the maximum code length in symbol units is 2 m - 1. Here, N, K, and P are positive integers.

[0051] The codeword encoded with the RS code can be an N-dimensional vector c0, c1, …, c N-1 obtained from the coefficients of the code polynomial c(x). Here, the code polynomial c(x) can be an Nth-order polynomial for x that does not have a constant term, and the codeword encoded with the RS code can be from the code polynomial The obtained N-dimensional vectors c0, c1, …, c N-1 .

[0052] In addition, the code polynomial c(x) can be expressed as the product of the information polynomial m(x) and the generator polynomial g(x). In other words, there can be .

[0053] Here, the information polynomial m(x) can correspond to K data symbols and can be a polynomial of degree K in x. In addition, there can be a generator polynomial , and the generator polynomial g(x) can be a polynomial of degree P in x.

[0054] When x is an element of the Galois field GF(2 m ), the value of the generator polynomial g(x) can be 0. In addition, when x is a power of m which is a primitive element of the Galois field GF(2 ), the value of the generator polynomial g(x) can be 0. That is to say, in the generator polynomial g(x), there can be .

[0055] Therefore, because and , there can be .

[0056] At this time, the powers of which are P primitive elements can be substituted into x in the code polynomial , and the result of substituting the powers of which are P primitive elements into the code polynomial c(x) can be expressed as a matrix product as shown in Equation 1 below.

[0057] [Equation 1]

[0058]

[0059] Here, can represent the primitive element of the Galois field GF(2 m ).

[0060] In addition, can be a matrix that defines the rule for generating parity check symbols of an RS code, which includes K data symbols and P parity check symbols and has a total of N symbols. This matrix can be called the H matrix.

[0061] In addition, the columns in the H matrix that multiply the 0th coefficient c0 to the (K - 1)th coefficient c k-1 of the code polynomial can be defined as H K , and the column in the H matrix that multiplies the Kth coefficient c Kto the N-1th coefficient c N-1 The multiplied columns can be defined as H P , a K-dimensional vector can be defined as C K , and a P-dimensional vector can be defined as C P . At this time, the right side of Equation 1 can be expressed as .

[0062] In this case, because there is , it can be satisfied that . Therefore, there can be .

[0063] That is to say, the encoder 200 can calculate by using K data symbols, and can generate a codeword including K data symbols and P parity check symbols by using the calculated and . Here, the codeword encoded by the RS code can be the N-dimensional vector c0, c1,..., c N-1 obtained from the coefficients of the code polynomial c(x).

[0064] In the following, a method of operating the decoder 300 according to some embodiments is described.

[0065] Figure 3 is a block diagram showing an example of the decoder 100 shown in Figure 2 .

[0066] Referring to Figure 3 , the decoder 300 may include an error correction device 310 and an RS code decoder 320.

[0067] The error correction device 310 and the RS code decoder 320 may receive the read data RD read from the storage cell array.

[0068] The error correction device 310 may determine the position and magnitude of the error included in the data RD in units of two consecutive symbols, and correct the error included in the read data RD based on the determined position and magnitude of the error. The error correction device 310 may output the error-corrected data DATA'.

[0069] That is to say, the error correction device 310 may determine the position and magnitude of the error for each of a plurality of groups including two consecutive symbols without overlap in parallel. For example, when the read data RD includes N symbols, the error correction device 310 may determine the position and magnitude of the error included in the 0th symbol and the first symbol, the position and magnitude of the error included in the second symbol and the third symbol, and the position and magnitude of the error included in the N-2th symbol and the N-1th symbol in parallel.

[0070] The RS code decoder 320 can determine the positions and magnitudes of all the errors included in the read data RD, and correct the errors included in the read data RD based on the determined positions and magnitudes of the errors. The RS code decoder 320 can output the error-corrected data DATA'.

[0071] That is, the RS code decoder 320 can determine the positions and magnitudes of the errors included in the 0th symbol to the (N-1)th symbol at once.

[0072] In addition, the error correction operation of the RS code decoder 320 can be performed in parallel with the error correction operation of the error correction device 310. That is, the error correction device 310 and the RS code decoder 320 can start the error correction operation simultaneously.

[0073] Since the error correction device 310 determines the positions and magnitudes of the errors in parallel for each of a plurality of groups including two consecutive symbols without overlap, the error correction device 310 can have fewer operations than the RS code decoder 320 that needs to determine the positions and magnitudes of all the errors included in the read data RD.

[0074] Therefore, the error correction operation of the error correction device 310 can be performed faster than the error correction operation of the RS code decoder 320.

[0075] When the error correction operation of the error correction device 310 is successful, since the error correction operation of the RS code decoder 320 does not need to be performed, the error correction device 310 can output a signal TERMINATION indicating the termination of the error correction operation of the RS code decoder 320 to the RS code decoder 320.

[0076] That is, when the error correction operation of the error correction device 310 is successful, the error-corrected data DATA' can be output by the error correction device 310, and when the error correction operation of the error correction device 310 fails, the error-corrected data DATA' can be output by the RS code decoder 320.

[0077] Before describing the error correction operation of the error correction device 310, the error correction operation of the RS code decoder 320 will be described in detail.

[0078] Figure 4A shows Figure 3 a block diagram of an example of the RS code decoder shown. Figure 4B shows Figure 3 a flowchart of an operation method of the RS code decoder shown. Hereinafter, Figure 3 the read data RD can be referred to as the read codeword RCW.

[0079] To illustrate this, it is assumed that the RS code has a total of N symbols. At this time, the decoded RS code may include K data symbols and P parity check symbols. The assumed RS code can correct up to P / 2 errors. That is, when N = K + P and one symbol is m bits, the maximum code length of the symbol unit is 2 m -1. Here, N, K, and P are positive integers.

[0080] Reference Figure 4A , the RS code decoder 400 may include a syndrome generation circuit 410, an error location polynomial generation circuit 420, an error location determination circuit 430, an error correction circuit 440, and a data buffer 450.

[0081] The RS code decoder 400 can receive the read codeword RCW and correct the errors included in the read codeword RCW. The RS code decoder 400 can output the error-corrected codeword CCW.

[0082] The data may be the read codeword RCW from the memory cell array. The read codeword RCW may be an N-dimensional vector R0, R1, …, R N-1 . The coefficients of the received polynomial R(x) can be obtained from the N-dimensional vector R0, R1, …, R N-1 of the read codeword RCW. Here, the received polynomial R(x) may be an Nth-order polynomial in x and can be determined according to the N-dimensional vector R0, R1, …, R N-1 of the read codeword RCW to determine the coefficients of the received polynomial

[0083] The error-corrected codeword CCW may be the same as the N-dimensional vector c0, c1, …, c Figure 2 obtained from the coefficients of the code polynomial c(x) described in the reference N-1 .

[0084] Here, the code polynomial c(x) may be an Nth-order polynomial in x without a constant term, and the error-corrected codeword CCW may be the same as the N-dimensional vector c0, c1, …, c obtained from the code polynomial N-1 .

[0085] In addition, the error polynomial E(x) may be defined as the difference between the received polynomial R(x) and the code polynomial c(x). That is, when x is a power of m which is a primitive element of the Galois field GF(2 ), when an error occurs, there may be an error polynomial , and when there is no error, may be satisfied.

[0086] The syndrome generation circuit 410 can receive the read codeword RCW and calculate a plurality of syndromes. The syndrome generation circuit 410 can identify whether there is an error in the read codeword RCW according to the calculated syndrome values.

[0087] For example, the values of the first to P-th syndromes can be calculated as in Equation 2 below.

[0088] [Equation 2]

[0089]

[0090] Here, Sp represents the value of the P-th syndrome, and represents the primitive element of the Galois field GF(2 m ).

[0091] That is to say, the values of the first to P-th syndromes can be calculated by substituting the P powers of into x in the received polynomial in turn. Here, when x is a power of m which is the primitive element of the Galois field GF(2 ), in the case of an error, there can be an error polynomial , and in the case of no error, can be satisfied.

[0092] When all the values of the first to P-th syndromes are 0, there may be no error in the read codeword RCW. When all the values of the first to P-th syndromes are not 0, the error may be in the read codeword RCW.

[0093] When all the values of the first to P-th syndromes are 0, the read codeword RCW temporarily stored in the data buffer 450 can be output to the outside of the RS code decoder 400 without separate error correction.

[0094] When all the values of the first to P-th syndromes are not 0, a plurality of syndromes can be sent to the error location polynomial generation circuit 420.

[0095] The error location polynomial generation circuit 420 can generate an error location polynomial for searching for the location of the error included in the read codeword RCW based on the plurality of syndromes.

[0096] The error locator polynomial generation circuit 420 may be referred to as a key equation solver. The error locator polynomial generation circuit 420 may generate an error locator polynomial by using the Berlekamp-Massey algorithm, the Peterson-Gorenstein-Zierler (PGZ) algorithm, the Step-By-Step (SBS) algorithm, the Euclidean algorithm, or the modified Euclidean algorithm . The error location can be obtained by taking the reciprocal of the roots of the error locator polynomial . In some embodiments, the error location can be obtained by taking the reciprocal of the roots of the error locator polynomial by using the chien search algorithm

[0097] The error location determination circuit 430 may calculate the error location based on the error locator polynomial and output flag signals e1, e2, …, e indicating the error location according to the calculation result N-1 . The error location determination circuit 430 may send the flag signals e1, e2, …, e indicating the error location to the error correction circuit 440 N-1 .

[0098] The error correction circuit 440 may correct the error of the read codeword RCW received from the data buffer 450 based on the flag signals e1, e2, …, e indicating the error location N-1 and output the error-corrected codeword CCW

[0099] In some embodiments, the error correction circuit 440 may identify the symbols that have had errors among the multiple symbols included in the codeword based on the flag signals e1, e2, …, e indicating the error location N-1 and may calculate the error values of the symbols that have had errors by using the Forney algorithm or the like. The error correction circuit 440 may output the error-corrected codeword CCW based on the read codeword RCW, the error location, and the error value provided from the data buffer 450

[0100] The data buffer 450 may receive the read codeword RCW, temporarily store the read codeword RCW, and provide the read codeword RCW to the error correction circuit 440

[0101] In some embodiments, when the values of the flag signals e1, e2, …, e N-1 are all 0, the error correction circuit 440 may output the read codeword RCW received from the data buffer 450 as it is without separate correction

[0102] In some embodiments, when not all of the values of the flag signals e1, e2, …, e N-1 are 0, the error correction circuit 440 may correct the error of the read codeword RCW received from the data buffer 450 based on the error position and the error value, and output the error-corrected codeword CCW.

[0103] Refer to Figure 4A and Figure 4B , in operation S110, the RS code decoder 400 may receive the codeword RCW read from the memory cell array. The read codeword RCW may include a plurality of symbols. For example, the read codeword RCW may include N symbols, and the N symbols decoded by the RS code decoder 400 may include K data symbols and P parity check symbols.

[0104] In operation S120, the syndrome generation circuit 410 may calculate a plurality of syndromes of the read codeword RCW. The syndrome may be data indicating whether there is an error in the data. When all the values of the syndromes are 0, there may be no error in the data. When not all the values of the syndromes are 0, an error may be in the data.

[0105] In operation S130, the error position polynomial generation circuit 420 may determine the error position polynomial based on a plurality of syndromes, and the error position determination circuit 430 may obtain the error position. The error position may be obtained by taking the reciprocal of the roots of the error position polynomial . The error position determination circuit 430 may output the flag signals e1, e2, …, e N-1 indicating the error position.

[0106] In operation S140, the error correction circuit 440 may identify the symbols in which errors have occurred among the plurality of symbols included in the read codeword RCW based on the flag signals e1, e2, …, e N-1 indicating the error position, and may calculate the error values of the symbols in which errors have occurred by using the Forney algorithm or the like. The error correction circuit 440 may output the error-corrected codeword CCW based on the read codeword RCW provided by the data buffer 450, the error position, and the error value.

[0107] In addition, among operations S110 to S140, the RS code decoder 400 requires the most operations in operation S130. For example, when using the Berlekamp-Massey algorithm in operation S130, the RS code decoder 400 performs a predetermined number (e.g., the number P of parity check symbols) of repeated operations regardless of the number of errors that have actually occurred, and the amount of operations performed in each repeated operation is also large. In addition, when using the PGZ algorithm in operation S130, matrix inverse transformation and matrix multiplication are required, which have high complexity, and this complexity increases the time required for RS decoding.

[0108] According to some embodiments, in addition to the RS code decoder 400, the decoder 300 further includes an error correction device 310 that corrects errors in units of two consecutive symbols ( Figure 3 ), thereby reducing the time required for RS decoding. Therefore, the read latency can be improved.

[0109] Hereinafter, the error correction operation of the error correction device 310 will be described in detail.

[0110] Figure 5 is a block diagram showing Figure 3 an example of the error correction device 310 shown.

[0111] Referring to Figure 5 , the error correction device 500 may include a syndrome generation circuit 510, an error position determination circuit 520, an adjacent two-symbol error check circuit 530, an error value determination circuit 540, an error correction circuit 550, a re-syndrome generation circuit 560, and a data buffer 570.

[0112] The syndrome generation circuit 510 may receive data and output a first syndrome to a sixth syndrome for the data. Here, the first syndrome to the sixth syndrome may be calculated by substituting powers of the primitive element m of the Galois field GF(2 ) into the received polynomial R(x) based on the data. The exponents of the powers of each primitive element used to calculate the first syndrome to the third syndrome may increase sequentially, and the exponents of the powers of each primitive element used to calculate the fourth syndrome to the sixth syndrome may increase sequentially. For example, the exponents of the powers of each primitive element used to calculate the first syndrome to the third syndrome may increase by 1 sequentially, and the exponents of the powers of each primitive element used to calculate the fourth syndrome to the sixth syndrome may increase by 1 sequentially.

[0113] In addition, for example, the data may be a codeword RCW read from a memory cell array. The read codeword RCW may be an N-dimensional vector R0, R1,..., R N-1 . The N-dimensional vector R0, R1,..., R of the read codeword RCW can be used...N-1 Obtain the coefficients of the received polynomial R(x). Here, the received polynomial R(x) can be an Nth-order polynomial in x and can be determined according to the N-dimensional vector R0, R1, …, R of the read codeword RCW N-1 to determine the coefficients of the received polynomial . The syndrome generation circuit 510 can calculate the syndrome by substituting the powers of the primitive element m of the Galois field GF(2 ) into the received polynomial whose coefficients are determined based on the data .

[0114] Refer to Figure 5 , in some embodiments, the second syndrome S2 can be the same as the fourth syndrome S2, and the third syndrome S3 can be the same as the fifth syndrome S3. That is, the exponent of the power of each primitive element used to calculate the first syndrome S1, the second syndrome S2, the third syndrome S3, and the sixth syndrome S4 can increase sequentially.

[0115] For example, when the first syndrome S1 is , the second syndrome S2 can be , and the third syndrome S3 can be . In addition, when the fourth syndrome S2 is , the fifth syndrome S3 can be , and the sixth syndrome S4 can be .

[0116] However, the inventive concept is not limited thereto, and different from Figure 5 , the second syndrome can be different from the fourth syndrome, and the third syndrome can be different from the fifth syndrome.

[0117] The syndrome generation circuit 510 can provide the calculated syndrome to the error location determination circuit 520 and the error value determination circuit 540. Refer to Figure 5 , the syndrome generation circuit 510 can provide the first syndrome S1, the second syndrome S2, the third syndrome S3, the fourth syndrome S2, the fifth syndrome S3, and the sixth syndrome S4 to the error location determination circuit 520, and can provide the first syndrome S1 and the second syndrome S2 to the error value determination circuit 540.

[0118] The error location determination circuit 520 can determine the coefficients of the first error location polynomial based on the first syndrome S1, the second syndrome S2, and the third syndrome S3, and determine the coefficients of the second error location polynomial based on the fourth syndrome S2, the fifth syndrome S3, and the sixth syndrome S4. In addition, the error location determination circuit 520 can obtain the locations of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial.

[0119] Reference Figure 6A 、 Figure 6B and Figure 6C A method for obtaining the locations of errors included in the data in units of two consecutive symbols, which is performed by the error location determination circuit 520, will be described in detail.

[0120] Figure 6A is a block diagram showing an example of the Figure 5 error location determination circuit shown.

[0121] The error location determination circuit 520 may include a plurality of sub-error location determination circuits. The plurality of sub-error location determination circuits may receive the first syndrome to the sixth syndrome, and each of the plurality of sub-error location determination circuits may output an error flag signal indicating whether there is an error in two consecutive symbols. Here, each of the plurality of sub-error location determination circuits may match two non-overlapping consecutive symbols, and each of the plurality of sub-error location determination circuits may output an error flag signal indicating whether there is an error in the two matched symbols.

[0122] That is, the error location determination circuit 520 can determine in parallel whether there is an error in each of a plurality of groups including two non-overlapping consecutive symbols.

[0123] Reference Figure 6A , the error location determination circuit 520 may include a first sub-error location determination circuit 520-1 to a Qth sub-error location determination circuit 520-Q. Here, N represents the total number of symbols included in the read codeword RCW, and may be a positive integer and an even number. In addition, Q may be (N - 2) / 2.

[0124] The first sub-error location determination circuit 520-1 may receive the first syndrome S d 、the second syndrome S d+1 、the third syndrome S d+2 、the fourth syndrome S f 、the fifth syndrome S f+1 and the sixth syndrome S f+2 , and output a 0&1 error flag signal indicating whether there is an error in the 0th symbol and the first symbol . The second sub-error position determination circuit 520-2 can receive the first syndrome S d , the second syndrome S d+1 , the third syndrome S d+2 , the fourth syndrome S f , the fifth syndrome S f+1 and the sixth syndrome S f+2 , and can output a 2&3 error flag signal indicating whether there is an error in the second symbol and the third symbol . The Qth sub-error position determination circuit 520-Q can receive the first syndrome S d , the second syndrome S d+1 , the third syndrome S d+2 , the fourth syndrome S f , the fifth syndrome S f+1 and the sixth syndrome S f+2 , and can output an N-2&N-1 error flag signal indicating whether there is an error in the N-2th symbol and the N-1th symbol .

[0125] In some embodiments, when the error is in two consecutive symbols, each sub-error position determination circuit can output an error flag signal indicating whether there is an error in the two consecutive symbols, such that the value of the error flag signal is 1. When there is no error in the two consecutive symbols, each sub-error position determination circuit can output an error flag signal indicating whether there is an error in the two consecutive symbols, such that the value of the error flag signal is 0.

[0126] For example, when there is no error in the 0th symbol and the first symbol, the first sub-error position determination circuit 520-1 can output a 0&1 error flag signal indicating 0 . In addition, when there is an error in the second symbol and the third symbol, the second sub-error position determination circuit 520-2 can output a 2&3 error flag signal indicating 1 .

[0127] Figure 6B is a block diagram showing an example of the sub-error position determination circuit shown Figure 6A . Figure 6B is a block diagram showing the i / 2+1th sub-error position determination circuit for determining whether there is an error in the ith symbol and the (i+1)th symbol. Here, i can be one of 0, 2… and / or N-2. For convenience, the i / 2+1th sub-error position determination circuit is referred to as the i&i+1 sub-error position determination circuit 520-i&i+1.

[0128] The first sub-error position determination circuit 520-1 to the Qth sub-error position determination circuit 520-Q can have the same configuration. Therefore, hereinafter, it is described Figure 6BConfiguration and operation of the i&i+1 sub-error position determination circuit 520-i&i+1 for determining whether the i-th symbol and the (i+1)-th symbol include errors as shown.

[0129] The i&i+1 sub-error position determination circuit 520-i&i+1 can receive the first syndrome S d , the second syndrome S d+1 , the third syndrome S d+2 , the fourth syndrome S f , the fifth syndrome S f+1 and the sixth syndrome S f+2 , and can output an i&i+1 error flag signal indicating whether there is an error in the i-th symbol and the (i+1)-th symbol .

[0130] The i&i+1 sub-error position determination circuit 520-i&i+1 can include an error position polynomial generation circuit 521 and an error position checker circuit 523.

[0131] The error position polynomial generation circuit 521 can receive the first syndrome S d , the second syndrome S d+1 , the third syndrome S d+2 , the fourth syndrome S f , the fifth syndrome S f+1 and the sixth syndrome S f+2 . In addition, the error position polynomial generation circuit 521 can determine the coefficients of the first error position polynomial based on the first syndrome S d , the second syndrome S d+1 and the third syndrome S d+2 . In addition, the error position polynomial generation circuit 521 can determine the coefficients of the second error position polynomial based on the fourth syndrome S f , the fifth syndrome S f+1 and the sixth syndrome S f+2 .

[0132] In some embodiments, the error position polynomial generation circuit 521 can determine the coefficients of the first error position polynomial based on Equation 3 below. In addition, the error position polynomial generation circuit 521 can determine the coefficients of the second error position polynomial based on Equation 4 below.

[0133] [Equation 3]

[0134]

[0135] [Equation 4]

[0136]

[0137] Here, represents a primitive element of the Galois field GF(2 m ), represents a first error location polynomial, represents a second error location polynomial, , , respectively represent a first syndrome to a third syndrome, , and respectively represent a fourth syndrome to a sixth syndrome, and d and f are positive integers and may be different from each other.

[0138] In addition, in some embodiments, the second syndrome may be the same as the fourth syndrome, the third syndrome may be the same as the fifth syndrome, and the exponents of the powers of each primitive element used to calculate the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome may increase by 1 in sequence.

[0139] At this time, the error location polynomial generation circuit 521 may determine the coefficients of the first error location polynomial based on Equation 5 below. In addition, the error location polynomial generation circuit 521 may determine the coefficients of the second error location polynomial based on Equation 6 below. For example, d may be 1, and f may be 2.

[0140] [Equation 5]

[0141]

[0142] [Equation 6]

[0143]

[0144] Here, may represent a primitive element of the Galois field GF(2 m ), may represent a first error location polynomial, may represent a second error location polynomial, may represent a first syndrome, may represent a second syndrome, may represent a third syndrome, and may represent a sixth syndrome.

[0145] For Equation 5 and Equation 6, assuming that the error is included in the i-th symbol and the (i + 1)-th symbol as consecutive symbols, the error value of the i-th symbol is defined as , and the error value of the (i + 1)-th symbol is defined as .

[0146] In this case, the first syndrome S1 satisfies , the second syndrome S2 satisfies , and the third syndrome S3 satisfies . When using the first syndrome S1, the second syndrome S2, and the third syndrome S3 to erase the error value of the i-th symbol and the error value of the (i + 1)-th symbol , the following can be derived . Similarly, when using the second syndrome S2, the third syndrome S3, and the sixth syndrome S4 to erase the error value of the i-th symbol and the error value of the (i + 1)-th symbol , the following can be derived .

[0147] Since and are quadratic equations for , when there exists a and that satisfies both (i.e., a common root), errors may be included in the i-th symbol and the (i + 1)-th symbol.

[0148] The error location polynomial generation circuit 521 can provide a first error location polynomial and a second error location polynomial to the error location checker circuit 523.

[0149] The error location checker circuit 523 can output an i&i + 1 error flag signal indicating whether there are errors in the i-th symbol and the (i + 1)-th symbol based on the first error location polynomial and the second error location polynomial .

[0150] In some embodiments, when there exists an exponent that satisfies and , the error location checker circuit 523 can output an i&i + 1 error flag signal indicating that "errors are included in the i-th symbol and the (i + 1)-th symbol". In addition, when there is no exponent that satisfies and , the error location checker circuit 523 can output an i&i + 1 error flag signal indicating that "there are no errors in the i-th symbol and the (i + 1)-th symbol".

[0151] For example, when there exists an exponent that satisfies and When there is, the error position checker circuit 523 can output an error flag signal indicating 1 . In addition, when there is no exponent and satisfying , the error position checker circuit 523 can output an i&i+1 error flag signal indicating 0 .

[0152] In some embodiments, the first error position polynomial and the second error position polynomial can be polynomials related to the powers of the primitive elements of the Galois field having exponents , and when there is an exponent for which the value of the first error position polynomial and the value of the second error position polynomial are determined to be 0 , the error position determination circuit 520 can output an i&i+1 error flag signal indicating that "the error is included in the i-th symbol and the (i + 1)-th symbol" .

[0153] Figure 6C is a block diagram showing an example of the error position polynomial generation circuit shown in Figure 6B . Figure 6C is a block diagram showing the error position polynomial generation circuit 521 included in the i&i+1 sub-error position determination circuit 520-i&i+1. Here, i can be one of 0, 2, …, and / or N - 2

[0154] In some embodiments, in the Galois field GF(2 ) defined by the primitive polynomial 8 , can be satisfied. Here, m above can be 8. That is, in the finite elements GF(2 8 ) of size 2 8 , there can be GF(2 8 ) = {0, 1, , …, }. The 256 symbols, which are the numbers of all cases that can be represented by an 8-bit symbol, and all 256 elements of GF(2 8 ) can have a one-to-one mapping relationship

[0155] The error position polynomial generation circuits included in the first sub-error position determination circuit 520-1 to the Q-th sub-error position determination circuit 520-Q can have the same configuration. Therefore, hereinafter, Figure 6CThe configuration and operation of the error location polynomial generation circuit 521 included in the i&i+1 sub-error location determination circuit 520-i&i+1 that determines whether the i-th symbol and the i+1-th symbol include errors as shown are described.

[0156] In this case, the second syndrome may be the same as the fourth syndrome, the third syndrome may be the same as the fifth syndrome, and the exponents of the powers of each primitive element used to calculate the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome may increase by 1 in sequence.

[0157] Refer to Figure 6C , the error location polynomial generation circuit 521 may include a first multiplier 61-1, a second multiplier 61-2, a third multiplier 61-3, and a fourth multiplier 61-4, and a first adder 63-1, a second adder 63-2, a third adder 63-3, and a fourth adder 63-4.

[0158] As described above, since there is , the first error location polynomial can be expressed as , and the second error location polynomial can be expressed as .

[0159] Therefore, as Figure 6C shown, the error location polynomial generation circuit 521 may receive the first syndrome S1, the second syndrome S2, the third syndrome S3, and the sixth syndrome S4, and may output the first error location polynomial and the second error location polynomial by using the first multiplier to the fourth multiplier 61-1, 61-2, 61-3, 61-4 and the first adder 63-1, the second adder 63-2, the third adder 63-3, and the fourth adder 63-4.

[0160] For example, when i = 2, the error location polynomial generation circuit 521 included in the 2&3 sub-error location determination circuit corresponding to the second sub-error location determination circuit 520-2 as Figure 6A shown may output the first error location polynomial and the second error location polynomial to the error location checker circuit 523 included in the 2&3 sub-error location determination circuit.

[0161] When the value of the first error location polynomial and the value of the second error location polynomial are 0, the error location checker circuit 523 may output an error flag signal indicating that "there is an error in the second symbol and the third symbol".

[0162] When the value of the first error location polynomial and the value of the second error location polynomial are not 0, the error location checker circuit 523 can output an error flag signal indicating that "there is no error in the second symbol and the third symbol" .

[0163] Return reference Figure 5 , according to the reference Figure 6A 、 Figure 6B and Figure 6C described in some embodiments, the error location determination circuit 520 can obtain the location of the error included in the data in units of two consecutive symbols.

[0164] That is to say, the error location determination circuit 520 can output an error flag signal indicating whether two consecutive symbols include an error, and the error location determination circuit 520 can output an error flag signal for each of multiple groups including two non-overlapping consecutive symbols.

[0165] Reference Figure 5 , the error location determination circuit 520 can output 0&1 error flag signals to N-2&N-1 error flag signals . The error location determination circuit 520 can provide 0&1 error flag signals to N-2&N-1 error flag signals to the adjacent two-symbol error checking circuit 530.

[0166] The adjacent two-symbol error checking circuit 530 can receive multiple error flag signals and check whether an error has occurred in two actual consecutive symbols.

[0167] When an error occurs in two actual consecutive symbols, only one of the 0&1 error flag signals to N-2&N-1 error flag signals needs to indicate 1, and the remaining error flag signals need to indicate 0.

[0168] That is to say, when all error flag signals indicate 0, it can correspond to the situation where the error location determination circuit 520 may not find the location of the error. When an error is included in the data but does not occur in two consecutive symbols, all error flag signals can be 0.

[0169] When the 0&1 error flag signals to N-2&N-1 error flag signals When all the indications are 0, the adjacent two-symbol error checking circuit 530 can output a failure signal FAIL to the error correction circuit 550 and the recheck sub-generation circuit 560 to terminate the decoding operation. At this time, the error correction circuit 550 and the recheck sub-generation circuit 560 can terminate the decoding operation in response to the failure signal FAIL.

[0170] The error value determination circuit 540 can pre-calculate the possible error values of the data in units of two consecutive symbols based on two syndromes. In addition, the error value determination circuit 540 can provide the pre-calculated error values to the error correction circuit 550.

[0171] Reference Figure 5 , the error value determination circuit 540 can pre-calculate the possible error values of the data in units of two consecutive symbols based on the first syndrome S1 and the second syndrome S2, and can provide the 0th error value signal indicating the pre-calculated error values to the error correction circuit 550 to the (N - 1)th error value signal .

[0172] Refer to Figure 7A and Figure 7B for a detailed description of the method of pre-calculating the possible error values of the data in units of two consecutive symbols performed by the error value determination circuit 540.

[0173] Figure 7A is a block diagram showing an example of the Figure 5 shown error value determination circuit. Figure 7B is a block diagram showing an example of the Figure 7A shown error value determination circuit.

[0174] The error value determination circuit 540 can include a plurality of sub-error value determination circuits. Under the assumption that an error is included in consecutive symbols, the error value determination circuit 540 can output two error values in units of two consecutive symbols by using two syndromes.

[0175] Each of the plurality of sub-error value determination circuits can receive the first syndrome and the second syndrome, and can output two error value signals indicating the error values of two consecutive symbols. Here, each of the plurality of sub-error value determination circuits can match two non-overlapping consecutive symbols, and can output two error value signals indicating the error values of the two matched symbols.

[0176] That is, assuming that an error has occurred in each of a plurality of groups including two non-overlapping consecutive symbols, the error value determination circuit 540 can determine the error values in parallel.

[0177] Reference Figure 7A, the error value determination circuit 540 may include a first sub-error value determination circuit 540-1 to a Qth sub-error value determination circuit 540-Q. Here, N represents the total number of symbols included in the read codeword RCW, and may be a positive integer and an even number. In addition, Q may be (N - 2) / 2.

[0178] The first sub-error value determination circuit 540-1 may receive a first syndrome S1 and a second syndrome S2, and output a 0th error value signal indicating the magnitude of the error of the 0th symbol and a first error value signal indicating the magnitude of the error of the first symbol . The second sub-error value determination circuit 540-2 may receive the first syndrome S1 and the second syndrome S2, and output a second error value signal indicating the magnitude of the error of the second symbol and a third error value signal indicating the magnitude of the error of the third symbol . The Qth sub-error value determination circuit 540-Q may receive the first syndrome S1 and the second syndrome S2, and output an (N - 2)th error value signal indicating the magnitude of the error of the (N - 2)th symbol and an (N - 1)th error value signal indicating the magnitude of the error of the (N - 1)th symbol .

[0179] The (i / 2 + 1)th sub-error value determination circuit that outputs an ith error value signal indicating the magnitude of the error of the ith symbol and an (i + 1)th error value signal indicating the magnitude of the error of the (i + 1)th symbol will be described . Here, i may be one of 0, 2,..., and / or N - 2. For convenience, the (i / 2 + 1)th sub-error value determination circuit is referred to as the i&i+1 sub-error value determination circuit 540-i&i+1.

[0180] Assuming that errors are included in the ith symbol and the (i + 1)th symbol as consecutive symbols, the error value of the ith symbol is defined as , and the error value of the (i + 1)th symbol is defined as .

[0181] When calculating the first syndrome S1 and the second syndrome S2 by substituting and into x in the received polynomial , the following Equation 7 is satisfied.

[0182] [Equation 7]

[0183]

[0184] Here, represents the Galois field GF(2 mThe original element of (), S1 represents the first syndrome, and S2 represents the second syndrome. represents the error value of the i-th symbol, and represents the error value of the (i + 1)-th symbol.

[0185] That is to say, because the first syndrome S1 satisfies , the sum of the code polynomial and the error polynomial satisfies , and the right curly brace term satisfies 0, so Equation 7 can be derived. Similarly, because the second syndrome S2 satisfies , the sum of the code polynomial and the error polynomial satisfies , and the right curly brace term satisfies 0, so Equation 7 can be derived.

[0186] The error value of the i-th symbol in Equation 7 and the error value of the (i + 1)-th symbol can be summarized as the following Equation 8.

[0187] [Equation 8]

[0188]

[0189] Here, represents the primitive element of the Galois field GF(2 m ), S1 represents the first syndrome, S2 represents the second syndrome, represents the error value of the i-th symbol, and represents the error value of the (i + 1)-th symbol.

[0190] That is to say, the i&i + 1 sub-error value determination circuit 540-i&i + 1 can output the i-th error value signal indicating the magnitude of the error of the i-th symbol and the (i + 1)-th error value signal indicating the magnitude of the error of the (i + 1)-th symbol based on the first syndrome S1, the second syndrome S2, and the above Equation 8.

[0191] Figure 7B is a block diagram showing the i&i + 1 sub-error value determination circuit 540-i&i + 1. Here, i can be one of 0, 2,... and / or N - 2. The first sub-error value determination circuit 540-1 to the Q-th sub-error value determination circuit 540-Q can have the same configuration. Therefore, hereinafter, the Figure 7B shown configuration and operation of the i&i + 1 sub-error value determination circuit 540-i&i + 1 that outputs the error values of the i-th symbol and the (i + 1)-th symbol will be described.

[0192] Refer to Figure 7B, the i&i+1 sub-error value determination circuit 540-i&i+1 may include a first multiplier 71-1, a second multiplier 71-2, a third multiplier 71-3, a fourth multiplier 71-4, a first adder 73-1, and a second adder 73-2.

[0193] The i&i+1 sub-error value determination circuit 540-i&i+1 may receive a first syndrome S1 and a second syndrome S2, and output an i-th error value signal indicating the magnitude of the error of the i-th symbol and an (i+1)-th error value signal indicating the magnitude of the error of the (i+1)-th symbol by using the first multiplier 71-1, the second multiplier 71-2, the third multiplier 71-3, the fourth multiplier 71-4, the first adder 73-1, and the second adder 73-2. and an (i+1)-th error value signal indicating the magnitude of the error of the (i+1)-th symbol , as Figure 7B shown.

[0194] For example, when i = 2, the 2&3 sub-error value determination circuit corresponding to the second sub-error value determination circuit 540-2 shown in Figure 7A may output a second error value signal indicating the second symbol of and a third error value signal indicating the third symbol of and indicating . .

[0195] Return reference Figure 5 , the error correction circuit 550 may correct the error included in the data based on the position and value of the error.

[0196] Reference Figure 5 , the error position determination circuit 520 may provide a 0&1 error flag signal to an (N-2)&(N-1) error flag signal to the error correction circuit 550. The error value determination circuit 540 may provide a 0-th error value signal to an (N-1)-th error value signal to the error correction circuit 550.

[0197] In some embodiments, the error correction circuit 550 may correct the error included in the data based on the position and value of the error, as shown in Equation 9 below.

[0198] [Equation 9]

[0199]

[0200] Here, represents the i-th symbol of the error-corrected codeword CCW, represents the (i+1)-th symbol of the error-corrected codeword CCW, represents the i-th symbol of the read codeword RCW, represents the (i + 1)-th symbol of the read codeword RCW, represents the i&i + 1 error flag signal, represents the error value of the i-th symbol, and represents the error value of the (i + 1)-th symbol.

[0201] That is to say, the error correction circuit 550 can correct the i-th symbol and the (i + 1)-th symbol of the read codeword RCW according to the value of the i&i + 1 error flag signal and output the i-th symbol and the (i + 1)-th symbol of the read codeword RCW as the i-th symbol and the (i + 1)-th symbol of the error-corrected codeword CCW.

[0202] When the value of the i&i + 1 error flag signal is 0, the error correction circuit 550 can output the i-th symbol and the (i + 1)-th symbol of the read codeword RCW as the i-th symbol and the (i + 1)-th symbol of the error-corrected codeword CCW without correction.

[0203] When the value of the i&i + 1 error flag signal is 1, by adding the error value of the i-th symbol to the i-th symbol of the read codeword RCW and adding the error value of the (i + 1)-th symbol to the (i + 1)-th symbol of the read codeword RCW, the error correction circuit 550 can output the i-th symbol and the (i + 1)-th symbol of the error-corrected codeword CCW.

[0204] The error correction circuit 550 can output the error-corrected codeword CCW based on the 0&1 error flag signal to the N - 2&N - 1 error flag signals , the 0-th error value signal to the N - 1-th error value signal and the read codeword RCW.

[0205] Here, the data buffer 570 can receive the read codeword RCW, temporarily store the read codeword RCW, and provide the read codeword RCW to the error correction circuit 550.

[0206] That is to say, the error correction circuit 550 can correct the error of the read codeword RCW received from the data buffer 570 based on the 0&1 error flag signal to the N - 2&N - 1 error flag signals and the 0-th error value signal to the N - 1-th error value signal and output the error-corrected codeword CCW.

[0207] The error correction circuit 550 can provide the error-corrected codeword CCW to the re-verification sub-generation circuit 560.

[0208] The re-check syndrome generation circuit 560 can receive the error-corrected codeword CCW, and re-calculate the syndrome of the error-corrected codeword CCW to determine whether the error correction operation is successful. Equation 2 above can be used to re-calculate the syndrome. For example, when the syndrome is , the re-check syndrome generation circuit 560 can determine that the error correction operation is successful.

[0209] When the error correction operation is successful, the re-check syndrome generation circuit 560 can output the error-corrected codeword CCW to the outside. In addition, the re-check syndrome generation circuit 560 can output a signal TERMINATION indicating the termination of the error correction operation of the RS code decoder 320 ( Figure 3 ) to the RS code decoder 320 ( Figure 3 ).

[0210] Figure 8 is a flowchart showing an error correction method of a decoder according to Figure 3 shown. Hereinafter, with reference to Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A and Figure 7B will be described Figure 8 , and its redundant description will be omitted. The decoder 300 can include an error correction device 310 and an RS code decoder 320.

[0211] Referring to Figure 8 , in operation S210, the error correction device 310 can receive the data read from the storage cell array and calculate the first to sixth syndromes. Here, the error correction device 310 and the RS code decoder 320 can start the error correction operation simultaneously. In addition, the first to sixth syndromes can be calculated by substituting the powers of the primitive element m of the Galois field GF(2 ) into the received polynomial R(x) based on the data. The exponents of the powers of each primitive element used to calculate the first to third syndromes can increase sequentially, and the exponents of the powers of each primitive element used to calculate the fourth to sixth syndromes can increase sequentially. For example, the exponents of the powers of each primitive element used to calculate the first to third syndromes can increase by 1 sequentially, and the exponents of the powers of each primitive element used to calculate the fourth to sixth syndromes can increase by 1 sequentially.

[0212] Operations S220 and S230 can start simultaneously and are not limited to the Figure 8 shown precedence relationship.

[0213] In operation S220, the error correction device 310 may determine the coefficients of the first error locator polynomial based on the first to third syndromes, may determine the coefficients of the second error locator polynomial based on the fourth to sixth syndromes, and may obtain the positions of the errors included in the data in units of two consecutive symbols based on the first error locator polynomial and the second error locator polynomial.

[0214] In operation S230, the error correction device 310 may pre-calculate the values of the errors that the data may have in units of two consecutive symbols based on the first and second syndromes.

[0215] In operation S240, the error correction device 310 may correct the errors included in the data based on the positions and values of the errors.

[0216] In operation S250, the error correction device 310 may re-calculate multiple syndromes of the error-corrected data to determine whether the error correction operation is successful, and when the error correction operation is successful, may output a signal TERMINATION indicating the termination of the error correction operation of the RS code decoder 320.

[0217] Figure 9 shows Figure 2 a block diagram of another example of the decoder shown.

[0218] Referring to Figure 9 , the decoder 600 may include an error correction device 610 and an RS code decoder 620. The error correction device 610 and the RS code decoder 620 may respectively correspond to the error correction device 310 and the RS code decoder 320 described in Figure 3 and redundant descriptions thereof will be omitted.

[0219] Different from the error correction device 310 and the RS code decoder 320 that perform error correction operations in parallel described in Figure 3 , the error correction operation of the RS code decoder 620 may be performed only when the error correction operation of the error correction device 610 fails.

[0220] That is, when the error correction operation of the error correction device 610 fails, the error correction operation of the RS code decoder 620 may start.

[0221] Referring to Figure 9 , when the error correction operation of the error correction device 610 fails, the error correction device 610 may output a signal START indicating the start of the error correction operation of the RS code decoder 620 to the RS code decoder 620.

[0222] That is, when the error correction operation of the error correction device 610 is successful, the corrected data DATA' can be output by the error correction device 610, and when the error correction operation of the error correction device 610 fails, the corrected data DATA' can be output by the RS code decoder 620.

[0223] Figure 10 shows Figure 9 a block diagram of an example of the error correction device shown.

[0224] Refer to Figure 10 , the error correction device 700 may include a syndrome generation circuit 710, an error position determination circuit 720, an adjacent two-symbol error check circuit 730, an error value determination circuit 740, an error correction circuit 750, a re-syndrome generation circuit 760, and a data buffer 770.

[0225] The syndrome generation circuit 710, the error position determination circuit 720, the adjacent two-symbol error check circuit 730, the error value determination circuit 740, the error correction circuit 750, and the data buffer 770 may respectively correspond to the syndrome generation circuit 510, the error position determination circuit 520, the adjacent two-symbol error check circuit 530, the error value determination circuit 540, the error correction circuit 550, and the data buffer 570 described in Figure 5 the reference, and redundant descriptions thereof will be omitted.

[0226] That is, Figure 5 the re-syndrome generation circuit 560 shown and Figure 10 the operations of the re-syndrome generation circuit 760 shown are different from each other, and therefore, the re-syndrome generation circuit 760 will be described.

[0227] The re-syndrome generation circuit 760 may receive the error-corrected codeword CCW and re-calculate the syndrome of the error-corrected codeword CCW to determine whether the error correction operation is successful. The above equation 2 can be used to re-calculate the syndrome. For example, when the syndrome is , the re-syndrome generation circuit 760 may determine that the error correction operation is successful. When the syndrome is not , the re-syndrome generation circuit 760 may determine that the error correction operation fails. In addition, when the re-syndrome generation circuit 760 receives the failure signal FAIL from the adjacent two-symbol error check circuit 730, the re-syndrome generation circuit 760 may determine that the error correction operation fails.

[0228] When the error correction operation is successful, the re-syndrome generation circuit 560 may output the error-corrected codeword CCW to the outside.

[0229] When the error correction operation fails, the re-syndrome generation circuit 560 may output to the RS code decoder 620 ( Figure 9) Outputs a signal START indicating the start of the error correction operation of the RS code decoder 620 ( Figure 9 )

[0230] Figure 11 Is a flowchart showing the error correction method of the decoder according to Figure 9 shown. Hereinafter, reference will be made to Figures 9 to 10 to describe Figure 11 , and its redundant description will be omitted. The decoder 600 may include an error correction device 610 and an RS code decoder 620.

[0231] Referring to Figure 11 , in operation S310, the error correction device 610 may receive data read from the storage cell array and calculate the first to sixth syndromes. In addition, the first to sixth syndromes may be calculated by substituting the powers of the primitive element m of the Galois field GF(2 ) into the received polynomial R(x) based on the data. The exponents of the powers of each primitive element used to calculate the first to third syndromes may increase sequentially, and the exponents of the powers of each primitive element used to calculate the fourth to sixth syndromes may increase sequentially. For example, the exponents of the powers of each primitive element used to calculate the first to third syndromes may increase by 1 sequentially, and the exponents of the powers of each primitive element used to calculate the fourth to sixth syndromes may increase by 1 sequentially.

[0232] Operations S320 and S330 may start simultaneously and are not limited to Figure 11 shown precedence relationship.

[0233] In operation S320, the error correction device 610 may determine the coefficients of the first error location polynomial based on the first to third syndromes, determine the coefficients of the second error location polynomial based on the fourth to sixth syndromes, and obtain the positions of the errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial.

[0234] In operation S330, the error correction device 610 may pre-calculate the possible error values of the data in units of two consecutive symbols based on the first and second syndromes.

[0235] In operation S340, the error correction device 610 may correct the errors included in the data based on the positions and values of the errors.

[0236] In operation S350, the error correction device 610 may re-calculate the syndromes of the error-corrected data to determine whether the error correction operation is successful, and when the error correction operation fails, may output a signal START indicating the start of the error correction operation of the RS code decoder 620.

[0237] Here, the RS code decoder 620 can start an error correction operation in response to a signal START indicating the start of the error correction operation.

[0238] Figure 12 is a diagram showing a storage device according to some embodiments.

[0239] Reference Figure 12 , the storage device 900 may include control logic 910, a refresh address generator 915, an address buffer 920, bank control logic 930, a row address multiplexer 940, a column address (CA) latch 950, a row decoder, a memory cell array, a sense amplifier unit, an input / output (I / O) strobe circuit 990, a data I / O buffer 995, and an ECC engine 1000.

[0240] The memory cell array may include a first bank array 980a, a second bank array 980b, a third bank array 980c, and a fourth bank array 980d. The row decoder may include a first bank row decoder 960a, a second bank row decoder 960b, a third bank row decoder 960c, and a fourth bank row decoder 960d respectively connected to the first bank array 980a, the second bank array 980b, the third bank array 980c, and the fourth bank array 980d. The column decoder may include a first bank column decoder 970a, a second bank column decoder 970b, a third bank column decoder 970c, and a fourth bank column decoder 970d respectively connected to the first bank array 980a, the second bank array 980b, the third bank array 980c, and the fourth bank array 980d. The sense amplifier unit may include a first bank sense amplifier 985a, a second bank sense amplifier 985b, a third bank sense amplifier 985c, and a fourth bank sense amplifier 985d respectively connected to the first bank array 980a, the second bank array 980b, the third bank array 980c, and the fourth bank array 980d. The first bank array 980a, the second bank array 980b, the third bank array 980c, and the fourth bank array 980d, the first bank row decoder 960a, the second bank row decoder 960b, the third bank row decoder 960c, and the fourth bank row decoder 960d, the first bank column decoder 970a, the second bank column decoder 970b, the third bank column decoder 970c, and the fourth bank column decoder 970d, and the first bank sense amplifier 985a, the second bank sense amplifier 985b, the third bank sense amplifier 985c, and the fourth bank sense amplifier 985d may respectively constitute a first bank, a second bank, a third bank, and a fourth bank. Figure 12FIG. 0 illustrates an example of a memory device 900 including four banks, but according to some embodiments, the memory device 900 may include any number of banks.

[0241] In addition, according to some embodiments, the memory device 900 may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR), a graphics double data rate (GDDR) SDRAM, or a Rambus dynamic random access memory (RDRAM), or any volatile memory device that requires a refresh operation.

[0242] Control logic 910 may control the operation of the memory device 900. For example, control logic 910 may generate control signals for the memory device 900 to perform a write operation or a read operation. Control logic 910 may include a command decoder 911 that decodes a command CMD received from a memory controller, and a mode register 912 that sets an operation mode of the memory device 900. For example, command decoder 911 may decode a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, and a chip select signal / CS to generate control signals corresponding to the command CMD.

[0243] Control logic 910 may also receive a clock CLK and a clock enable signal CKE for driving the memory device 900 in a synchronous manner. Control logic 910 may control a refresh address generator 915 to perform an auto-refresh operation in response to a refresh command, or control the refresh address generator 915 to perform a self-refresh operation in response to a self-refresh input command.

[0244] The refresh address generator 915 may generate a refresh address REF_ADDR corresponding to a row of memory cells to be refreshed. The refresh address generator 915 may generate the refresh address REF_ADDR at a refresh rate with a period longer than a refresh period defined in standard or conventional parameters of the memory device 900. Accordingly, the refresh current and refresh power of the memory device 900 may be reduced.

[0245] An address buffer 920 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller. In addition, the address buffer 920 may provide the received bank address BANK_ADDR to bank control logic 930, provide the received row address ROW_ADDR to a row address multiplexer 940, and provide the received column address COL_ADDR to a column address latch 950.

[0246] The bank control logic 930 may generate bank control signals in response to a bank address BANK_ADDR. In response to the bank control signals, the bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 960a, the second bank row decoder 960b, the third bank row decoder 960c, and the fourth bank row decoder 960d may be activated, and the bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 970a, the second bank column decoder 970b, the third bank column decoder 970c, and the fourth bank column decoder 970d may be activated.

[0247] The bank control logic 930 may generate bank group control signals in response to determining the bank address BANK_ADDR of a bank group. In response to the bank group control signals, the row decoder of the bank group corresponding to the bank address BANK_ADDR among the first bank row decoder 960a, the second bank row decoder 960b, the third bank row decoder 960c, and the fourth bank row decoder 960d may be activated, and the column decoder of the bank group corresponding to the bank address BANK_ADDR among the first bank column decoder 970a, the second bank column decoder 970b, the third bank column decoder 970c, and the fourth bank column decoder 970d may be activated.

[0248] The row address multiplexer 940 may receive a row address ROW_ADDR from the address buffer 920 and a refresh row address REF_ADDR from the refresh address generator 915. The row address multiplexer 940 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR. The row address ROW_ADDR output from the row address multiplexer 940 may be applied to each of the first bank row decoder 960a, the second bank row decoder 960b, the third bank row decoder 960c, and the fourth bank row decoder 960d.

[0249] The bank row decoder among the first bank row decoder 960a, the second bank row decoder 960b, the third bank row decoder 960c, and the fourth bank row decoder 960d activated by the bank control logic 930 may decode the row address ROW_ADDR output from the row address multiplexer 940 to activate the word line corresponding to the row address ROW_ADDR. For example, the activated bank row decoder may apply a word line drive voltage to the word line corresponding to the row address ROW_ADDR.

[0250] The column address latch 950 may receive a column address COL_ADDR from the address buffer 920 and temporarily store the received column address COL_ADDR. The column address latch 950 may increment the received column address COL_ADDR in burst mode. The column address latch 950 may apply the temporarily stored or incremented column address COL_ADDR to each of the first to fourth bank column decoders 970a, 970b, 970c, and 970d.

[0251] Among the first to fourth bank column decoders 970a, 970b, 970c, and 970d, the bank column decoder activated by the bank control logic 930 may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output strobe circuit 990.

[0252] The input / output strobe circuit 990 may include input data masking logic, a read data latch for storing data output from the first to fourth bank arrays 980a, 980b, 980c, and 980d, a write driver for writing data to the first to fourth bank arrays 980a, 980b, 980c, and 980d, and a circuit for strobing input / output data.

[0253] Data DQ to be read from one of the first to fourth bank arrays 980a, 980b, 980c, and 980d may be sensed and amplified by a sense amplifier and stored in the read data latch. The data DQ stored in the read data latch may be provided to the memory controller through the data input / output buffer 995. Data DQ to be written to one of the first to fourth bank arrays 980a, 980b, 980c, and 980d may be provided to the data input / output buffer 995 from the memory controller. The data DQ provided to the data input / output buffer 995 may be written to a bank array through the write driver.

[0254] The ECC engine 1000 may correspond to Figures 1 to 11 the decoders 100, 300, and 600 shown. The ECC engine 1000 may include Figures 1 to 11 the error correction devices 310, 500, 610, or 700 shown. The ECC engine 1000 may reduce the required latency by performing error correction operations on two consecutive symbols.

[0255] In addition, Figure 12It is shown that the ECC engine 1000 is included in the storage device 900, but the ECC engine 1000 is not limited thereto and may be included in a memory controller.

[0256] Figure 13 is a diagram showing a system of an application storage device according to some embodiments.

[0257] Referring Figure 13 , Figure 13 The system 2000 of may be substantially a mobile system such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 13 The system 2000 of is not necessarily limited to a mobile system and may be a personal computer, a laptop computer, a server, a media player, or an automotive device such as navigation.

[0258] Referring Figure 13 , the system 2000 may include a main processor 2100, memories 2200a and 2200b, and storage devices 2300a and 2300b, and may also include one or more of the following: an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

[0259] The main processor 2100 may control the overall operation of the system 2000, and more specifically, the operations of other components included in the system 2000. The main processor 2100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0260] The main processor 2100 may include one or more CPU cores 2110, and may also include a controller 2120 for controlling the memories 2200a and 2200b and / or the storage devices 2300a and 2300b. According to some embodiments, the main processor 2100 may also include an accelerator 2130 as a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. Such an accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 2100.

[0261] Memories 2200a and 2200b can be used as the main storage devices of system 2000, may include volatile memories such as SRAM and / or DRAM, but may include non-volatile memories such as flash memory, PRAM, and / or RRAM. Memories 2200a and 2200b can be implemented in the same package as main processor 2100.

[0262] Storage devices 2300a and 2300b can be used as non-volatile storage devices that store data whether powered or not, and can have a relatively large storage capacity compared to memories 2200a and 2200b. Storage devices 2300a and 2300b can include storage controllers 2310a and 2310b and non-volatile memories (NVM) 2320a and 2320b that store data under the control of storage controllers 2310a and 2310b. NVM 2320a and 2320b can each include flash memory with a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but can include other types of NVM such as PRAM and / or RRAM.

[0263] Storage devices 2300a and 2300b can be included in system 2000 while being physically separated from main processor 2100, or can be implemented in the same package as main processor 2100. In addition, storage devices 2300a and 2300b can be in the form of, for example, solid state devices (SSDs) or memory cards so as to be detachably combined with other components of system 2000 through an interface such as connection interface 2480 to be described below. Such storage devices 2300a and 2300b can be devices that apply standard conventions such as universal flash storage (UFS), embedded multimedia card (eMMC), or non-volatile memory express (NVMe), but are not limited thereto.

[0264] Image capture device 2410 can capture still images or moving images, and can be a camera, a video camera, and / or a webcam.

[0265] User input device 2420 can receive various types of data input by a user of system 2000, and can be a touchpad, a keypad, a keyboard, a mouse, and / or a microphone.

[0266] Sensor 2430 can detect various types of physical quantities that can be obtained from the outside of system 2000 and convert the detected physical quantities into electrical signals. Sensor 2430 can be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0267] The communication device 2440 can send and receive signals with other devices external to the system 2000 according to various communication protocols. The communication device 2440 can be implemented by including an antenna, a transceiver, and / or a modem (MODEM).

[0268] The display 2450 and the speaker 2460 can be used as output devices for respectively outputting visual information and auditory information to the user of the system 2000.

[0269] The power supply device 2470 can appropriately convert the power supplied from a battery (not shown) and / or an external power supply embedded in or connected to the system 2000, and supply the power to each component of the system 2000.

[0270] The connection interface 2480 can provide a connection between the system 2000 and an external device that is connected to the system 2000 and capable of sending data to the system 2000 and receiving data from the system 1000. The connection interface 2480 can be implemented in various interface methods (e.g., Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), eMMC, UFS, Embedded UFS (eUFS), and Compact Flash (CF) card interface).

[0271] Figure 14 is a block diagram showing an example of applying a memory controller to an SSD system according to some embodiments.

[0272] Reference Figure 14 , the SSD system 3000 can include a host 3100 and an SSD 3200. The SSD 3200 can send signals to the host 3100 and receive signals from the host 3100 through a signal connector, and can receive power through a power connector. The SSD 3200 can include an SSD controller 3210, an auxiliary power supply 3220, and storage devices 3230, 3240, and 3250. At this time, the SSD 3200 can use the above reference Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8 ,Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 described embodiments are implemented.

[0273] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An error correction device, comprising: A syndrome generation circuit configured to: receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data, where the first syndrome, the second syndrome, the third syndrome, the fourth syndrome, the fifth syndrome, and the sixth syndrome for the data are determined by substituting powers of primitive elements of a Galois field into a received polynomial based on the data, wherein the corresponding exponents of the powers of the corresponding primitive elements used to determine the first syndrome, the second syndrome, and the third syndrome among the primitive elements increase sequentially, and wherein the corresponding exponents of the powers of the corresponding primitive elements used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome among the primitive elements increase sequentially; An error location determination circuit configured to: determine coefficients of a first error location polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine coefficients of a second error location polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain positions of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial; An error value determination circuit configured to: pre-determine values of the errors in units of two consecutive symbols based on the first syndrome and the second syndrome; and An error correction circuit configured to: correct errors included in the data based on the positions of the errors and the values of the errors.

2. The error correction device according to claim 1, Among them, wherein the error location determination circuit is configured to determine the first error location polynomial based on the following equation: ， and determine the second error location polynomial based on the following equation: ， wherein, represents the primitive element of the said Galois field, represents the said first error locator polynomial, represents the said second error locator polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, represents the said fourth syndrome, represents the said fifth syndrome, represents the said sixth syndrome, and d and f are positive integers and different from each other.

3. The error correction device according to claim 1, Among them, wherein the second syndrome is the same as the fourth syndrome, wherein the third syndrome is the same as the fifth syndrome, and wherein the corresponding exponents of the powers of the corresponding primitive elements used to determine the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome among the primitive elements increase sequentially.

4. The error correction device according to claim 3, Among them, wherein the error location determination circuit is configured to determine the first error location polynomial based on the following equation: ， and determine the second error location polynomial based on the following equation: ， Among them, represents the primitive element of the said Galois field, represents the said first error location polynomial, represents the said second error location polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, and represents the said sixth syndrome.

5. The error correction device according to claim 1, Among them, The first error location polynomial and the second error location polynomial are polynomials related to powers of a primitive element of a Galois field having exponents in corresponding exponents of said powers in powers of said primitive element of the Galois field, Among them, the error position determination circuit is configured to: when the original element with the exponent determines that the values of the first error position polynomial and the second error position polynomial are 0, output an error flag signal indicating an error in the i-th symbol and the (i + 1)-th symbol.

6. The error correction device according to claim 1, further comprising: A re-syndrome generation circuit configured to: receive the error-corrected data, determine a plurality of syndromes of the error-corrected data to determine whether an error correction operation is successful, and when the error correction operation is successful, output a signal indicating termination of the error correction operation of a Reed-Solomon (RS) code decoder.

7. The error correction device according to claim 1, further comprising: A syndrome generation circuit, configured to: receive the error-corrected data, determine a plurality of syndromes of the error-corrected data to determine whether an error correction operation is successful, and when the error correction operation fails, output a signal indicating the start of an error correction operation of a Reed-Solomon (RS) code decoder.

8. A memory system, comprising: A storage device including a plurality of storage units; And A memory controller configured to: correct data read from the storage device, Wherein the memory controller includes: An error correction device, wherein the error correction device includes: A syndrome generation circuit configured to: receive data and output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for the data, the first syndrome, the second syndrome, the third syndrome, the fourth syndrome, the fifth syndrome, and the sixth syndrome for the data being determined by substituting powers of a primitive element of a Galois field into a received polynomial based on the data, wherein corresponding exponents of the powers of the primitive element used to determine the first syndrome, the second syndrome, and the third syndrome increase sequentially, and wherein corresponding exponents of the powers of the primitive element used to determine the fourth syndrome, the fifth syndrome, and the sixth syndrome increase sequentially; An error position determination circuit configured to: determine coefficients of a first error position polynomial based on the first syndrome, the second syndrome, and the third syndrome, determine coefficients of a second error position polynomial based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain positions of errors included in the data in units of two consecutive symbols based on the first error position polynomial and the second error position polynomial; An error value determination circuit configured to: pre-determine values of the errors in units of two consecutive symbols based on the first syndrome and the second syndrome; and An error correction circuit configured to: correct errors included in the data based on the positions of the errors and the values of the errors.

9. The memory system according to claim 8, Among them, The error position determination circuit is configured to determine the first error position polynomial based on the following equation: ， And determine the second error position polynomial based on the following equation: ， Among them, represents the primitive element of the said Galois field, represents the said first error locator polynomial, represents the said second error locator polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, represents the said fourth syndrome, represents the said fifth syndrome, represents the said sixth syndrome, and d and f are positive integers and different from each other.

10. The memory system according to claim 8, Among them, The second syndrome is the same as the fourth syndrome, Wherein the third syndrome is the same as the fifth syndrome, and Wherein corresponding exponents of the powers of the primitive element used to determine the first syndrome, the second syndrome, the third syndrome, and the sixth syndrome increase sequentially.

11. The memory system according to claim 10, Among them, The error position determination circuit is configured to determine the first error position polynomial based on the following equation: ， And determine the second error position polynomial based on the following equation: ， Among them, represents the primitive element of the said Galois field, represents the said first error-location polynomial, represents the said second error-location polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, and represents the said sixth syndrome.

12. The memory system according to claim 8, Among them, The first error locator polynomial and the second error locator polynomial are polynomials related to powers of primitive elements in the Galois field with exponents in the corresponding exponents of the powers having the exponents of the powers of the primitive elements, Wherein, the error position determination circuit is configured to: when the original element with the exponent determines that the values of the first error position polynomial and the second error position polynomial are 0, output an error flag signal indicating an error in the i-th symbol and the (i + 1)-th symbol.

13. The memory system according to claim 8, Among them, The memory controller further includes a Reed-Solomon (RS) code decoder, and wherein, the error correction device further includes a re-parity check sub-generation circuit configured to: receive the error-corrected data, determine a plurality of parity checks of the error-corrected data to determine whether an error correction operation is successful, and when the error correction operation is successful, output a signal indicating termination of the error correction operation of the RS code decoder.

14. The memory system according to claim 8, Among them, The memory controller further includes a Reed-Solomon (RS) code decoder, and wherein, the error correction device further includes a re-parity check sub-generation circuit configured to: receive the error-corrected data, determine a plurality of parity checks of the error-corrected data to determine whether an error correction operation is successful, and when the error correction operation fails, output a signal indicating start of the error correction operation of the RS code decoder.

15. An error correction method, comprising: receiving data, and outputting a first parity check, a second parity check, a third parity check, a fourth parity check, a fifth parity check, and a sixth parity check for the data, the first parity check, the second parity check, the third parity check, the fourth parity check, the fifth parity check, and the sixth parity check for the data being determined by substituting powers of primitive elements in a Galois field into a received polynomial based on the data, wherein corresponding exponents of the powers of the primitive elements used to determine the first parity check, the second parity check, and the third parity check among the primitive elements increase sequentially, and wherein corresponding exponents of the powers of the primitive elements used to determine the fourth parity check, the fifth parity check, and the sixth parity check among the primitive elements increase sequentially; determining coefficients of a first error location polynomial based on the first parity check, the second parity check, and the third parity check, determining coefficients of a second error location polynomial based on the fourth parity check, the fifth parity check, and the sixth parity check, and obtaining positions of errors included in the data in units of two consecutive symbols based on the first error location polynomial and the second error location polynomial; predetermining values of the errors in units of two consecutive symbols based on the first parity check and the second parity check; and correcting the errors included in the data based on the positions and the values of the errors.

16. The error correction method according to claim 15, Among them, determining the first error location polynomial based on the following equation: ， and determining the second error location polynomial based on the following equation: ， wherein, represents the primitive element of the said Galois field, represents the said first error location polynomial, represents the said second error location polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, represents the said fourth syndrome, represents the said fifth syndrome, represents the said sixth syndrome, and d and f are positive integers and are different from each other.

17. The error correction method according to claim 15, Among them, the second parity check is the same as the fourth parity check, wherein, the third parity check is the same as the fifth parity check, and wherein corresponding exponents of the powers of the primitive elements used to determine the first parity check, the second parity check, the third parity check, and the sixth parity check among the primitive elements increase sequentially.

18. The error correction method according to claim 17, Among them, determining the first error location polynomial based on the following equation: ， and determining the second error location polynomial based on the following equation: ， wherein, represents the primitive element of the said Galois field, represents the said first error-location polynomial, represents the said second error-location polynomial, represents the said first syndrome, represents the said second syndrome, represents the said third syndrome, and represents the said sixth syndrome.

19. The error correction method according to claim 15, Among them, The first error location polynomial and the second error location polynomial are polynomials related to powers of primitive elements in the Galois field having exponents in the corresponding exponents of the powers of the primitive elements, Among them, obtaining the position of the error includes: when the original element with the exponent determines that the values of the first error position polynomial and the second error position polynomial are 0, an error flag signal indicating an error in the i-th symbol and the (i + 1)-th symbol is output.

20. The error correction method according to claim 15, further comprising: receiving the error-corrected data, calculating a plurality of syndrome bits of the error-corrected data to determine whether the error correction operation is successful, and when the error correction operation is successful, outputting a signal indicating termination of the error correction operation of the Reed-Solomon (RS) code decoder.

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