Digital automatic gain controller and OOK receiver

Abstract

The invention discloses a digital automatic gain controller and an OOK receiver, and relates to the technical field of gain controllers, and the method comprises an input module, a frequency control module and a frequency adjustment module which are adaptively connected; the input module is used for receiving an input signal AGCIN and generating a counting control signal COUNT according to the input signal AGCIN, and based on the working state of the digital automatic gain controller, the frequency control module controls the sampling frequency fs when the frequency regulation module samples the counting control signal COUNT; the working states of the digital automatic gain controller comprise a starting working state and a normal working state which are carried out in sequence, and the sampling frequency fs of the frequency regulation module for sampling the counting control signal COUNT in the starting working state is greater than the sampling frequency fs of the frequency regulation module for sampling the counting control signal COUNT in the normal working state. The digital automatic gain controller has high working efficiency and high gain adjustment precision.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic gain controllers, and in particular to a digital automatic gain controller and an OOK receiver. Background Art

[0002] The OOK (On-Off Keying) signal, that is, the on-off keying signal, is modulated by multiplying a binary digital code and a carrier signal. As a carrier for information transmission, due to its simple implementation and strong reliability, it is widely used in wireless communication. The OOK signal receiver is used to receive and demodulate the OOK signal, and demodulate the signal obtained by multiplying the digital modulation with a sine carrier into the 0 and 1 digital codes before modulation, which is convenient for digital baseband recognition and signal processing.

[0003] Traditional OOK receivers use an analog automatic gain controller to adjust the gains of radio frequency and intermediate frequency amplifiers so that their gains are within an appropriate range. By detecting the signal output by the limiter and adjusting the magnitude of the gain control voltage, however, the current analog automatic gain controller has problems such as limited working accuracy, low working efficiency, being interfered by noise signals, poor stability, and limited gain adjustment range.

[0004] In addition, when the OOK signal is low, the received signal is close to the low level, which will cause the control voltage not to work. Therefore, a large external capacitor needs to be connected to the chip to keep the control voltage working when the signal is low, and an additional output port is added, resulting in a low overall circuit integration degree of the OOK receiver. Summary of the Invention

[0005] In view of the above problems and technical requirements, the inventor of the present invention has proposed a digital automatic gain controller and an OOK receiver. The technical solution of the present invention is as follows:

[0006] A digital automatic gain controller includes an input module, a frequency control module, and a frequency adjustment module that are adaptively connected;

[0007] The input module is used to receive the input signal AGC_IN and generate a count control signal COUNT according to the input signal AGC_IN. The count control signal COUNT is loaded to the frequency control module and the frequency adjustment module;

[0008] Based on the working state of the digital automatic gain controller, the frequency control module controls the sampling frequency fs when the frequency adjustment module samples the count control signal COUNT, where

[0009] The working states of the digital automatic gain controller include a startup working state and a normal working state that are carried out in sequence. The sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT in the startup working state is greater than the sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT in the normal working state.

[0010] A further technical solution thereof is that it further includes a counter X10 and a decoder X11;

[0011] The frequency adjustment module controls the counting direction of the counter X10 and configures the frequency f of the counting clock CK of the counter X10 according to the working state of the digital automatic gain controller, the sampled count control signal COUNT, and the sampling frequency fs. CK , wherein,

[0012] The frequency f of the counting clock CK in the startup working state CK is greater than the frequency f of the counting clock CK in the normal working state CK ;

[0013] When the count control signal COUNT controls the counter X10 to count up in the normal working state, the frequency f of the counting clock CK CK is less than the frequency f of the counting clock CK when the count control signal COUNT controls the counter X10 to count down CK ;

[0014] The counter X10 generates a count value based on the count control signal COUNT and the counting clock CK and outputs it to the decoder X11, and the decoder X11 generates a gain control code group according to the count value.

[0015] A further technical solution thereof is that the frequency adjustment module includes a first frequency divider X17. When the frequency control module controls the sampling frequency fs according to the working state of the digital automatic gain controller, it includes:

[0016] The frequency control module outputs an enable signal ENN1 according to the working state of the digital automatic gain controller. The frequency adjustment module determines the sampling frequency fs according to the frequency f0 of the input clock CK_AGC input to the frequency adjustment module under the control of the enable signal ENN1, wherein,

[0017] In the startup working state, the frequency control module outputs an enable signal ENN1 in the second level state, and under the control of the enable signal ENN1, the sampling frequency fs = f0;

[0018] Under normal working conditions, the frequency control module outputs an enable signal ENN1 in the first level state. Under the control of the enable signal ENN1, the sampling frequency fs = f0 / N1, where N1 is the division value of the first frequency divider X17.

[0019] A further technical solution thereof is that the input module includes a NOR gate X12 and a NOT gate X13, where

[0020] The first input terminal of the NOR gate X12 is connected to the input signal AGC_IN, and the second input terminal of the NOR gate is connected to the enable signal ENN2;

[0021] The output terminal of the NOR gate X12 is connected to the input terminal of the NOT gate X13. The output terminal of the NOT gate X13 forms the output terminal of the input module and is connected to the control terminal of the counter X10;

[0022] When the digital gain controller works, it configures the enable signal ENN2 to be in the first level state and generates a count control signal COUNT through the output terminal of the input module. The level state of the count control signal COUNT is the same as the level state of the input signal AGC_IN;

[0023] The frequency control module includes a power-on reset module X1, an AND gate X9, a NOT gate X2, a NOT gate X3, an RS flip-flop X4, a NAND gate X5, a NOT gate X6, a NAND gate X7, and a NAND gate X8, where

[0024] The input terminal of the power-on reset module X1 is connected to the inverted signal of the enable signal ENN0. It generates a Z0NS signal according to the enable signal ENN0. The output terminal of the power-on reset module X1 is connected to the input terminal of the NOT gate X2. The output terminal of the NOT gate X2 is connected to the input terminal of the NOT gate X3. The reset terminal of the counter X10 is connected to the inverted signal of the output terminal of the NOT gate X2. The output terminal of the NOT gate X3 is connected to the reset R terminal of the RS flip-flop;

[0025] The count value includes eight-bit count codes. The first input terminal of the AND gate X9 is connected to the fifth count code of the count value. The second input terminal of the AND gate X9 is connected to the sixth count code of the count value. The output terminal of the AND gate X9 is connected to the set S terminal of the RS flip-flop. The output QN terminal of the RS flip-flop is connected to the second input terminal of the NAND gate X5;

[0026] The first input terminal of the NAND gate X5 is connected to the output terminal of the input module to access the counting control signal COUNT. The output terminal of the NAND gate X5 is connected to the input terminal of the NOT gate X6. The output terminal of the NOT gate X6 is connected to the second input terminal of the NAND gate X8. The first input terminal of the NAND gate X8 is connected to the output terminal of the NAND gate X7. The output terminal of the NAND gate X8 is connected to the second input terminal of the NAND gate X7. The first input terminal of the NAND gate X7 accesses the inverted signal of the Z0NS signal. The output terminal of the NAND gate X7 is used to form the output terminal of the frequency control module for outputting the enable signal ENN1.

[0027] A further technical solution thereof is that the frequency adjustment module includes a D flip-flop X14, a NOR gate X15, a NAND gate X16, a data selector X18, a NOT gate X19, a NOT gate X20, an OR gate X21, an AND gate X22, a NOT gate X23, and a second frequency divider X24, wherein,

[0028] The first input terminal of the NOR gate X15 accesses the input clock CK_AGC with a frequency of f0. The second input terminal of the NOR gate X15 accesses the enable signal ENN2. The output terminal of the NOR gate X15 is connected to the second input terminal of the NAND gate X16;

[0029] The first input terminal of the NAND gate X16 accesses the inverted signal of the enable signal ENN1. The output terminal of the NAND gate X16 is connected to the output terminal of the first frequency divider X17. The signal output by the output terminal of the first frequency divider X17 is inverted and then accesses the first input terminal of the OR gate X21;

[0030] The second input terminal of the NAND gate X16 is connected to the first input terminal of the NAND gate X19. The second input terminal of the NAND gate X19 is connected to the input terminal of the NOT gate X20 and accesses the enable signal ENN1. The signal output by the output terminal of the NAND gate X19 is inverted and then accesses the second input terminal of the OR gate X21. The output terminal of the OR gate X21 is connected to the first input terminal of the AND gate X22. The output terminal of the NOT gate X20 is connected to the second input terminal of the AND gate X22;

[0031] The output terminal of the AND gate X22 is connected to the clock terminal of the D flip-flop X14 to output a sampling clock CLK with a frequency of the sampling frequency fs to the clock terminal of the D flip-flop X14. The output terminal of the AND gate X22 is also connected to the input terminal of the NOT gate X23 and the first input terminal of the data selector X18. The output terminal of the NOT gate X23 is connected to the input terminal of the second frequency divider X24. The output terminal of the second frequency divider X24 is connected to the second input terminal of the data selector X18. The output terminal of the data selector X18 is connected to the clock terminal of the counter;

[0032] The input terminal of the D flip-flop X14 is connected to the output terminal of the output module to access the count control signal COUNT, and the output terminal of the D flip-flop X14 is connected to the control terminal of the data selector X18.

[0033] In a further technical solution, when the count control signal COUNT controls the counter X10 to count up, the count control signal COUNT is in the second level state; when the count control signal COUNT controls the counter X10 to count down, the count control signal COUNT is in the first level state;

[0034] The frequency adjustment module adjusts the frequency f of the counting clock CK of the counter X10 according to the working state of the digital automatic gain controller, the counting direction of the counter X10 controlled by the sampled count control signal COUNT, and the sampling frequency fs CK when including:

[0035] The count control signal COUNT is sampled by the D flip-flop X14 and output to the control terminal of the data selector X18 to control the frequency f of the counting clock CK output by the data selector X18 CK ;

[0036] In the startup working state, the count control signal COUNT in the second level state controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f of the counting clock CK CK = fs / N2 = f0 / N2, where N2 is the division value of the second frequency divider X24, and N1 > N2;

[0037] In the normal working state, when the count control signal COUNT is in the second level state, the count control signal COUNT controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f of the counting clock CK CK = fs / N2 = f0 / N1N2;

[0038] In the normal working state, when the count control signal COUNT is in the first level state, the count control signal COUNT controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f of the counting clock CK CK = fs = f0 / N1.

[0039] In a further technical solution, the gain control code group includes a first intermediate frequency gain control code IF AGCA, a second intermediate frequency gain control code IF AGCB, a third intermediate frequency gain control code IF AGCC, and a radio frequency gain control code RF_AGC, where

[0040] The first intermediate frequency gain control code IF_AGCA, the second intermediate frequency gain control code IF_AGCB, and the radio frequency gain control code RF_AGC are generated based on the second to seventh digit codes of the count value;

[0041] The third intermediate frequency gain control code IF_AGCC is generated based on the zeroth digit code and the first digit code of the count value;

[0042] The output order of each control code in the gain control code group includes: the third intermediate frequency gain control code IF_AGCC, the second intermediate frequency gain control code IF_AGCB, the radio frequency gain control code RF_AGC, and the first intermediate frequency gain control code IF_AGCA.

[0043] An OOK receiver includes the digital automatic gain controller described above;

[0044] The OOK receiver further includes a comparator, a low noise amplifier, a mixer, an intermediate frequency filter, a variable gain amplifier module, a peak detector, and a limiter that are adaptively connected. Among them,

[0045] The input end of the low noise amplifier is connected to an input OOK signal. The input OOK signal is sequentially processed by a mixer, an intermediate frequency filter, a variable gain amplifier module, and a peak detector and then input to the limiter;

[0046] The comparator compares the output signal of the limiter and a reference voltage and then generates a comparison signal as the input signal AGC_IN of the digital automatic gain controller. The digital automatic gain controller generates a gain control code group according to the input signal AGC_IN, and the gain control code group is used to adjust the gains of the mixer and the variable gain amplifier module.

[0047] A further technical solution thereof is that the variable gain amplifier module includes a first variable gain amplifier sub-module and a second variable gain amplifier sub-module;

[0048] The first variable gain amplifier sub-module includes m1 pre-stage variable gain amplifier units. The pre-stage variable gain amplifier unit includes a variable gain amplifier and a first variable resistor array connected to the output end group of the variable gain amplifier;

[0049] The first variable resistor array includes n1 / 2 switches and n1 resistors connected in series. Among the n1 resistors connected in series, the second end of the i-th resistor is connected to the first end of the (n1 - i + 1)-th resistor through the i-th switch, where 1 ≤ i ≤ n1 / 2;

[0050] The second variable gain amplifier sub-module includes m2 post-stage variable gain amplifier units, and each post-stage variable gain amplifier unit includes a variable gain amplifier and a second variable resistor array connected to the output end group of the variable gain amplifier;

[0051] The second variable resistor array includes n2 / 2 switches and n2 resistors connected in series. Among the n2 resistors connected in series, the second end of the j-th resistor is connected to the first end of the (n1 - j + 1)-th resistor through the j-th switch, where 1 ≤ j ≤ n2 / 2;

[0052] The resistances of the n1 resistors in the first variable resistor array are equal, the resistances of the n2 resistors in the second variable resistor array are equal, and the resistance of the resistors in the second variable resistor array is greater than the resistance of the resistors in the first variable resistor array.

[0053] 10. The OOK receiver according to claim 9, wherein the first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB are loaded into the first variable gain amplifier sub-module, and the third intermediate frequency gain control code IF_AGCC is loaded into the second variable gain amplifier sub-module;

[0054] The first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB together include m1n1 / 2 control digits, and the m1n1 / 2 control digits are respectively loaded into the control ends of the m1n1 / 2 switches in the first variable gain amplifier sub-module;

[0055] The third intermediate frequency gain control code IF_AGCC includes m2n2 / 2 control digits, and the m2n2 / 2 control digits are respectively loaded into the control ends of the m2n2 / 2 switches in the second variable gain amplifier sub-module.

[0056] The beneficial technical effects of the present invention are:

[0057] (1) A digital automatic gain controller (DAGC, Digital Automatic Gain Control) is provided, which can configure the sampling frequency of the count control signal COUNT according to the working state of the DAGC, perform high-frequency sampling on the count control signal COUNT in the startup state, and perform downsampling on the count control signal COUNT in the normal working state, that is, use digital decimation filtering technology to reduce the influence of the DAGC on the input signal fluctuation and improve the working efficiency.

[0058] (2) The DAGC provided by the present invention also controls the counting frequency of the counter according to the working state and the counting direction, further improves the working efficiency, and improves the accuracy of the output gain control code group, and can accurately control the gain.

[0059] (3) The DAGC controls the gain by adjusting the resistance value of the variable resistance array, and can adjust the gain in a large range, solving the problem that the traditional analog AGC has a small gain adjustment range for the OOK receiver. Moreover, when the DAGC is applied to the OOK receiver, it can eliminate the large external capacitors and additional output pins required by the analog AGC, further increasing the integration of the receiver. Description of the Drawings

[0060] Figure 1 is a structural block diagram of an embodiment of the digital automatic gain controller provided by the present invention.

[0061] Figure 2 is a circuit schematic diagram of an embodiment of the digital automatic gain controller provided by the present invention.

[0062] Figure 3 is a structural block diagram of an embodiment of the OOK receiver provided by the present invention.

[0063] Figure 4 is a schematic diagram of an embodiment of the variable gain amplifier module provided by the present invention.

[0064] Figure 5 is a circuit schematic diagram of an embodiment of the first variable resistance array provided by the present invention.

[0065] Figure 6 is a circuit schematic diagram of an embodiment of the second variable resistance array provided by the present invention.

[0066] Figure 7 is a working logic flowchart of an embodiment of the digital automatic gain controller provided by the present invention. Detailed Embodiments

[0067] The following further describes the detailed embodiments of the present invention with reference to the drawings.

[0068] The present invention provides a digital automatic gain controller, including an input module, a frequency control module, and a frequency adjustment module that are adaptively connected;

[0069] The input module is used to receive the input signal AGC_IN and generate a count control signal COUNT according to the input signal AGC_IN. The count control signal COUNT is loaded to the frequency control module and the frequency adjustment module;

[0070] According to the working state of the digital automatic gain controller, the frequency control module controls the sampling frequency fs when the frequency adjustment module samples the count control signal COUNT, where

[0071] The working states of the digital automatic gain controller include a startup working state and a normal working state in sequence. In the startup working state, the sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT is greater than the sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT in the normal working state.

[0072] Specifically, Figure 1 Figure 5 shows a structural block diagram of a digital automatic gain controller (hereinafter simply referred to as DAGC). As Figure 1 shown, the input module, the frequency control module, and the frequency adjustment module are adaptively connected. Specifically, it means that the output end of the input module is connected to the frequency adjustment module and the frequency control module, and the frequency control module is connected to the frequency adjustment module. The specific implementation manners of the input module, the frequency control module, and the frequency adjustment module can refer to the following description.

[0073] Generally, DAGC can be applied to the negative feedback loop in data processing systems such as OOK receivers. The negative feedback loop usually includes a comparator and a gain control element. The input signal AGC_IN of DAGC is generated by the comparator in the negative feedback loop. The comparator generates the input signal AGC_IN according to the magnitudes of the comparator input signal and the reference voltage. DAGC adjusts the gain of the gain control element according to the input signal AGC_IN, thereby controlling the magnitude of the comparator input signal to stabilize the comparator input signal near the reference voltage.

[0074] The working states of DAGC include a startup working state and a normal working state in sequence. Specifically, before power-on, DAGC generally defaults to controlling the gain of the gain control element to be zero. In a period of time just after power-on, that is, when DAGC is in the startup state, the comparator input signal is stably less than the reference voltage, and the level state of the input signal AGC_IN of DAGC is in a stable state. The stable control DAGC increases the gain of the gain control element until the level state of the input signal AGC_IN of DAGC flips for the first time, and then DAGC automatically enters the normal working state.

[0075] It can be seen from the above description that in the startup working state, the level state of the DAGC input signal AGC_IN is stable and there are fewer interference signals; while in the normal working state, the level state of the DAGC input signal AGC_IN fluctuates with the state of the comparator input signal, and there are more noise and interference signals. Also, since the input module in the present invention generates the count control signal COUNT according to the input signal AGC_IN. Therefore, in the startup working state, there are fewer interference signals in the count control signal COUNT; while in the normal working state, there are more noise and interference signals in the count control signal COUNT.

[0076] Therefore, the present invention controls the sampling frequency f of the frequency adjustment module to sample the count control signal COUNT in the startup working state through the frequency control module s , which is greater than the sampling frequency f of the frequency adjustment module to sample the count control signal COUNT in the normal working state s , that is, high-frequency sampling of the count control signal COUNT is performed in the startup state to improve work efficiency; low-frequency sampling of the count control signal COUNT is performed in the normal working state to avoid mis-sampling of interference signals and reduce the influence of the DAGC on the input signal fluctuation. The specific method for the frequency control module to control the sampling frequency f of the frequency adjustment module to sample the count control signal COUNT can be referred to the following description. s

[0077] Furthermore, the DAGC further includes a counter X10 and a decoder X11;

[0078] The frequency adjustment module controls the counting direction of the counter X10 and adjusts the frequency f of the counting clock CK of the counter X10 according to the working state of the digital automatic gain controller and the sampled count control signal COUNT CK , where

[0079] The frequency f of the counting clock CK in the startup working state CK , is greater than the frequency f of the counting clock CK in the normal working state CK ;

[0080] The frequency f of the counting clock CK when the count control signal COUNT controls the counter X10 to count up in the normal working state CK , is less than the frequency f of the counting clock CK when the count control signal COUNT controls the counter X10 to count down CK ;

[0081] The counter X10 generates a count value based on the count control signal COUNT and the counting clock CK and outputs it to the decoder X11, and the decoder X11 generates a gain control code group according to the count value.

[0082] ​Specifically, the level state of the counting control signal COUNT generated by the input module is the same as the level state of the input signal AGC_IN. When the comparator input signal is less than the reference voltage, the DAGC input signal AGC_IN is in the second level state, and the counting control signal COUNT generated by the input module based on the input signal AGC_IN is also in the second level state; when the comparator input signal is greater than the reference voltage, the DAGC input signal AGC_IN is in the first level state, and the counting control signal COUNT generated by the input module based on the input signal AGC_IN is also in the first level state. In an embodiment of the present invention, the first level state is a low level state, and the second level state is a high level state. The gain control code group is input to the gain control element to control the gain size.

[0083] When the counting control signal COUNT is in the second level state, the counting control signal COUNT controls the counter X10 to count up, the count value output by the counter X10 increases, and the gain control code group output by the decoder X11 increases the gain of the gain control element; when the counting control signal COUNT is in the first level state, the counting control signal COUNT controls the counter X10 to count down. The count value output by the counter X10 decreases, and the gain control code group output by the decoder X11 decreases the gain of the gain control element. The specific forms of the counter X10 and the decoder X11 can be consistent with the prior art.

[0084] The frequency f of the counting clock CK CK is the counting frequency of the counter X10. In the startup working state, the counting control signal COUNT is always in the second level state, and the counter X10 needs to quickly accumulate the count value upward to increase the gain of the gain control element through the gain control code, so that the DAGC can enter the normal working state as soon as possible. Therefore, a larger counting frequency is adopted in the startup working state of the present invention, which can improve the working efficiency of the DAGC.

[0085] In the normal working state, the counting control signal COUNT may be in the first / second level state. To achieve precise adjustment of the gain, a smaller counting frequency is required in the normal working state. At the same time, since the input signal of the comparator is prone to glitches due to external interference when the gain is large, to avoid interference caused by glitches to the operation of the data processing system where the DAGC is located, the counting frequency when the counter X10 counts down needs to be greater than the frequency when it counts up in the normal working state.

[0086] Figure 2 shows the circuit structure of the DAGC, as Figure 2 shown, the input module includes a NOR gate X12 and a NOT gate X13, where,

[0087] The first input terminal of the NOR gate X12 is connected to the input signal AGC_IN, and the second input terminal of the NOR gate is connected to the enable signal ENN2;

[0088] The output terminal of the NOR gate X12 is connected to the input terminal of the NOT gate X13. The output terminal of the NOT gate X13 forms the output terminal of the input module and is connected to the control terminal of the counter X10;

[0089] The enable signal ENN2 is an externally input signal. When the digital gain controller operates, the enable signal ENN2 is configured to be in the first level state, so that the level state of the count control signal COUNT output from the output terminal of the input module is the same as the level state of the input signal AGC_IN.

[0090] Further, the frequency control module includes a power-on reset module X1, an AND gate X9, a NOT gate X2, a NOT gate X3, an RS flip-flop X4, a NAND gate X5, a NOT gate X6, a NAND gate X7, and a NAND gate X8. Among them,

[0091] The input terminal of the power-on reset module X1 is connected to the inverted signal of the enable signal ENN0. The Z0NS signal is generated according to the enable signal ENN0. The output terminal of the power-on reset module X1 is connected to the input terminal of the NOT gate X2. The output terminal of the NOT gate X2 is connected to the input terminal of the NOT gate X3. The reset terminal of the counter X10 is connected to the inverted signal of the output terminal of the NOT gate X2. The output terminal of the NOT gate X3 is connected to the reset R terminal of the RS flip-flop.

[0092] The count value includes eight-bit count codes. The first input terminal of the AND gate X9 is connected to the fifth count code of the count value. The second input terminal of the AND gate X9 is connected to the sixth count code of the count value. The output terminal of the AND gate X9 is connected to the set S terminal of the RS flip-flop. The output QN terminal of the RS flip-flop is connected to the second input terminal of the NAND gate X5;

[0093] The first input terminal of the NAND gate X5 is connected to the output terminal of the input module to access the count control signal COUNT. The output terminal of the NAND gate X5 is connected to the input terminal of the NOT gate X6. The output terminal of the NOT gate X6 is connected to the second input terminal of the NAND gate X8. The first input terminal of the NAND gate X8 is connected to the output terminal of the NAND gate X7. The output terminal of the NAND gate X8 is connected to the second input terminal of the NAND gate X7. The first input terminal of the NAND gate X7 is connected to the inverted signal of the Z0NS signal. The output terminal of the NAND gate X7 forms the output terminal of the frequency control module for outputting the enable signal ENN1.

[0094] Specifically, the count value can be expressed as Q<7:0>. The count digits generally refer to each digit that constitutes the count value. The fifth count digit of the count value can be expressed as Q<5>, and the sixth count digit of the count value can be expressed as Q<6>. The enable signal ENN0 is an external input signal, and the enable signal ENN0 is also input to the enable terminal of the decoder X11. The power-on reset module X1 can adopt the common form of those skilled in the art, such as a POR module, etc.

[0095] The frequency control module controls the sampling frequency f according to the working state of the digital automatic gain controller s When it includes:

[0096] The frequency control module outputs an enable signal ENN1 according to the working state of the digital automatic gain controller. The frequency adjustment module determines the sampling frequency f according to the frequency f0 of the input clock CK_AGC under the control of the enable signal ENN1 s where,

[0097] The specific working principle of the frequency control module outputting the enable signal ENN1 according to the working state of the DAGC is as follows: After the DAGC is powered on, the configuration enables the signal ENN0 to change from a high level state to a low level state, and the Z0NS signal output by the power-on reset module X1 also changes from a high level state to a low level state. At the same time, the decoder X11 starts to work. At this time, the DAGC works in the startup working state, the count control signal COUNT signal is in the high level state, the fifth to sixth count digits of the counter, namely Q<5>-Q<6>, are 0. The Z0NS signal is inverted by the NOT gate X2 and then input to the reset terminal of the counter, causing the counter X10 to start counting from zero, and then input to the reset R terminal of the RS flip-flop X4 through the NOT gate X3. The reset R terminal of the RS flip-flop X4 inputs a low level signal. Therefore, the output QN terminal of the RS flip-flop X4 outputs a high level signal to the second input terminal of the NAND gate X5. The second input terminal of the NAND gate X8 inputs a high level signal, and the signal input to the first input terminal of the NAND gate X7 changes from a low level signal to a high level signal. At this time, the output terminal of the NAND gate X7 outputs the enable signal ENN1 in the high level state;

[0098] After the input signal AGC_IN flips for the first time, the count control signal COUNT flips to the low level state for the first time, and the second input terminal of the NAND gate X8 inputs a low level signal. The DAGC automatically enters the normal working state. After entering the normal working state, the Z0NS signal output by the power-on reset module X1 still remains in the low level state, and the first input terminal of the NAND gate X7 inputs a high level signal. Therefore, the output terminal of the NAND gate X7 latches and outputs the enable signal ENN1 in the low level state. The frequency adjustment module determines the sampling frequency f according to the frequency f0 of the input clock CK_AGC under the control of the enable signal ENN1 s The specific working principle of

[0099] Further, the frequency adjustment module includes a D flip-flop X14, a NOR gate X15, a NAND gate X16, a first frequency divider X17, a data selector X18, a NOT gate X19, a NOT gate X20, an OR gate X21, an AND gate X22, a NOT gate X23, and a second frequency divider X24, where

[0100] The first input terminal of the NOR gate X15 is connected to an input clock CK_AGC with a frequency of f0, the second input terminal of the NOR gate X15 is connected to an enable signal ENN2, and the output terminal of the NOR gate X15 is connected to the second input terminal of the NAND gate X16;

[0101] The first input terminal of the NAND gate X16 is connected to the inverted signal of the enable signal ENN1, the output terminal of the NAND gate X16 is connected to the output terminal of the first frequency divider X17, and the signal output from the output terminal of the first frequency divider X17 is inverted and then connected to the first input terminal of the OR gate X21;

[0102] The second input terminal of the NAND gate X16 is connected to the first input terminal of the NAND gate X19, the second input terminal of the NAND gate X19 is connected to the input terminal of the NOT gate X20 and is connected to the enable signal ENN1, the signal output from the output terminal of the NAND gate X19 is inverted and then connected to the second input terminal of the OR gate X21, the output terminal of the OR gate X21 is connected to the first input terminal of the AND gate X22, and the output terminal of the NOT gate X20 is connected to the second input terminal of the AND gate X22;

[0103] The output terminal of the AND gate X22 is connected to the clock terminal of the D flip-flop X14 to output a sampling clock CLK with a frequency of sampling frequency f s to the clock terminal of the D flip-flop X14. The output terminal of the AND gate X22 is also connected to the input terminal of the NOT gate X23 and the first input terminal of the data selector X18. The output terminal of the NOT gate X23 is connected to the input terminal of the second frequency divider X24. The output terminal of the second frequency divider X24 is connected to the second input terminal of the data selector X18. The output terminal of the data selector X18 is connected to the clock terminal of the counter;

[0104] The input terminal of the D flip-flop X14 is connected to the output terminal of the output module to access a count control signal COUNT, and the output terminal of the D flip-flop X14 is connected to the control terminal of the data selector X18.

[0105] Specifically, the sampling frequency f s Specifically refers to the frequency of the sampling clock CLK loaded to the clock terminal of the D flip-flop X14. The working principle of the frequency adjustment module for determining the sampling frequency fs according to the frequency f0 of the input clock CK_AGC under the control of the enable signal ENN1 is as follows:

[0106] In the startup working state, the enable signal ENN1 is at a high level. The input clock CK_AGC is input to the clock terminal of the D flip-flop X14 through the NOR gate X15, NAND gate X19, OR gate X21, and AND gate X22 in sequence. At this time, the input clock CK_AGC is the sampling clock CK, and the sampling frequency fs is equal to the frequency f0 of the input clock CK_AGC. In this embodiment, the frequency f0 of the input clock CK_AGC is 3.38 MHz.

[0107] In the normal working state, the enable signal ENN1 is at a low level. The input clock CK_AGC enters the first frequency divider X17 for frequency division after passing through the NAND gate X16, and then is input to the clock terminal of the D flip-flop X14 through the OR gate X21 and AND gate X22. At this time, the sampling clock CK is the input clock CK_AGC after being frequency-divided by the first frequency divider X17, and the sampling frequency fs = f0 / N1, where N1 is the frequency division value of the first frequency divider and N1 is a positive integer. In this embodiment, N1 = 128, and in the normal working state, the sampling frequency fs = 3.38 MHz / 128 = 26.41 KHz.

[0108] Furthermore, the frequency adjustment module configures the frequency f of the counting clock CK of the counter X10 according to the working state of the digital automatic gain controller, the sampled counting control signal COUNT to control the counting direction of the counter X10, and the sampling frequency fs. CK The specific working principle is as follows:

[0109] In the startup working state, the counting control signal COUNT is at a high level. The counting control signal COUNT is sampled by the D flip-flop X14 and output to the control terminal (S terminal) of the data selector X18, serving as the gating signal of the data selector X18 to control the data selector X18 to select the clock signal input from the second input terminal as the counting clock CK output. At this time, the input of the second input terminal is the sampling clock CLK in the startup working state after being frequency-divided by the second frequency divider X24. At this time, the frequency f of the counting clock CK CK = fs / N2 = f0 / N2, where N2 is the frequency division value of the second frequency divider X24, N1 > N2, and N2 is a positive integer. In this embodiment, N2 = 16, so in the startup working state, f CK = 3.38 MHz / 16 = 211.25 KHz.

[0110] In the normal working state, the counting control signal COUNT is in a low level state / high level state to increase / decrease the gain. When the counting control signal COUNT is in a low level state, the counter X10 counts downwards, and a low level signal is input to the control terminal of the selector X18. The data selector X18 selects the clock signal input from the first input terminal as the counting clock CK output. At this time, the input of the first input terminal is the sampling clock CLK in the normal working state. At this time, the frequency f of the counting clock CK CK = fs = fs / N1 = 26.41KHz; when the counting control signal COUNT is in a high level state, the counter X10 counts upwards, and a high level signal is input to the control terminal of the selector X18. The data selector X18 selects the clock signal input from the second input terminal as the counting clock CK output. At this time, the input of the second input terminal is the sampling clock CLK in the normal working state after being divided by the second frequency divider X24. At this time, the frequency f of the counting clock CK CK = fs / N2 = f0 / N1N2 = 26.41KHz / 16 = 1.65KHz. In summary, in this embodiment, the counting frequency of the counter X10 in the startup state is the high frequency 211.25KHz, the counting frequency when counting upwards in the normal working state (i.e., increasing the gain) is 1.65KHz, and the counting frequency when counting downwards in the normal working state (i.e., decreasing the gain) is 26.41KHz.

[0111] In an embodiment of the present invention, the gain control code group includes a first intermediate frequency gain control code IF_AGCA, a second intermediate frequency gain control code IF_AGCB, a third intermediate frequency gain control code IF_AGCC, and a radio frequency gain control code RF_AGC, where

[0112] The second to seventh digit counting codes of the count value are input to the first input terminal of the decoder X11, and the zeroth and first digit counting codes of the count value are input to the second input terminal of the decoder X11. The first intermediate frequency gain control code IF_AGCA, the second intermediate frequency gain control code IF_AGCB, and the radio frequency gain control code RF_AGC are generated based on the second to seventh digit counting codes of the count value; the third intermediate frequency gain control code IF_AGCC is generated based on the zeroth and first digit counting codes of the count value. That is, each output state of the first intermediate frequency gain control code IF_AGCA, the second intermediate frequency gain control code IF_AGCB, and the radio frequency gain control code RF_AGC corresponds to each counting state of the second to seventh digit counting codes, and each output state of the third intermediate frequency gain control code IF_AGCC corresponds to each counting state of the zeroth to first digit counting codes of the count value. The specific manner in which the decoder generates the gain control code according to the count value can be consistent with the prior art.

[0113] Meanwhile, in this embodiment, the output order of each control code in the gain control code group is: the third intermediate frequency gain control code IF_AGCC, the second intermediate frequency gain control code IF_AGCB, the radio frequency gain control code RF_AGC, and the first intermediate frequency gain control code IF_AGCA. Specifically, during implementation, the number of gain control codes included in the gain control code group, the number of bits of each control code included in each gain control code, and the output order of each gain control code can all be determined according to the form of the gain control element to which the gain control code group is loaded.

[0114] Based on the above DAGC, the present invention provides an OOK receiver that uses the above DAGC to adjust the gain. The OOK receiver includes the above DAGC;

[0115] The OOK receiver further includes a comparator, a low-noise amplifier, a mixer, an intermediate frequency filter, a variable gain amplifier module, a peak detector, and a limiter that are adaptively connected. Among them,

[0116] The input of the low-noise amplifier is connected to the input OOK signal. The input OOK signal is sequentially processed by the mixer, the intermediate frequency filter, the variable gain amplifier module, and the peak detector and then input to the limiter;

[0117] The comparator compares the output signal of the limiter and the reference voltage and then generates a comparison signal as the input signal AGC_IN of the digital automatic gain controller. The digital automatic gain controller generates a gain control code group according to the input signal AGC_IN. The gain control code group is used to adjust the gains of the mixer and the variable gain amplifier module.

[0118] Specifically, Figure 3 shows a schematic structural diagram of the OOK receiver, as Figure 3As shown, the OOK receiver further includes an output driver circuit, a dynamic threshold circuit, a power management module, a crystal oscillator, and a phase-locked loop circuit. The output end of the low-noise amplifier is connected to the input end of the mixer, the output end of the mixer is connected to the output end of the intermediate-frequency filter, the output end of the intermediate-frequency filter is connected to the input end of the variable gain amplifier module, the output end of the variable gain amplifier module is connected to the input end of the peak detector, the peak detector is connected to the input end of the limiter, the first output end of the limiter is connected to the inverting input end of the comparator, the output end of the comparator is connected to the DAGC, and the output end of the DAGC is connected to the mixer and the variable gain amplifier module to form a negative feedback loop. The power management module is connected to the non-inverting input end of the comparator for providing a reference voltage to the comparator and powering the above-mentioned components at the same time. The second output end of the limiter is connected to the input end of the dynamic threshold circuit and the output driver circuit, and the output driver circuit is used to output the demodulated OOK signal. The crystal oscillator is connected to the phase-locked loop circuit for providing a clock signal to the phase-locked loop circuit, and the phase-locked loop circuit is connected to the mixer for providing a local oscillator signal to the mixer.

[0119] When the OOK receiver works, the input OOK signal is amplified by the low-noise amplifier and then sent to the mixer for mixing. The mixed intermediate-frequency signal is sent to the intermediate-frequency filter for filtering to remove the DC component and the image signal. The filtered intermediate-frequency signal enters the variable gain amplifier for further amplification and then enters the peak detector to detect the peak to extract the envelope signal of the input OOK signal, and then enters the limiter to control the amplitude of the envelope signal within a preset range. The output signal after the limiter limits the amplitude enters the comparator to be compared with the reference voltage. If the output signal after the limiter limits the amplitude is greater than the reference voltage, the DAGC outputs a gain control code group to reduce the gains of the mixer and the variable gain amplifier, and vice versa to increase the gains of the mixer and the variable gain amplifier, so as to perform negative feedback regulation.

[0120] Consistent with the prior art, during demodulation, the output signal of the limiter is output to the dynamic threshold circuit. The dynamic threshold circuit takes the mean value of the maximum and minimum values of the signal envelope. In the output driver circuit, the envelope signal is compared with the mean value, and the signal higher than the mean value is output as a high level, and the signal lower than the mean value is output as a low level, and thus the demodulation is completed.

[0121] In the described gain control code group, the radio frequency gain control code RF_AGC is loaded into the mixer, and the first intermediate frequency gain control code IF_AGCA, the second intermediate frequency gain control code IF_AGCB, and the third intermediate frequency gain control code IF_AGCC are loaded into the variable gain amplifier module to adjust the gains of the mixer and the variable gain amplifier module. The way of loading the radio frequency gain control code RF_AGC into the mixer to adjust the mixer gain can be consistent with the prior art, and the specific way of adjusting the gain of the variable gain amplifier module by the intermediate frequency gain control code can refer to the following description.

[0122] Further, the variable gain amplifier module includes a first variable gain amplifier sub-module and a second variable gain amplifier sub-module;

[0123] The first variable gain amplifier sub-module includes m1 pre-stage variable gain amplifier units, and each pre-stage variable gain amplifier unit includes a variable gain amplifier and a first variable resistor array connected to the output end group of the variable gain amplifier;

[0124] The first variable resistor array includes n1 / 2 switches and n1 resistors connected in series. The n1 resistors connected in series are sorted in sequence. The second end of the i-th resistor is connected to the first end of the (n1 - i + 1)-th resistor through the i-th switch, where 1 ≤ i ≤ n1 / 2;

[0125] The second variable gain amplifier sub-module includes m2 post-stage variable gain amplifier units, and each post-stage variable gain amplifier unit includes a variable gain amplifier and a second variable resistor array connected to the output end group of the variable gain amplifier;

[0126] The second variable resistor array includes n2 / 2 switches and n2 resistors connected in series. The n2 resistors connected in series are sorted in sequence. The second end of the j-th resistor is connected to the first end of the (n1 - j + 1)-th resistor through the j-th switch, where 1 ≤ j ≤ n2 / 2, and both n1 and n2 are positive even numbers.

[0127] The first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB are loaded into the first variable gain amplifier sub-module, and the third intermediate frequency gain control code IF_AGCC is loaded into the second variable gain amplifier sub-module;

[0128] The first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB together include m1n1 / 2 control digital codes, and the m1n1 / 2 control digital codes are respectively loaded into the control ends of m1n1 / 2 switches in the first variable gain amplifier sub-module;

[0129] The third intermediate frequency gain control code IF_AGCC includes m2n2 / 2 bits of control digital codes, and the m2n2 / 2 bits of control digital codes are respectively loaded to the control terminals of m2n2 / 2 switches in the second variable gain amplifier sub-module.

[0130] Specifically, the gain control code group controls the equivalent resistance values of the first variable resistance array and the second variable resistance array by controlling the states of the switches in the first variable resistance array and the second variable resistance array, so as to control the gain of the variable gain amplifier module. In an embodiment of the present invention, as Figure 4 shown, the first variable gain amplifier sub-module includes 5 cascaded pre-stage variable gain amplifier units, that is, m1 = 5. The second variable gain amplifier sub-module includes 1 post-stage variable gain amplifier unit, that is, m2 = 1. The first variable resistance array in the last pre-stage variable gain amplifier unit in the first variable gain amplifier sub-module is connected to the post-stage variable gain amplifier unit.

[0131] In an embodiment of the present invention, the first variable resistance array includes 10 switches and 20 resistors connected in series, that is, n1 = 20. As Figure 5 shown, in the first variable resistance array, the 20 resistors connected in series are sequentially denoted as R1, R2,..., R20, and the 10 switches in the first variable resistance array are sequentially denoted as SWITCH1, SWITCH2,..., SWITCH10. The second end of R1 is connected to the first end of R20 through SWITCH1, the second end of R2 is connected to the first end of R19 through SWITCH1,..., and the second end of R10 is connected to the first end of R11 through SWITCH1.

[0132] In an embodiment of the present invention, the second variable resistance array includes 4 switches and 8 resistors connected in series, that is, n2 = 8. As Figure 6 shown, in the second variable resistance array, the 8 resistors connected in series are sequentially denoted as R21, R22,..., R28, and the 4 switches in the first variable resistance array are sequentially denoted as SWITCH11, SWITCH12, SWITCH13, SWITCH14. The second end of R21 is connected to the first end of R28 through SWITCH11, the second end of R22 is connected to the first end of R27 through SWITCH12,..., and the second end of R24 is connected to the first end of R25 through SWITCH14.

[0133] The variable gain amplifiers in the pre-stage variable gain amplifier unit and the post-stage variable gain amplifier unit both adopt a differential input / output form. All the resistors in the first variable resistor array are connected in series between the positive-phase output terminal and the inverting-phase output terminal of the corresponding variable gain amplifier. All the resistors in the second variable resistor array are connected in series between the positive-phase output terminal and the inverting-phase output terminal of the corresponding variable gain amplifier.

[0134] The first variable gain amplifier sub-module includes a total of 50 switches. The second variable gain amplifier sub-module includes a total of 4 switches. To correspond to the number of switches, in this embodiment, the first intermediate frequency gain control code IF_AGCA includes 30 control digits, which can be denoted as IF_AGCA<29:0>. The second intermediate frequency gain control code IF_AGCB includes 20 control digits, which can be denoted as IF_AGCB<19:0>. The third intermediate frequency gain control code IF_AGCC includes 4 control digits, which can be denoted as IF_AGCC<3:0>. In addition, the radio frequency gain control code RF_AGC includes 13 control digits, which can be denoted as RF_AGC<12:0>.

[0135] In this embodiment, the 0th to 9th bits of the first intermediate frequency gain control code IF_AGCA are sequentially loaded to the control terminals of the switches in the first first variable resistor array. That is, the 0th control digit of the first intermediate frequency gain control code IF_AGCA is loaded to the control terminal of SWITCH1 in the first first variable resistor array. The 1st control digit of the first intermediate frequency gain control code IF_AGCA is loaded to the control terminal of SWITCH2 in the first first variable resistor array, and so on. The 10th to 19th bits of the first intermediate frequency gain control code IF_AGCA are sequentially loaded to the control terminals of the switches in the second first variable resistor array. The 20th to 29th bits of the first intermediate frequency gain control code IF_AGCA are sequentially loaded to the control terminals of the switches in the third first variable resistor array. The 0th to 9th bits of the second intermediate frequency gain control code IF_AGCB are sequentially loaded to the control terminals of the switches in the fourth first variable resistor array. The 10th to 19th bits of the second intermediate frequency gain control code IF_AGCB are sequentially loaded to the control terminals of the switches in the fifth first variable resistor array. The 0th to 4th bits of the third intermediate frequency gain control code IF_AGCC are sequentially loaded to the control terminals of SWITCH11 - 14.

[0136] Meanwhile, in this embodiment, the resistances of 20 resistors in the first variable resistor array are made equal, the resistances of 8 resistors in the second variable resistor array are made equal, and the resistance of the resistor in the second variable resistor array is greater than that of the resistor in the first variable resistor array. When the decoder outputs the gain control code, the third intermediate frequency gain control code IF_AGCC is preferentially output. Since the resistance of the resistor in the second variable resistor array is relatively large, preferentially outputting the third intermediate frequency gain control code IF_AGCC can greatly adjust the gain of the corresponding variable gain amplifier. Subsequently, the second intermediate frequency gain control code IF_AGCB and the first intermediate frequency gain control code IF_AGCA are output in sequence, and the first variable resistor array is used to slightly adjust the gain of the corresponding variable gain amplifier. That is, the overall gain of the variable gain amplifier adjustment module is adjusted in the process of first greatly adjusting and then slightly adjusting each time.

[0137] Figure 7 Fig. shows the logic flow chart when the above DAGC works in an OOK receiver, as Figure 7 shown. After the DAGC is powered on, it works in the startup state. As can be seen from the above description, the output signal of the limiter in the startup state is less than the reference voltage, and the comparison signal output by the comparator is stably logic "1", that is, the input signal AGC_IN is always in the high level state, the count control signal COUNT is in the high level state, and the counter X10 starts counting upward from zero in the startup state, and the counting frequency f CK is the high frequency 211.25 KHz. Each time the counter receives a clock pulse, the count value output by the counter X10 is incremented by 1, and the count value output by the counter X10 continues to accumulate. The decoder X11 outputs a group of gain control codes corresponding to the count value, and the corresponding gain control code is shifted to the left, and the gain of the mixer and variable gain amplifier module increases until the voltage of the output signal of the limiter is greater than the reference voltage, and then the comparison signal output by the comparator is inverted to logic "0", and the DAGC enters the normal working state.

[0138] When the DAGC just enters the normal working state, the comparison signal output by the comparator is logic "0", that is, the input signal AGC_IN is in the low level state, the count control signal COUNT is in the low level state, and the configured counting frequency f CK is 26.4 KHz. Each time the counter receives a clock pulse, the count value output by the counter X10 is decremented by 1, and the corresponding gain control code output by the decoder is shifted one bit to the right, and the gain of the mixer and variable gain amplifier module decreases. The comparator continuously compares the size of the output signal of the limiter and the reference voltage. If the comparison signal output by the comparator is still logic "0", the above adjustment process is repeated; if the comparison signal output by the comparator is inverted to logic "1", the configured counting frequency f CKIt is 1.65 KHz. Each time the counter receives a clock pulse, the count value output by the counter X10 increases by 1, and the corresponding gain control code output by the decoder is shifted left by one bit, increasing the gain of the mixer and variable gain amplifier module.

[0139] The left / right shift of the gain control code specifically refers to the left / right circular shift of the gain control code. Taking the left shift of the third intermediate frequency gain control code IF_AGCC by 1 bit as an example, in this embodiment, the initial value of the third intermediate frequency gain control code IF_AGCC is "1111". The third intermediate frequency gain control code IF_AGCC is generated based on the 0th and 1st count digits of the count value. When the count value represented by the 0th and 1st count digits of the count value increases by 1, the third intermediate frequency gain control code IF_AGCC is shifted left by 1 bit to become "1110", and so on.

[0140] It should be noted that in actual application, the upper computer can also monitor the eight-bit count digits of the count value and the output signal of the comparator in real time. If all the eight-bit count digits of the count value are the numerical value 1 and the comparator outputs logic "1", it means that the gains of the mixer and variable gain amplifier module have both been adjusted to the maximum, but the output voltage of the limiter still has not reached the reference voltage. This is an abnormal situation, and at this time, the upper computer controls the counter X10 to stop counting. Or, if all the eight-bit count digits of the count value are the numerical value 0 and the comparator outputs logic "0", it means that the gains of the mixer and variable gain amplifier module have both been adjusted to the minimum, but the output voltage of the limiter is still greater than the reference voltage. This is an abnormal situation, and at this time, the upper computer also controls the counter X10 to stop counting.

[0141] It should be noted that the terms "first" and "second" used in the above description are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0142] The above is only the preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A digital automatic gain controller, characterized in that, It includes an input module, a frequency control module, and a frequency adjustment module that are adaptively connected; The input module is used to receive an input signal AGC_IN and generate a count control signal COUNT according to the input signal AGC_IN. The count control signal COUNT is loaded to the frequency control module and the frequency adjustment module; Based on the working state of the digital automatic gain controller, the frequency control module controls the sampling frequency fs when the frequency adjustment module samples the count control signal COUNT. Among them, The working state of the digital automatic gain controller includes a startup working state and a normal working state that are carried out in sequence. The sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT in the startup working state is greater than the sampling frequency fs at which the frequency adjustment module samples the count control signal COUNT in the normal working state.

2. The digital automatic gain controller according to claim 1, wherein It also includes a counter X10 and a decoder X11; The frequency adjustment module configures the frequency f of the counting clock CK according to the working state of the digital automatic gain controller, the counting control signal COUNT to control the counting direction of the counter X10, and the sampling frequency fs CK , where The frequency f of the counting clock CK in the startup working state CK , is greater than the frequency f of the counting clock CK in the normal working state CK ; When the counting control signal COUNT controls the counter X10 to count up in the normal working state, the frequency f of the counting clock CK CK , is less than the frequency f of the counting clock CK when the counting control signal COUNT controls the counter X10 to count down CK ; The counter X10 generates a count value based on the count control signal COUNT and a count clock CK and outputs it to the decoder X11. The decoder X11 generates a gain control code group according to the count value.

3. The digital automatic gain controller according to claim 2, wherein The frequency adjustment module includes a first frequency divider X17. When the frequency control module controls the sampling frequency fs according to the working state of the digital automatic gain controller, it includes: The frequency control module outputs an enable signal ENN1 according to the working state of the digital automatic gain controller. The frequency adjustment module determines the sampling frequency fs according to the frequency f0 of the input clock CK_AGC input to the frequency adjustment module under the control of the enable signal ENN1. Among them, In the startup working state, the frequency control module outputs an enable signal ENN1 in the second level state. Under the control of the enable signal ENN1, the sampling frequency fs = f0; In the normal working state, the frequency control module outputs an enable signal ENN1 in the first level state. Under the control of the enable signal ENN1, the sampling frequency fs = f0 / N1, where N1 is the frequency division value of the first frequency divider X17.

4. The digital automatic gain controller according to claim 3, wherein The input module includes a NOR gate X12 and a NOT gate X13. Among them, The first input terminal of the NOR gate X12 is connected to the input signal AGC_IN, and the second input terminal of the NOR gate is connected to the enable signal ENN2; The output terminal of the NOR gate X12 is connected to the input terminal of the NOT gate X13. The output terminal of the NOT gate X13 is used to form the output terminal of the input module and is connected to the control terminal of the counter X10; When the digital gain controller works, it configures the enable signal ENN2 to be in the first level state and generates a count control signal COUNT through the output terminal of the input module. The level state of the count control signal COUNT is the same as the level state of the input signal AGC_IN; The frequency control module includes a power-on reset module X1, an AND gate X9, a NOT gate X2, a NOT gate X3, an RS flip-flop X4, a NAND gate X5, a NOT gate X6, a NAND gate X7, and a NAND gate X8. Among them, The input end of the power-on reset module X1 is connected to the inverted signal of the enable signal ENN0, and the Z0NS signal is generated according to the enable signal ENN0. The output end of the power-on reset module X1 is connected to the input end of the NOT gate X2. The output end of the NOT gate X2 is connected to the input end of the NOT gate X3. The reset end of the counter X10 is connected to the inverted signal of the output end of the NOT gate X2. The output end of the NOT gate X3 is connected to the reset R end of the RS flip-flop; The count value includes eight count digits. The first input end of the AND gate X9 is connected to the fifth count digit of the count value. The second input end of the AND gate X9 is connected to the sixth count digit of the count value. The output end of the AND gate X9 is connected to the set S end of the RS flip-flop. The output QN end of the RS flip-flop is connected to the second input end of the NAND gate X5; The first input end of the NAND gate X5 is connected to the output end of the input module to access the count control signal COUNT. The output end of the NAND gate X5 is connected to the input end of the NOT gate X6. The output end of the NOT gate X6 is connected to the second input end of the NAND gate X8. The first input end of the NAND gate X8 is connected to the output end of the NAND gate X7. The output end of the NAND gate X8 is connected to the second input end of the NAND gate X7. The first input end of the NAND gate X7 is connected to the inverted signal of the Z0NS signal. The output end of the NAND gate X7 is used to form the output end of the frequency control module for outputting the enable signal ENN1.

5. The digital automatic gain controller according to claim 3, characterized in that The frequency adjustment module includes a D flip-flop X14, a NOR gate X15, a NAND gate X16, a data selector X18, a NOT gate X19, a NOT gate X20, an OR gate X21, an AND gate X22, a NOT gate X23, and a second frequency divider X24, where The first input end of the NOR gate X15 is connected to the input clock CK_AGC with a frequency of f0. The second input end of the NOR gate X15 is connected to the enable signal ENN2. The output end of the NOR gate X15 is connected to the second input end of the NAND gate X16; The first input end of the NAND gate X16 is connected to the inverted signal of the enable signal ENN1. The output end of the NAND gate X16 is connected to the output end of the first frequency divider X17. The signal output from the output end of the first frequency divider X17 is inverted and then connected to the first input end of the OR gate X21; The second input end of the NAND gate X16 is connected to the first input end of the NAND gate X19. The second input end of the NAND gate X19 is connected to the input end of the NOT gate X20 and is connected to the enable signal ENN1. The signal output from the output end of the NAND gate X19 is inverted and then connected to the second input end of the OR gate X21. The output end of the OR gate X21 is connected to the first input end of the AND gate X22. The output end of the NOT gate X20 is connected to the second input end of the AND gate X22; The output terminal of the AND gate X22 is connected to the clock terminal of the D flip-flop X14 to output a sampling clock CLK with a frequency of the sampling frequency fs to the clock terminal of the D flip-flop X14. The output terminal of the AND gate X22 is also connected to the input terminal of the NOT gate X23 and the first input terminal of the multiplexer X18. The output terminal of the NOT gate X23 is connected to the input terminal of the second frequency divider X24. The output terminal of the second frequency divider X24 is connected to the second input terminal of the multiplexer X18. The output terminal of the multiplexer X18 is connected to the clock terminal of the counter; The input terminal of the D flip-flop X14 is connected to the output terminal of the output module to access the count control signal COUNT. The output terminal of the D flip-flop X14 is connected to the control terminal of the multiplexer X18.

6. The digital automatic gain controller according to claim 5, wherein When the count control signal COUNT controls the counter X10 to count up, the count control signal COUNT is in the second level state; when the count control signal COUNT controls the counter X10 to count down, the count control signal COUNT is in the first level state; The frequency adjustment module adjusts the frequency f of the counting clock CK of the counter X10 according to the working state of the digital automatic gain controller, the sampled count control signal COUNT to control the counting direction of the counter X10, and the sampling frequency fs CK When, it includes: The counting control signal COUNT is sampled by the D flip-flop X14 and output to the control terminal of the multiplexer X18 to control the frequency f of the counting clock CK output by the multiplexer X18 CK ; In the startup working state, the counting control signal COUNT in the second level state controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f of the counting clock CK CK = fs / N2 = f0 / N2, where N2 is the division value of the second frequency divider X24, and N1 > N2; When the counting control signal COUNT is in the second level state under the normal working condition, the counting control signal COUNT controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f of the counting clock CK CK = fs / N2 = f0 / N1N2; In the normal working state, when the counting control signal COUNT is in the first level state, the counting control signal COUNT controls the data selector X18 to select the clock signal input by the second input terminal as the counting clock CK, and the frequency f CK = fs = f0 / N1.

7. The digital automatic gain controller according to claim 2, wherein The gain control code group includes a first intermediate frequency gain control code IF_AGCA, a second intermediate frequency gain control code IF_AGCB, a third intermediate frequency gain control code IF_AGCC, and a radio frequency gain control code RF_AGC, where, The first intermediate frequency gain control code IF_AGCA, the second intermediate frequency gain control code IF_AGCB, and the radio frequency gain control code RF_AGC are generated based on the second to seventh count digits of the count value; The third intermediate frequency gain control code IF_AGCC is generated based on the zero and first count digits of the count value; The output order of each control code in the gain control code group includes: the third intermediate frequency gain control code IF_AGCC, the second intermediate frequency gain control code IF_AGCB, the radio frequency gain control code RF_AGC, and the first intermediate frequency gain control code IF_AGCA.

8. An OOK receiver, characterized in that, Including the digital automatic gain controller according to any one of claims 1-7; The OOK receiver further includes a comparator, a low noise amplifier, a mixer, an intermediate frequency filter, a variable gain amplifier module, a peak detector, and a limiter that are adaptively connected, where, The input terminal of the low noise amplifier accesses the input OOK signal. The input OOK signal is sequentially processed by the mixer, the intermediate frequency filter, the variable gain amplifier module, and the peak detector and then input to the limiter; The comparator compares the output signal of the limiter and the reference voltage and generates a comparison signal as the input signal AGC_IN of the digital automatic gain controller. The digital automatic gain controller generates a gain control code group according to the input signal AGC_IN. The gain control code group is used to adjust the gains of the mixer and the variable gain amplifier module.

9. The OOK receiver according to claim 8, wherein, The variable gain amplifier module includes a first variable gain amplifier sub-module and a second variable gain amplifier sub-module; The first variable gain amplifier sub-module includes m1 pre-stage variable gain amplifier units, and each pre-stage variable gain amplifier unit includes a variable gain amplifier and a first variable resistor array connected to the output terminal group of the variable gain amplifier; The first variable resistor array includes n1 / 2 switches and n1 resistors connected in series. Among the n1 resistors connected in series, the second terminal of the i-th resistor is connected to the first terminal of the (n1 - i + 1)-th resistor through the i-th switch, where 1 ≤ i ≤ n1 / 2; The second variable gain amplifier sub-module includes m2 post-stage variable gain amplifier units, and each post-stage variable gain amplifier unit includes a variable gain amplifier and a second variable resistor array connected to the output terminal group of the variable gain amplifier; The second variable resistor array includes n2 / 2 switches and n2 resistors connected in series. Among the n2 resistors connected in series, the second terminal of the j-th resistor is connected to the first terminal of the (n2 - j + 1)-th resistor through the j-th switch, where 1 ≤ j ≤ n2 / 2; The resistances of the n1 resistors in the first variable resistor array are equal, the resistances of the n2 resistors in the second variable resistor array are equal, and the resistance of the resistor in the second variable resistor array is greater than the resistance of the resistor in the first variable resistor array.

10. The OOK receiver according to claim 9, wherein The first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB are loaded into the first variable gain amplifier sub-module, and the third intermediate frequency gain control code IF_AGCC is loaded into the second variable gain amplifier sub-module; The first intermediate frequency gain control code IF_AGCA and the second intermediate frequency gain control code IF_AGCB together include m1n1 / 2 control digits, and the m1n1 / 2 control digits are respectively loaded into the control terminals of the m1n1 / 2 switches in the first variable gain amplifier sub-module; The third intermediate frequency gain control code IF_AGCC includes m2n2 / 2 control digits, and the m2n2 / 2 control digits are respectively loaded into the control terminals of the m2n2 / 2 switches in the second variable gain amplifier sub-module.

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