Nuclear power multi-device time synchronization and SOE recording system based on FPGA

Abstract

The invention discloses a nuclear power multi-device time synchronization and SOE recording system based on an FPGA, and relates to the technical field of time synchronization, the system comprises a control station, a device module in the control station comprises a first controller, a second controller and an IO module, the IO module comprises a DI module, and the DI module is divided into a DI universal acquisition module and a DI-SOE module; the first controller and the second controller select one path of time information from the two paths of time information as output time information; the first controller or the second controller updates local time according to the selected time information, and time slot broadcast time information is sent to the IO module in each bus period; after receiving the time slot broadcast time information, the IO module updates local time; and the DI-SOE module updates the local time by using the time information obtained in the last time slot of the time slot broadcast time information, so that the time synchronization of the nuclear power multiple devices can be realized, and the time accuracy of recording the SOE event is improved at the same time.

Description

Technical Field

[0001] This application relates to the technical field of time synchronization, and particularly to a nuclear power multi-device time synchronization and SOE recording system based on FPGA. Background Art

[0002] In the digital instrument control system (DCS) of a nuclear power plant, the role of the sequence of event (SOE) recording is to record the time and sequence of switch actions during an accident, providing an important basis for accident cause analysis. Effective management and maintenance can be carried out through the SOE data to distinguish the sequence of each important signal, especially the first-occurring fault, to diagnose and eliminate faults in a timely manner, and ensure the normal operation of the system.

[0003] The resolution of the digital instrument control system in a nuclear power plant is generally 1 ms. In the conventional design method, there is a pulse source that generates a pulse signal to the SOE acquisition module. The pulse source device records the second-level moment of the time jump, and the SOE acquisition device records the millisecond-level moment of the data. The two data are added to obtain the occurrence moment of the actual signal. The acquisition device records the millisecond-level moment and data by obtaining the pulse per second (PPS) signal. After the acquisition data bus transmits the data to the controller, the controller module stamps the acquisition data with a time mark, so there will be a deviation in time accuracy. If the sampling device does not receive the PPS pulse, there will be a problem of incorrect recording time. At the same time, there is a delay in the moment when multiple devices receive the PPS pulse, resulting in inconsistent references for multiple devices and ultimately inaccurate recording of the SOE moment. Summary of the Invention

[0004] The purpose of this application is to provide a nuclear power multi-device time synchronization and SOE recording system based on FPGA, which can realize the time synchronization of nuclear power multi-devices and improve the time accuracy of recording SOE events at the same time.

[0005] To achieve the above purpose, this application provides the following solutions: This application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA. The nuclear power multi-device time synchronization and SOE recording system based on FPGA includes: a control station, and the device modules in the control station include a first controller, a second controller, and an IO module. The IO module includes a DI module, and the DI module is divided into a DI general acquisition module and a DI-SOE module; each of the device modules uses FPGA. Both the first controller and the second controller collect two paths of time signals, and parse each path of time signals into time information; both the first controller and the second controller select one path of time information from the two paths of time information, and send the selected one path of time information in the form of time slot broadcast through two local buses in each bus cycle. Both the first controller and the second controller update the local time according to the selected one path of time information, and start the local time self-keeping. The IO module is used to perform redundant selection after receiving the time information of each time slot broadcast, and update the local time with the time information of time slot 0 parsed from the selected one path of time information, and start the local time self-keeping. The DI-SOE module is used to collect SOE events. The DI-SOE module updates the local time with the time information of the last time slot of the selected one path of time information, and starts the local time self-keeping. The DI-SOE module uses the local time after self-keeping as the recording time when collecting SOE events.

[0006] Optionally, the FPGA-based nuclear power multi-device time synchronization and SOE recording system further includes an engineer station. The engineer station is used to send the configuration information of the multi-device module configuration to the control station; the configuration information is used to distinguish each DI module into a DI general acquisition module or a DI-SOE module.

[0007] Optionally, both the two paths of time signals collected by the first controller and the second controller are IRIG-B codes.

[0008] Optionally, in terms of selecting one path of time information from the two paths of time signals, the first controller or the second controller specifically is used for: Judge whether the first path of time information is normal to obtain a first judgment result; the two paths of time information are the first path of time information and the second path of time information respectively. If the first judgment result is yes, use the first path of time information as the selected one path of time signal. If the first judgment result is no, judge whether the second path of time information is normal to obtain a second judgment result. If the second judgment result is yes, use the second path of time information as the selected one path of time signal. If the second judgment result is no, do not select time information.

[0009] Optionally, in terms of local time self-keeping, the first controller, the second controller and the IO module all perform self-keeping through the local crystal oscillator.

[0010] Optionally, the DI-SOE module includes a plurality of DI channels, and the SOE events collected by each DI channel are stored in a first-in first-out queue in the order of occurrence of the SOE events.

[0011] Optionally, the DI-SOE module and the DI general acquisition module share the bus bandwidth of the local bus.

[0012] Optionally, the bus bandwidth is 64 bytes; In the DI-SOE module, 32 DI channels altogether occupy 64 bytes. The first 8 bytes are the digital input values and quality information of the 32 DI channels, and the last 56 bytes are the SOE events; The DI general acquisition module includes 32 channels, and each channel is stored according to 2 bytes; Each SOE event is 8 bytes, and each SOE event includes time information, time stamp, channel value, quality bit and channel number.

[0013] Optionally, the device module further includes a communication module; The communication module is used to perform redundancy selection after receiving the time information of each time slot broadcast, and update the local time with the time information of the 0th time slot parsed from the selected time information, and start the local time self-keeping time.

[0014] Optionally, the first controller and the second controller communicate synchronously through S_LINK.

[0015] According to the specific embodiments provided by this application, the following technical effects are disclosed in this application: This application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA. Both the first controller and the second controller collect two channels of time signals and parse each channel of time signals into time information. The first controller and the second controller both select one channel of time information from the two channels of time information, and broadcast the selected one channel of time information in each bus cycle through two local buses. Both controllers update the local time according to the corresponding selected one channel of time information and start the local time self-keeping time, so that the input-output (IO) module receives redundant time information and improves the reliability of time synchronization. The DI-SOE module is used to collect SOE events. The DI-SOE module obtains the time information at the last time slot of the selected one channel of time information, updates the local time, and starts the local time self-keeping time. After the local time self-keeping time, the local time is used to collect the time when the SOE events are recorded, that is, this application improves the time accuracy of recording SOE events through redundant time information. In addition, the system of this application realizes multi-device time synchronization based on the hardware architecture of the field programmable gate array (FPGA) technology, does not rely on the microprocessor and software, improves the reliability of time synchronization, and at the same time improves the time accuracy of recording SOE events. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 FIG. is a schematic structural diagram of a nuclear power multi-device time synchronization and SOE recording system based on FPGA provided by an embodiment of the present application.

[0018] Figure 2 FIG. is a schematic diagram of the redundant B code hardware design provided by an embodiment of the present application.

[0019] Figure 3 FIG. is a schematic diagram of the controller time acquisition and L-BUS transmission provided by an embodiment of the present application.

[0020] Figure 4 FIG. is a schematic diagram of the time reception and time synchronization of other modules in the control station provided by an embodiment of the present application.

[0021] Figure 5Schematic diagram of a method for bus sharing of a nuclear power multi-device time synchronization and SOE recording system based on FPGA provided by an embodiment of the present application.

[0022] Figure 6 Schematic diagram of bus sharing allocation of the DI-SOE module provided by an embodiment of the present application.

[0023] Figure 7 Schematic diagram of bus sharing allocation of the DI general acquisition module provided by an embodiment of the present application.

[0024] Figure 8 Schematic diagram of an example of bus sharing allocation of the DI-SOE module provided by an embodiment of the present application. Detailed implementation manners

[0025] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0026] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0027] In an exemplary embodiment, the present application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA, as Figure 1 shown. The nuclear power multi-device time synchronization and SOE recording system based on FPGA includes: a control station. The device modules in the control station include a first controller, a second controller, a communication module, and an IO module. The IO module includes a digital input (Digital Input, DI) module. The DI module is divided into a DI general acquisition module and a DI-SOE module, that is, the DI module is a DI general acquisition module or a DI-SOE module. The first controller is the Figure 1 controller in the Figure 1 (slot 0), and the second controller is the

[0028] controller in the

[0029] Both the first controller and the second controller collect two paths of time signals and parse each path of time signals into time information. Both the first controller and the second controller select one path of time information from the two paths of time information, and in each bus cycle, broadcast the selected one path of time information through two local buses (Local-Bus, L_BUS).

[0030] Both the first controller and the second controller update the local time according to the selected one path of time information and start the local time self-timing.

[0031] The IO module is used to perform redundant selection after receiving the time information broadcast in each time slot, and update the local time with the time information of the 0th time slot parsed from the selected one path of time information, and start the local time self-timing. More specifically, the IO module will receive two paths of time information broadcast by each local bus, and receive a total of four paths of time information through the two local buses. Redundant selection is performed from the four paths of time information. The redundant selection is to use the time information that is first judged to be normal as the selected one path of time information. If there is no normal time information in the four paths of time information, no selection is made.

[0032] The communication module is used to perform redundant selection after receiving the time information broadcast in each time slot, and update the local time with the time information of the 0th time slot parsed from the selected one path of time information, and start the local time self-timing.

[0033] The DI-SOE module is used to collect SOE events. The DI-SOE module updates the local time with the time information of the last time slot of the selected one path of time information and starts the local time self-timing. The DI-SOE module uses the local time after self-timing as the recording time when collecting SOE events.

[0034] In an exemplary embodiment, the FPGA-based nuclear power multi-device time synchronization and SOE recording system further includes an engineer station.

[0035] The engineer station is used to send the configuration information of the multi-device module configuration to the control station; the configuration information is used to distinguish each DI module into a DI general acquisition module or a DI-SOE module.

[0036] In the download mode, the engineer station downloads the configuration information.

[0037] After the download is completed, the mode is switched to the operation mode. According to the configuration information, the DI module is configured as a DI general acquisition module or a DI-SOE module.

[0038] This application realizes the time synchronization of multiple devices in the DCS of the nuclear industry control field, SOE event recording, general digital input acquisition, and SOE acquisition bus sharing. The method of this application is a method for time synchronization of multiple devices in nuclear power DCS based on FPGA technology and bandwidth sharing between the DI general acquisition module and the DI-SOE module. That is, in the DCS control system in the nuclear industry control field, users can configure through the engineer station according to application requirements to achieve time synchronization of mixed insertion configuration of all device modules (including general acquisition modules and SOE modules) in the control station.

[0039] The functions of a nuclear power multi-device time synchronization and SOE recording system based on FPGA in this application are implemented by using the hardware chip of FPGA and the corresponding programming language of FPGA.

[0040] In an exemplary embodiment, both of the two time signals collected by the first controller and the second controller are IRIG-B codes.

[0041] In an exemplary embodiment, in terms of selecting one of the two time signals, the first controller or the second controller is specifically used for: 1) judging whether the first path of time information is normal to obtain a first judgment result; the two paths of time information are the first path of time information and the second path of time information respectively. 2) If the first judgment result is yes, then use the first path of time information as the selected time signal. 3) If the first judgment result is no, then judge whether the second path of time information is normal to obtain a second judgment result. 4) If the second judgment result is yes, then use the second path of time information as the selected time signal. 5) If the second judgment result is no, then no time information is selected.

[0042] Judging whether the first path of time information is normal and judging whether the second path of time information is normal are both judged according to the width of its code source and whether there is a code source.

[0043] If there is no code source for the first path of time information, it is determined that the first path of time information is abnormal. If the first path of time information has a code source and the code source of the first path of time information is within the preset width range, it is judged that the first path of time information is normal, otherwise it is determined that the first path of time information is abnormal. The method for judging whether the second path of time information is normal is the same as the method for judging the second path of time information.

[0044] In an exemplary embodiment, in terms of local time self-keeping time, the first controller, the second controller, the communication module, and the IO module all keep time by the local crystal oscillator.

[0045] In an exemplary embodiment, the DI-SOE module includes a plurality of DI channels, and the SOE events collected by each DI channel are stored in a First Input First Output (FIFO) queue in the order of occurrence of the SOE events.

[0046] In an exemplary embodiment, the DI-SOE module and the DI general acquisition module share the bus bandwidth.

[0047] In an exemplary embodiment, the bus bandwidth is 64 bytes.

[0048] Thirty-two DI channels in the DI-SOE module altogether occupy 64 bytes. The first 8 bytes are the digital input values and quality information of the 32 DI channels, and the last 56 bytes are the SOE events. The quality information is a quality bit.

[0049] The DI general acquisition module includes 32 channels, and each channel is stored according to 2 bytes.

[0050] In an exemplary embodiment, each SOE event is 8 bytes, and each SOE event includes time information, time stamp, channel value, quality bit, and channel number.

[0051] In an exemplary embodiment, the online controller communicates with the IO module through a local bus; the first controller and the second controller synchronously communicate through a redundant synchronization link (S_LINK).

[0052] The control station further includes a maintenance interface module. The engineer station communicates with the maintenance interface module through a maintenance link communication protocol (Maintenance Network, M-NET). The engineer station is used to send a download package and a maintenance package to the maintenance interface module. The download package includes configuration information. Each module in the control station communicates through a local maintenance communication bus (Maintenance -Bus, M-BUS).

[0053] In an exemplary embodiment, the working process of a nuclear power multi-device time synchronization and SOE recording system based on FPGA provided by this application is as follows.

[0054] In the first step, after the system is powered on, the user performs configuration of the mixed plug-in device module on the engineer station according to the system requirements. The mixed plug-in device module includes a first controller, a second controller, a communication module, an IO module (DI, DO, AI, AO, PI, PO), and among them, the DI module can be configured as a DI general acquisition module or a DI-SOE module (a module for collecting SOE events) through configuration to generate configuration information.

[0055] In the second step, in the download mode, the engineer station downloads the above configuration information. In the third step, after the download is completed, switch to the operation mode, power on and initialize all modules in the system, and obtain the above configuration information of the engineer station. Among them, the DI module needs to determine whether it is a DI-SOE acquisition module or a DI general acquisition module. There are 32 channels in total for the DI module.

[0056] In the fourth step, after all the above modules are initialized, the redundant controllers respectively collect redundant clock source signals. The redundant controllers include a first controller and a second controller. As Figure 2 shown, that is, on the controller A slot (slot 0) and the controller B slot (slot 1), redundant IRIGB codes (IRIGB0 and IRIGB1) are connected, and the physical layer is RS485. The time information parsing and sending of the first controller or the second controller are as Figure 3 shown. After receiving two IRIGB signals, the redundant controller performs de-redundancy selection processing, and broadcasts time information in the time slot on the L-BUS (the communication bus between the controller module and the communication module and the IO module) every cycle. The L-BUS is the communication bus between the controller and the communication module, and between the controller and the IO module. Controller A is the first controller, and controller B is the second controller.

[0057] 1. After the redundant controller receives two IRIGB signals, it respectively parses the time information of the two IRIGB signals through the IRIGB code (B code) parsing module.

[0058] 2. The parsed time information passes through the redundancy selection module, selects one path, and outputs the time information t0. The selection and output principle is: the two time information are respectively represented as path A and path B. If path A is normal, select path A; otherwise, check path B. If path B is normal, select path B; when both paths are incorrect, no time information is output.

[0059] The time status information includes: 1) After power-on, so far, no B code has been received. 2) After power-on, B code has been received, and the current normal or abnormal status of path A and path B.

[0060] 3. The time information t0 output by the above first controller and second controller enters the self-timing module to update the time and self-timing t1. The self-timing module outputs two paths of time information through two local buses. The time information output by the self-timing module and the two local buses is accurate to the microsecond (us) level. Similar to other IO modules, through the redundant local buses, the availability and reliability of the time information are guaranteed.

[0061] 1) After power-on, no time information is received, the current time is all 0, and the output time information t1 is 0.

[0062] 2) After power-on, upon receiving the time information t0, update according to the B-code accurate second, with the updated time being the time information t0, and start the self-timing t1.

[0063] 3) After power-on, when the B-code is disconnected after receiving the time information sent by the first controller and the second controller, self-time with the local crystal oscillator as t1', and the output time is t1'.

[0064] 4. The t1 time is sent on the L-BUS sending end (TX) module.

[0065] The controller sends the time information through the L-BUS bus every cycle. When it is controller A, at time slot 0, obtain the time information t1 of the current self-timing and send it on the L-BUS ACK frame, that is, send it on L-BUS ACK0. When it is controller B, obtain the time information t1 of the current self-timing and send it on the L-BUS ACK frame at time slot 12. The ACK frame is a control frame used to confirm the successful reception of data frames in a computer network. According to the predefined time slot technology of the control station, the sending time slots of a controller are 0 to 11, a total of 12 time slots; so the design of controller B is to send at the 12th time slot (L-BUS ACK12).

[0066] When the time information sent by the ACK frame is 0, it means it is not in time.

[0067] The fifth step is to receive and parse and synchronize the time information of other modules (communication module, IO module) in the control station, such as Figure 4 .

[0068] 1. After other modules (communication module, IO module) in the control station are successfully powered on initially, after receiving the L-BUS data of the controller, join the token bus ring and parse the redundant L-BUS ACK time information t1 of time slot 0 of controller A received.

[0069] 2. The parsed time information t1 passes through the redundant selection module to select one path of time information t1 and output the time status information.

[0070] 3. The above time information t1 enters the self-timing module (the time information is accurate to the microsecond level). If the time is valid, update the current time to the time information t1 and start self-timing t2 with the local crystal oscillator.

[0071] 4. For the DI-SOE module and the local time self-timing module, obtain the time information t2 at the last time slot of the L-BUS bus cycle, update the local time, and start the local time self-timing t3 for the SOE channel to mark the time. The local time is accurate to the microsecond level.

[0072] Among them, if the above DI module is configured as a DI-SOE acquisition module, the DI channel is used to acquire SOE events, and the SOE acquired by each channel is stored in the FIFO queue in the order of occurrence of the events.

[0073] The designed bus shared bandwidth is 64 bytes. The first 8 bytes are the acquisition values and quality information of 32 channels, that is, each digital input acquisition channel value uses 2 bits, and 32 channels altogether occupy 8 bytes; the latter 56 bytes are SOE events, and each SOE event is designed as 8 bytes. At most 7 SOE events are supported on the bus in a single cycle, as Figure 5 shown; the SOE event is designed to include time information, acquisition event information, channel information, and valid information, as shown in Table 1.

[0074] Table 1 DI-SOE event (56bit)

[0075] Since the FPGA uses parallel processing, μs in the above table is the resolution time, ensuring that the resolution of the SOE events acquired by the channels can reach μs.

[0076] A time flag of 0 indicates that the time information is normal.

[0077] If the above DI module is configured as a DI general acquisition module, the DI channel is used for general digital input acquisition. The 64-byte bus shared bandwidth is designed as 2 bytes per channel, and 32 channels altogether are 64 bytes, as Figure 6 .

[0078] According to the predefined time slot technology of the control station, when it is the bus transmission time slot of the DI module, the above 64 bytes are sent on the bus and transmitted to the first controller or the second controller to realize the bus sharing of the DI general acquisition module and the DI-SOE module.

[0079] The above steps realize the time synchronization of all device modules in the station and the SOE recording.

[0080] This application adopts FPGA technology and utilizes its parallel working principle to transmit μs-level time information on the bus. All modules on the bus can obtain accurate time (the delay time on the bus is less than μs level and can be ignored), and can achieve self-timing to realize the time synchronization of all devices in the station. The FPGA technology time synchronization can improve the resolution of SOE to μs level. At the same time, the hardware of the DI general quantity acquisition module and the DI-SOE module is the same, and it does not depend on the microprocessor and software, improving the stability of the system operation.

[0081] In an exemplary embodiment, this application provides a working process of a nuclear power multi-device time synchronization and SOE recording system based on FPGA as follows.

[0082] First step, after the system is powered on, the user performs mixed-module device plug-in configuration on the engineer station according to application requirements, such as Figure 1 , including a first controller, a second controller, a DI-SOE acquisition module with 8 DI-SOE channels, a DI-SOE acquisition module with 3 DI-SOE channels, a DI general module, a communication module, and other IO modules, to generate configuration information.

[0083] Second step, in the download mode, the engineer station downloads the above configuration information.

[0084] Third step, after the download is completed, switch the mode to the running mode, and all modules in the station are initialized to load the above configuration information of the engineer station.

[0085] Fourth step, the first controller starts to collect redundant B-code time for parsing and redundancy selection. The selected time information t0 is 78 days (March 19th) 9:50:30.015 seconds. The self-timing module of the first controller performs self-timing. According to the bus token ring time slot predefinition technology, the self-timing time information t1 output on the ACK frame of its L-BUS 0 time slot is 78 days (March 19th) 9:50:30.0182 seconds. The processing flow of the second controller is the same as that of the first controller in this step.

[0086] Fifth step, other modules on the L-BUS bus in the station (DI-SOE acquisition module with 8 DI-SOE channels, DI-SOE acquisition module with 3 DI-SOE channels, DI general module, communication module, other IO modules) receive the redundant L-BUS ACK data (t1: 78 days (March 19th) 9:50:30.0182 seconds) sent by the above controller in the 0 time slot. Each module is independent and performs time synchronization and self-timing respectively. If the self-timing module determines that the time is valid, it updates the time information t1 of the current time to 78 days (March 19th) 9:50:30.0182 seconds, and starts self-timing t2 with the local crystal oscillator.

[0087] Sixth step, for the DI-SOE acquisition module with 8 DI-SOE channels, the local time self-timing module obtains the time information t2 as 78 days (March 19th) 9:50:30.0332 seconds at the last time slot of the 15ms L-BUS bus cycle, updates the local time, and starts local time self-timing t3. Assume that in the next bus cycle, SOE events occur in Channel 1, Channel 12, Channel 3, and Channel 1 in sequence. Then each channel collects and obtains the time information t3 to record the SOE events of each channel, and stores them in the common FIFO in the order of event occurrence.

[0088] SOE1 (Channel 1): 78 days (March 19th), 9:50:30.330250 seconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 1.

[0089] The specific byte information of SOE event 1 is (001001110 01001 110010 011110 00001000010011111010 0 1 0 000001).

[0090] SOE2 (Channel 12): 78 days (March 19th), 9:50:30.34751 seconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 12.

[0091] The specific byte information of SOE event 2 is (001001110 01001 110010 011110 00001000101011101110 0 1 0 001100).

[0092] SOE3 (Channel 3): 78 days (March 19th), 9:50:30.35001 seconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 3.

[0093] The specific byte information of SOE event 3 is (001001110 01001 110010 011110 00001000110000000001 0 1 0 000011) SOE4 (Channel 1): 78 days (March 19th), 9:50:30.35100 seconds, time valid 0 (valid), channel value 0, channel quality bit 0 (good), channel number 1.

[0094] The specific byte information of SOE event 4 is (001001110 01001 110010 011110 00001000110001100100 0 0 0 000001).

[0095] 4 SOE events are stored in the FIFO in the order of occurrence, as Figure 6 shown.

[0096] According to the predefined time slot technology, when it is the bus transmission time slot of this module, the module will read the first 8 - byte channel data and the first 7 SOE events in the FIFO, and form 64 bytes to be sent to the bus. That is, 2 bits for each channel, 8 bytes for 32 channels in total, 8 bytes for each SOE event, 32 bytes for 4 SOE events, and the remaining bytes are 0. The data is as Figure 8 .

[0097] Step 7: For the DI general acquisition module, acquire digital input data and store it. The shared bandwidth is 64 bytes, with 2 bytes of data per channel (1 byte of channel data and 1 byte of quality bit), and a total of 64 bytes for 32 channels. For example, Figure 7 ; According to the predefined time slot technology, when it comes to the bus transmission time slot of this module, read the above-mentioned 64 bytes of data and send it on the bus.

[0098] The above steps achieve time synchronization for mixed insertion configuration of multiple nuclear power devices, general acquisition, and SOE bus sharing.

[0099] The module controlled by FPGA in this application is a platform based on "hard" logic, with high reliability and integrity. The system adopts a hardware architecture based on FPGA technology, transmits time information at the microsecond level on redundant buses, and performs time synchronization for the entire system every 15 ms of the operating cycle to achieve time synchronization for all devices within the system (including DI-SOE). The stable operation of the system does not depend on microprocessors and software. The resolution of DI-SOE generated based on FPGA control can reach the microsecond level, which is more accurate than the 1 ms resolution achieved by the CPU method.

[0100] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0101] Specific examples are used in this article to elaborate on the principle and implementation method of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, based on the idea of this application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A nuclear power multi-device time synchronization and SOE recording system based on FPGA, characterized in that, The FPGA-based nuclear power multi-device time synchronization and SOE recording system includes: a control station, and the device modules in the control station include a first controller, a second controller, and an IO module. The IO module includes a DI module, and the DI module is divided into a DI general acquisition module and a DI-SOE module; each of the device modules uses an FPGA; Both the first controller and the second controller collect two channels of time signals, and resolve each channel of time signals into time information; both the first controller and the second controller select one channel of time information from the two channels of time information, and send the selected one channel of time information in the form of a time slot broadcast through two local buses in each bus cycle; Both the first controller and the second controller update the local time according to the selected one channel of time information, and start the local time self-keeping time; The IO module is used to perform redundant selection after receiving the time information of each time slot broadcast, and update the local time with the time information of the 0th time slot parsed from the selected one channel of time information, and start the local time self-keeping time; The DI-SOE module is used to collect SOE events. The DI-SOE module updates the local time with the time information of the last time slot of the selected one channel of time information, and starts the local time self-keeping time. The DI-SOE module uses the local time after self-keeping time as the recording time when collecting SOE events.

2. The nuclear power multi-device time synchronization and SOE recording system based on FPGA according to claim 1, wherein The FPGA-based nuclear power multi-device time synchronization and SOE recording system further includes an engineer station; The engineer station is used to send the configuration information of the multi-device module configuration to the control station; the configuration information is used to distinguish each DI module as a DI general acquisition module or a DI-SOE module.

3. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein Both of the two channels of time signals collected by the first controller and the second controller are IRIG-B codes.

4. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, characterized in that In terms of selecting one channel of time information from the two channels of time signals, the first controller or the second controller specifically is used for: Judge whether the first channel of time information is normal, and obtain a first judgment result; the two channels of time information are the first channel of time information and the second channel of time information respectively; If the first judgment result is yes, then use the first channel of time information as the selected one channel of time signal; If the first judgment result is no, then judge whether the second channel of time information is normal, and obtain a second judgment result; If the second judgment result is yes, then use the second channel of time information as the selected one channel of time signal; If the second judgment result is no, then no time information is selected.

5. The nuclear power multi-device time synchronization and SOE recording system based on FPGA according to claim 1, characterized in that In terms of the local time self-keeping time, the first controller, the second controller, and the IO module all perform self-keeping time through a local crystal oscillator.

6. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, characterized in that The DI-SOE module includes a plurality of DI channels, and the SOE events collected by each DI channel are stored in a first-in first-out queue in the order of occurrence of the SOE events.

7. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, characterized in that, The DI-SOE module and the DI general acquisition module share the bus bandwidth of the local bus.

8. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 7, characterized in that, The bus bandwidth is 64 bytes; The 32 DI channels in the DI-SOE module altogether occupy 64 bytes. The first 8 bytes are the digital input acquisition values and quality information of the 32 DI channels, and the last 56 bytes are the SOE events; The DI general acquisition module includes 32 channels, and each channel is stored according to 2 bytes; Each SOE event is 8 bytes, and each SOE event includes time information, time annotation, channel value, quality bit and channel number.

9. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, characterized in that, The device module further includes a communication module; The communication module is used for performing redundancy selection after receiving the time information of each time slot broadcast, and updating the local time with the time information of the 0th time slot parsed from the selected time information, and starting the self-timing of the local time.

10. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, characterized in that, The first controller and the second controller communicate synchronously through S_LINK.

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