Sudoku difference readout CMOS image sensor based on spatial similarity

Abstract

The invention relates to the field of image sensors, and provides a sudoku difference readout CMOS image sensor based on spatial similarity, and the sensor comprises a key global module which is used for providing a time sequence control signal, a ramp signal and a bias voltage for a key column level module; the key column level module comprises a successive approximation type analog-to-digital converter and a monoclinic type analog-to-digital converter and is used for reading and processing the voltage value of each pixel in the pixel array according to the signals; wherein the pixel array is divided into a plurality of Sudoku units, and each Sudoku unit comprises a central pixel and eight peripheral pixels surrounding the central pixel; the successive approximation analog-to-digital converter is used for quantizing and reading out a central pixel; and the monoclinic analog-to-digital converter is used for quantizing and reading the difference between the peripheral pixels and the central pixel. The problem that extra power consumption and energy efficiency depend on image boundaries due to prediction errors in the prior art is solved, and a low-power-consumption and high-energy-efficiency CMOS image sensor without introducing extra power consumption overhead is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a complementary metal oxide semiconductor (CMOS) image sensor based on spatial similarity nine-square grid difference readout. Background Art

[0002] With the rapid development of the Internet of Things, mobile devices, wearable devices, and biomedical devices, low-power complementary metal oxide semiconductor (CMOS) image sensors have received great attention in these fields. Especially in applications such as remote imaging, intelligent monitoring, and medical imaging, the power consumption of image sensors has become one of the main limiting factors in the design. As the resolution of image sensors continues to increase, the power consumption problem has become more prominent, seriously affecting the battery life and performance of the device. Especially in smart Internet of Things applications, image sensors not only need to meet the requirements of low power consumption, but also need to process a large amount of image data, which further increases the burden of power consumption and data transmission. Therefore, how to reduce the power consumption of image sensors while ensuring image quality has become an important issue that the industry needs to solve urgently.

[0003] Existing CMOS image sensors usually use traditional analog-to-digital conversion and interface data transmission architecture, which will generate huge power consumption waste when processing a large amount of raw image signals. Especially in high-resolution image sensors, the analog-to-digital conversion and data transmission process consumes a lot of energy, resulting in low energy efficiency and high average power consumption of edge sensor nodes.

[0004] In order to deal with this problem, some difference readout algorithms based on image spatial similarity have been proposed in the prior art. They use the similarity between adjacent pixels to reduce the processing of redundant data, thereby reducing power consumption. For example, when reading a certain pixel, the multi-column parallel difference readout algorithm retains the most significant bit (MSB) conversion result of the previous pixel to reduce the MSB switching power consumption, thereby improving overall energy efficiency. However, this algorithm is prone to prediction errors at the image boundaries (i.e., areas with large differences between adjacent pixels), resulting in additional conversion power consumption overhead. In order to avoid prediction errors, existing solutions usually detect the difference before conversion, but this not only adds additional comparison cycles, but also fails to effectively reduce the total power consumption and fails to significantly improve the readout speed. Summary of the invention

[0005] The present invention provides a CMOS image sensor with nine-square grid difference readout based on spatial similarity, which solves the problems in the prior art of extra power consumption and energy efficiency dependence on image boundaries caused by prediction errors, and realizes a low-power and high-energy-efficiency CMOS image sensor that can work efficiently in various image scenes without introducing extra power consumption overhead.

[0006] The present invention provides a nine - grid difference - reading CMOS image sensor based on spatial similarity, comprising: A key global module for providing a timing control signal, a ramp signal, and a bias voltage to a key column - level module; The key column - level module, including a successive approximation analog - to - digital converter and a single - slope analog - to - digital converter, is used to read and process the voltage value of each pixel in a pixel array according to the timing control signal, the ramp signal, and the bias voltage, and quantize and read out the voltage value; wherein, the pixel array is divided into a plurality of nine - grid units, and each nine - grid unit includes a central pixel and eight peripheral pixels surrounding the central pixel; The successive approximation analog - to - digital converter is used for quantization and reading of the central pixel; The single - slope analog - to - digital converter is used for difference quantization and reading of the peripheral pixels and the central pixel.

[0007] For the nine - grid difference - reading CMOS image sensor based on spatial similarity provided by the present invention, the key column - level module further includes an analog multiplexer, an amplifier, and a chopper; The analog multiplexer, connected to the pixel array, is used to select and read out the corresponding column pixel signals of the nine - grid units in the pixel array according to a control signal; The successive approximation analog - to - digital converter is connected to the analog multiplexer and is used to perform quantization on the central pixel in terms of precision, including a comparator and being reused for comparison of the difference sign bit; The amplifier is connected to the successive approximation analog - to - digital converter and is used to match the least significant bit step size of the successive approximation analog - to - digital converter and the single - slope analog - to - digital converter; The chopper is connected to the amplifier and is used to determine whether to flip the output voltage signal of the amplifier according to the sign bit, and its output is sent to the single - slope analog - to - digital converter for quantization and reading; The single - slope analog - to - digital converter is connected to the chopper and is used to perform quantization on the difference between the peripheral pixel and the central pixel in terms of power consumption.

[0008] For the nine - grid difference - reading CMOS image sensor based on spatial similarity provided by the present invention, the key global module includes a row scan and global timing generation circuit, a global ramp generation circuit, and a global bias circuit; The row scan and global timing generation circuit is used to generate a timing control signal; The global ramp generation circuit is used to generate a ramp signal; The global bias circuit is used to generate the bias voltage for each module of the circuit.

[0009] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the input end of the analog multiplexer is connected to the pixel array, the control end is connected to the column selection signal, and the output end is respectively connected to the first input end of the successive approximation analog - to - digital converter and the amplifier.

[0010] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the input end of the successive approximation analog - to - digital converter is connected to the output end of the analog multiplexer, the first output end is connected to the second input end of the amplifier, and the second output end is used to output a digital signal with a first preset number of bits after quantifying the central pixel. The output end of the comparator in the successive approximation analog - to - digital converter is connected to the third input end of the chopper.

[0011] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the first input end of the amplifier is connected to the output end of the analog multiplexer, the second input end is connected to the first output end of the successive approximation analog - to - digital converter, the first output end is connected to the first input end of the chopper, and the second output end is connected to the second input end of the chopper.

[0012] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the first input end of the chopper is connected to the first output end of the amplifier, the second input end of the chopper is connected to the second output end of the amplifier, the third input end of the chopper is connected to the output end of the comparator in the successive approximation analog - to - digital converter, and the output end of the chopper is connected to the input end of the single - slope analog - to - digital converter.

[0013] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the input end of the single - slope analog - to - digital converter is connected to the output end of the chopper, and the output end is used to output a digital signal with a second preset number of bits after quantization.

[0014] The present invention provides a nine - grid difference reading method for the CMOS image sensor with nine - grid difference reading based on spatial similarity as described in any one of the above, including: Reading the first voltage value of the central pixel of the nine - grid unit and converting the first voltage value into a digital signal with a first preset number of bits; After completing the reading of the central pixel, reading the second voltage value of the pixel in the first column of the second row in the nine - grid unit, calculating the voltage difference between it and the central pixel, and amplifying the voltage difference through the amplifier; if the voltage difference is negative, inverting the output signal of the amplifier through the chopper to make the signal input to the single - slope analog - to - digital converter positive, and then converting the voltage difference into a digital signal through the single - slope analog - to - digital converter; Read the remaining peripheral pixels in the nine - grid unit in sequence according to the preset sequence rule, calculate the voltage difference between the remaining peripheral pixels and the central pixel, and convert the voltage difference into a digital signal with a second preset number of bits through a single - slope analog - to - digital converter.

[0015] According to the nine - grid difference reading method provided by the present invention, the preset sequence rule is that the row - by - row reading order is 2, 3, 1.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the nine - grid difference reading method as described in any one of the above is implemented.

[0017] The present invention also provides a non - transitory computer - readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the nine - grid difference reading method as described in any one of the above is implemented.

[0018] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the nine - grid difference reading method as described in any one of the above is implemented.

[0019] The nine - grid difference reading CMOS image sensor based on spatial similarity provided by the present invention has the following beneficial effects: By adopting the nine - grid difference reading algorithm based on spatial similarity, the CMOS image sensor can make full use of the similarity between adjacent pixels, significantly reduce the processing of redundant data, and thus effectively reduce power consumption. By combining the successive - approximation analog - to - digital converter (SAR ADC) and the single - slope analog - to - digital converter (SS ADC) in a two - step quantization method, the sensor can quickly and with low power consumption quantify the difference between the peripheral pixels and the central pixel while ensuring high - precision quantization of the central pixel, further improving energy efficiency. The present invention avoids the additional power consumption caused by the prediction error of the traditional difference reading algorithm at the image boundary, ensuring efficient operation in various image scenarios. Due to the unified management of the global timing control signal, ramp signal, and bias voltage, the design complexity of the sensor is not increased, and a balance between high frame rate and low power consumption can be achieved. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1It is a simplified diagram of the existing readout algorithm of the differential readout CMOS image sensor based on image spatial similarity provided by the present invention.

[0022] Figure 2 It is a schematic diagram of detecting prediction errors using two inserted capacitors provided by the present invention.

[0023] Figure 3 It is a structural composition diagram of a nine - grid difference readout CMOS image sensor based on spatial similarity provided by the present invention.

[0024] Figure 4 It is an overall working architecture diagram of a nine - grid difference readout CMOS image sensor based on spatial similarity provided by the present invention.

[0025] Figure 5 It is a schematic flow diagram of the nine - grid difference readout method provided by the present invention.

[0026] Figure 6 It is a schematic diagram of reading the central pixel of the nine - grid provided by the present invention.

[0027] Figure 7 It is a schematic diagram of reading the pixel in the first column of the second row provided by the present invention.

[0028] Figure 8 It is a schematic diagram of sequentially reading the remaining peripheral pixels in the nine - grid in order provided by the present invention.

[0029] Figure 9 It is a schematic diagram of a photo taken in actual test provided by the present invention.

[0030] Figure 10 It is a schematic diagram of the structure of an electronic device provided by the present invention. Specific embodiments

[0031] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0032] In recent years, low-power CMOS image sensors have been highly anticipated in many applications, including but not limited to remote imaging, mobile devices, wearable devices, and biomedical devices. In these applications, power consumption is one of the main design limitations, and as the resolution increases, power consumption plays an increasingly important role in restricting the performance of image sensors. Image sensors in intelligent Internet of Things applications face problems such as high power consumption, data redundancy, and small size. Traditional image sensing architectures result in a huge waste of power consumption during the analog-to-digital conversion and interface data transmission processes of a large number of raw image signals, leading to low effective energy efficiency and high average power consumption at the edge sensing nodes.

[0033] To reduce the power consumption of sensing nodes and improve the overall data processing energy efficiency, algorithms such as redundancy elimination algorithms, image preprocessing algorithms, and data compression need to be implemented in the internal part of the sensor, that is, in the analog signal domain, so as to greatly reduce the amount of data output from the sensor node and slow down the power consumption overhead of high-level image processing in the subsequent digital domain. By studying the input signal distribution characteristics of natural images, it can be found that the spatial difference of captured natural pictures is often very limited because for the same object in the image, the difference between pixels is relatively small. For example, in satellite images used for remote sensing applications, the difference between adjacent pixels is usually very small. In fact, in this case, sometimes the difference between most pixel values in the entire image is very small. In addition, due to the limitations of the optical system or camera resolution, the difference between adjacent pixel values will be further reduced.

[0034] By studying the sparse characteristics of pixel information in the time-space domain, a high-energy efficiency data conversion and compression technology based on image spatial similarity in the mixed signal domain is designed to reduce the readout of redundant data and simultaneously reduce the amount of data generated by the sensor node. At the same time, by using a single-slope analog-to-digital converter to quantify this relatively small difference between adjacent pixels, the conversion power consumption of the single-slope analog-to-digital converter can be effectively reduced, achieving an overall improvement in the energy efficiency of the CMOS image sensor.

[0035] Traditional differential readout algorithm schemes all have the possibility of prediction errors, introducing additional conversion power consumption overhead, which greatly restricts the overall energy efficiency improvement of CMOS image sensors. To avoid the additional power consumption overhead caused by prediction failures, the present invention proposes a novel pixel difference conversion scheme based on a nine-grid.

[0036] The present invention is the first solution that utilizes the information of all surrounding pixels for readout pixels, and this innovation significantly differentiates from previous works and technical solutions. In traditional related technologies, in order to achieve low power consumption and high energy efficiency, a differential readout algorithm based on image spatial similarity is usually adopted. These algorithms mainly rely on the information of the previous one or several pixels for prediction to save power consumption. For example, a simplified diagram of the readout algorithm of an existing differential readout CMOS image sensor based on image spatial similarity is as shown in Figure 1 shown. This is a multi-column parallel differential readout algorithm, that is, when reading a certain pixel, the MSB conversion result of the previous pixel is retained to achieve energy efficiency improvement. Taking j-column parallel (that is, j columns of pixels share one readout circuit such as an ADC) as an example, its pixel readout timing is as follows: start reading from the first row and the first column, and retain the MSB conversion result of this pixel after reading. When reading the first row and the second column, directly transfer the retained MSB conversion result to the capacitive digital-to-analog converter CDAC, and retain the MSB conversion result of this pixel after reading. And so on to the i-th row and the j-th column.

[0037] For CIS (CMOS image sensor) applications based on successive approximation type or single-slope type ADCs, this signal-predictive analog-to-digital converter readout algorithm saves the MSB switching power consumption, which accounts for a relatively large proportion in the total power consumption, compared with the traditional solution, and improves the overall energy efficiency. However, the problem with this solution is that prediction errors will occur at the boundaries of the readout image (that is, where the code values between adjacent pixels differ greatly). In order to avoid this situation in the above solution, the difference is detected before conversion, and the prediction error is detected by using two inserted capacitors (as shown in Figure 2 shown). That is, when the difference between the current pixel electrical signal and the MSB of the previous pixel electrical signal exceeds a certain range, this readout algorithm will perform quantization conversion again with the traditional solution, resulting in higher switching stable power consumption. At the same time, the additional comparison period for detecting the difference makes its total number of cycles not ultimately reduced, that is, it does not save the readout power consumption of the readout circuit and has no speed advantage either.

[0038] Existing solutions have problems such as additional power consumption caused by prediction errors, and the energy efficiency improvement effect highly depends on the number of boundaries in the image.

[0039] To avoid the power consumption problem caused by prediction errors, the present invention proposes a nine - grid difference read - out algorithm based on spatial similarity, which can further utilize the similarity between adjacent pixels without the power consumption cost of prediction failure and can effectively optimize the energy efficiency under various images. Different from previous solutions that only utilize the information of the previous one or several pixels, the present invention fully utilizes all the pixel information around the read - out pixel, that is, within a nine - grid range, in addition to the central pixel, its surrounding 8 pixels are also considered. In this way, the present invention utilizes the similarity between pixels to a greater extent, thereby improving the prediction accuracy and energy efficiency.

[0040] In terms of specific implementation, the present invention adopts a two - step SAR + SS ADC (Successive Approximation Register Analog - to - Digital Converter + Single - Slope Analog - to - Digital Converter) architecture. First, the central pixel is quantized and read out through the SAR ADC, and then the difference between the surrounding pixels and the central pixel is quantized. This difference quantization process is realized by the SS ADC. Since only the difference is quantized, the single - conversion cycle can be greatly reduced, and the frame rate can be increased. At the same time, due to the utilization of all the information of the surrounding pixels, the present invention can show a high energy - efficiency optimization under various images.

[0041] The following combines Figures 3 - 9 to specifically describe the embodiments of the present invention.

[0042] Figure 3 The present invention provides a schematic diagram of the composition of a nine - grid difference read - out CMOS image sensor based on spatial similarity, including: A key global module 310, which is used to provide timing control signals, ramp signals, and bias voltages for the key column - level module 120; The key column - level module 320, which includes a successive approximation register analog - to - digital converter and a single - slope analog - to - digital converter, is used to read and process the voltage values of each pixel in the pixel array according to the timing control signals, ramp signals, and bias voltages, and quantize and read out the voltage values; wherein, the pixel array is divided into multiple nine - grid units, and each nine - grid unit includes a central pixel and eight surrounding pixels around the central pixel; The successive approximation register analog - to - digital converter is used for the quantization and read - out of the central pixel; The single - slope analog - to - digital converter is used for the difference quantization and read - out between the surrounding pixels and the central pixel.

[0043] According to the nine - grid difference - readout CMOS image sensor based on spatial similarity provided by the present invention, the key column - level module further includes an analog multiplexer, an amplifier, and a chopper; the analog multiplexer is connected to the pixel array and is used to select and read out the corresponding column pixel signals of the nine - grid units in the pixel array according to a control signal; the successive - approximation analog - to - digital converter is connected to the analog multiplexer and is used to quantify the central pixel in terms of precision, including a comparator and the comparison reused for the difference sign bit; the amplifier is connected to the successive - approximation analog - to - digital converter and is used to match the least - significant - bit step of the successive - approximation analog - to - digital converter and the single - slope analog - to - digital converter; the chopper is connected to the amplifier and is used to decide whether to flip the output voltage signal of the amplifier according to the sign bit, and its output is sent to the single - slope analog - to - digital converter for quantization readout; the single - slope analog - to - digital converter is connected to the chopper and is used to quantify the difference between the peripheral pixel and the central pixel in terms of power consumption.

[0044] According to the nine - grid difference - readout CMOS image sensor based on spatial similarity provided by the present invention, the key global module includes a row scan and global timing generation circuit, a global ramp generation circuit, and a global bias circuit; the row scan and global timing generation circuit is used to generate timing control signals; the global ramp generation circuit is used to generate ramp signals; the global bias circuit is used to generate bias voltages for each module of the circuit.

[0045] Specifically, the readout timing control signals are generated by the global timing generation circuit. Compared with the traditional readout circuit scheme, no additional design complexity is introduced. The row scan and global timing generation circuit is used to generate timing control signals including a reset signal RST, a row selection signal TX, a row selection signal RS, and a column selection signal CS, etc.; the global ramp generation circuit is used for the column - level SSADC.

[0046] According to the nine - grid difference - readout CMOS image sensor based on spatial similarity provided by the present invention, the input end of the analog multiplexer is connected to the pixel array, the control end is connected to the column selection signal, and the output end is respectively connected to the first input end of the successive - approximation analog - to - digital converter and the amplifier.

[0047] According to the nine - grid difference - readout CMOS image sensor based on spatial similarity provided by the present invention, the input end of the successive - approximation analog - to - digital converter is connected to the output end of the analog multiplexer, the first output end is connected to the second input end of the amplifier, the second output end is used to output a digital signal of a first preset number of bits after quantifying the central pixel, and the output end of the comparator in the successive - approximation analog - to - digital converter is connected to the third input end of the chopper.

[0048] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the first input end of the amplifier is connected to the output end of the analog multiplexer, the second input end is connected to the first output end of the successive approximation analog - to - digital converter, the first output end is connected to the first input end of the chopper, and the second output end is connected to the second input end of the chopper.

[0049] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the first input end of the chopper is connected to the first output end of the amplifier, the second input end of the chopper is connected to the second output end of the amplifier, the third input end of the chopper is connected to the output end of the comparator in the successive approximation analog - to - digital converter, and the output end of the chopper is connected to the input end of the single - slope analog - to - digital converter.

[0050] According to the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the present invention, the input end of the single - slope analog - to - digital converter is connected to the output end of the chopper, and the output end is used to output a digital signal with a second preset number of bits after quantization.

[0051] Specifically, Figure 4 The following shows the overall working architecture diagram of the CMOS image sensor with nine - grid difference reading based on spatial similarity provided by the embodiments of the present invention. In this sensor, the row scanning and global timing generation circuit of the key global module is used to generate timing control signals, and the timing control signals include a reset signal RST, a row selection signal TX, a row selection signal RS, a column selection signal CS, etc.; the global ramp generation circuit is used for the column - level single - slope analog - to - digital converter SSADC; the global bias circuit is used to generate the bias voltages of each module of the circuit.

[0052] The key column - level module, the analog multiplexer MUX, selects and reads the corresponding column pixel signals according to the control signal; the successive approximation analog - to - digital converter SAR ADC is used for the quantization reading of the central pixel (the second row and the second column), and the internal comparator is reused for the comparison of the difference sign bit. The SSADC is used for the difference quantization reading of the peripheral pixels (except the second row and the second column in the nine - grid) and the central pixel. The amplifier A is used to match the least - significant - bit step sizes of the two ADCs. The chopper Chopper decides whether to flip the output voltage signal of the amplifier according to the sign bit, and its output is sent to the SS ADC for quantization reading.

[0053] Next, the nine - grid difference reading method provided by the present invention will be described. Figure 5 This is one of the schematic flowcharts of the nine - grid difference reading method provided by the present invention. As Figure 5 shown, the method includes the following steps: S510. Read the first voltage value of the central pixel of the nine - grid unit, and convert the first voltage value into a digital signal with a first preset number of bits.

[0054] S520. After completing the reading of the central pixel, read the second voltage value of the pixel in the first column of the second row in the nine - grid unit, calculate the voltage difference between it and the voltage of the central pixel, and amplify the voltage difference through an amplifier; if the voltage difference is negative, invert the output signal of the amplifier through a chopper so that the signal input to the single - slope analog - to - digital converter is positive, and then convert the voltage difference into a digital signal through the single - slope analog - to - digital converter.

[0055] S550. Sequentially read the remaining peripheral pixels in the nine - grid unit according to a preset order rule, calculate the voltage differences between the remaining peripheral pixels and the central pixel, and convert the voltage differences into digital signals with a second preset number of bits through the single - slope analog - to - digital converter.

[0056] Specifically, the working algorithm and circuit working steps and details are as follows: 1. As Figure 6 shown, in the read - out period of each nine - grid, first select through the control signals RST, TX, RS, and CS, and read the voltage value of the middle pixel (the second row and the second column) through an analog multiplexer. Its voltage value will be quantized by a 10 - bit successive - approximation register (SAR) ADC, and the digital signal DOUT_SAR<1:10> will be output.

[0057] 2. As Figure 7 shown, after completing the read - out of the middle pixel, select and read the voltage value of pixel 4 (the first column of the second row) through the control signal and the analog multiplexer. The difference between this voltage value and the voltage value of the middle pixel will be amplified by an amplifier, and the voltage value of the middle pixel will be given by DOUT_SAR<1:10> using the CDAC of the SAR ADC. If the difference is negative (the positive - negative judgment function is implemented by the comparator inside the multiplexed SAR ADC), the sign bit SGN will output 0, and the output of the amplifier will be inverted by the chopper to ensure that the input to the subsequent ADC is always positive. The amplified difference between the pixels will be read and quantized by an 8 - bit single - slope (SS) ADC, and the digital signal DOUT_SAR<1:8> will be output.

[0058] 3. As Figure 8 shown, 3. The voltage values of the remaining peripheral pixels will be sequentially selected and read through the control signal and the analog multiplexer. The row - column read - out order is both 2, 1, 3.

[0059] The present invention has been taped out and verified under the standard TSMC 180nm process. The pixel array size is 256×256, the pixel size is 10μm, and the ADC accuracy of the readout circuit is 10bit. At a power supply voltage of 3.3V / 1.8V and a frame rate of 380fps, the power consumption is about 22mW, and the obtained energy efficiency index is 883pJ / pixel.

[0060] Among them, the power consumption ratio of the pixel array is 40%, and the analog and digital parts of the readout circuit account for 47% and 13% respectively. Since this solution uses an 8-bit SSADC to quantize the surrounding pixels, the single conversion cycle is greatly reduced, so the frame rate is effectively increased. At the same time, the overall energy efficiency is also effectively improved. Figure 9 It is a photo actually taken by using this working circuit at a frame rate of 380 frames per second.

[0061] Figure 10 Illustrates a schematic physical structure diagram of an electronic device, as Figure 10 shown, the electronic device may include: a processor 1010, a communication interface 1020, a memory 1030, and a communication bus 1040. Among them, the processor 1010, the communication interface 1020, and the memory 1030 complete mutual communication through the communication bus 1040. The processor 1010 can call the logical instructions in the memory 1030 to execute the nine-grid difference readout method, which includes: reading the first voltage value of the central pixel of the nine-grid unit and converting the first voltage value into a digital signal of a first preset number of bits; After completing the reading of the central pixel, read the second voltage value of the pixel in the first column of the second row in the nine-grid unit, calculate the voltage difference between it and the voltage of the central pixel, and amplify the voltage difference through an amplifier; if the voltage difference is negative, invert the output signal of the amplifier through a chopper so that the signal input to the single-slope analog-to-digital converter is positive, and then convert the voltage difference into a digital signal through the single-slope analog-to-digital converter; Read the remaining surrounding pixels in the nine-grid unit in sequence according to a preset order rule, calculate the voltage differences between the remaining surrounding pixels and the central pixel, and convert the voltage differences into digital signals of a second preset number of bits through a single-slope analog-to-digital converter.

[0062] In addition, when the logical instructions in the above-mentioned memory 1030 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0063] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the nine-grid difference reading method provided by the above-mentioned various methods. The method includes: reading a first voltage value of the central pixel of the nine-grid unit and converting the first voltage value into a digital signal with a first preset number of bits; After completing the reading of the central pixel, read a second voltage value of the pixel in the first column of the second row in the nine-grid unit, calculate the voltage difference between it and the voltage of the central pixel, and amplify the voltage difference through an amplifier; if the voltage difference is negative, invert the output signal of the amplifier through a chopper so that the signal input to the single-slope analog-to-digital converter is positive, and then convert the voltage difference into a digital signal through the single-slope analog-to-digital converter; Read the remaining peripheral pixels in the nine-grid unit in sequence according to a preset order rule, calculate the voltage differences between the remaining peripheral pixels and the central pixel, and convert the voltage differences into digital signals with a second preset number of bits through the single-slope analog-to-digital converter.

[0064] In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the nine-grid difference reading method provided by the above-mentioned various methods. The method includes reading a first voltage value of the central pixel of the nine-grid unit and converting the first voltage value into a digital signal with a first preset number of bits; After the reading of the central pixel is completed, the second voltage value of the pixel in the first column of the second row in the nine-grid unit is read, the voltage difference between it and the central pixel is calculated, and the voltage difference is amplified by an amplifier; if the voltage difference is negative, the output signal of the amplifier is inverted by a chopper so that the signal input to the single-slope analog-to-digital converter is positive, and then the voltage difference is converted into a digital signal by the single-slope analog-to-digital converter; The remaining peripheral pixels in the nine-grid unit are sequentially read according to a preset sequence rule, the voltage differences between the remaining peripheral pixels and the central pixel are calculated, and the voltage differences are converted into digital signals with a second preset number of bits by the single-slope analog-to-digital converter.

[0065] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0066] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A nine - grid difference - reading complementary metal - oxide - semiconductor image sensor based on spatial similarity, characterized in that, Comprising: A key global module for providing a timing control signal, a ramp signal, and a bias voltage to a key column-level module; The key column-level module, including a successive approximation analog-to-digital converter and a single-slope analog-to-digital converter, is used to read and process the voltage value of each pixel in the pixel array according to the timing control signal, the ramp signal, and the bias voltage, and read out the voltage value after quantization; wherein, the pixel array is divided into a plurality of nine-square grid units, and each nine-square grid unit includes a central pixel and eight peripheral pixels surrounding the central pixel; The successive approximation analog-to-digital converter is used for the quantization readout of the central pixel; The single-slope analog-to-digital converter is used for the differential quantization readout of the peripheral pixels and the central pixel.

2. The complementary metal oxide semiconductor image sensor with nine-grid difference reading based on spatial similarity according to claim 1, wherein The key column-level module further includes an analog multiplexer, an amplifier, and a chopper; The analog multiplexer, connected to the pixel array, is used to select and read out the corresponding column pixel signals of the nine-square grid units in the pixel array according to a control signal; The successive approximation analog-to-digital converter is connected to the analog multiplexer and is used to perform quantization on the central pixel in terms of accuracy, including a comparator and being reused for the comparison of the differential sign bit; The amplifier is connected to the successive approximation analog-to-digital converter and is used to match the least significant bit step size of the successive approximation analog-to-digital converter and the single-slope analog-to-digital converter; The chopper is connected to the amplifier and is used to decide whether to invert the output voltage signal of the amplifier according to the sign bit, and its output is sent to the single-slope analog-to-digital converter for quantization readout; The single-slope analog-to-digital converter is connected to the chopper and is used to perform quantization on the difference between the peripheral pixel and the central pixel in terms of power consumption.

3. The complementary metal oxide semiconductor image sensor based on spatial similarity and with nine-grid difference reading according to claim 1, wherein The key global module includes a row scan and global timing generation circuit, a global ramp generation circuit, and a global bias circuit; The row scan and global timing generation circuit is used to generate a timing control signal; The global ramp generation circuit is used to generate a ramp signal; The global bias circuit is used to generate the bias voltage for each module of the circuit.

4. The complementary metal oxide semiconductor image sensor with nine-grid difference reading based on spatial similarity according to claim 2, characterized in that, The input end of the analog multiplexer is connected to the pixel array, the control end is connected to the column selection signal, and the output end is respectively connected to the first input ends of the successive approximation analog-to-digital converter and the amplifier.

5. The complementary metal oxide semiconductor image sensor based on spatial similarity and with nine-grid difference reading according to claim 2, wherein The input end of the successive approximation analog-to-digital converter is connected to the output end of the analog multiplexer, the first output end is connected to the second input end of the amplifier, the second output end is used to output a digital signal of a first preset number of bits after quantization of the central pixel, and the output end of the comparator in the successive approximation analog-to-digital converter is connected to the third input end of the chopper.

6. The complementary metal oxide semiconductor image sensor based on the nine-grid difference readout of spatial similarity according to claim 2, wherein, The first input end of the amplifier is connected to the output end of the analog multiplexer, the second input end is connected to the first output end of the successive approximation analog-to-digital converter, the first output end is connected to the first input end of the chopper, and the second output end is connected to the second input end of the chopper.

7. The complementary metal oxide semiconductor image sensor based on spatial similarity for nine-grid difference reading according to claim 2, characterized in that, The first input terminal of the chopper is connected to the first output terminal of the amplifier, the second input terminal of the chopper is connected to the second output terminal of the amplifier, the third input terminal of the chopper is connected to the output terminal of the comparator in the successive approximation analog-to-digital converter, and the output terminal of the chopper is connected to the input terminal of the single-slope analog-to-digital converter.

8. The complementary metal oxide semiconductor image sensor based on spatial similarity for nine-grid difference reading according to claim 2, characterized in that, The input terminal of the single-slope analog-to-digital converter is connected to the output terminal of the chopper, and the output terminal is used to output a digital signal with a second preset number of bits after quantization.

9. A nine-grid difference reading method for a complementary metal-oxide semiconductor image sensor based on spatial similarity according to any one of claims 1-8, characterized in that, Comprising: Reading the first voltage value of the central pixel of the nine-grid unit and converting the first voltage value into a digital signal with a first preset number of bits; After completing the reading of the central pixel, reading the second voltage value of the pixel in the first column of the second row in the nine-grid unit, calculating the voltage difference between it and the voltage of the central pixel, and amplifying the voltage difference through an amplifier; if the voltage difference is negative, inverting the output signal of the amplifier through a chopper so that the signal input to the single-slope analog-to-digital converter is positive, and then converting the voltage difference into a digital signal through the single-slope analog-to-digital converter; Sequentially reading the remaining peripheral pixels in the nine-grid unit according to a preset sequential rule, calculating the voltage differences between the remaining peripheral pixels and the central pixel, and converting the voltage differences into digital signals with a second preset number of bits through the single-slope analog-to-digital converter.

10. The nine-grid difference reading method according to claim 9, characterized in that, The preset sequential rule is that the row and column reading orders are both 2, 3, 1.

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