Timing synchronization method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a timing synchronization method and device, electronic equipment and a storage medium, relates to the technical field of communication, is applied to a receiving end, and comprises the following steps: calculating a timing phase deviation of a received signal based on a first position of the received signal; based on the timing phase deviation, calculating a timing jitter error and performing judgment adjustment on the first position to obtain a second position; and extracting a timing synchronization signal from the received signal based on the timing jitter error and the second position. By applying the technical scheme provided by the embodiment of the invention, the timing synchronization rate of the signal between the receiving end and the transmitting end is improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a timing synchronization method, apparatus, electronic device, and storage medium. Background Art

[0002] Non-terrestrial network communication has the characteristics of high dynamics and low signal-to-noise ratio. Under communication conditions with such characteristics, it is difficult for the timing synchronization technology based on the feedback structure to achieve fast timing synchronization for short burst signals in a short time, and it takes about dozens of symbols to converge when implementing the timing synchronization based on the feedback structure in engineering. This is the magnitude of the entire short burst signal, and the preamble data symbols of the short burst signal are relatively short. In this way, the timing synchronization will affect the optimal sampling of the data part symbols, thereby causing a decline in the performance of the communication system. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide a timing synchronization method, apparatus, electronic device, and storage medium to improve the timing synchronization rate of signals between the receiving end and the sending end. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of this application provide a timing synchronization method applied to a receiving end. The method includes:

[0005] Calculating the timing phase deviation of the received signal based on the first position of the received signal;

[0006] Calculating the timing jitter error and making a decision adjustment to the first position based on the timing phase deviation to obtain a second position;

[0007] Extracting a timing synchronization signal from the received signal based on the timing jitter error and the second position.

[0008] In some embodiments, the step of calculating the timing phase deviation of the received signal based on the first position of the received signal includes:

[0009] Reading a frame of signal starting from the first position of the received signal as a sample signal;

[0010] Calculating the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal.

[0011] In some embodiments, the step of calculating the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal includes:

[0012] Determining the sum of signals at n sampling points in the sample signal based on the amplitude and phase factor of the sample signal;

[0013] Perform an angular operation on the signal sum to obtain the timing phase deviation of the sample signal, which is used as the timing phase deviation of the received signal.

[0014] In some embodiments, the phase factor is obtained based on the length of the sample signal and the interpolation multiple when acquiring the received signal.

[0015] In some embodiments, the timing jitter error is obtained based on the timing phase deviation and the interpolation multiple when acquiring the received signal.

[0016] In some embodiments, the step of making a decision adjustment to the first position based on the timing phase deviation to obtain a second position includes:

[0017] If the timing phase deviation indicates that the first position is later than the starting position of the timing synchronization signal, then adjust the first position forward by a first preset position value to obtain the second position;

[0018] If the timing phase deviation indicates that the first position is earlier than the starting position of the timing synchronization signal, then adjust the first position backward by a second preset position value to obtain the second position.

[0019] In some embodiments, after obtaining the second position, the method further includes:

[0020] When the second position meets the adjustment condition, update the second position to a third preset value.

[0021] In some embodiments, the adjustment condition is that the starting position of the I-channel signal obtained by adjusting the second position based on a preset adjustment factor is less than the starting position of the received signal.

[0022] In some embodiments, when the absolute value of the timing phase deviation is less than or equal to a first preset value, it indicates that the first position is later than the starting position of the timing synchronization signal;

[0023] When the absolute value of the timing phase deviation is greater than or equal to a second preset value, it indicates that the first position is earlier than the starting position of the timing synchronization signal;

[0024] The first preset value is less than the second preset value.

[0025] In some embodiments, the step of extracting the timing synchronization signal from the received signal based on the timing jitter error and the second position includes:

[0026] Extract the I-channel signal and the Q-channel signal starting from the second position of the received signal;

[0027] Based on the timing jitter error, perform error correction on the I-channel signal and the Q-channel signal to obtain the timing synchronization signal.

[0028] In some embodiments, the timing synchronization method is used for the timing synchronization of short burst signals.

[0029] In some embodiments, the receiving end is a terminal or a network device.

[0030] In a second aspect, an embodiment of the present application provides a timing synchronization device, which is applied to a receiving end, and the device includes:

[0031] A first calculation module, configured to calculate a timing phase deviation of the received signal based on a first position of the received signal;

[0032] A second calculation module, configured to calculate a timing jitter error and perform a decision adjustment on the first position based on the timing phase deviation to obtain a second position;

[0033] An extraction module, configured to extract a timing synchronization signal from the received signal based on the timing jitter error and the second position.

[0034] In some embodiments, the first calculation module includes:

[0035] A reading sub-module, configured to start reading a frame of signal from the first position of the received signal as a sample signal;

[0036] A calculation sub-module, configured to calculate a timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal.

[0037] In some embodiments, the calculation sub-module is specifically configured to:

[0038] Determine a signal sum of n sampling points in the sample signal based on the amplitude and phase factor of the sample signal;

[0039] Perform an angle operation on the signal sum to obtain a timing phase deviation of the sample signal as the timing phase deviation of the received signal.

[0040] In some embodiments, the phase factor is obtained according to the length of the sample signal and the interpolation multiple when acquiring the received signal.

[0041] In some embodiments, the timing jitter error is obtained according to the timing phase deviation and the interpolation multiple when acquiring the received signal.

[0042] In some embodiments, the second calculation module is specifically configured to:

[0043] If the timing phase deviation indicates that the first position is later than the starting position of the timing synchronization signal, adjust the first position forward by a first preset position value to obtain a second position;

[0044] If the timing phase deviation indicates that the first position is earlier than the starting position of the timing synchronization signal, the first position is adjusted backward by a second preset position value to obtain a second position.

[0045] In some embodiments, the apparatus further includes:

[0046] An adjustment module, configured to update the second position to a third preset value when the second position meets an adjustment condition after obtaining the second position.

[0047] In some embodiments, the adjustment condition is that the starting position of the I-channel signal obtained by adjusting the second position based on a preset adjustment factor is less than the starting position of the received signal.

[0048] In some embodiments, that the absolute value of the timing phase deviation is less than or equal to a first preset value indicates that the first position is later than the starting position of the timing synchronization signal;

[0049] That the absolute value of the timing phase deviation is greater than or equal to a second preset value indicates that the first position is earlier than the starting position of the timing synchronization signal;

[0050] The first preset value is less than the second preset value.

[0051] In some embodiments, the extraction module is specifically configured to:

[0052] Extract an I-channel signal and a Q-channel signal starting from the second position of the received signal;

[0053] Perform error correction on the I-channel signal and the Q-channel signal based on the timing jitter error to obtain a timing synchronization signal.

[0054] In some embodiments, the timing synchronization device is used for timing synchronization of short burst data.

[0055] In some embodiments, the receiving end is a terminal or a network device.

[0056] In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0057] The memory is used to store a computer program;

[0058] The processor, when executing the program stored in the memory, implements the method steps described in any one of the first aspects above.

[0059] Fourthly, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method steps described in any one of the first aspects above are implemented.

[0060] Beneficial effects of the embodiments of the present application:

[0061] In the technical solution provided by the embodiment of the present application, the receiving end calculates the timing phase deviation of the received signal based on the first position of the received signal, and based on the timing phase deviation, calculates the timing jitter error and makes a decision adjustment on the first position to obtain the second position, and performs decimation sampling on the received signal based on the second position and the timing jitter error to obtain the timing synchronization signal. It can be seen that in the technical solution provided by the embodiment of the present application, the timing synchronization signal can be accurately obtained by using the feedforward method, without the need for interaction feedback between the receiving end and the sending end, which improves the timing synchronization rate of the signal between the receiving end and the sending end. Since the timing synchronization rate is improved, the sampling effect of the signal is also improved, that is, the demodulation performance of the signal is improved, thereby improving the data output rate, saving system hardware resources, reducing the system complexity, reducing the calculation amount, and improving the system performance.

[0062] Of course, it is not necessary for any product or method implementing the present application to achieve all the above advantages at the same time. Description of the drawings

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0064] Figure 1 It is the first flow diagram of the timing synchronization method provided by the embodiment of the present application;

[0065] Figure 2 It is a flow diagram of a method for calculating the timing phase deviation provided by the embodiment of the present application;

[0066] Figure 3 It is a refined flow diagram of step S22 provided by the embodiment of the present application;

[0067] Figure 4 It is a flow diagram of a method for decision adjustment of the first position provided by the embodiment of the present application;

[0068] Figure 5 It is the second flow diagram of the timing synchronization method provided by the embodiment of the present application;

[0069] Figure 6 It is a schematic diagram of a refined process of step S13 provided by an embodiment of the present application;

[0070] Figure 7 It is the third schematic diagram of the timing synchronization method provided by an embodiment of the present application;

[0071] Figure 8 It is a constellation diagram obtained without timing synchronization;

[0072] Figure 9 It is a constellation diagram obtained by performing timing synchronization using the technical solution provided by an embodiment of the present application;

[0073] Figure 10 It is a schematic structural diagram of a timing synchronization device provided by an embodiment of the present application;

[0074] Figure 11 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0075] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0076] For ease of understanding, the terms that appear in the embodiments of the present application are explained below.

[0077] Short burst transmission: In the communication process, the duration of the communication signal is very short. Terminals with non-terrestrial network communication functions such as smart phones and tablets can use the short burst transmission method to directly connect to non-terrestrial network nodes such as low-earth orbit satellites. Non-terrestrial network nodes include network nodes located in the air such as satellites, space stations, and drones. The communication signal transmitted during the short burst transmission is the short burst signal. To ensure the correct demodulation of the short burst signal, based on the characteristics of the short burst transmission, the non-terrestrial network node or the terminal needs to complete the timing synchronization and information transmission of the short burst signal within a very short time.

[0078] Non-terrestrial network communication: Communication within the signal coverage range of non-terrestrial network nodes such as satellites.

[0079] For the network communication service of a ground terminal, the terminal can support the ground network communication function only within the signal coverage area of the ground base station. However, for special scenarios such as deserts and seas where there are no ground base stations, it is particularly important for the terminal to support non-ground network communication functions. For example, when an emergency occurs, the terminal can send out a distress message through the non-ground network communication function. The non-ground network communication system has the characteristics of low latency and low cost. Combining it with the terminal application can realize satellite-ground voice call services and fill the gap in terminal communication services in special scenarios.

[0080] In special scenarios, such as when the terminal is directly connected to a non-ground network node in a low-earth orbit non-ground network communication system, the terminal uses short burst signals to communicate with the low-earth orbit non-ground network node. To ensure communication quality, the terminal or the non-ground network node needs to complete the timing synchronization and information transmission of the short burst signal within a very short time.

[0081] However, in non-ground network communication, due to the instability of the local clock and the relative motion between the terminal and the non-ground network node, the wireless link timing drifts, and there will be serious jitter in timing in scenarios with low signal-to-noise ratio. This will not only introduce inter-symbol interference (ISI), reduce the useful signal-to-noise ratio, but also bring difficulties to the subsequent carrier synchronization establishment. Therefore, accurately restoring the optimal sampling signal through timing synchronization technology plays an important role and significance in the accurate demodulation of the receiver of the non-ground network node or the terminal.

[0082] Timing synchronization algorithms include synchronous sampling clock recovery algorithms and asynchronous sampling clock recovery algorithms. Currently, asynchronous sampling clock recovery algorithms are mainly used in non-ground network communication, that is, by estimating the timing error and controlling the interpolation filter to find the optimal sampling point. Common timing error estimation algorithms include the early-late gate synchronization method, the OM (Oerder M Meyr H) algorithm, and the Gardner algorithm. The Gardner algorithm samples four sampling points for each symbol, and the computational complexity is between the early-late gate synchronization method and the OM algorithm. The biggest advantage is that it is insensitive to carrier frequency offset and phase offset and can be independent of carrier synchronization.

[0083] The technical research on the existing OM algorithm and Gardner algorithm mainly focuses on the timing synchronization technology based on the feedback structure. However, non-terrestrial network communication has the characteristics of high dynamics and low signal-to-noise ratio. Under the communication conditions with such characteristics, it is very difficult for the timing synchronization technology based on the feedback structure to achieve fast timing synchronization for short burst signals in a short time. Moreover, when the timing synchronization based on the feedback structure is implemented in engineering, it takes about dozens of symbols to converge, which is the magnitude of the entire short burst signal. The preamble data symbols of the short burst signal are relatively short, so the timing synchronization will affect the optimal sampling of the data part symbols, resulting in a decline in the performance of the non-terrestrial network communication system.

[0084] To solve the above problems, the embodiments of the present application provide a timing synchronization method for obtaining a timing synchronization signal, which is the above-mentioned optimal sampling signal and is the result obtained by accurately demodulating the short burst signal. This timing synchronization method is applied to the receiving end, and the receiving end receives the signal sent by the sending end. The receiving end can be a terminal or a network device. The terminal can be a smart phone, a tablet computer and other devices with non-terrestrial network communication functions. The network device includes non-terrestrial network nodes and terrestrial network nodes in the non-terrestrial network. The terrestrial network nodes include network nodes located on the ground such as gateway stations, signal base stations, and servers. For the convenience of description, the following will be described with an electronic device as the execution subject, which does not play a limiting role.

[0085] As Figure 1 shown, Figure 1 FIG. 10 is a first flow diagram of the timing synchronization method provided by the embodiments of the present application, which is applied to the receiving end. The method includes the following steps.

[0086] Step S11, calculate the timing phase deviation of the received signal based on the first position of the received signal.

[0087] Step S12, calculate the timing jitter error and make a decision adjustment on the first position based on the timing phase deviation to obtain the second position.

[0088] Step S13, extract the timing synchronization signal from the received signal based on the timing jitter error and the second position.

[0089] In the technical solution provided by the embodiment of the present application, the receiving end calculates the timing phase deviation of the received signal based on the first position of the received signal, and based on the timing phase deviation, calculates the timing jitter error and makes a decision adjustment on the first position to obtain the second position. The received signal is decimated and sampled based on the second position and the timing jitter error to obtain a timing synchronization signal. It can be seen that the technical solution provided by the embodiment of the present application can accurately obtain the timing synchronization signal by using the feedforward method, without the need for interaction and feedback between the receiving end and the sending end, improving the timing synchronization rate of the signal between the receiving end and the sending end. Since the timing synchronization rate is improved, the sampling effect of the signal is also improved, that is, the demodulation performance of the signal is improved, thereby improving the data output rate, saving system hardware resources, reducing the system complexity, reducing the amount of calculation, and thus improving the system performance.

[0090] In the above step S11, the received signal is the signal received by the electronic device at a preset symbol rate, which can be regarded as the signal obtained by interpolating the signal sent by the sending end. The interpolation multiple can be any preset multiple, and the interpolation multiple corresponds to the preset symbol rate. When the electronic device is a terminal, the received signal can be the signal received by the terminal from a low-earth orbit non-terrestrial network node or other non-terrestrial network nodes. When the electronic device is a low-earth orbit non-terrestrial network node, the received signal can be the signal received by the low-earth orbit non-terrestrial network node from the terminal or other network devices. The received signal can include short burst signals or other signals in non-terrestrial network communications. The first position is the rough acquisition frame header position in the received signal obtained according to a preset method, that is, the head position of the rough short burst signal. The timing phase deviation is the phase deviation between the received signal and the timing synchronization signal. Due to the different sampling frequencies and clock asynchronization between the electronic device and the end that sends the timing synchronization signal, a phase deviation is generated. In the embodiment of the present application, the electronic device can calculate the timing phase deviation of the received signal based on the first position of the received signal. For example, the electronic device can read the sample signal backward based on the first position of the received signal and calculate the timing phase deviation of the received signal based on the sample signal, or calculate the timing phase deviation in other ways, which is not limited here.

[0091] In the above step S12, since the received signal is a complex frequency signal, including an in-phase signal component and a quadrature signal component, there will be a certain error between the in-phase signal component and the quadrature signal component when the received signal is acquired, resulting in the synthesized signal being different from the timing synchronization signal, and it is necessary to correct it through the timing jitter error. In the embodiment of the present application, the timing jitter error can be obtained according to the timing phase deviation and the interpolation multiple when the received signal is acquired.

[0092] In the embodiments of the present application, the electronic device can determine whether the first position is the accurate head position of the timing synchronization signal according to the timing phase deviation. When the first position is inaccurate, after adjusting the first position to obtain the second position, subsequent extraction can be started from the second position of the received signal, so as to obtain the timing synchronization signal. In the embodiments of the present application, the electronic device can perform corresponding adjustments by determining the decision adjustment conditions satisfied by the timing phase deviation. The specific decision adjustment conditions can be set according to the actual situation and are not limited here.

[0093] In the above step S13, the timing synchronization signal is a signal extracted by the electronic device from the received signal based on the second position and the timing jitter error. The timing synchronization signal has the same sampling frequency as the signal transmitted by the transmitting end. In the embodiments of the present application, the electronic device extracts the received signal based on the extraction multiple, and the extraction multiple is the same as the interpolation multiple when obtaining the received signal, that is, the electronic device interpolates to obtain the received signal according to the interpolation multiple, and then extracts the received signal according to the extraction multiple to obtain the timing synchronization signal, so that the timing synchronization signal has the same sampling frequency as the signal transmitted by the transmitting end.

[0094] In the embodiments of the present application, the electronic device can directly extract a frame of signal, or extract it by components according to other methods. For specific details, please refer to the relevant descriptions below and will not be elaborated here. By adjusting the starting position of extracting the signal from the received signal, the obtained timing synchronization signal is time-synchronized with the signal transmitted by the transmitting end, and the obtained timing synchronization signal restores the signal transmitted by the transmitting end, that is, accurate demodulation of the signal is achieved.

[0095] In the embodiments of the present application, the above steps S11 - S13 executed by the electronic device are actually the feedforward method. That is, when obtaining the timing synchronization signal by the feedforward method, as long as the received signal is obtained, the timing synchronization signal of the signal transmitted by the transmitting end can be obtained through the above process. While the feedback method only detects the quality of the output timing synchronization signal and needs to adjust the demodulation model of the signal transmitted by the transmitting end according to the quality of the output signal. Dozens of symbols are required to achieve the convergence of the quality of the timing output signal during engineering implementation. The technical solution provided by the embodiments of the present application greatly improves the timing synchronization rate of the signal between the receiving end and the transmitting end compared with the existing feedback structure timing synchronization method. Due to the improvement of the timing synchronization rate, the sampling effect of the signal is improved, that is, the demodulation performance of the signal is improved, and then the data output rate is increased, saving system hardware resources, reducing the system complexity, reducing the calculation amount, and thus improving the system performance.

[0096] In some embodiments, the embodiments of the present application provide a method for calculating the timing phase deviation, as Figure 2 shown, the above step S11 may include the following steps.

[0097] Step S21: Read a frame of signal starting from the first position of the received signal as the sample signal.

[0098] Step S22: Calculate the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal.

[0099] In the technical solution provided by the embodiments of the present application, calculating the timing phase deviation of the received signal based on a frame of sample signal can quickly obtain the timing phase deviation of the received signal, thereby improving the timing synchronization rate, improving the signal sampling effect, that is, improving the demodulation performance of the signal, further improving the data output rate, saving system hardware resources, reducing system complexity, reducing the amount of calculation, and thus improving system performance.

[0100] In the above step S21, the sample signal is used to calculate the timing phase deviation of the received signal. The electronic device can read a frame of signal starting from the first position of the received signal as the sample signal. In the embodiments of the present application, the electronic device can directly read a frame of signal starting from the first position of the received signal, or read it by components, which is not limited herein.

[0101] In the above step S22, the electronic device can calculate the timing phase deviation of the sample signal based on the amplitude and phase factor of the sample signal as the timing phase deviation of the received signal.

[0102] In the embodiments of the present application, the amplitude of the sample signal can be obtained through an operation of taking the absolute value. In one example, the signal sent by the sending end is a short burst signal, and the length of the short burst signal is L data , the received signal is x(n), the interpolation multiple when obtaining the received signal is interp, the electronic device interpolates the signal sent by the sending end according to the interp multiple to obtain x(n), the first position is toa, the electronic device reads a frame of signal starting from the toa position of x(n) as the sample signal, and performs an amplitude operation on the sample signal to obtain s(n),

[0103] s(n) = abs(x(toa:interp*L data +toa - 1))

[0104] where abs() represents the operation of taking the absolute value (i.e., the amplitude operation), n = 0, 1,..., interp*L data -1, and s(n) is the amplitude of the sample signal.

[0105] In the embodiments of the present application, the phase factor of the sample signal can be obtained according to the phase factor of the received signal, or calculated according to the sample signal itself. The electronic device can use the Fourier transform to obtain the phase factor of the received signal or the phase factor of the sample signal.

[0106] In some embodiments, the phase factor of the sample signal can be obtained according to the length of the sample signal and the interpolation multiple when acquiring the received signal. In one example, the length of the sample signal is L data , and the interpolation multiple is interp, then the phase factor phase data can be obtained based on L rotation (n) is:

[0107]

[0108] where n = 0, 1, ……, interp * L data -1, and exp() represents the exponential operation.

[0109] In some embodiments, as Figure 3 shown, the above step S22 may include the following steps.

[0110] Step S31, determine the sum of the signals of n sampling points in the sample signal based on the amplitude and phase factor of the sample signal.

[0111] Step S32, perform an angular operation on the sum of the signals to obtain the timing phase deviation of the sample signal as the timing phase deviation of the received signal.

[0112] In the embodiments of the present application, by calculating the sum of the signals of n sampling points in the sample signal and performing an angular operation on the sum of the signals, the timing phase deviation of the received signal can be obtained more accurately. Furthermore, according to the timing phase deviation, the second position can be adjusted more accurately and a more accurate timing jitter error can be obtained, so that the timing synchronization signal extracted according to the timing jitter error and the second position is more accurate, that is, the sampling effect and demodulation performance of the signal are improved, and thus the system performance is improved.

[0113] In the above step S31, the sample signal includes n sampling points, n is the product of the interpolation multiple when acquiring the received signal and the length of the sample signal, the signal of each sampling point is the product of the amplitude of the sampling point and the phase factor, and the electronic device can obtain the sample signal according to the dot product of the amplitude and phase factor of the sample signal, and then determine the sum of the signals of n sampling points in the sample signal. In one example, the amplitude of the sample signal is s(n), and the phase factor of the sample signal is phase rotation (n), then the sample signal s’(n) = s(n).*phase rotation (n), where “.*” represents the multiplication of the corresponding elements of two matrices. The sum of the signals of n sampling points in the sample signal is s mag = sum(s’(n)), where sum() represents the summation operation.

[0114] In the above step S32, the product of the amplitude of the sample signal and the phase factor is a complex number. The electronic device performs an angle calculation on the sum of the signals in the complex form of the obtained n sampling points, and the timing phase deviation of the received signal can be obtained. In one example, the sum of the signals is s mag , and the timing phase deviation err phase is:

[0115]

[0116] where angle() represents the angle calculation operation.

[0117] In some embodiments, the embodiments of the present application further provide a method for determining and adjusting a first position. As Figure 4 shown, the determination and adjustment of the first position include the following steps.

[0118] Step S41: Based on the timing phase deviation, determine the sequence relationship between the first position and the starting position of the timing synchronization signal. If the first position is later than the starting position of the timing synchronization signal, execute step S42; if the first position is earlier than the starting position of the timing synchronization signal, execute step S43.

[0119] Step S42: Adjust the first position forward by a first preset position value to obtain a second position.

[0120] Step S43: Adjust the first position backward by a second preset position value to obtain a second position.

[0121] In the technical solution provided by the embodiments of the present application, the electronic device determines the sequence relationship between the first position and the starting position of the timing synchronization signal through the timing phase deviation, and then determines and adjusts the second position. The electronic device can extract the timing synchronization signal from the second position of the received signal more accurately, further improving the sampling effect and demodulation performance of the signal, and thus improving the system performance.

[0122] In the embodiments of the present application, since the timing phase deviation describes the phase deviation between the received signal and the signal transmitted by the transmitting end, the electronic device can determine whether the first position in the received signal is the same as the starting position of the timing synchronization signal by judging the magnitude of the timing phase deviation, so as to adjust the first position. The first preset position value can be set to natural numbers such as 1, 2, etc. The second preset position value can be set to natural numbers such as 1, 2, etc. The first preset position value and the second preset position value can be the same or different. The first preset position value and the second preset position value can be specifically set according to the actual situation and are not limited here.

[0123] In the above step S41, the electronic device determines the sequence relationship between the first position and the starting position of the timing synchronization signal based on the timing phase deviation. If the timing phase deviation indicates that the first position is later than the starting position of the timing synchronization signal, it means that the electronic device extracts the timing synchronization signal relatively late from the first position and cannot obtain a complete timing synchronization signal, which affects the sampling effect and demodulation performance of the timing synchronization signal. Then, step S42 is executed to adjust the first position forward by a first preset position value to obtain a second position;

[0124] If the timing phase deviation indicates that the first position is earlier than the starting position of the timing synchronization signal, it means that the electronic device extracts the timing synchronization signal relatively early from the first position and obtains invalid data, which affects the sampling effect and demodulation performance of the timing synchronization signal. Then, step S43 is executed to adjust the first position backward by a second preset position value to obtain a second position;

[0125] If the timing phase deviation indicates that the first position is the same as the starting position of the timing synchronization signal, there is no need to adjust the first position. The first position is directly used as the starting position of the timing synchronization signal, and the timing synchronization signal is extracted from the received signal based on the first position and the timing jitter error.

[0126] In some embodiments, the electronic device can set two thresholds, namely the first preset value and the second preset value, to determine the sequence relationship between the first position and the starting position of the timing synchronization signal according to the timing phase deviation: when the absolute value of the timing phase deviation is less than or equal to the first preset value, it indicates that the first position is later than the starting position of the timing synchronization signal; when the absolute value of the timing phase deviation is greater than or equal to the second preset value, it indicates that the first position is earlier than the starting position of the timing synchronization signal; the first preset value is less than the second preset value. In the embodiments of the present application, the first preset value and the second preset value can be set according to the actual situation, and it is required that both the first preset value and the second preset value are greater than 0, and the first preset value is less than the second preset value. In one example, the first position is toa, the first preset value is 0.125, and the second preset value is 0.375. Then, when the absolute value of the timing phase deviation satisfies less than or equal to 0.125, it indicates that toa is later than the starting position of the timing synchronization signal; when the absolute value of the timing phase deviation satisfies greater than or equal to 0.375, it indicates that toa is earlier than the starting position of the timing synchronization signal; when the absolute value of the timing phase deviation satisfies between 0.125 and 0.375 or between -0.375 and -0.125, it indicates that toa is the same as the starting position of the timing synchronization signal, and there is no need to adjust toa. The timing synchronization signal is extracted from the received signal based on toa and the timing jitter error.

[0127] In some embodiments, the embodiments of the present application further provide a timing synchronization method, as Figure 5 shown, and this method includes the following steps.

[0128] Step S51: Calculate the timing phase deviation of the received signal based on the first position of the received signal. This is the same as step S11 above.

[0129] Step S52: Calculate the timing jitter error based on the timing phase deviation and determine the order relationship between the first position and the starting position of the timing synchronization signal. If the first position is later than the starting position of the timing synchronization signal, execute step S53; if the first position is earlier than the starting position of the timing synchronization signal, execute step S54. Reference can be made to step S12 and step S41 above.

[0130] Step S53: Adjust the first position forward by a first preset position value to obtain a second position, and execute step S55. Reference can be made to step S42 above.

[0131] Step S54: Adjust the first position backward by a second preset position value to obtain a second position, and execute step S55. Reference can be made to step S43 above.

[0132] Step S55: Determine whether the second position meets the adjustment condition. If so, execute step S56; if not, execute step S57.

[0133] Step S56: Update the second position to a third preset value, and execute step S57.

[0134] Step S57: Extract the timing synchronization signal from the received signal based on the timing jitter error and the second position. This is the same as step S13 above.

[0135] In the technical solution provided by the embodiment of the present application, since the second position obtained after the electronic device makes a judgment and adjustment on the first position may not exist or be unreasonable, in order to make the second position after the judgment and adjustment more accurate, so as to obtain a more accurate timing synchronization signal, the electronic device can set an adjustment condition. When the second position does not exist or is unreasonable, update the second position to a third preset value that exists and is reasonable, so as to improve the signal sampling effect, that is, improve the signal demodulation performance, and then improve the data output rate, save system hardware resources, reduce the system complexity, reduce the calculation amount, and thus improve the system performance.

[0136] In the embodiment of the present application, the step of calculating the timing jitter error in step S52 and the steps of making a judgment and adjustment on the first position to obtain the second position in steps S52 to S56 do not have a sequence. Just obtain the second position and the timing jitter error respectively before step S57.

[0137] In the above step S55, after the electronic device obtains the second position through decision adjustment, it determines whether the second position meets the adjustment condition. If it meets, it executes step S56 to update the second position to a third preset value, and then executes step S57 to extract the timing synchronization signal from the received signal according to the timing jitter error and the updated second position. If it does not meet, there is no need to adjust the second position, and step S57 is executed to extract the timing synchronization signal according to the second position and the timing jitter error.

[0138] In the above step S56, the third preset value is a relatively reasonable and existing position in the received signal. For example, the third preset value can be set to 1. Since the second position obtained after the decision adjustment in the above steps S52 to S54 may not exist or be unreasonable, in order to make the second position after the decision adjustment more accurate, so as to obtain a more accurate timing synchronization signal, in the embodiments of the present application, the electronic device can set an adjustment condition. When the second position does not exist or is unreasonable, the second position is updated to the position indicated by the reasonable and existing third preset value in the received signal.

[0139] In some embodiments, the adjustment condition in the above step S55 may be: the starting position of the I-channel signal obtained after adjusting the second position based on a preset adjustment factor is less than the starting position of the received signal. In the embodiments of the present application, the preset adjustment factor can be set according to the actual situation, such as natural numbers such as 1, 2, etc., which are not limited here. In one example, the preset adjustment factor is set to mk = 1, the second position is poe, and the starting position of the received signal is 1. When the starting position of the I-channel signal obtained after adjusting the second position based on the preset adjustment factor 1 is poe + mk - 1 < 1, the second position meets the adjustment condition, and the second position is updated to the third preset value, such as natural numbers such as 1, 2, etc., which are not limited here and only need to meet the actual requirements.

[0140] In some embodiments, as Figure 6 shown, the above step S13 may include the following steps.

[0141] Step S61, extract the I-channel signal and the Q-channel signal starting from the second position of the received signal.

[0142] Step S62, based on the timing jitter error, correct the errors of the I-channel signal and the Q-channel signal to obtain the timing synchronization signal.

[0143] In the technical solution provided by the embodiments of the present application, the electronic device extracts the I-channel signal and the Q-channel signal starting from the second position after the decision adjustment, and corrects the errors of the extracted I-channel signal and Q-channel signal to obtain the timing synchronization signal, further improving the sampling effect of the signal, that is, improving the demodulation performance of the signal and improving the system performance.

[0144] In the above step S61, the received signal is a complex frequency signal, including an I-channel signal and a Q-channel signal. The I-channel signal is the in-phase signal component, and the Q-channel signal is the quadrature signal component. The electronic device extracts the I-channel signal and the Q-channel signal starting from the second position of the received signal, and a complete complex frequency signal can be formed.

[0145] In the above step S62, since there may be certain errors in the I-channel signal and the Q-channel signal respectively, resulting in the synthesized signal being out of sync with the signal transmitted by the transmitting end, the electronic device needs to correct the errors of the I-channel signal and the Q-channel signal based on the timing jitter error, and then obtain the timing synchronization signal.

[0146] In one example, the I-channel signal and the Q-channel signal extracted by the electronic device from the received signal are respectively:

[0147] x i ′ (n) = x(poe + mk - 1:interp:interp*L data + poe + mk - 2)

[0148] x ′ q (n) = x(poe + mk:interp:interp*L data + poe + mk - 1)

[0149] where, x i ′ (n) is the I-channel signal, x ′ q (n) is the Q-channel signal, poe is the second position, mk is the adjustment factor, interp is the extraction multiple, which is the same as the interpolation multiple when obtaining the received signal, and n = 0, 1,..., L data - 1.

[0150] The electronic device obtains the error (i.e., the timing jitter error) according to the timing phase deviation and the extraction multiple as:

[0151] err0 = interp*err phase - round(interp*err phase )

[0152] where, err0 is the timing jitter error, interp is the extraction multiple, err phase is the timing phase deviation, and round() represents the rounding operation.

[0153] The electronic device corrects the errors of the I-channel signal and the Q-channel signal according to the timing jitter error err0, and the obtained timing synchronization signal x ′ (n) is:

[0154] x ′ (n) = (1 - err0) * x i ′ (n) + err0 * x ′ q (n)

[0155] where n = 0, 1, ……, L data -1, the sampling frequency of the timing synchronization signal is the same as that of the signal sent by the sending end.

[0156] To more clearly illustrate the above timing synchronization method, an embodiment of the present application provides a flowchart of a timing synchronization method as shown in Figure 7 shown, which may include the following steps.

[0157] Step a1, the electronic device captures the received data, that is, the electronic device obtains the received signal.

[0158] Step a2, based on the captured frame header position toa, the electronic device reads a frame of sample data from the received data and performs an amplitude operation. The captured frame header position is the first position, that is, the electronic device starts reading a frame of signal from the first position of the received signal as the sample signal and calculates the amplitude of the sample signal.

[0159] Step a3, based on the length of a frame of sample data, multiplying by -2π can obtain the phase factor.

[0160] Step a4, based on the product of the amplitude of the sample signal and the phase factor, the electronic device obtains the sample signal.

[0161] Step a5, the electronic device performs a summation operation on the sample signal to obtain the signal sum, that is, determines the signal sum of the sampling points in the sample signal.

[0162] Step a6, the electronic device performs an angle calculation on the signal sum to obtain the timing phase deviation, that is, calculates the timing phase deviation.

[0163] Steps a2 to a6 can refer to the relevant descriptions in the above steps S11, steps S21 to S22, and steps S31 to S32.

[0164] Step a7, based on the timing phase deviation, the electronic device makes a decision adjustment on the captured frame header position to obtain a new captured frame header position, that is, the above step S12. Based on the timing phase deviation, a decision adjustment is made on the first position to obtain the second position.

[0165] Step a8, based on the new captured frame header position obtained after the decision adjustment, the electronic device extracts the I-channel data (i.e., the I-channel signal) and the Q-channel data (i.e., the Q-channel signal) from the received data, that is, the above step S61.

[0166] Step a9, the electronic device calculates the timing jitter error based on the timing phase deviation, and adjusts and sums the I-channel data and the Q-channel data according to the timing jitter error to obtain a timing output signal (i.e., a timing synchronization signal). Refer to the above steps S11 and S62.

[0167] In one example, the timing synchronization process of the electronic device for short burst data is as follows.

[0168] Step b1: The electronic device captures the received data x(n), where the received data includes a short burst signal with a length of L. data , the interpolation multiple interp is 4, the adjustment factor mk is set to 1, and the captured frame header position is toa.

[0169] Step b2: Based on the captured frame header position toa, the electronic device reads a frame of sample data from the received data x(n) and performs an amplitude operation to obtain s(n). The calculation expression is:

[0170] s(n) = abs(x(toa:interp*L data +toa - 1))

[0171] where s(n) is the amplitude of the sample data, and abs() represents the absolute value operation; n = 0, 1,..., interp*L data - 1.

[0172] Step b3: Based on the length of a frame of sample data, the electronic device multiplies by -2π to obtain the phase factor phase rotation (n). The calculation expression is:

[0173]

[0174] where exp() represents the exponential operation; j represents the complex factor.

[0175] Step b4: Based on the sample data amplitude s(n) and the phase factor phase rotation (n), the electronic device can obtain the sample signal s'(n). The calculation expression is:

[0176] s'(n) = s(n).*phase rotation (n)

[0177] where ".*" represents the element-by-element multiplication of two matrices.

[0178] Step b5: The electronic device sums the signal s'(n) to obtain the signal sum s mag , and the calculation expression is:

[0179] smag = sum(s’(n))

[0180] where sum() represents the summation operation.

[0181] Step b6: The electronic device is based on the signal and s mag The required timing phase deviation err can be obtained phase , and its calculation expression is:

[0182]

[0183] where angle() represents the angle calculation operation.

[0184] Step b7: The electronic device is based on the timing phase deviation err phase , and makes a decision adjustment on the captured frame header position toa to poe.

[0185] Step b8: The electronic device performs numerical decimation by a factor of interp on the received data x(n) based on the decision-adjusted poe, and obtains the I-channel data x i ′ (n) and the Q-channel data x ′ q (n), and its calculation expression is:

[0186] x i ′ (n) = x(poe + mk - 1:interp:interp*L data + poe + mk - 2)

[0187] x ′ q (n) = x(poe + mk:interp:interp*L data + poe + mk - 1)

[0188] Step b9: The electronic device adjusts the I-channel and Q-channel data based on the timing jitter error value of the timing phase deviation err phase and sums them to obtain the timing output signal x’(n).

[0189] The above step b7 may include the following steps:

[0190] Step c1: If the timing phase deviation err phase satisfies err phase ≤ 0.125 and err phase ≥ -0.125, then:

[0191] poe = toa - 1;

[0192] Step c2: If the timing phase deviation errphase Satisfy err phase ≥0.375 or err phase ≤ -0.375, then:

[0193] poe = toa + 1;

[0194] Step c3: If the poe adjusted by the decision satisfies poe + mk - 1 ≤ 0, then:

[0195] poe = 1.

[0196] The above step b9 may include the following steps:

[0197] Step d1: The electronic device calculates the timing jitter error err0 based on the timing phase deviation err phase The calculation expression is as follows:

[0198] err0 = interp * err phase - round(interp * err phase )

[0199] where round() represents the rounding operation.

[0200] Step d2: The electronic device obtains the timing synchronization signal x i ′ (n) and the Q-channel data x ′ q (n), and the timing jitter error err0, and its calculation expression is as follows: ′ The calculation expression is as follows:

[0201] x ′ (n) = (1 - err0) * x i ′ (n) + err0 * x ′ q (n)

[0202] where n = 0, 1, ……, L data - 1.

[0203] In an example, taking the L-band application and the short burst information rate of 800 bps as an example, the timing synchronization of the signal is obtained without performing timing synchronization and applying the timing synchronization method provided in the embodiment of the present application respectively Figure 8 and Figure 9 The shown BPSK constellation diagrams, Figure 8 is the BPSK (Binary Phase Shift Keying) constellation diagram without timing synchronization, Figure 9The BPSK constellation diagram for timing synchronization using the technical solution provided by the embodiment of the present application. Starting from Figure 8 and Figure 9 As can be seen from the simulation results shown, after adopting the technical solution provided by the embodiment of the present application, the signal converges faster and the synchronization efficiency is higher.

[0204] Corresponding to the above timing synchronization method, as Figure 10 shown, the embodiment of the present application also provides a timing synchronization device, which is applied to the receiving end. The device includes:

[0205] The first calculation module 101 is configured to calculate the timing phase deviation of the received signal based on the first position of the received signal;

[0206] The second calculation module 102 is configured to calculate the timing jitter error and perform a decision adjustment on the first position based on the timing phase deviation to obtain a second position;

[0207] The extraction module 103 is configured to extract the timing synchronization signal from the received signal based on the timing jitter error and the second position.

[0208] In the technical solution provided by the embodiment of the present application, the receiving end calculates the timing phase deviation of the received signal based on the first position of the received signal, and based on the timing phase deviation, calculates the timing jitter error and performs a decision adjustment on the first position to obtain a second position. The received signal is extracted and sampled based on the second position and the timing jitter error to obtain the timing synchronization signal. It can be seen that the technical solution provided by the embodiment of the present application can accurately obtain the timing synchronization signal by using the feedforward method, without the need for interaction and feedback between the receiving end and the sending end, improving the timing synchronization rate of the signal between the receiving end and the sending end. Since the timing synchronization rate is improved, the sampling effect of the signal is also improved, that is, the demodulation performance of the signal is improved, thereby improving the data output rate, saving system hardware resources, reducing the system complexity, reducing the calculation amount, and thus improving the system performance.

[0209] In some embodiments, the first calculation module 101 may include:

[0210] The reading sub-module is configured to start reading a frame of signal from the first position of the received signal as a sample signal;

[0211] The calculation sub-module is configured to calculate the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal.

[0212] In some embodiments, the calculation sub-module may specifically be configured to:

[0213] Based on the amplitude and phase factor of the sample signal, determine the sum of the signals of n sampling points in the sample signal;

[0214] Perform an angular operation on the signals sum to obtain the timing phase deviation of the sample signal, which is used as the timing phase deviation of the received signal.

[0215] In some embodiments, the phase factor can be obtained based on the length of the sample signal and the interpolation multiple when acquiring the received signal.

[0216] In some embodiments, the timing jitter error can be obtained based on the timing phase deviation and the interpolation multiple when acquiring the received signal.

[0217] In some embodiments, the second calculation module 102 can specifically be used for:

[0218] If the timing phase deviation indicates that the first position is later than the starting position of the timing synchronization signal, then adjust the first position forward by a first preset position value to obtain a second position;

[0219] If the timing phase deviation indicates that the first position is earlier than the starting position of the timing synchronization signal, then adjust the first position backward by a second preset position value to obtain a second position.

[0220] In some embodiments, the above-mentioned timing synchronization device may further include:

[0221] An adjustment module, configured to update the second position to a third preset value when the second position meets the adjustment condition after obtaining the second position.

[0222] In some embodiments, the adjustment condition may be: the starting position of the I-channel signal obtained by adjusting the second position based on a preset adjustment factor is less than the starting position of the received signal.

[0223] In some embodiments, that the absolute value of the timing phase deviation is less than or equal to a first preset value may indicate that the first position is later than the starting position of the timing synchronization signal;

[0224] That the absolute value of the timing phase deviation is greater than or equal to a second preset value may indicate that the first position is earlier than the starting position of the timing synchronization signal;

[0225] The first preset value is less than the second preset value.

[0226] In some embodiments, the extraction module 103 can specifically be used for:

[0227] Extract the I-channel signal and the Q-channel signal starting from the second position of the received signal;

[0228] Based on the timing jitter error, perform error correction on the I-channel signal and the Q-channel signal to obtain the timing synchronization signal.

[0229] In some embodiments, the above-mentioned timing synchronization device can be used for the timing synchronization of short burst data.

[0230] In some embodiments, the above-mentioned receiving end may be a terminal or a network device.

[0231] An embodiment of the present application further provides an electronic device, such as the above-mentioned receiving end, as Figure 11 shown, including a processor 111, a communication interface 112, a memory 113, and a communication bus 114. Among them, the processor 111, the communication interface 112, and the memory 113 complete mutual communication through the communication bus 114.

[0232] The memory 113 is used to store a computer program.

[0233] When the processor 111 is used to execute the program stored on the memory 113, the steps of any of the above-mentioned timing synchronization methods are implemented.

[0234] The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0235] The communication interface is used for communication between the above electronic device and other devices.

[0236] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0237] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0238] In another embodiment provided by the present application, a computer-readable storage medium is further provided. A computer program is stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of any of the above timing synchronization methods are implemented.

[0239] In another embodiment provided by the present application, a computer program product including instructions is further provided. When it runs on a computer, the computer is caused to execute any of the timing synchronization methods in the above embodiments.

[0240] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrating one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

[0241] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0242] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, electronic device, and storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0243] The foregoing are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included within the protection scope of the present application.

Claims

1. A timing synchronization method, characterized in that, Applied to the receiving end, the method includes: Calculating a timing phase deviation of the received signal based on a first position of the received signal; Calculating a timing jitter error and making a decision adjustment to the first position based on the timing phase deviation to obtain a second position; Extracting a timing synchronization signal from the received signal based on the timing jitter error and the second position.

2. The method according to claim 1, characterized in that The step of calculating the timing phase deviation of the received signal based on the first position of the received signal includes: Reading a frame of signal starting from the first position of the received signal as a sample signal; Calculating the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal.

3. The method according to claim 2, wherein The step of calculating the timing phase deviation of the received signal based on the amplitude and phase factor of the sample signal includes: Determining a signal sum of n sampling points in the sample signal based on the amplitude and phase factor of the sample signal; Performing an angle operation on the signal sum to obtain the timing phase deviation of the sample signal as the timing phase deviation of the received signal.

4. The method according to claim 2 or 3, characterized in that, The phase factor is obtained according to the length of the sample signal and the interpolation multiple when acquiring the received signal.

5. The method according to claim 1, wherein The timing jitter error is obtained according to the timing phase deviation and the interpolation multiple when acquiring the received signal.

6. The method according to claim 1, wherein The step of making a decision adjustment to the first position based on the timing phase deviation to obtain a second position includes: If the timing phase deviation indicates that the first position is later than the starting position of the timing synchronization signal, adjusting the first position forward by a first preset position value to obtain a second position; If the timing phase deviation indicates that the first position is earlier than the starting position of the timing synchronization signal, adjusting the first position backward by a second preset position value to obtain a second position.

7. The method according to claim 6, wherein After obtaining the second position, the method further includes: When the second position meets the adjustment condition, updating the second position to a third preset value.

8. The method according to claim 7, wherein The adjustment condition is that the starting position of the I-channel signal obtained by adjusting the second position based on a preset adjustment factor is less than the starting position of the received signal.

9. The method according to any one of claims 6 - 8, characterized in that, The absolute value of the timing phase deviation being less than or equal to a first preset value indicates that the first position is later than the starting position of the timing synchronization signal; The absolute value of the timing phase deviation being greater than or equal to a second preset value indicates that the first position is earlier than the starting position of the timing synchronization signal; The first preset value is less than the second preset value.

10. The method according to claim 1, characterized in that The step of extracting a timing synchronization signal from the received signal based on the timing jitter error and the second position includes: Extracting an I-channel signal and a Q-channel signal starting from the second position of the received signal; Performing error correction on the I-channel signal and the Q-channel signal based on the timing jitter error to obtain a timing synchronization signal.

11. The method according to claim 1, wherein The timing synchronization method is used for timing synchronization of short burst signals.

12. The method according to claim 1, wherein The receiving end is a terminal or a network device.

13. A timing synchronization device, characterized in that, Applied to the receiving end, the device includes: A first calculation module for calculating a timing phase deviation of the received signal based on a first position of the received signal; A second calculation module, configured to calculate a timing jitter error based on the timing phase deviation and perform a decision adjustment on the first position to obtain a second position; An extraction module, configured to extract a timing synchronization signal from the received signal based on the timing jitter error and the second position.

14. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used for storing a computer program; The processor is configured to implement the method steps described in any one of claims 1-12 when executing the program stored on the memory.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the method steps described in any one of claims 1-12 are implemented.

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