Method of forming memory device

Abstract

A method includes forming a stack over a substrate, the stack including a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer; forming a first groove and a second groove; forming bottom electrodes in the first groove and the second groove; forming a patterned mask over the stack, wherein the patterned mask has an opening exposing the stack; performing an etching process on the stack via the opening of the patterned mask, where the etching process etches a first portion of the stack to form a recess, while a second portion of the stack laterally between the first trench and the second trench is protected by a polymer, the polymer being generated during the performing of the etching process; removing the first and second sacrificial layers from the stack; forming a capacitor dielectric layer over the bottom electrode; and forming a top electrode over the capacitor dielectric layer. Based on this configuration, the stability and efficiency of the memory device may be improved.

Description

Technical Field

[0001] The present invention relates to a method of forming a memory device. Background Art

[0002] Semiconductor devices, such as memory devices for storing information, Dynamic Random Access Memories (DRAMs), etc., are currently widely used in various applications. A DRAM includes a plurality of DRAM cells, and each DRAM cell includes a capacitor for storing information and a transistor coupled to the capacitor to regulate the charging or discharging timing of the capacitor. During a read operation, a word line (WL) is set, thereby turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via a bit line (BL). During a write operation, when the WL is set, the data to be written is provided on the BL. Summary of the Invention

[0003] In some embodiments of the present invention, a method of forming a memory device includes the following steps: forming a stack above a substrate, the stack including a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer; forming a first trench and a second trench in the stack; forming bottom electrodes in the first trench and the second trench respectively; forming a patterned mask above the stack, wherein the patterned mask has an opening exposing the stack; performing an etching process on the stack via the opening of the patterned mask, wherein the etching process etches a first portion of the stack to form a groove, and a second portion of the stack laterally located between the first trench and the second trench is protected by a polymer generated during the etching process; removing the first sacrificial layer and the second sacrificial layer from the stack via the groove; forming capacitor dielectric layers above the bottom electrodes respectively; and forming top electrodes above the capacitor dielectric layers respectively.

[0004] In some embodiments, a polymer is formed on the surface of the bottom electrode during the etching process.

[0005] In some embodiments, a portion of the second support layer of the second portion of the stack is etched during the etching process.

[0006] In some embodiments, the method further includes the following steps: removing the patterned mask after removing the first sacrificial layer and the second sacrificial layer; and removing the polymer.

[0007] In some embodiments, the method further includes the following step: removing the polymer after removing the patterned mask.

[0008] In some embodiments, the capacitor dielectric layer is formed above the second support layer and within the groove.

[0009] In some embodiments, the method further comprises the steps of: forming an insulating layer over the top electrode; and filling the groove.

[0010] In some embodiments, the method further comprises the steps of: forming a transistor in a substrate, wherein one of the bottom electrodes is electrically connected to the transistor.

[0011] In some embodiments, the polymer extends from a first portion of the bottom electrode within the first trench to a second portion of the bottom electrode within the second trench.

[0012] In some embodiments, the method further comprises the steps of: forming a first trench and a second trench in the stack, the step further comprising the steps of: forming a third trench in the stack, wherein the shortest distance between the first trench and the second trench is less than the shortest distance between the first trench and the third trench, and wherein the groove is formed laterally between the first trench and the third trench.

[0013] In some embodiments of the present invention, a method of forming a memory device comprises the steps of: forming a stack over a substrate, the stack comprising a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer; forming a first trench, a second trench, and a third trench in the stack, wherein the distance between the first trench and the second trench is less than the distance between the first trench and the third trench; forming bottom electrodes in the first, second, and third trenches respectively; forming a patterned mask over the stack, wherein the patterned mask has an opening exposing the stack; performing an etching process on the stack via the opening of the patterned mask to form a groove in the stack, wherein after the etching process is completed, a first portion of the second support layer located laterally between the first trench and the second trench remains, and a second portion of the second support layer located laterally between the first trench and the third trench is removed; removing the first sacrificial layer and the second sacrificial layer from the stack via the groove; forming a capacitor dielectric layer over the bottom electrodes respectively; and forming top electrodes over the capacitor dielectric layers respectively.

[0014] In some embodiments, the method further comprises the steps of: performing an etching process, the step further comprising the steps of: forming a polymer over the first portion of the second support layer.

[0015] In some embodiments, the polymer further extends to portions of the bottom electrodes within the first trench and the second trench.

[0016] In some embodiments, the polymer wraps around the tops of the bottom electrodes within the first trench and the second trench.

[0017] In some embodiments, the method further comprises the steps of: removing the patterned mask after removing the first sacrificial layer and the second sacrificial layer; and removing the polymer after removing the patterned mask.

[0018] In some embodiments, the method further comprises the steps of: removing a polymer, the step further comprising the steps of: removing a first portion of a second support layer.

[0019] In some embodiments, after the etching process is completed, the top surface of the first portion of the second support layer is lower than the top end of the bottom electrode.

[0020] In some embodiments, an etching process is performed such that the thickness of the first portion of the second support layer is reduced.

[0021] In some embodiments, the method further comprises the steps of: forming a transistor in a substrate, wherein one of the bottom electrodes is electrically connected to a source / drain region of the transistor.

[0022] In some embodiments, an etching process is performed such that a first sacrificial layer, a first support layer, and a portion of a second sacrificial layer below a second portion of the second support layer are removed. Description of the Drawings

[0023] In conjunction with the accompanying drawings, the present invention can be more fully understood by reading the following detailed description of the embodiments:

[0024] Figure 1 A circuit diagram of a memory cell of a memory device according to some embodiments of the present invention.

[0025] Figures 2A to 10C A method for forming various stages of a memory device according to some embodiments of the present invention. Detailed Description of the Embodiments

[0026] Reference will now be made in detail to the current embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0027] Figure 1A circuit diagram of a memory cell of a memory device according to some embodiments of the present invention. The circuit diagram of the memory device 100 is shown in the figure. In some embodiments, the memory device 100 is a dynamic random access memory (DRAM) device. The memory device 100 includes a transistor 100T, a capacitor 100C, a word line WL1, and a bit line BL1. The transistor 100T is electrically connected to the word line WL1 and is also connected to the bit line BL1 arranged perpendicular to the word line WL1. One side of the capacitor 100C is electrically connected to the transistor 100T, and the other side of the capacitor 100C is grounded. The operation of the device can be realized by using the word line WL1 and the bit line BL1, and data can be stored by controlling the charge in the capacitor 100C. The charge transfer on the capacitor 100C can be determined by the control of the transistor 100T, and the transistor 100T can be manipulated through the bit line BL1 and the word line WL1 to characterize the reading and writing of signals.

[0028] Figures 2A to 10C A method for forming each stage of a memory device according to some embodiments of the present invention. More specifically, Figures 2A to 10C Describe the formation of Figure 1 The memory device 100 shown. Although Figures 2A to 10C Described as a series of actions, it should be understood that these actions are not limited thereto. In other embodiments, the order of the actions can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted in whole or in part.

[0029] Refer to Figures 2A to 2C where Figure 2A Is a top view of the memory device, and Figure 2B And Figure 2C Are cross-sectional views along lines B-B and C-C of Figure 2A Respectively.

[0030] The substrate 105 is shown in the figure. In some embodiments, the substrate 105 can be a suitable semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, germanium, indium antimonide, indium phosphide, indium arsenide, etc. The substrate 105 can also be doped with a suitable dopant.

[0031] A plurality of gate structures 111 are formed in the substrate 105. In some embodiments, each gate structure 111 can include a gate dielectric layer 115, a gate electrode 120, and a gate cap 125. The substrate 105 can include doped regions 110 located on opposite sides of each gate structure 111. In some embodiments, the gate structure 111, the doped region 110, and the portion of the substrate 105 along the surface of the gate structure 111 (e.g., the channel region) can jointly form as Figure 1The transistor 100T of the memory device 100 shown. In some embodiments, the doped region 110 can serve as the source / drain region of the transistor.

[0032] In some embodiments, the gate dielectric layer 115 can include an oxide, such as silicon oxide. In some embodiments, the gate electrode 120 can include a suitable conductive material, such as polysilicon, cobalt, nickel, titanium, titanium nitride, tungsten, tungsten nitride, etc. or a combination thereof. In some embodiments, the gate cap 125 can include a dielectric material, such as silicon oxide, silicon nitride, etc., or a combination thereof. In some embodiments, the doped region 110 can include a conductive type opposite to that of the substrate 105. For example, when the substrate 105 is a p-type substrate, the doped region 110 can be an n-type doped region. Similarly, when the substrate 105 is an n-type substrate, the doped region 110 can be a p-type doped region.

[0033] The dielectric layer 130 is formed on the top surface of the substrate 105. In some embodiments, the dielectric layer 130 can include silicon oxide (SiO2), carbon-doped silicon oxide, silicon nitride (Si3N4), silicon oxynitride (N x O y Si), silicon oxynitride (N2OSi2), flowable oxide (FOx), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorocarbon (a-CFx), parylene, benzocyclobutene (BCB), polyimide (PI), or a combination thereof. In some embodiments, the dielectric layer 130 can be provided by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0034] The contact 135 is formed in the dielectric layer 130. In some embodiments, the contact 135 can be formed to be electrically connected to the doped region 110 of the substrate 105. In some embodiments, the contact 135 can include doped polysilicon (poly-Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), copper (Cu), aluminum (Al), or an alloy thereof. In some embodiments, the contact 135 can be provided by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0035] A stack of a first sacrificial layer 140, a first support layer 145, a second sacrificial layer 150, and a second support layer 155 is formed over the dielectric layer 130. The first sacrificial layer 140 and the second sacrificial layer 150 may be made of the same material, such as silicon oxide. In some embodiments, the first support layer 145 and the second support layer 155 may be made of a material different from that of the first sacrificial layer 140 and the second sacrificial layer 150. For example, the first support layer 145 and the second support layer 155 may be made of a material that exhibits different etching properties from those of the first sacrificial layer 140 and the second sacrificial layer 150. In some embodiments, the first support layer 145 and the second support layer 155 may be made of the same material, such as silicon nitride, aluminum oxide, hafnium oxide, etc. or other suitable materials.

[0036] In some embodiments, the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 may be deposited by, for example, ALD, CVD, PVD, or other suitable methods.

[0037] See Figures 3A to 3C , where Figure 3A is a top view of the memory device, Figure 3B and Figure 3C are cross-sectional views along lines B-B and C-C of Figure 3A respectively.

[0038] Using an appropriate lithography process, a plurality of trenches are formed in the stack of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155. In some embodiments, the trenches at least include trenches T1, T2, T3, and T4. In some embodiments, the trenches T1, T2, T3, and T4 may expose respective contacts 135.

[0039] In some embodiments, the trenches may be formed, for example, by forming a patterned mask (e.g., photoresist) over the second support layer 155, where the patterned mask may include openings that define the positions of the trenches (e.g., trenches T1 to T4). Thereafter, an etching process may be performed via the openings of the patterned mask to remove portions of the second support layer 155, the second sacrificial layer 150, the first support layer 145, and the first sacrificial layer 140, thereby forming the trenches. In some embodiments, the etching process may be an anisotropic dry etching process.

[0040] It should be noted that Figure 3B is a cross-sectional view along trenches T1 and T2, and Figure 3C is a cross-sectional view along trenches T1 and T3. A shortest distance D1 may be included between trenches T1 and T2, and a shortest distance D2 may be included between trenches T1 and T3. In some embodiments, the distance D1 is greater than the distance D2.

[0041] See Figures 4A to 4C , where Figure 4A is a top view of the memory device, and Figure 4B and Figure 4C are cross-sectional views along lines B-B and C-C of Figure 4A respectively. After forming trenches (e.g., trenches T1 to T4), bottom electrodes 160 are respectively formed in the trenches and are in contact with corresponding contacts 135. Accordingly, the bottom electrodes 160 can be electrically connected to corresponding doped regions 110 in the substrate 105. In some embodiments, the bottom electrodes 160 can include a metal material such as titanium nitride (TiN) or ruthenium (Ru).

[0042] See Figures 5A to 5C , where Figure 5A is a top view of the memory device, and Figure 5B and Figure 5C are cross-sectional views along lines B-B and C-C of Figure 5A respectively. A patterned mask 165 is formed over the stack of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155. In some embodiments, the patterned mask 165 can include at least one opening that exposes a portion of the second support layer 155. For example, as shown in the top view of Figure 5A , at least one opening of the patterned mask 165 exposes the region of the second support layer 155 surrounded by trenches T1, T2, T3, and T4.

[0043] See Figures 6A to 6C , where Figure 6A is a top view of the memory device, and Figure 6B and Figure 6C are cross-sectional views along lines B-B and C-C of Figure 6A respectively. After forming the patterned mask 165, an etching process is performed to remove portions of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 via the openings of the patterned mask 165. During the etching process, a polymer 170 can also be formed as a by-product of the etching process. Due to various chemical reactions, the polymer 170 is continuously deposited over the substrate 105 while the etching process is also continuously performed. Accordingly, the etching of the stack of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 and the formation of the polymer 170 occur substantially simultaneously and continuously. In some embodiments, the polymer 170 can be formed to cover the exposed surface of the bottom electrode 160. In some embodiments, the polymer 170 can wrap around the top end of the bottom electrode 160.

[0044] As Figure 6BAs shown in the cross-sectional view, the etching process can remove portions of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 that are laterally located between the trenches T1 and T2, thereby forming a recess R1 between the trenches T1 and T2.

[0045] On the other hand, as Figure 6C shown in the cross-sectional view, during the etching process, the etching process can first remove a portion of the second support layer 155. However, due to the short distance between the trenches T1 and T3, portions of the polymer 170 can fill the gap between the trenches T1 and T3 and can merge together above the etched second support layer 155. Therefore, in Figure 6C , the merged polymer 170 can act as a protective layer to prevent portions of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 that are laterally located between the trenches T1 and T3 from being etched. Thus, once the etching process is completed, portions of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155 that are laterally located between the trenches T1 and T3 can be retained, while the second support layer 155 is slightly etched. In some embodiments, during the etching process, the thickness of the portion of the second support layer 155 located between the trenches T1 and T3 is reduced. In some embodiments, as Figure 7B shown, after the etching process is performed, the surface of the second support layer 155 located between the trenches T1 and T3 is lower than the top end of the bottom electrode 160.

[0046] Referring again to Figure 6A the top view, it should be noted that the polymer 170 can also merge together and fill the gaps between the trenches T1 and T4, between the trenches T2 and T3, and between the trenches T2 and T4, respectively. In some embodiments, the polymer 170 can merge at the small gaps between the trenches (e.g., the gaps between the trenches T1 and T3, between the trenches T1 and T4, between the trenches T2 and T3, or between the trenches T2 and T4), and the merged polymer 170 is formed in a self-aligned manner and can well define the boundaries of the openings of the patterned mask 165, thereby improving the etching performance. On the other hand, the polymer 170 can also act as a protective layer for the top end of the bottom electrode 160.

[0047] In some embodiments, the etching process is an anisotropic dry etching, such as plasma dry etching. The etching gas used during the dry etching can include CF4, CHF3, CH2F2, CH3F, SF6, NF3, etc. or a combination thereof. The carrier gas used during the dry etching can include H2, N2, Ar, etc. or a combination thereof. In some embodiments, the polymer 170 can include C x H y F z .

[0048] See Figure 7A and Figure 7B , wherein Figure 7A and Figure 7B respectively follow the cross-sectional views of Figure 6B and Figure 6C Another etching process may be performed to remove the first sacrificial layer 140 and the second sacrificial layer 150. In some embodiments, the etching process may be an isotropic wet etching process to remove the entire first sacrificial layer 140 and the second sacrificial layer 150 through the grooves R1 in the stack of the first sacrificial layer 140, the first support layer 145, the second sacrificial layer 150, and the second support layer 155. Thus, the first support layer 145 and the second support layer 155 can be suspended above the substrate 105. In some embodiments, the etching rate of the etching process for the first sacrificial layer 140 and the second sacrificial layer 150 may be higher than the etching rate for the first support layer 145 and the second support layer 155.

[0049] See Figure 8A and Figure 8B , wherein Figure 8A and Figure 8B respectively follow the cross-sectional views of Figure 7A and Figure 7B Remove the patterned mask 165. In some embodiments where the patterned mask 165 is a photoresist, an ashing process or a lift-off process may be used to remove the patterned mask 165. Thereafter, a cleaning process may be performed to remove the polymer 170, thereby exposing the top of the bottom electrode 160. Since the polymer 170 can protect the bottom electrode 160 during the previous etching process, the bottom electrode 160 has no loss or negligible loss, thus improving the device performance.

[0050] As shown in the cross-sectional view of Figure 8B , during the cleaning process, a part of the second support layer 155 located between the trenches T1 and T3 is also removed. As described above, this part may be consumed during the previous etching process, so the remaining material of this part of the second support layer 155 can be removed together during the cleaning process.

[0051] See Figure 9A and Figure 9B , wherein Figure 9A and Figure 9B respectively follow the cross-sectional views of Figure 8A and Figure 8BCross-sectional view. The capacitor dielectric layer 175 is formed to fill the trenches (e.g., trenches T1 to T4) and the recess R1, and extends along the surface of the bottom electrode 160 and the surfaces of the second support layer 155, the first support layer 145, and the dielectric layer 130. In some embodiments, the capacitor dielectric layer 175 may include tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), strontium bismuth tantalum oxide (SrBi2Ta2O9, SBT), barium strontium titanate oxide (BaSrTiO3, BST), a dielectric material having a dielectric constant higher than that of silicon dioxide (SiO2), or a dielectric material having a dielectric constant of about 4.0 or greater. In some embodiments, each capacitor dielectric layer 175 may be formed of a single layer or may be formed of stacked layers. In some embodiments, the capacitor dielectric layer 175 may be provided by, for example, ALD, CVD, PVD, or other suitable methods.

[0052] Subsequently, a top electrode 180 is formed to fill the trenches (e.g., trenches T1 to T4) and the recess R1, and covers the capacitor dielectric layer 175. In some embodiments, the bottom electrode 160 may include a metallic material such as titanium nitride (TiN) or ruthenium (Ru). In some embodiments, the top electrode 180 may be provided by, for example, ALD, CVD, PVD, RPCVD, PECVD, LPCVD, coating, or other suitable methods.

[0053] An insulating layer 185 is formed above the top electrode 180 and fills the remaining space in the structure as shown in Figure 8A and Figure 8B . In some embodiments, the insulating layer 185 may include, for example, borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), phosphorus-doped tetraethyl orthosilicate (PTEOS), epoxy-based materials (e.g., FR4), resin-based materials (e.g., bismaleimide-triazine (BT)), polypropylene (PP), molding compounds, or other suitable materials.

[0054] See Figures 10A to 10C , where Figure 10A is a top view of the memory device, and Figure 10B and Figure 10C are cross-sectional views along lines B-B and C-C of Figure 10A , respectively. A planarization process is performed on the structures shown in Figure 9A and Figure 9B until the second support layer 155 is exposed. In some embodiments, the bottom electrode 160, the capacitor dielectric layer 175, and the top electrode 180 within each trench may be collectively used as the capacitor 100C of the memory device 100, as shown in Figure 1 . In some embodiments, the planarization process may be a chemical mechanical polishing (CMP) process.

[0055] Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the claims of the invention should not be limited to the description of the embodiments contained herein.

[0056] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In summary, the present invention is intended to cover modifications and variations of the present invention as long as such modifications and variations fall within the scope of the claims of the invention.

[0057]

Symbol Explanation

[0058] 100: Memory device

[0059] 100C: Capacitor

[0060] 100T: Transistor

[0061] 105: Substrate

[0062] 110: Doped region

[0063] 111: Gate structure

[0064] 115: Gate dielectric layer

[0065] 120: Gate electrode

[0066] 125: Gate cap

[0067] 130: Dielectric layer

[0068] 135: Contact

[0069] 140: First sacrificial layer

[0070] 145: First support layer

[0071] 150: Second sacrificial layer

[0072] 155: Second support layer

[0073] 160: Bottom electrode

[0074] 165: Patterned mask

[0075] 170: Polymer

[0076] 175: Capacitor dielectric layer

[0077] 180: Top electrode

[0078] 185: Insulating layer

[0079] B - B, C - C: Lines

[0080] BL1: Bit line

[0081] D1, D2: Distance

[0082] R1: Groove

[0083] T1 to T4: Groove

[0084] WL1: Word line.

Claims

1. A method of forming a memory device, characterized in that, comprising the following steps: forming a stack above a substrate, the stack including a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer; forming a first trench and a second trench in the stack; forming a plurality of bottom electrodes in the first trench and the second trench respectively; forming a patterned mask above the stack, wherein the patterned mask has an opening exposing the stack; performing an etching process on the stack via the opening of the patterned mask, wherein the etching process etches a first portion of the stack to form a groove, and a second portion of the stack that is laterally between the first trench and the second trench is protected by a polymer that is generated during the performing of the etching process; removing the first sacrificial layer and the second sacrificial layer from the stack via the groove; forming a plurality of capacitor dielectric layers above the plurality of bottom electrodes respectively; and forming a plurality of top electrodes above the plurality of capacitor dielectric layers respectively.

2. The method according to claim 1, wherein the polymer is formed on a plurality of surfaces of the plurality of bottom electrodes during the performing of the etching process.

3. The method according to claim 1, wherein a portion of the second support layer of the second portion of the stack is etched during the etching process.

4. The method according to claim 1, wherein further comprising the following steps: removing the patterned mask after removing the first sacrificial layer and the second sacrificial layer; and removing the polymer.

5. The method according to claim 4, wherein the polymer is removed after removing the patterned mask.

6. The method according to claim 1, wherein the plurality of capacitor dielectric layers are formed above the second support layer and in the groove.

7. The method according to claim 1, wherein further comprising the following steps: forming an insulating layer above the plurality of top electrodes; and filling the groove.

8. The method according to claim 1, wherein, further comprising the following steps: forming a transistor in the substrate, wherein one of the plurality of bottom electrodes is electrically connected to the transistor.

9. The method according to claim 1, wherein the polymer extends from a first portion of the plurality of bottom electrodes in the first trench to a second portion of the plurality of bottom electrodes in the second trench.

10. The method according to claim 1, wherein the step of forming the first trench and the second trench in the stack further comprises the following steps: forming a third trench in the stack, the shortest distance between the first trench and the second trench being less than the shortest distance between the first trench and the third trench, and wherein the groove is formed laterally between the first trench and the third trench.

11. A method of forming a memory device, characterized in that, comprising the following steps: forming a stack above a substrate, the stack including a first sacrificial layer, a first support layer, a second sacrificial layer, and a second support layer; forming a first trench, a second trench, and a third trench in the stack, wherein the distance between the first trench and the second trench is less than the distance between the first trench and the third trench; forming a plurality of bottom electrodes in the first trench, the second trench, and the third trench respectively; A patterned mask is formed over the stack, wherein the patterned mask has an opening exposing the stack; An etching process is performed on the stack through the opening of the patterned mask to form a groove in the stack, wherein after the etching process is completed, a first portion of the second support layer that is laterally located between the first trench and the second trench remains, and a second portion of the second support layer that is laterally located between the first trench and the third trench is removed; The first sacrificial layer and the second sacrificial layer are removed from the stack through the groove; A plurality of capacitor dielectric layers are formed respectively over the plurality of bottom electrodes; And A plurality of top electrodes are formed respectively over the plurality of capacitor dielectric layers.

12. The method according to claim 11, wherein the step of performing the etching process further comprises the step of forming a polymer over the first portion of the second support layer.

13. The method according to claim 12, wherein the polymer further extends to a plurality of portions of the plurality of bottom electrodes within the first trench and the second trench.

14. The method according to claim 13, wherein the polymer wraps around a plurality of tops of the plurality of bottom electrodes within the first trench and the second trench.

15. The method according to claim 12, wherein, Further comprising the steps of: Removing the patterned mask after removing the first sacrificial layer and the second sacrificial layer; and Removing the polymer after removing the patterned mask.

16. The method according to claim 15, wherein the step of removing the polymer further comprises the step of removing the first portion of the second support layer.

17. The method according to claim 11, wherein after the etching process is completed, a top surface of the first portion of the second support layer is lower than a plurality of tops of the plurality of bottom electrodes.

18. The method according to claim 11, wherein the etching process is performed such that a thickness of the first portion of the second support layer is reduced.

19. The method according to claim 11, wherein, Further comprising the step of forming a transistor in the substrate, wherein one of the plurality of bottom electrodes is electrically connected to a source / drain region of the transistor.

20. The method according to claim 11, wherein the etching process is performed such that a plurality of portions of the first sacrificial layer, the first support layer, and the second sacrificial layer below the second portion of the second support layer are removed.

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