Method for manufacturing semiconductor element
By forming openings of contact field plates in the LDMOS transistors, exposing a larger area of the field plate top surface, the breakdown problem caused by uneven electric field distribution is solved, and the stability and reliability of semiconductor components under long-term bias and radio frequency conditions are achieved.
Patent Information
- Application Number
- CN202410062981.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-02
- Filing Date
- 2024-01-16
- Publication Date
- 2025-07-04
AI Technical Summary
Existing LDMOS transistors are prone to breakdown under long-term bias and radio frequency conditions, and it is difficult for the prior art to effectively control the electric field distribution between the gate and drain.
During the manufacturing process of transistors, a larger area of the field plate top surface is exposed by forming openings of the contact field plate, and the overlap area between the contact field plate and the field plate is increased to evenly distribute the electric field and avoid breakdown.
By increasing the overlap area between the contact field plate and the field plate, the breakdown phenomenon of transistors during operation is effectively avoided, and the stability and reliability of semiconductor components under long-term bias and radio frequency conditions are ensured.
Smart Images
Figure CN120264791A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a field plate. Background Art
[0002] For a lateral diffused metal-oxide-semiconductor (LDMOS) transistor, in order to enable the device to maintain good DC characteristics under long-term bias conditions for normal operation under radio frequency (RF) conditions, a field plate is usually provided between the gate and the drain. In this way, during the operation of the device, by applying a voltage to the contact field plate (CFP) connected to the field plate, the electric field distribution under the field plate can be controlled to avoid breakdown. Summary of the Invention
[0003] The present invention provides a method for manufacturing a semiconductor device, wherein the opening for forming the contact field plate exposes a large area of the top surface of the field plate, so that a large overlapping area can be formed between the formed contact field plate and the field plate.
[0004] The method for manufacturing a semiconductor device of the present invention includes the following steps. A transistor is formed on a substrate, wherein the drain of the transistor is separated from the gate structure by a certain distance. A field plate is formed on the substrate between the drain and the gate structure of the transistor, wherein the field plate extends to the sidewall and the top surface of the gate structure. A first dielectric layer is formed on the substrate, wherein the first dielectric layer covers the transistor and the field plate. A second dielectric layer is formed on the first dielectric layer, wherein the second dielectric layer has a first opening, and the first opening exposes a part of the first dielectric layer located on the field plate. Through the first opening, a part of the first dielectric layer is removed to form a second opening, wherein the second opening extends from the exposed sidewall of the second dielectric layer towards the inside of the second dielectric layer. A third opening exposing the gate, source, and drain of the transistor is formed in the second dielectric layer. A conductive layer is formed in the second opening and the third opening.
[0005] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the second opening is only located above the field plate.
[0006] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the method for forming the field plate includes the following steps. A field plate material layer is conformally formed on the substrate. A patterning process is performed to remove a portion of the field plate material layer, and the field plate material layer located between the drain and the gate structure and on the sidewalls and top surface of the gate structure is retained.
[0007] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the field plate material layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer sequentially formed on the substrate.
[0008] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the material of the field plate material layer includes silicon oxide.
[0009] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the material of the first dielectric layer includes silicon nitride.
[0010] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the method for removing a portion of the first dielectric layer to form the second opening includes performing a wet etching process.
[0011] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the method for forming the third opening includes the following steps. After forming the second opening, a patterned mask layer is formed on the second dielectric layer, where the patterned mask layer exposes the area where the third opening is to be formed and fills the second opening. Using the patterned mask layer as a mask, an etching process is performed to remove a portion of the second dielectric layer and a portion of the first dielectric layer. The patterned mask layer is removed.
[0012] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the material of the patterned mask layer includes photoresist.
[0013] In an embodiment of the method for manufacturing a semiconductor device of the present invention, the method for forming the conductive layer includes the following steps. A conductive material layer is formed on the second dielectric layer, where the conductive material layer fills the second opening and the third opening. The conductive material layer outside the second opening and the third opening is removed.
[0014] Based on the above, in the method for manufacturing a semiconductor device of the present invention, after forming the first opening, a wet etching process is performed on the first dielectric layer through the first opening to form the second opening. Therefore, the second opening can extend from the sidewall of the second dielectric layer towards the inside of the second dielectric layer to expose a larger area of the top surface of the field plate, so that a larger overlapping area can be achieved between the subsequently formed contact field plate (CFP) and the field plate. In this way, during the operation of the semiconductor device, the electric field under the field plate can be more evenly distributed, effectively avoiding the occurrence of breakdown phenomena. Description of the Drawings
[0015] Figures 1A to 1F It is a schematic cross-sectional view of the manufacturing process of the semiconductor device according to an embodiment of the present invention.
[0016] Symbol Description
[0017] 100: Substrate
[0018] 102: Field plate
[0019] 102a, 102c: Silicon oxide layer
[0020] 102b: Silicon nitride layer
[0021] 104: First dielectric layer
[0022] 106: Second dielectric layer
[0023] 108: Patterning mask layer
[0024] 110: Conductive layer
[0025] CT1, CT2, CT3, CT4: Contact window
[0026] D: Drain
[0027] H1, H2, H3, H4, H5: Opening
[0028] GE: Gate
[0029] GI: Gate insulating layer
[0030] S: Source
[0031] SP: Spacer
[0032] SW: Sidewall
[0033] TR: Transistor Detailed Description of the Invention
[0034] Examples will be listed below and described in detail with reference to the accompanying drawings. However, the examples provided are not intended to limit the scope covered by the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original scale. For ease of understanding, the same elements will be denoted by the same reference numerals in the following description.
[0035] Regarding the terms "comprising", "including", "having", etc. used in the text, they are all open-ended terms, that is, "including but not limited to".
[0036] When elements are described using terms such as "first", "second", etc., they are only used to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, the first element may also be referred to as the second element, and the second element may also be referred to as the first element, and this does not deviate from the scope of the present invention.
[0037] In addition, the directional terms mentioned in the text, such as "up", "down", etc., are only for reference to the direction of the drawings and are not used to limit the present invention. Therefore, it should be understood that "up" can be used interchangeably with "down", and when an element such as a layer or a film is placed "on" another element, the element can be directly placed on the other element, or there may be an intermediate element. On the other hand, when it is said that an element is "directly" placed "on" another element, there is no intermediate element between the two.
[0038] Figures 1A to 1F It is a schematic cross-sectional view of the manufacturing process of the semiconductor element according to the embodiment of the present invention.
[0039] First, please refer to Figure 1A , a substrate 100 is provided. In this embodiment, the substrate 100 is a silicon substrate, but the present invention is not limited thereto. Next, a transistor TR is formed on the substrate 100. In this embodiment, the transistor TR is a laterally diffused metal oxide semiconductor transistor. The transistor TR includes a gate GE, a gate insulating layer GI, a spacer SP, a source S, and a drain D. The gate GE is formed on the substrate 100, the gate insulating layer GI is formed between the gate GE and the substrate 100, and the spacer SP is formed on the sidewalls of the gate GE and the gate insulating layer GI. In this embodiment, the gate GE, the gate insulating layer GI, and the spacer SP constitute a gate structure. The source S and the drain D are respectively formed in the substrate 100 on both sides of the gate structure, wherein the source S is adjacent to the gate structure, and the drain D is separated from the gate structure by a certain distance. For a laterally diffused metal oxide semiconductor transistor, the architecture of the transistor TR is only exemplary and is not intended to limit the present invention.
[0040] Next, please refer to Figure 1B, a field plate 102 is formed on the substrate 100 between the drain D of the transistor TR and the gate structure. In this embodiment, the field plate 102 is formed on the substrate 100 and extends to the sidewalls and the top surface of the gate structure. That is to say, in this embodiment, the field plate 102 is located on the substrate 100 between the gap wall SP adjacent to the drain D of the gate structure and the drain D, and covers a part of the top surface of the gap wall SP adjacent to the drain D of the gate structure and the gate GE.
[0041] In this embodiment, the field plate 102 is a composite dielectric field plate composed of a silicon oxide layer 102a, a silicon nitride layer 102b, and a silicon oxide layer 102c. The formation method of the field plate 102 may include the following steps. First, a field plate material layer is conformally formed on the substrate 100, that is, a silicon oxide layer 102a, a silicon nitride layer 102b, and a silicon oxide layer 102c are sequentially formed on the substrate 100. After that, a patterning process is performed on the field plate material layer to remove a part of the silicon oxide layer 102a, a part of the silicon nitride layer 102b, and a part of the silicon oxide layer 102c, and the silicon oxide layer 102a, the silicon nitride layer 102b, and the silicon oxide layer 102c located between the drain D and the gate structure and on the sidewalls and the top surface of the gate structure are retained. In other embodiments, depending on the actual situation and requirements, the field plate 102 may be a single-layer dielectric field plate composed only of a silicon oxide layer.
[0042] After the field plate 102 is formed, a first dielectric layer 104 is formed on the substrate 100. In this embodiment, the first dielectric layer 104 is conformally formed on the substrate 100 and covers the transistor TR and the field plate 102. There is an etching selectivity between the first dielectric layer 104 and the silicon oxide layer 102c to avoid damaging the field plate 102 during the subsequent removal of the first dielectric layer 104. In this embodiment, the material of the first dielectric layer 104 is silicon nitride, but the present invention is not limited thereto. In addition, the first dielectric layer 104 can be used as a contact etch stop layer (CESL) in subsequent manufacturing processes.
[0043] Then, please refer to Figure 1C , a second dielectric layer is formed on the first dielectric layer 104. In this embodiment, the second dielectric layer 106 is a silicon oxide layer, which serves as an inter-layer dielectric (ILD) layer. After the second dielectric layer 106 is formed, an opening H1 is formed in the second dielectric layer 106. The opening H1 exposes a part of the first dielectric layer 104 located on the field plate 102. The opening H1 is used to form a contact window (contact field plate) connected to the field plate 102, which will be further described later. In this embodiment, the opening H1 is located above the field plate 102, so the sidewall SW of the second dielectric layer 106 exposed by the opening H1 will be located above the field plate 102.
[0044] Next, please refer to Figure 1D , through the opening H1, a part of the first dielectric layer 104 is removed to form the opening H1 into an opening H2. Specifically, in this embodiment, through the opening H1, a wet etching process is performed on the first dielectric layer 104. During the wet etching process, the first dielectric layer 104 exposed by the opening H1 is removed, and based on the characteristics of the wet etching process itself, the etchant will remove the first dielectric layer 104 that is not exposed by the opening H1 from the sidewall SW of the second dielectric layer 106 towards the inside of the second dielectric layer 106. Therefore, the size of the formed opening H2 will be larger than the size of the opening H1, and will extend from the sidewall SW of the second dielectric layer 106 towards the inside of the second dielectric layer 106 to expose the top surface of the field plate 102 as much as possible. That is to say, in this embodiment, compared with only removing the first dielectric layer 104 exposed by the opening H1, performing the wet etching process through the opening H1 can expose the top surface of a larger area of the field plate 102.
[0045] On the other hand, in this embodiment, the wet etching process is used to form the opening H2, so the area of the top surface of the field plate 102 to be exposed can be precisely controlled by controlling the wet etching time. In addition, in this embodiment, the opening H2 is only located above the field plate 102. In other words, during the wet etching, the etchant can be controlled so that it does not overly remove the first dielectric layer 104 to expose the gate GE or the source D.
[0046] Then, please refer to Figure 1E , openings are formed in the second dielectric layer 106 to expose the gate GE, the source S, and the drain D of the transistor TR. The openings are used to form contact windows connected to the gate GE, the source S, and the drain D. Specifically, in this embodiment, after the opening H2 is formed, a patterned mask layer 108 is formed on the second dielectric layer 106. The patterned mask layer 108 exposes the areas where the above openings are to be formed and fills the opening H2. The material of the patterned mask layer 108 can be photoresist, but the present invention is not limited thereto. Then, using the patterned mask layer 108 as a mask, an anisotropic etching process is performed to remove a part of the second dielectric layer 106 and a part of the first dielectric layer 104. In this way, an opening H3 that exposes the gate GE, an opening H4 that exposes the source S, and an opening H5 that exposes the drain D are formed. In addition, since the patterned mask layer 108 fills the opening H2, the field plate 102 will not be damaged during the etching, and the profile of the opening H2 will not be changed.
[0047] After that, please refer to Figure 1F, the patterned mask layer 108 is removed. Then, a conductive layer 110 is formed in the openings H2, H3, H4, and H5. The conductive layer 110 located in the opening H2 forms a contact window CT1 connected to the field plate 102 to serve as a contact field plate. In addition, the conductive layer 110 located in the opening H3 forms a contact window CT2 connected to the gate GE, the conductive layer 110 located in the opening H4 forms a contact window CT3 connected to the source S, and the conductive layer 110 located in the opening H5 forms a contact window CT4 connected to the drain D. The method of forming the conductive layer 110 may include the following steps. First, a conductive material layer is formed on the second dielectric layer 106 such that the conductive material layer fills the openings H2, H3, H4, and H5. Then, the conductive material layer outside the openings H2, H3, H4, and H5 is removed.
[0048] In this way, the semiconductor device of this embodiment is completed. In addition, after the contact windows CT1, CT2, CT3, and CT4 are formed, a patterned wiring layer can be formed on the second dielectric layer 106 to electrically connect the contact windows CT1, CT2, CT3, and CT4 to a voltage source.
[0049] In the manufacturing method of the semiconductor device of this embodiment, after the opening H1 is formed, through the opening H1, a wet etching process is performed on the first dielectric layer 104 to form the opening H2 such that the opening H2 can extend from the sidewall SW of the second dielectric layer 106 toward the inside of the second dielectric layer 106 to expose a larger area of the top surface of the field plate 102. In addition, by controlling the time of the wet etching, the area of the exposed top surface of the field plate 102 can be precisely controlled. In this way, a larger overlapping area can be achieved between the subsequently formed contact window CT1 (contact field plate) and the field plate, enabling the electric field under the field plate to be more evenly distributed and controllable during the operation of the semiconductor device of this embodiment, and thus effectively avoiding the occurrence of breakdown phenomena.
[0050] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, comprising: Forming a transistor on a substrate, wherein a drain of the transistor is separated from a gate structure by a distance; Forming a field plate on the substrate between the drain of the transistor and the gate structure, wherein the field plate extends to sidewalls and a top surface of the gate structure; Forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the transistor and the field plate; Forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a first opening, and the first opening exposes a part of the first dielectric layer located on the field plate; Via the first opening, removing a part of the first dielectric layer to form a second opening, wherein the second opening extends from an exposed sidewall of the second dielectric layer towards the interior of the second dielectric layer; Forming a third opening in the second dielectric layer that exposes the gate, source, and drain of the transistor; And Forming a conductive layer in the second opening and the third opening.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the second opening is only located above the field plate.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the field plate comprises: Conformally forming a field plate material layer on the substrate; And Performing a patterning process to remove a part of the field plate material layer, and retaining the field plate material layer located between the drain and the gate structure and on the sidewalls and top surface of the gate structure.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the field plate material layer comprises a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer sequentially formed on the substrate.
5. The method for manufacturing a semiconductor device according to claim 3, wherein the material of the field plate material layer comprises silicon oxide.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the first dielectric layer comprises silicon nitride.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the method for removing a part of the first dielectric layer to form the second opening comprises performing a wet etching process.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the third opening comprises: After forming the second opening, forming a patterned mask layer on the second dielectric layer, wherein the patterned mask layer exposes an area where the third opening is to be formed and fills the second opening; And Using the patterned mask layer as a mask, performing an etching process to remove a part of the second dielectric layer and a part of the first dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the material of the patterned mask layer comprises photoresist.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the conductive layer comprises: Forming a conductive material layer on the second dielectric layer, wherein the conductive material layer fills the second opening and the third opening; And Removing the conductive material layer outside the second opening and the third opening.