Asymmetric high-reliability trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides an asymmetric high-reliability trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) and a preparation method thereof. The preparation method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a shunt region and a P-type well region are formed; a barrier layer is formed again, and metal is etched and deposited to form a Schottky metal layer; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type base region, a P-type source region and an N-type source region are formed; forming a barrier layer again, etching and depositing metal, and forming a source metal layer; a barrier layer is formed again, and an insulating medium layer is formed through etching and deposition; according to the preparation method, the asymmetric trench gate structure is adopted, the after-conduction characteristics of the device are ensured at a single side, the follow current characteristics of a diode of the device are ensured at a single side, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to an asymmetric highly reliable trench-gate silicon carbide VDMOS and a manufacturing method thereof. Background Art

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices inherently have the characteristics of low gate charge and high switching speed compared with Si VDMOS devices. However, due to the relationship of the material bandgap width and the immature manufacturing process of the insulating medium, the gate reliability of the devices has not been fully resolved. At the same time, since the current density of the devices is larger than that of Si, the situation of the body diode freewheeling burnout is likely to occur, and it is necessary to improve the body diode freewheeling ability of the devices to improve the reliability of the devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an asymmetric highly reliable trench-gate silicon carbide VDMOS and a manufacturing method thereof, which adopt an asymmetric trench-gate structure to ensure the post-conduction characteristics of the device on one side and the body diode freewheeling characteristics of the device on the other side, thereby improving the reliability of the device.

[0004] In the first aspect, the present invention provides a manufacturing method of an asymmetric highly reliable trench-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a shunt region; Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region; Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the drift layer and the P-type well region, and deposit metal to form a Schottky metal layer; Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type base region; Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region; Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to the upper side of the P-type source region, and deposit metal to form a source metal layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and etch the drift layer, shunt region, and P-type well region to form a first groove, and deposit to form an insulating dielectric layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, and etch the insulating dielectric layer to form a trench, deposit metal to form a gate metal layer, and remove the blocking layer to complete the preparation.

[0005] In a second aspect, the present invention provides an asymmetric high-reliability trench-gate silicon carbide VDMOS, which is prepared by using the preparation method of an asymmetric high-reliability trench-gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are as follows: First, the present invention constructs an asymmetric high-reliability trench-gate structure, and this structure reflects asymmetry and reliability from two aspects: protecting the insulating dielectric layer from the P-type well region and constructing a Schottky parasitic diode. Second, the asymmetric P-type well region constructed by the present invention, and the space charge region formed by the P-type well region, drift layer, and shunt region under reverse voltage withstand conditions can effectively suppress the electric field concentration caused at the gate corner of the device, thereby improving the gate reliability of the device. Third, the N-type source region and P-type source region of the present invention are not symmetrically distributed on the left and right sides of the gate. This is because the Schottky metal layer constructed on one side of the device gate semi-wrapped by the P-type well region is in direct contact with the N-type source region, which can increase the low-resistance contact area between the Schottky metal layer and the source metal layer and improve the current-carrying capacity of the Schottky diode. Fourth, the asymmetric P-type well region of the present invention increases the pn-junction contact area of the parasitic pn-junction body diode of the device, which can synchronously increase the freewheeling capacity of the pn-junction body diode. The structural optimization of the two body diodes can improve the freewheeling capacity when the device is turned off and improve the device reliability. Description of the Drawings

[0007] The present invention will be further described below with reference to the drawings in conjunction with embodiments.

[0008] Figure 1 It is a schematic diagram of an asymmetric high-reliability trench-gate silicon carbide VDMOS of the present invention.

[0009] Figure 2 It is a process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS of the present invention Figure 1 。

[0010] Figure 3 It is a process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS of the present invention Figure 2 。

[0011] Figure 4 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 3 。

[0012] Figure 5 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 4 。

[0013] Figure 6 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 5 。

[0014] Figure 7 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 6 。

[0015] Figure 8 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 7 。

[0016] Figure 9 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 8 。

[0017] Figure 10 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 9 。

[0018] Figure 11 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 10 。

[0019] Figure 12 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 10 One.

[0020] Figure 13 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 10 Two.

[0021] Figure 14 Process cross-section of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to the present invention Figure 10 Three. Specific embodiments

[0022] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0024] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0025] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0026] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0027] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing an asymmetric high-reliability trench-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102; Step 2: Form a blocking layer 100 above the drift layer 102, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a shunt region 1032; Step 3: Remove the blocking layer 100 in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type well region 103; Step 4: Remove the blocking layer 100 in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, etch the drift layer 102 and the P-type well region 103, and deposit metal to form a Schottky metal layer 106; Step 5: Remove the blocking layer 100 in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type base region 1033; Step 6: Remove the blocking layer 100 in Step 5, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type source region 104; Step 7: Remove the blocking layer 100 in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 105; Step 8: Remove the blocking layer 100 in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and etch the drift layer 102 to the upper side of the P-type source region 104, and deposit metal to form a source metal layer; Step 9: Remove the blocking layer 100 in Step 8, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, etch the drift layer 102, the shunt region 1032 and the P-type well region 103 to form a first groove 1031, and deposit to form an insulating dielectric layer 107; Step 10: Remove the barrier layer 100 of Step 9, reform the barrier layer 100, etch the barrier layer 100 to form a through hole, and etch the insulating dielectric layer 107 to form a groove 1071. Deposit metal to form a gate metal layer 108, and remove the barrier layer 100 to complete the preparation.

[0028] In this embodiment, preferably, the drift layer 102 is provided with a second groove (not shown in the figure), and the lower part of the Schottky metal layer 106 is disposed in the second groove.

[0029] In this embodiment, preferably, the lower side surface of the gate metal layer 108 is lower than the lower side surface of the P-type base region 1033.

[0030] In this embodiment, preferably, the doping concentration of the shunt region 1032 is greater than the doping concentration of the P-type base region 1033, and the doping concentration of the P-type well region 103 is greater than the doping concentration of the P-type base region 1033.

[0031] In this embodiment, preferably, the doping concentration of the shunt region 1032 is greater than the doping concentration of the drift layer 102, and the doping concentration of the P-type well region 103 is greater than the doping concentration of the drift layer 102.

[0032] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: A silicon carbide substrate 101, A drift layer 102, the lower side surface of the drift layer 102 is connected to the upper side surface of the silicon carbide substrate 101; A P-type well region 103, the lower side surface of the P-type well region 103 is connected to the upper side surface of the drift layer 102; a first groove 1031, a shunt region 1032, and a P-type base region 1033 are provided in the P-type well region 103. The lower side surface of the shunt region 1032 is connected to the upper side surface of the drift layer 102. The shunt region 1032 is located at the lower left corner of the first groove 1031. The lower side surface of the P-type base region 1033 is connected to the shunt region 1032 and is located on the left side of the first groove 1031; A P-type source region 104, the lower side surface of the P-type source region 104 is connected to the upper side surface of the P-type well region 103; An N-type source region 105, the lower side surface of the N-type source region 105 is respectively connected to the P-type well region 103 and the P-type base region 1033, and the N-type source region 105 is connected to the P-type source region 104; A Schottky metal layer 106, the lower side surface of the Schottky metal layer 106 is connected to the drift layer 102, and one side surface of the Schottky metal layer 106 is connected to one side surface of the P-type well region 103 and one side surface of the N-type source region 105; The insulating dielectric layer 107, the lower part of the insulating dielectric layer 107 is arranged in the first groove 1031, and the outer sides of the insulating dielectric layer 107 are respectively connected to the P-type source region 104, the N-type source region 105, the P-type well region 103, the P-type base region 1033 and the shunt region 1032; a groove 1071 is arranged in the insulating dielectric layer 107; The gate metal layer 108, the gate metal layer 108 is arranged in the groove 1071; The source metal layer 109, the source metal layer is respectively connected to the P-type source region 104, the N-type source region 105 and the Schottky metal layer 106; And, the drain metal layer 110, the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101.

[0033] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102 and the shunt region 1032 are all N-type, the doping concentration of the silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentration of the drift layer 102 is 6 - 10e15 cm -3 , the doping concentration of the shunt region 1032 is 6 - 10e16 cm -3 , the doping concentration of the P-type well region 103 is 1 - 5e17 cm -3 , the doping concentration of the P-type base region 1033 is 1 - 5e16 cm -3 , the doping concentration of the P-type source region 104 is 1 - 5e19 cm -3 , the doping concentration of the N-type source region 105 is 2 - 8e18 cm -3 , the material of the insulating dielectric layer 107 can be silicon dioxide; The doping concentration of the silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a compromise between the reverse breakdown voltage and the on-resistance of the device. The doping concentration design of the P-type well region 103 is to protect the gate and source of the device, shield the gate-drain capacitance, reduce the Miller capacitance and improve the switching speed of the device; The design of the doping concentration of the shunt region 1032: one is to reduce the body resistance of the device and the conduction loss of the device; the other is to divert the electrons from one side when the device is conducting, so as to increase the effective freewheeling area of the device, reduce the on-resistance and avoid heat concentration; The Schottky metal layer 106 is used to construct a parasitic Schottky diode inside the device, thereby reducing the freewheeling loss of the body diode of the device; the doping concentration of the P-type source region 104 is to reduce the loss of the parasitic pn junction body diode of the device; the doping concentration design of the N-type source region 105 and the P-type source region 104 is to reduce the contact resistance of the device, thereby reducing the on-resistance of the device; the doping concentration of the N-type base region is to reduce the gate charge on the basis of ensuring the turn-off characteristics of the device, reducing the drive loss of the device. The thickness of the silicon carbide substrate 101 of the device is 1 μm, and the thickness of the drift layer 102 is 50 - 100 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The maximum thickness of the P-type well region 103 on one side of the P-type base region 1033 is 1.2 μm, and the maximum width is 900 nm; the width of the P-type source region 104 on one side of the P-type base region 1033 is 600 m, and the thickness is 300 nm; the thickness of the N-type source region 105 on one side of the P-type base region 1033 is 300 nm, and the width is 600 nm; this is to construct a Schottky diode. The width of the Schottky metal layer 106 is 300 nm, which is the design of the current capacity of the device. The thickness of the Schottky metal layer 106 is 1.5 μm, and its lower side is 300 nm lower than the lower side of the P-type well region 103. This is to increase the Schottky junction contact area of the Schottky diode and improve the current capacity of the Schottky diode; the width of the P-type base region 1033 is 300 nm, and the thickness is 300 nm. This is to ensure the gate control ability of the device. The maximum width of the shunt region 1032 is 900 nm, and the maximum thickness is 600 nm. This is to make its bottom flush with the bottom of the P-type well region 103 to ensure the structural integrity of the device. The width of the P-type well region 103 on one side of the Schottky metal layer 106 is 1.5 μm. This is to ensure the semi-wrapping of the device gate. The width of the insulating dielectric layer 107 is 1.2 μm, the bottom thickness of the insulating dielectric layer 107 is 100 nm, and the thickness of both the left and right sides is 50 nm to ensure the breakdown voltage ability of the insulating dielectric at the bottom of the device and improve the reliability. The thickness of the insulating dielectric on both left and right sides of the device is 50 nm to ensure the gate control ability of the device. The width of the device gate metal layer 108 is 1.1 μm, and the thickness is 1.1 μm. This is to ensure that the lower side of the gate metal layer 108 is lower than the lower side of the P-type base region 1033 to ensure the gate control ability of the device.

[0034] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of an asymmetric high-reliability trench-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a shunt region; Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region; Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the drift layer and the P-type well region, and deposit metal to form a Schottky metal layer; Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type base region; Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region; Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the drift layer to the upper side of the P-type source region, and deposit metal to form a source metal layer; Step 9: Remove the blocking layer in Step 8, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the drift layer, the shunt region and the P-type well region to form a first groove, and deposit to form an insulating dielectric layer; Step 10: Remove the blocking layer in Step 9, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the insulating dielectric layer to form a trench, deposit metal to form a gate metal layer, and remove the blocking layer to complete the preparation.

2. The manufacturing method of an asymmetric high-reliability trench-gate silicon carbide VDMOS according to claim 1, characterized in that: The drift layer is provided with a second groove, and the lower part of the Schottky metal layer is arranged in the second groove.

3. The manufacturing method of an asymmetric high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The lower side of the gate metal layer is lower than the lower side of the P-type base region.

4. The manufacturing method of an asymmetric high-reliability trench-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the shunt region is greater than the doping concentration of the P-type base region, and the doping concentration of the P-type well region is greater than the doping concentration of the P-type base region.

5. The manufacturing method of an asymmetric high-reliability trench-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the shunt region is greater than the doping concentration of the drift layer, and the doping concentration of the P-type well region is greater than the doping concentration of the drift layer.

6. An asymmetric high-reliability trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of Claims 1 to 5.

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