Manufacturing method of silicon carbide device terminal structure

Abstract

The invention discloses a manufacturing method of a silicon carbide device terminal structure. The manufacturing method comprises the following steps: S1, preparing a 4H-SiC substrate with an epitaxial layer; s2, manufacturing a first hard mask on the upper surface of the epitaxial layer; s3, performing primary channel injection of Al ions at normal temperature, and forming a first JTE ring, a second JTE ring and a third JTE ring on the epitaxial layer; s4, removing the first hard mask, and manufacturing a second hard mask on the upper surface of the epitaxial layer; s5, high-energy Al ions are injected at a high temperature, a P + main junction region is formed, and a plurality of P + rings are formed in the region where the JTE rings are located; s6, removing the second hard mask, depositing a layer of field oxide on the upper surface of the epitaxial layer, forming a source electrode on the P + main junction region, and forming a drain electrode on the lower surface of the 4H-SiC substrate; and S7, performing high-temperature annealing to obtain the silicon carbide device terminal structure. The silicon carbide device terminal structure integrates the advantages of channel injection, a ring auxiliary technology and segmented JTE, the process cost is effectively reduced, the breakdown voltage is remarkably improved, and the sensitivity of the breakdown voltage to the JTE injection dosage is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a manufacturing method for a terminal structure of a silicon carbide device. Background Art

[0002] Silicon carbide power devices require a good design for the terminal structure. A reasonably designed terminal structure can ensure a relatively high breakdown voltage (strong voltage resistance). The existing terminal structure has a complex process and poor reliability. There is an urgent need for a terminal structure with good voltage resistance and a simple manufacturing process. Summary of the Invention

[0003] In view of the above problems, the present invention overcomes at least one deficiency and provides a manufacturing method for a terminal structure of a silicon carbide device.

[0004] The technical solution adopted by the present invention is as follows: A manufacturing method for a terminal structure of a silicon carbide device, comprising the following steps: S1. Prepare a 4H-SiC substrate, on the upper surface of which an epitaxial layer is formed; S2. Fabricate a first hard mask on the upper surface of the epitaxial layer, and three first annular windows are formed on the first hard mask at intervals; S3. Perform a primary channel implantation of Al ions at room temperature, and then implant high-energy Al ions at a high temperature to form three JTE rings at intervals on the epitaxial layer. The JTE rings are, from the inside to the outside, the first JTE ring, the second JTE ring, and the third JTE ring in sequence; only two ion implantations are required to form the three JTE rings; S4. Remove the first hard mask, fabricate a second hard mask on the upper surface of the epitaxial layer, and a main junction window and a plurality of second annular windows located above the corresponding JTE rings are formed on the second hard mask. The main junction window and the first JTE ring have an overlapping area; S5. Implant high-energy Al ions at a high temperature. In the area corresponding to the main junction window of the epitaxial layer, a P+ main junction region is formed, and a plurality of P+ rings are formed in the area where the JTE rings are located. The plurality of P+ rings are, from the inside to the outside, the first P+ ring to the nth P+ ring in sequence. The depth of the P+ main junction region is less than the depth of the JTE rings, and the depth of the P+ rings is less than the depth of the JTE rings; S6. Remove the second hard mask, deposit a layer of field oxide on the upper surface of the epitaxial layer, form a source electrode on the upper surface of the P+ main junction region through a magnetron sputtering process, and form a drain electrode on the lower surface of the 4H-SiC substrate; S7. Perform high-temperature annealing to obtain the terminal structure of the silicon carbide device.

[0005] Floating field rings (FFRs) and junction termination extensions (JTEs) are the most commonly used techniques for protecting the edges of SiC devices. However, FFRs typically require complex patterning and etching processes to define the narrow spaces between the heavily doped p+ rings, which increases the manufacturing difficulty. On the other hand, while the standard implanted JTE (SZ-JTE) is simple to operate, it is extremely sensitive to the implantation dose. The multi-zone JTE (MZ-JTE), although not requiring precise linewidth control, has extremely high requirements for dose control, which also poses process challenges.

[0006] Channel ion implantation is a technique that utilizes the lattice structure of crystalline materials to implant ions along specific crystal orientations. In crystalline materials, atoms are arranged in a regular lattice structure, forming a series of parallel channels. When an ion beam is implanted along these channel directions, the ions are subjected to the collective forces of the lattice atoms and thus travel through the channels, reducing the probability of collision with the lattice atoms. In the present invention, channel implantation is carried out at room temperature. By introducing the channel implantation technique into the JTE edge termination design, the sensitivity of the JTE structure to the fixed charges in the oxide layer is reduced. Combining with the segmented structure, the JTE dose window is effectively expanded, and at the same time, the process steps are still very simple.

[0007] This application only requires two ion implantations in the terminal part (JTE ring) to fully meet the requirements of 650 V power devices. The terminal structure of the silicon carbide device in this application integrates the advantages of channel implantation, ring-assisted technology, and segmented JTE, not only effectively reducing the process cost, but also significantly improving the breakdown voltage, reducing the sensitivity of the breakdown voltage to the JTE implantation dose, and achieving these performance improvements with a shorter terminal length. In addition, its wide implantation dose window ensures the feasibility and reliability of this technology in practical applications. In the silicon carbide manufacturing process, it is an unavoidable phenomenon to generate surface fixed charges at the silicon carbide and oxide interface. The structure proposed in the present invention can well improve the influence of the electric field distribution of the fixed charges. At the same time, the depletion layer is extended as far as possible to the end of the device, achieving the purpose of improving the terminal efficiency.

[0008] In this application, the P+ main junction region and the first JTE ring have an overlapping part. Such a design can make the electric field evenly distributed between the P+ main junction region and the JTE region, avoid excessive local electric field, and reduce the breakdown risk.

[0009] In actual operation, in steps S3 and S5, the high temperature refers to 500 °C, and the dose magnitude is generally on the order of 10 11 cm -2 -10 15 cm -2 .

[0010] In actual operation, the source electrode can be 4 μm of Al / Ti, and the drain electrode can be 5 μm of Ti / Al.

[0011] In actual operation, the high-temperature annealing temperature in step S7 is 850 °C. By high-temperature annealing, the interface states at the metal-semiconductor interface are reduced to achieve an ohmic contact with an ideal contact resistance.

[0012] In one embodiment of the present invention, the thickness of the epitaxial layer is 4 μm to 7 μm, and the doping concentration of the epitaxial layer is 1×10 16 cm -3 .

[0013] In one embodiment of the present invention, the distance between the first JTE ring and the second JTE ring is S1, and the distance between the second JTE ring and the third JTE ring is S2; S1 is 1 μm and S2 is 1.4 μm.

[0014] In one embodiment of the present invention, the ring width of the overlapping region between the main junction window and the first JTE ring is L, the ring width of the first JTE ring is L0, the ring width of the second JTE ring is L1, and the ring width of the third JTE ring is L2. L is 5 μm, L0 is 22 μm, L1 is 18.6 μm, and L2 is 18.2 μm.

[0015] In one embodiment of the present invention, among the multiple P+ rings on the JTE ring, the distance between the first P+ ring and the inner circle of the JTE ring where it is located is s1, and the distance between the nth P+ ring and the (n - 1)th P+ ring is sn. sn = s1 + A(n - 1), where A is an increasing factor.

[0016] In one embodiment of the present invention, s1 is 2.2 μm and A is 0.1.

[0017] In one embodiment of the present invention, among the multiple P+ rings on the JTE ring, the ring width of the nth P+ ring is wn, and wn is 2.5 μm.

[0018] In one embodiment of the present invention, in step S5, after injecting high-energy Al ions, it further includes a step of performing high-temperature annealing at 1700 °C.

[0019] In one embodiment of the present invention, the materials of the first hard mask and the second hard mask are SiO2.

[0020] In one embodiment of the present invention, the field oxide is a SiO2 layer, and the thickness of the field oxide is 1 μm to 2 μm.

[0021] In the solution of this application, improvements such as spatial modulation JTE (SM-JTE), multi-floating zone JTE (MFZ-JTE), and counter doping (CD-JTE) are realized to expand the dose tolerance window of JTE. Compared with the traditional SZ-JTE and two-zone JTE (TZ-JTE), SM-JTE and RA-JTE provide higher breakdown voltages under high-dose and low-dose conditions, respectively.

[0022] The beneficial effects of the present invention are as follows: The terminal structure of the silicon carbide device of this application integrates the advantages of channel implantation, ring-assisted technology, and segmented JTE, which not only effectively reduces the process cost, but also significantly improves the breakdown voltage, reduces the sensitivity of the breakdown voltage to the JTE implantation dose, and realizes these performance improvements with a shorter terminal length. Description of the Drawings

[0023] Figure 1 It is a schematic diagram of forming a JTE region by channel implantation; Figure 2 It is a schematic diagram of forming a main junction and a P+ ring by ordinary implantation; Figure 3 It is a schematic diagram of the terminal structure of a silicon carbide device; Figure 4 It is a schematic diagram of the electric field distribution of the terminal structure of a silicon carbide device.

[0024] Each reference numeral in the figure is as follows: 1, 4H-SiC substrate; 2, epitaxial layer; 3, first hard mask; 31, first annular window; 41, first JTE ring; 42, second JTE ring; 43, third JTE ring; 401, P+ ring; 5, second hard mask; 51, main junction window; 52, second annular window; 6, P+ main junction region; 7, field oxide; 8, source electrode; 9, drain electrode. Detailed Embodiments

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. Usually, the components of the embodiments of this application described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "inner" and "outer" is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present application. In addition, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0027] In the description of the present application, it should also be noted that unless otherwise clearly specified and limited, the terms "set" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0028] The present invention will be described in detail below with reference to the accompanying drawings.

[0029] As Figures 1 to 3 shown, a manufacturing method of a silicon carbide device terminal structure includes the following steps: S1, see Figure 1 , prepare a 4H-SiC substrate 1, and an epitaxial layer 2 is formed on the upper surface of the 4H-SiC substrate 1; S2, see Figure 1 , fabricate a first hard mask 3 on the upper surface of the epitaxial layer 2, and three first annular windows 31 are formed on the first hard mask 3 at intervals; S3, see Figure 1 , perform a primary channel implantation of Al ions at room temperature, and then implant high-energy Al ions at a high temperature to form three JTE rings arranged at intervals on the epitaxial layer 2. The JTE rings are, from the inside to the outside, a first JTE ring 41, a second JTE ring 42, and a third JTE ring 43 in sequence; only two ion implantations are required to form the three JTE rings; S4, see Figure 2 , remove the first hard mask 3, fabricate a second hard mask 5 on the upper surface of the epitaxial layer 2, a main junction window 51 and a plurality of second annular windows 52 located above the corresponding JTE rings are formed on the second hard mask 5, and the main junction window 51 and the first JTE ring 41 have an overlapping area; S5, see Figure 2, high-energy Al ions are implanted at high temperature. In the corresponding area of the main junction window 51 of the epitaxial layer 2, a P+ main junction region 6 is formed, and multiple P+ rings 401 are formed in the area where the JTE ring is located. The multiple P+ rings 401 are the first P+ ring 401 to the nth P+ ring 401 in sequence from the inside to the outside. The depth of the P+ main junction region 6 is less than the depth of the JTE ring, and the depth of the P+ ring 401 is less than the depth of the JTE ring; S6. See Figure 3 , the second hard mask 5 is removed, a field oxide 7 is deposited on the upper surface of the epitaxial layer 2, a source electrode 8 is formed on the upper surface of the P+ main junction region 6 through a magnetron sputtering process, and a drain electrode 9 is formed on the lower surface of the 4H-SiC substrate 1; S7. See Figure 3 , high-temperature annealing is performed to obtain the terminal structure of the silicon carbide device.

[0030] In actual operation, in steps S3 and S5, implanting high-energy Al ions at high temperature refers to conventional Al ion implantation. The temperature is usually 500°C, and the dose level is generally on the order of 10 11 cm -2 -10 15 cm -2 .

[0031] In this embodiment, the source electrode 8 is 4 μm of Al / Ti, and the drain electrode 9 is 5 μm of Ti / Al.

[0032] In this embodiment, the high-temperature annealing temperature in step S7 is 850°C. By high-temperature annealing, the interface states at the metal-semiconductor interface are reduced to achieve an ohmic contact with an ideal contact resistance.

[0033] In this embodiment, the thickness of the epitaxial layer 2 is 6 μm, and the doping concentration of the epitaxial layer 2 is 1×1016 cm-3.

[0034] As Figure 1 、 2 and shown in 3, in this embodiment, the interval between the first JTE ring 41 and the second JTE ring 42 is S1, and the interval between the second JTE ring 42 and the third JTE ring 43 is S2; S1 is 1 μm and S2 is 1.4 μm.

[0035] As Figure 3 shown, in this embodiment, the ring width of the overlapping region between the main junction window 51 and the first JTE ring 41 is L (that is, the ring width of the overlapping region between the P+ main junction region 6 and the first JTE ring 41 is L), the ring width of the first JTE ring 41 is L0, the ring width of the second JTE ring 42 is L1, and the ring width of the third JTE ring 43 is L2. L is 5 μm, L0 is 22 μm, L1 is 18.6 μm, and L2 is 18.2 μm.

[0036] As Figure 2 and3 As shown, in this embodiment, among the multiple P+ rings 401 on the JTE ring, the distance between the first P+ ring 401 and the inner ring of the JTE ring where it is located is s1, and the distance between the nth P+ ring 401 and the (n - 1)th P+ ring 401 is sn, and sn = s1 + A(n - 1), where A is an increasing factor.

[0037] In this embodiment, s1 is 2.2 μm and A is 0.1.

[0038] As Figure 2 and 3 As shown, in this embodiment, among the multiple P+ rings 401 on the JTE ring, the ring width of the nth P+ ring 401 is wn, and wn is 2.5 μm.

[0039] In this embodiment, in step S5, after injecting high-energy Al ions, it further includes a step of performing high-temperature annealing at 1700 °C.

[0040] In this embodiment, the materials of the first hard mask and the second hard mask are SiO2, the field oxide is a SiO2 layer, and the thickness of the field oxide is 1 μm to 2 μm.

[0041] In this embodiment, the channel implantation is carried out at room temperature. Introducing the channel implantation technology into the JTE edge termination design reduces the sensitivity of the JTE structure to the fixed charge in the oxide layer. Combining with the segmented structure, it effectively expands the JTE dose window and at the same time achieves the effect that the process steps are still very simple.

[0042] This application only requires two ion implantations in the terminal part (JTE ring) to fully meet the requirements of 650 V power devices. The terminal structure of the silicon carbide device of this application integrates the advantages of channel implantation, ring assist technology and segmented JTE, which not only effectively reduces the process cost, but also significantly improves the breakdown voltage, reduces the sensitivity of the breakdown voltage to the JTE implantation dose, and realizes these performance improvements with a shorter terminal length. In addition, its wide implantation dose window ensures the feasibility and reliability of this technology in practical applications. In the silicon carbide manufacturing process, it is an unavoidable phenomenon to generate surface fixed charges at the interface between silicon carbide and the oxide layer.

[0043] The P+ main junction region 6 of this application has an overlapping part with the first JTE ring. Such a design can make the electric field evenly distributed between the P+ main junction region 6 and the JTE region, avoid too high local electric field, and reduce the breakdown risk.

[0044] As Figure 4As shown, it is a schematic diagram of the electric field distribution of the terminal structure of a silicon carbide device. The structure proposed by the present invention can well improve the influence of the electric field distribution of fixed charges. At the same time, the purpose of making the depletion layer extend as far as possible to the end of the device and improving the terminal efficiency is achieved.

[0045] The above are only the preferred embodiments of the present invention, and thus do not limit the patent protection scope of the present invention. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention, directly or indirectly applied in other related technical fields, shall be similarly included in the protection scope of the present invention.

Claims

1. A manufacturing method for a terminal structure of a silicon carbide device, characterized in that, It includes the following steps: S1. Prepare a 4H-SiC substrate, and an epitaxial layer is formed on the upper surface of the 4H-SiC substrate; S2. Fabricate a first hard mask on the upper surface of the epitaxial layer, and three first annular windows are formed on the first hard mask at intervals; S3. Perform a primary channel implantation of Al ions at room temperature, and then implant high-energy Al ions at a high temperature to form three JTE rings arranged at intervals on the epitaxial layer. The JTE rings are, from the inside to the outside, the first JTE ring, the second JTE ring, and the third JTE ring in sequence; S4. Remove the first hard mask, fabricate a second hard mask on the upper surface of the epitaxial layer, and a main junction window and a plurality of second annular windows located above the corresponding JTE rings are formed on the second hard mask. The main junction window and the first JTE ring have an overlapping area; S5. Implant high-energy Al ions at a high temperature. In the area corresponding to the main junction window of the epitaxial layer, a P+ main junction region is formed, and a plurality of P+ rings are formed in the area where the JTE rings are located. The plurality of P+ rings are, from the inside to the outside, the first P+ ring to the nth P+ ring in sequence; S6. Remove the second hard mask, deposit a layer of field oxide on the upper surface of the epitaxial layer, form a source electrode on the upper surface of the P+ main junction region through a magnetron sputtering process, and form a drain electrode on the lower surface of the 4H-SiC substrate; S7. Perform a high-temperature annealing to obtain a silicon carbide device terminal structure.

2. The manufacturing method of the silicon carbide device terminal structure according to claim 1, characterized in that, The thickness of the epitaxial layer is 4 μm to 7 μm, and the doping concentration of the epitaxial layer is 1×10 16 cm -3 .

3. The manufacturing method of the silicon carbide device terminal structure according to claim 1, wherein, The interval between the first JTE ring and the second JTE ring is S1, and the interval between the second JTE ring and the third JTE ring is S2; S1 is 1 μm, and S2 is 1.4 μm.

4. The manufacturing method of the silicon carbide device terminal structure according to claim 3, characterized in that, The ring width of the overlapping area between the main junction window and the first JTE ring is L, the ring width of the first JTE ring is L0, the ring width of the second JTE ring is L1, and the ring width of the third JTE ring is L2. L is 5 μm, L0 is 22 μm, L1 is 18.6 μm, and L2 is 18.2 μm.

5. The manufacturing method of the silicon carbide device terminal structure according to claim 4, characterized in that, Among the plurality of P+ rings on the JTE ring, the distance between the first P+ ring and the inner circle of the JTE ring where it is located is s1, and the distance between the nth P+ ring and the (n - 1)th P+ ring is sn. sn = s1 + A(n - 1), and A is an increasing factor.

6. The manufacturing method of the silicon carbide device terminal structure according to claim 5, characterized in that, s1 is 2.2 μm, and A is 0.

1.

7. The manufacturing method of the silicon carbide device terminal structure according to claim 5, characterized in that, Among the plurality of P+ rings on the JTE ring, the ring width of the nth P+ ring is wn, and wn is 2.5 μm.

8. The manufacturing method of the silicon carbide device terminal structure according to claim 1, characterized in that, In step S5, after implanting high-energy Al ions, it further includes a step of performing a high-temperature annealing at 1700 °C.

9. The manufacturing method of the silicon carbide device terminal structure according to claim 1, characterized in that, The materials of the first hard mask and the second hard mask are SiO2.

10. The manufacturing method of the silicon carbide device terminal structure according to claim 1, characterized in that, The field oxide is a SiO2 layer, and the thickness of the field oxide is 1 μm to 2 μm.

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