Common-drain double-MOSFET chip packaging structure

Abstract

The invention provides a common drain electrode double metal-oxide-semiconductor field effect transistor (MOSFET) chip packaging structure. The invention relates to a lead frame packaging structure, which comprises a lead frame base island, a plurality of lead frame pins, a first MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) chip, a second MOSFET chip and a plastic packaging body, wherein the plurality of lead frame pins are arranged on two opposite sides of the lead frame base island; the first MOSFET chip and the second MOSFET chip are stacked on the lead frame base island; the plastic packaging body wraps the lead frame base island, the plurality of lead frame pins, the first MOSFET chip and the second MOSFET chip; the plurality of lead frame pins comprise a lead frame second S-pole pin arranged on one side of the lead frame base island, and a lead frame first G-pole pin and a lead frame second G-pole pin which are arranged on the other side of the lead frame; the outer surfaces of the lead frame base island, the lead frame first G pole pin, the lead frame second G pole pin and the lead frame second S pole pin are located on the same plane, and the outer surfaces are exposed out of the plastic package body. The common-drain double-MOSFET chip packaging structure disclosed by the invention has the advantage of small size.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging, and specifically to a common-drain dual-MOSFET chip packaging structure. Background Art

[0002] The application of BMS (power management system) requires two MOS chips to be electrically connected back-to-back (the D poles are connected to each other). Currently, the components used for BMS on the market are two MOS chips separately packaged in two PDFN56 lead frames, and then connected through PCB board wiring, which is not conducive to the miniaturization and thinning of BMS terminals. Summary of the Invention

[0003] The purpose of the present invention is to provide a common-drain dual-MOSFET chip packaging structure that is conducive to the miniaturization and thinning of the circuit.

[0004] In an embodiment of the present invention, a common-drain dual-MOSFET chip packaging structure is provided, which includes a lead frame base island, a plurality of lead frame pins arranged on opposite sides of the lead frame base island, a first MOSFET chip and a second MOSFET chip stacked on the lead frame base island, and a plastic package that wraps the lead frame base island, the plurality of lead frame pins, the first MOSFET chip, and the second MOSFET chip. The plurality of lead frame pins include a lead frame second S pole pin arranged on one side of the lead frame base island, a lead frame first G pole pin, and a lead frame second G pole pin arranged on the other side of the lead frame. The S poles and G poles of the first MOSFET chip and the second MOSFET chip are both arranged on the front side of the chip. The D poles of the first MOSFET chip and the second MOSFET chip are both arranged on the back side of the chip. The front side of the first MOSFET chip faces the lead frame base island and is welded to the lead frame base island, and the S pole and G pole of the first MOSFET chip are respectively electrically connected to the lead frame base island and the lead frame first G pole pin. The back side of the second MOSFET chip faces the back side of the first MOSFET chip, and the D poles of the second MOSFET chip and the first MOSFET chip remain electrically connected. The G pole and S pole of the second MOSFET chip are respectively connected to the lead frame second G pole pin and the lead frame second S pole pin. The outer surfaces of the lead frame base island, the lead frame first G pole pin, the lead frame second G pole pin, and the lead frame second S pole pin are all located on the same plane and are all exposed outside the plastic package.

[0005] In an embodiment of the present invention, the first MOSFET chip and the second MOSFET chip are back-to-back and the positions of their G electrodes are staggered. The G electrode of the first MOSFET chip is electrically connected to the first G electrode of the lead frame by welding, and the G electrode of the second MOSFET chip is electrically connected to the second G electrode of the lead frame by a copper wire.

[0006] In an embodiment of the present invention, the multiple lead frame pins further include two mutually electrically connected D-pole shared pins of the lead frame disposed between the first G-pole pin of the lead frame and the second G-pole pin of the lead frame. The D-pole shared pins of the lead frame are electrically connected to the D electrodes of the first MOSFET chip and the second MOSFET chip.

[0007] In an embodiment of the present invention, the D-pole shared pins of the lead frame are electrically connected to the D electrodes of the first MOSFET chip and the second MOSFET chip through a copper clip disposed between the first MOSFET chip and the second MOSFET chip.

[0008] In an embodiment of the present invention, the D electrodes of the first MOSFET chip and the second MOSFET chip are electrically connected by welding, and the first MOSFET chip and the second MOSFET chip are staggered and overlapped, so that a part of the D electrode of the first MOSFET chip is exposed. The D-pole shared pin of the lead frame is electrically connected to the exposed D electrode of the first MOSFET chip through a copper wire.

[0009] In an embodiment of the present invention, the second S pin of the lead frame is electrically connected to the S electrode of the second MOSFET chip through a copper clip.

[0010] In an embodiment of the present invention, the multiple lead frame pins further include two lead frame floating pins disposed between the first G-pole pin of the lead frame and the second G-pole pin of the lead frame.

[0011] In an embodiment of the present invention, the D electrodes of the first MOSFET chip and the second MOSFET chip are electrically connected by welding.

[0012] In an embodiment of the present invention, the second S pin of the lead frame is electrically connected to the S electrode of the second MOSFET chip through a copper clip or a copper wire.

[0013] In an embodiment of the present invention, recessed portions are provided around the front surface of the lead frame base island. Each of the multiple lead frame pins includes a corresponding root portion, and the backs of the multiple lead frame pins protrude from the root portions of the multiple lead frame pins.

[0014] Compared with the prior art, by adopting the common-drain dual-MOSFET chip packaging structure of the present invention, the circuits formed by two MOS chips are packaged back-to-back in a plastic package, thereby reducing the circuit area of the two chips, directly saving half of the area installed on the circuit board, and being beneficial to the miniaturization and thinness of the terminal. Brief Description of the Drawings

[0015] Figure 1 is a schematic circuit connection diagram of a common-drain dual-MOSFET chip.

[0016] Figure 2 is a schematic pin diagram of the common-drain dual-MOSFET chip packaging structure according to an embodiment of the present invention.

[0017] Figure 3 is a schematic structural diagram of the lead frame of the common-drain dual-MOSFET chip packaging structure according to an embodiment of the present invention.

[0018] Figure 4 is an implementation of an embodiment of the present invention Figure 1 in the schematic packaging process diagram of the common-drain dual-MOSFET chip packaging structure.

[0019] Figure 5 is another implementation of an embodiment of the present invention Figure 1 in the schematic packaging process diagram of the common-drain dual-MOSFET chip packaging structure.

[0020] Figure 6 is another schematic circuit connection diagram of a common-drain dual-MOSFET chip.

[0021] Figure 7 is an implementation of an embodiment of the present invention Figure 6 in the schematic packaging process diagram of the common-drain dual-MOSFET chip packaging structure.

[0022] Figure 8 is another implementation of an embodiment of the present invention Figure 6 in the schematic packaging process diagram of the common-drain dual-MOSFET chip packaging structure. Detailed Description of the Embodiments

[0023] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] The present invention provides a common-drain dual-MOSFET chip packaging structure, which realizes the purpose of reducing the circuit area by encapsulating two MOSFET chips back to back in a plastic package. The common-drain dual-MOSFET chip packaging structure includes a lead frame base island, a plurality of lead frame pins arranged on opposite sides of the lead frame base island, a first MOSFET chip and a second MOSFET chip stacked on the lead frame base island, and a plastic package that wraps the lead frame base island, the plurality of lead frame pins, the first MOSFET chip, and the second MOSFET chip. It should be noted that in the present invention, the S poles and G poles of the first MOSFET chip and the second MOSFET chip are both arranged on the front side of the chip, and the D poles of the first MOSFET chip and the second MOSFET chip are both arranged on the back side of the chip.

[0025] The present invention will be described in detail below with reference to specific embodiments.

[0026] As Figure 1 shown, the circuit connection method of a common-drain dual-MOSFET chip is as follows: The D poles of the first MOSFET chip and the second MOSFET chip are electrically connected and led out to the lead frame D-pole common pins D1 / D2 for subsequent testing.

[0027] As Figure 2 shown, among the plurality of lead frame pins exposed after packaging, it includes four lead frame second S-pole pins S2 arranged on one side of the lead frame base island S1, a lead frame first G-pole pin G1, a lead frame second G-pole pin G2 arranged on the other side of the lead frame, and two mutually electrically connected lead frame D-pole common pins D1 / D2 arranged between the lead frame first G-pole pin G1 and the lead frame second G-pole pin G2. It should be noted that in the embodiment of the present invention, the lead frame base island S1 is electrically connected to the S pole of the first MOSFET chip to serve as the external S pole of the first MOSFET chip. The lead frame D-pole common pins D1 / D2 are respectively electrically connected to the D poles of the first MOSFET chip and the second MOSFET chip. The lead frame first G-pole pin G1 is electrically connected to the G pole of the first MOSFET chip. The four lead frame second S-pole pins S2 are mutually electrically connected and are electrically connected to the S pole of the second MOS chip. The lead frame second G-pole pin G2 is electrically connected to the G pole of the second MOS chip. Of course, the number of the lead frame second S-pole pins S2 is not limited to four, and it can be set according to actual needs, and the invention does not limit this.

[0028] As Figure 3As shown in the figure, the lead frame corresponding to the common-drain dual-MOSFET chip package structure of the present invention includes a lead frame base island S1, four interconnected lead frame second S-pole pins S2 disposed on one side of the lead frame base island, a lead frame first G-pole pin G1 disposed on the opposite side of the lead frame second S-pole pins S2, a lead frame second G-pole pin G2, and two interconnected D-pole common pins D1, D2 disposed between the lead frame first G-pole pin G1 and the lead frame second G-pole pin G2. The outer surfaces of the lead frame base island S1, the lead frame first G-pole pin G1, the lead frame second G-pole pin G2, the lead frame second S-pole pins S2, and the two D-pole common pins D1, D2 are all located on the same plane, so that during packaging, their outer surfaces are all exposed outside the plastic package, facilitating the chip after packaging to be mounted on the PCB. It should be noted that a recess 11 is provided around the front surface of the lead frame base island S1 for storing excess solder. The plurality of lead frame pins each include a corresponding root 12, and the backs of the plurality of lead frame pins protrude from the roots 12 of the plurality of lead frame pins, so that during plastic packaging, the roots 12 are covered by the plastic package and the backs of the plurality of lead frame pins are exposed, making the pin plastic packaging more firm.

[0029] The following combines Figure 4 , and describes the structure and manufacturing process of the common-drain dual-MOSFET chip package structure having the lead frame common pins D1, D2.

[0030] First step, face the front of the first MOSFET chip M1 towards the lead frame base island S1 and weld it to the lead frame base island S1, and electrically connect the S-pole and G-pole of the first MOSFET chip M1 to the lead frame base island S1 and the lead frame first G-pole pin G1 respectively. It can be seen that the length of the lead frame first G-pole pin G1 is greater than that of several lead frame pins on the same side, and its purpose is to enable it to be directly electrically connected to the G-pole of the first MOSFET chip M1 by welding.

[0031] Second step, use a copper clip Clip1 to electrically connect the D-pole on the back of the first MOSFET chip M1 to the lead frame common pins D1, D2.

[0032] Third step, weld the D-pole on the back of the second MOSFET chip M2 to the copper clip Clip1.

[0033] Fourth step, electrically connect the S-pole of the second MOSFET chip M2 to the lead frame second S-pole pins S2 by welding using a copper clip Clip2.

[0034] In the fifth step, use a copper wire to electrically connect the G pole of the second MOSFET chip M2 to the second G pole pin G2 of the lead frame. It should be noted that the G pole positions of the first MOSFET chip M1 and the second MOSFET chip M2 are staggered, so as to facilitate the connection of the G poles of the two chips to the two G pole pins G1 and G2 of the lead frame.

[0035] Finally, perform plastic encapsulation so that the outer surfaces of the lead frame base island S1, the first G pole pin G1 of the lead frame, the second G pole pin G2 of the lead frame, the second S pole pin S2 of the lead frame, and the common pins D1 and D2 of the lead frame are all exposed outside the plastic encapsulation body.

[0036] As Figure 5 shown, for a common drain double MOSFET chip packaging structure with common pins D1 and D2 of the lead frame, another structure and manufacturing process can also be adopted. The following is an explanation.

[0037] In the first step, face the front of the first MOSFET chip M1 towards the lead frame base island S1 and weld it on the lead frame base island S1, and electrically connect the S pole and G pole of the first MOSFET chip M1 to the lead frame base island S1 and the first G pole pin G1 of the lead frame respectively. It can be seen that the length of the first G pole pin G1 of the lead frame is greater than several lead frame pins on the same side, and its purpose is to enable it to be directly electrically connected to the G pole of the first MOSFET chip M1 by welding.

[0038] In the second step, directly weld the back of the second MOSFET chip M2 to the back of the first MOSFET chip M1, so that the D pole of the second MOSFET chip M2 is electrically connected to the D pole of the first MOSFET chip M1. It should be noted that in this step, the first MOSFET chip M1 and the second MOSFET chip M2 are staggered and overlapped, so that a part of the D pole of the first MOSFET chip M1 is exposed, which is convenient for subsequent operations.

[0039] In the third step, use a copper wire to electrically connect the G pole of the second MOSFET chip M2 to the second G pole pin G2 of the lead frame, electrically connect the S pole of the second MOSFET chip M2 to the second S pole pin S2 of the lead frame, and electrically connect the exposed part of the part of the D pole of the first MOSFET chip M1 to the common pins D1 and D2 of the lead frame.

[0040] Finally, perform plastic encapsulation treatment so that the outer surfaces of the lead frame base island S1, the first G - pole pin G1 of the lead frame, the second G - pole pin G2 of the lead frame, the second S - pole pin S2 of the lead frame, and the common pins D1 and D2 of the lead frame are all exposed outside the plastic encapsulation body.

[0041] Of course, in some application scenarios, there is no need to lead out the D - poles of two MOSFET chips. The circuit structure is as Figure 6 shown. At this time, the common pins D1 and D2 of the lead frame are floating pins and do not need to be electrically connected to the D - poles of the first MOSFET chip M1 and the second MOSFET chip M2. At this time, the floating pins D1 and D2 of the lead frame can be omitted. Of course, for the overall lead frame, there are corresponding connection relationships for multiple pins on both sides of two adjacent lead frame units. Therefore, in the embodiments of the present invention, the floating pins D1 and D2 of the lead frame are still retained.

[0042] Next, in combination with Figure 7 , the manufacturing process of a common - drain dual - MOSFET chip packaging structure that does not lead out the D - poles of two MOSFET chips in the embodiments of the present invention will be described.

[0043] In the first step, face the front of the first MOSFET chip M1 towards the lead frame base island S1 and weld it on the lead frame base island S1, and electrically connect the S - pole and G - pole of the first MOSFET chip M1 to the lead frame base island S1 and the first G - pole pin G1 of the lead frame respectively. It can be seen that the length of the first G - pole pin G1 of the lead frame is greater than that of several lead frame pins on the same side, and its purpose is to enable it to be directly electrically connected to the G - pole of the first MOSFET chip M1 through welding.

[0044] In the second step, directly weld the back of the second MOSFET chip M2 to the back of the first MOSFET chip M1, so that the D - pole of the second MOSFET chip M2 is electrically connected to the D - pole of the first MOSFET chip M1.

[0045] In the third step, use the copper clip Clip2 welding method to electrically connect the S - pole of the second MOSFET chip M2 to the second S - pole pin S2 of the lead frame.

[0046] In the fourth step, use a copper wire to electrically connect the G - pole of the second MOSFET chip M2 to the second G - pole pin G2 of the lead frame.

[0047] Finally, perform potting so that the outer surfaces of the lead frame base island S1, the first G-pole pin G1 of the lead frame, the second G-pole pin G2 of the lead frame, and the second S-pole pin S2 of the lead frame are all exposed outside the potting body.

[0048] Next, in conjunction with Figure 8 , the manufacturing process of another common-drain dual-MOSFET chip packaging structure of the present invention that does not lead out the D-poles of two MOSFET chips will be described.

[0049] First step, face the front of the first MOSFET chip M1 towards the lead frame base island S1 and weld it to the lead frame base island S1, and electrically connect the S-pole and G-pole of the first MOSFET chip M1 to the lead frame base island S1 and the first G-pole pin G1 of the lead frame respectively. It can be seen that the length of the first G-pole pin G1 of the lead frame is greater than several lead frame pins on the same side, and its purpose is to enable it to be directly electrically connected to the G-pole of the first MOSFET chip M1 by welding.

[0050] Second step, directly weld the back of the second MOSFET chip M2 to the back of the first MOSFET chip M1, so that the D-pole of the second MOSFET chip M2 is electrically connected to the D-pole of the first MOSFET chip M1.

[0051] Third step, electrically connect the G-pole of the second MOSFET chip M2 to the second G-pole pin G2 of the lead frame and the S-pole of the second MOSFET chip M2 to the second S-pole pin S2 of the lead frame by means of copper wires.

[0052] Finally, perform potting so that the outer surfaces of the lead frame base island S1, the first G-pole pin G1 of the lead frame, the second G-pole pin G2 of the lead frame, and the second S-pole pin S2 of the lead frame are all exposed outside the potting body.

[0053] In summary, by adopting the common-drain dual-MOSFET chip packaging structure of the present invention, the circuits formed by two MOS chips are packaged back-to-back in a potting body, thereby reducing the circuit area of the two chips and directly saving half of the area installed on the circuit board, which is beneficial to the miniaturization and thinness of the terminal.

[0054] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A common-drain dual-MOSFET chip packaging structure, characterized in that, It includes a lead frame base island, a plurality of lead frame pins disposed on opposite sides of the lead frame base island, a first MOSFET chip and a second MOSFET chip stacked on the lead frame base island, and a plastic package that wraps the lead frame base island, the plurality of lead frame pins, the first MOSFET chip, and the second MOSFET chip. The plurality of lead frame pins include a lead frame second S-pole pin disposed on one side of the lead frame base island, a lead frame first G-pole pin, and a lead frame second G-pole pin disposed on the other side of the lead frame. The S-poles and G-poles of the first MOSFET chip and the second MOSFET chip are both disposed on the front side of the chip. The D-poles of the first MOSFET chip and the second MOSFET chip are both disposed on the back side of the chip. The front side of the first MOSFET chip faces the lead frame base island and is welded to the lead frame base island. The S-pole and G-pole of the first MOSFET chip are electrically connected to the lead frame base island and the lead frame first G-pole pin respectively. The back side of the second MOSFET chip faces the back side of the first MOSFET chip, and the D-poles of the second MOSFET chip and the first MOSFET chip remain electrically connected. The G-pole and S-pole of the second MOSFET chip are respectively connected to the lead frame second G-pole pin and the lead frame second S-pole pin. The outer surfaces of the lead frame base island, the lead frame first G-pole pin, the lead frame second G-pole pin, and the lead frame second S-pole pin are all on the same plane and are all exposed outside the plastic package.

2. The common-drain dual-MOSFET chip packaging structure according to claim 1, characterized in that The first MOSFET chip and the second MOSFET chip are back-to-back and the positions of their G-poles are staggered. The G-pole of the first MOSFET chip is electrically connected to the lead frame first G-pole by welding. The G-pole of the second MOSFET chip is electrically connected to the lead frame second G-pole by a copper wire.

3. The common-drain dual-MOSFET chip package structure according to claim 2, characterized in that, The plurality of lead frame pins further include two mutually electrically connected lead frame D-pole common pins disposed between the lead frame first G-pole pin and the lead frame second G-pole pin. The lead frame D-pole common pins are electrically connected to the D-poles of the first MOSFET chip and the second MOSFET chip.

4. The common-drain dual-MOSFET chip packaging structure according to claim 3, wherein The lead frame D-pole common pins are electrically connected to the D-poles of the first MOSFET chip and the second MOSFET chip through a copper clip disposed between the first MOSFET chip and the second MOSFET chip.

5. The common-drain dual-MOSFET chip packaging structure according to claim 3, wherein The D-pole of the first MOSFET chip and the D-pole of the second MOSFET chip are electrically connected by welding, and the first MOSFET chip and the second MOSFET chip are staggered and overlapped so that a part of the D-pole of the first MOSFET chip is exposed. The lead frame D-pole common pins are electrically connected to the exposed D-pole of the first MOSFET chip by a copper wire.

6. The common-drain dual-MOSFET chip packaging structure according to claim 3, wherein, The second S pin of the lead frame is electrically connected to the S pole of the second MOSFET chip through a copper clip.

7. The common-drain dual-MOSFET chip packaging structure according to claim 2, characterized in that, The multiple lead frame pins further include two lead frame floating pins disposed between the first G pin of the lead frame and the second G pin of the lead frame.

8. The common-drain dual-MOSFET chip package structure according to claim 7, wherein, The D poles of the first MOSFET chip and the second MOSFET chip are electrically connected by soldering.

9. The common-drain dual-MOSFET chip packaging structure according to claim 7, wherein The second S pin of the lead frame is electrically connected to the S pole of the second MOSFET chip through a copper clip or a copper wire.

10. The common-drain dual-MOSFET chip packaging structure according to claim 1, wherein, Depressions are provided around the front of the lead frame base island. Each of the multiple lead frame pins includes a corresponding root portion, and the backs of the multiple lead frame pins protrude from the root portions of the multiple lead frame pins.

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