Semiconductor structure and forming method thereof
By forming a photoelectric effect layer on the substrate surface and controlling the formation of conductive channels with light illumination, the problem of insufficient gate control capability of MOSFET devices is solved, simplifying the manufacturing process, improving performance and reducing costs.
Patent Information
- Application Number
- CN202311865699.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-04
AI Technical Summary
Traditional MOSFET devices lack the gate control capability of conductive channels, resulting in complex manufacturing processes and difficult performance improvement.
The photoelectric effect layer is formed on the substrate surface, and the number of free photoelectrons in the photoelectric effect layer is controlled by light to control the formation of conductive channels, avoiding the formation of gate electrodes and simplifying the manufacturing process.
Improves device performance, reduces manufacturing costs and manufacturing difficulty, and improves chip design efficiency.
Smart Images
Figure CN120264929A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a common semiconductor device widely used in electronic and circuit applications.
[0003] Traditional MOSFET devices control the flow of current between the source and drain by applying a voltage to their gate. When the gate voltage changes, the conductive state of the MOSFET also changes, allowing or preventing current from flowing. In order to ensure the gate voltage, high requirements are placed on the critical dimensions and film thickness of the back-end process of chip manufacturing, and many layers of back-end film layers need to be stacked and etched, which is a cumbersome process. Moreover, as the size of semiconductor devices continues to shrink in proportion, the gate's ability to control the conductive channel becomes increasingly lower, and very complex manufacturing processes need to be applied to improve the gate's ability to control the conductive channel.
[0004] Therefore, the performance of existing MOS devices needs to be improved urgently. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.
[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a source region and a drain region separated from each other in the substrate; a photoelectric effect layer located on the surface of the substrate between the source region and the drain region, the photoelectric effect layer is also located on a portion of the surface of the source region and a portion of the surface of the drain region, and the material of the photoelectric effect layer generates electrons after being irradiated with light; a cut-off protection layer located on the surface of the source region, the surface of the drain region, and the surface of the photoelectric effect layer; a dielectric layer structure located on the surface of the cut-off protection layer, the dielectric layer structure having a light through hole exposing a portion of the cut-off protection layer on the surface of the photoelectric effect layer, and the dielectric layer structure comprising an opaque material; a conductive structure located in the dielectric layer structure, the conductive structure being located on the surface of the source region and the surface of the drain region, respectively, and the conductive structure being isolated from the photoelectric effect layer.
[0007] Optionally, the material of the photoelectric effect layer includes a photoelectric material, and the photoelectric material includes a combination of one or more of GeSi, GgCdTe, InAs and GaSb.
[0008] Optionally, the material of the cutoff protection layer includes silicon nitride.
[0009] Optionally, the thickness range of the cutoff protection layer is from 500 angstroms to 2000 angstroms.
[0010] Optionally, it further includes: an encapsulation material located in the optical through-hole, and the refractive index of the encapsulation material is less than that of the photo-electric effect layer.
[0011] Optionally, the dielectric layer structure includes a dielectric layer and a passivation layer located on the surface of the dielectric layer; the conductive structure includes a first contact layer, a plurality of first metal interconnect layers located on the first contact layer and electrically connected to the first contact layer, a first lead-out layer located on the surface of the plurality of first metal interconnect layers, a second contact layer, a plurality of second metal interconnect layers located on the second contact layer and electrically connected to the second contact layer, and a second lead-out layer located on the surface of the plurality of second metal interconnect layers. The first lead-out layer and the second lead-out layer are located in the passivation layer, the first contact layer, the second contact layer, the plurality of first metal interconnect layers, and the plurality of second metal interconnect layers are located in the dielectric layer, and the first contact layer is located on the surface of the source region, and the second contact layer is located on the surface of the drain region.
[0012] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming mutually discrete source regions and drain regions in the substrate; forming a photo-electric effect layer on the surface of the substrate between the source region and the drain region, and the photo-electric effect layer also lies on the surface of a part of the source region and a part of the drain region, and electrons are generated when the material of the photo-electric effect layer is irradiated by light; forming a cutoff protection layer on the surfaces of the source region, the drain region, and the photo-electric effect layer; forming a dielectric layer structure on the surface of the cutoff protection layer, a conductive structure is provided in the dielectric layer structure, and an optical through-hole exposing a part of the surface of the cutoff protection layer is provided in the dielectric layer structure. The dielectric layer structure includes an opaque material, the conductive structure is respectively located on the surfaces of the source region and the drain region, and the conductive structure is isolated from the photo-electric effect layer.
[0013] Optionally, the method for forming the dielectric layer structure and the optical through-hole includes: forming the dielectric layer structure and the conductive structure on the surface of the cutoff protection layer; etching the dielectric layer structure until the surface of the cutoff protection layer is exposed, and forming the optical through-hole in the dielectric layer structure.
[0014] Optionally, the dielectric layer structure includes a dielectric layer and a passivation layer on the surface of the dielectric layer; the conductive structure includes a first contact layer, a plurality of first metal interconnect layers on the first contact layer and electrically connected to the first contact layer, a first lead-out layer on the surface of the plurality of first metal interconnect layers, a second contact layer, a plurality of second metal interconnect layers on the second contact layer and electrically connected to the second contact layer, and a second lead-out layer on the surface of the plurality of second metal interconnect layers. The first lead-out layer and the second lead-out layer are located within the passivation layer, the first contact layer, the second contact layer, the plurality of first metal interconnect layers, and the plurality of second metal interconnect layers are located within the dielectric layer, and the first contact layer is located on the surface of the source region, and the second contact layer is located on the surface of the drain region.
[0015] Optionally, the method for forming the dielectric layer structure and the conductive structure further includes: forming the dielectric layer on the surface of the cut-off protection layer, where the first contact layer, the second contact layer, the plurality of first metal interconnect layers, and the plurality of second metal interconnect layers are within the dielectric layer; forming the passivation layer on the surface of the dielectric layer, on the surface of the plurality of first metal interconnect layers, and on the surface of the plurality of second metal interconnect layers; and forming the first lead-out layer and the second lead-out layer within the passivation layer.
[0016] Optionally, it further includes: providing a laser generator for injecting laser into the optical through-hole to provide the light illumination.
[0017] Optionally, the material of the photoelectric effect layer includes a photoelectric material, and the photoelectric material includes one or a combination of GeSi, GgCdTe, InAs, and GaSb.
[0018] Optionally, the material of the cut-off protection layer includes silicon nitride.
[0019] Optionally, the thickness range of the cut-off protection layer is from 500 angstroms to 2000 angstroms.
[0020] Optionally, it further includes: filling an encapsulation material in the optical through-hole, and the refractive index of the encapsulation material is less than the refractive index of the photoelectric effect layer.
[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0022] In the semiconductor structure provided by the technical solution of the present invention, a photo - electric effect layer is disposed on the surface of the substrate between the source region and the drain region. The photo - electric effect layer also lies on the surfaces of part of the source region and part of the drain region. The material of the photo - electric effect layer generates electrons when irradiated by light. By controlling the number of free photoelectrons in the photo - electric effect layer through light irradiation, whether a conductive channel is formed in the photo - electric effect layer is controlled, thereby controlling the conductive state between the source region and the drain region of the device. Since there is no need to form a gate, problems such as the control ability of the gate on the conductive channel and the difficulties in the gate manufacturing process are avoided, the difficulty of chip design and manufacturing is reduced, the device performance is effectively improved, and the manufacturing cost is reduced.
[0023] Further, the material of the cut - off protection layer includes a dielectric material, which can play the roles of electrical insulation and surface passivation. When the material of the cut - off protection layer is selected as silicon oxide, since the stress generated by the contact between the silicon oxide material and the silicon material is small, it is beneficial to improve the adhesion between the cut - off protection layer and the substrate.
[0024] Further, the total reflection film layer located on the side wall of the optical through - hole is beneficial to improving the utilization rate of incident light in the photo - electric effect layer and enhancing the photoelectric conversion efficiency.
[0025] In the method for forming the semiconductor structure provided by the technical solution of the present invention, a photo - electric effect layer is formed on the surface of the substrate between the source region and the drain region. The photo - electric effect layer also lies on the surfaces of part of the source region and part of the drain region. The material of the photo - electric effect layer generates electrons when irradiated by light. By controlling the number of free photoelectrons in the photo - electric effect layer through light irradiation, whether a conductive channel is formed in the photo - electric effect layer is controlled, thereby controlling the conductive state between the source region and the drain region of the device. Since there is no need to form a gate, problems such as the control ability of the gate on the conductive channel and the difficulties in the gate manufacturing process are avoided, the difficulty of chip design and manufacturing is reduced, the device performance is effectively improved, and the manufacturing cost is reduced.
[0026] Further, the material of the cut - off protection layer includes silicon nitride, which can play the roles of passivation and antireflection. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figures 1 to 5 is a schematic structural diagram of each step of the method for forming the semiconductor structure according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0028] It should be noted that the "surface" and "on" in this specification are used to describe the relative spatial position relationship and do not limit whether there is direct contact.
[0029] As described in the background art, the control ability of the gate of the existing MOS device on the conductive channel is poor, and the performance urgently needs to be improved.
[0030] To solve the above problems, in a semiconductor structure and a method for forming the same provided by the present invention, a photoelectric effect layer is formed on the surface of the substrate between the source region and the drain region, and the photoelectric effect layer is also located on the surfaces of part of the source region and part of the drain region. The material of the photoelectric effect layer generates electrons when irradiated by light, and the number of free photoelectrons in the photoelectric effect layer is controlled by light irradiation to control whether a conductive channel is formed in the photoelectric effect layer, thereby controlling the conductive state between the source region and the drain region of the device. Since there is no need to form a gate, the problems of the control ability of the gate on the conductive channel and the difficulties in the gate manufacturing process are avoided, the difficulty of chip design and manufacturing is reduced, the device performance is effectively improved, and the manufacturing cost is reduced.
[0031] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0032] Figures 1 to 5 It is a schematic structural diagram of each step of the method for forming the semiconductor structure according to the embodiment of the present invention.
[0033] Please refer to Figure 1 , provide a substrate 100; mutually discrete source regions 101 and drain regions 102 are formed in the substrate 100.
[0034] In this embodiment, the material of the substrate 100 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0035] In this embodiment, the substrate 100 has a well region 103, and the source region 101 and the drain region 202 are located in the well region 103 and have a different conductivity type from the well region 103.
[0036] In this embodiment, the substrate 100 further has an isolation structure 104, and the isolation structure 104 is located between adjacent well regions 103. The isolation structure 104 is used to achieve electrical insulation between different devices.
[0037] In this embodiment, the method for forming the source region 201 and the drain region 202 includes: forming a patterned layer (not shown in the figure) on the substrate 100, and the patterned layer exposes part of the well region 103; using the patterned layer as a mask, doping ions are implanted into the substrate 100 to respectively form the source region 101 and the drain region 102.
[0038] Please refer to Figure 2 On the surface of the substrate 100 between the source region 101 and the drain region 102, a photo - electric effect layer 105 is formed. The photo - electric effect layer 105 also lies on the surfaces of part of the source region 101 and part of the drain region 102. The material of the photo - electric effect layer 105 generates electrons when irradiated by light.
[0039] In this embodiment, the material of the photo - electric effect layer 105 includes optoelectronic materials, and the optoelectronic materials include one or a combination of more of GeSi, GgCdTe, InAs, and GaSb.
[0040] Please refer to Figure 3 On the surfaces of the source region 101, the drain region 102, and the photo - electric effect layer 105, a cut - off protection layer 106 is formed.
[0041] The material of the cut - off protection layer 106 includes dielectric materials, and the dielectric materials include one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and silicon carbon oxynitride. The cut - off protection layer 106 plays roles of electrical insulation and surface passivation.
[0042] In this embodiment, the material of the cut - off protection layer 106 is silicon oxide. Since the stress generated by the contact between the silicon oxide material and the silicon material is small, it is beneficial to improve the adhesion between the cut - off protection layer 106 and the substrate 100.
[0043] In this embodiment, the thickness range of the cut - off protection layer 106 is from 500 angstroms to 2000 angstroms.
[0044] Subsequently, a dielectric layer structure is formed on the surface of the cut - off protection layer 106. There is a conductive structure in the dielectric layer structure, and there is a light through - hole in the dielectric layer structure that exposes part of the surface of the photo - electric effect layer of the cut - off protection layer. The dielectric layer structure includes light - impermeable materials. The conductive structures are respectively located on the surfaces of the source region 101 and the drain region 102, and the conductive structures are isolated from the photo - electric effect layer 105. The conductive structures are used to realize the electrical connection between the transistor and the outside.
[0045] In this embodiment, for the formation method of the dielectric layer structure and the light through - hole, please refer to Figures 4 to 5 .
[0046] Please refer to Figure 4 On the surface of the cut - off protection layer 106, the dielectric layer structure and the conductive structure are formed.
[0047] The material of the dielectric layer structure includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.
[0048] The dielectric layer structure includes multiple film layers of dielectric materials.
[0049] In this embodiment, the dielectric layer structure includes a dielectric layer 107 and a passivation layer 108 on the surface of the dielectric layer 107; the conductive structure includes a first contact layer 109a, several first metal interconnect layers 110a on the first contact layer 109a and electrically connected to the first contact layer 109a, a first lead-out layer 111a on the surface of several first metal interconnect layers 110a, a second contact layer 109b, several second metal interconnect layers 110b on the second contact layer 109b and electrically connected to the second contact layer 109b, and a second lead-out layer 111b on the surface of several second metal interconnect layers 110b. The first lead-out layer 111a and the second lead-out layer 111b are located within the passivation layer 108, the first contact layer 109a, the second contact layer 109b, several first metal interconnect layers 110a, and several second metal interconnect layers 110b are located within the dielectric layer 107, and the first contact layer 109a is located on the surface of the source region 101, and the second contact layer 109b is located on the surface of the drain region 102.
[0050] Specifically, the method for forming the dielectric layer structure and the conductive structure further includes: forming the dielectric layer 107 on the surface of the cut-off protection layer 106, with the first contact layer 109a, the second contact layer 109b, several first metal interconnect layers 110a, and several second metal interconnect layers 110b within the dielectric layer 107; forming the passivation layer 108 on the surface of the dielectric layer 107, on the surface of several first metal interconnect layers 110, and on the surface of several second metal interconnect layers 110b; forming the first lead-out layer 111a and the second lead-out layer 111b within the passivation layer 108.
[0051] It should be noted that in this embodiment Figure 4 only one layer of the first metal interconnect layer 110a and one layer of the second metal interconnect layer 110b are shown. In other embodiments, the number of layers of the first metal interconnect layer and the second metal interconnect layer can be set according to actual needs.
[0052] Please refer to Figure 5 , etch the dielectric layer structure until the surface of the cut-off protection layer 106 is exposed, and form the optical through-hole 112 within the dielectric layer structure.
[0053] At this point, the number of free photoelectrons in the photoelectric effect layer 105 is controlled by illumination to control whether a conductive channel is formed in the photoelectric effect layer, thereby controlling the conductive state between the source region 101 and the drain region 102 of the device. Since there is no need to form a gate, the problem of the gate's control over the conductive channel and the difficulty of the gate manufacturing process are avoided, thereby reducing the difficulty of chip design and manufacturing, effectively improving device performance and reducing manufacturing costs.
[0054] In this embodiment, the process for forming the optical via 112 includes a dry etching process, which is beneficial for improving the morphology of the formed optical via 112 .
[0055] In this embodiment, a laser generator (not shown in the figure) is further provided, and the laser generator is used to inject laser into the light through hole 112 to provide the illumination.
[0056] In this embodiment, a packaging material (not shown in the figure) is further filled in the optical through hole 112, and the refractive index of the packaging material is lower than the refractive index of the photoelectric effect layer 105. The refractive index of the packaging material is lower than the refractive index of the material of the photoelectric effect layer 105, and total reflection is easily generated when light is incident from the photoelectric effect layer 105 to the packaging material, which helps to improve the utilization rate of the incident light in the photoelectric effect layer 105 and improve the photoelectric conversion efficiency.
[0057] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 5 , comprising: a substrate 100; a source region 101 and a drain region 102 separated from each other in the substrate 100; a photoelectric effect layer 105 located on the surface of the substrate 100 between the source region 101 and the drain region 102, the photoelectric effect layer 105 also located on a portion of the surface of the source region 101 and a portion of the surface of the drain region 102, the material of the photoelectric effect layer 105 generates electrons after being irradiated with light; a cut-off protection layer 106 located on the surface of the source region 101, the surface of the drain region 102 and the surface of the photoelectric effect layer 105; a dielectric layer structure located on the surface of the cut-off protection layer 106, the dielectric layer structure having a light through hole 112 exposing a portion of the cut-off protection layer 106 on the surface of the photoelectric effect layer 105, the dielectric layer structure comprising an opaque material; a conductive structure located in the dielectric layer structure, the conductive structure being located on the surface of the source region 101 and the surface of the drain region 102 respectively, and the conductive structure being isolated from the photoelectric effect layer 105.
[0058] So far, by controlling the number of free photoelectrons in the photoelectric effect layer 105 through light, whether a conductive channel is formed in the photoelectric effect layer is controlled, thereby controlling the conductive state between the source region 101 and the drain region 102 of the device. Since there is no need to form a gate, problems such as the gate's control ability for the conductive channel and the difficulties in the gate manufacturing process are avoided, the difficulty of chip design and manufacturing is reduced, the device performance is effectively improved, and the manufacturing cost is reduced.
[0059] In this embodiment, the material of the photoelectric effect layer 105 includes a photoelectric material, and the photoelectric material includes one or a combination of more of GeSi, GgCdTe, InAs, and GaSb.
[0060] The material of the cut-off protection layer 106 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. The cut-off protection layer 106 functions as electrical insulation and surface passivation.
[0061] In this embodiment, the material of the cut-off protection layer 106 is silicon oxide. Since the stress generated by the contact between the silicon oxide material and the silicon material is small, it is beneficial to improve the adhesion between the cut-off protection layer 106 and the substrate 100.
[0062] In this embodiment, the thickness range of the cut-off protection layer 106 is from 500 angstroms to 2000 angstroms.
[0063] In this embodiment, the semiconductor structure further includes: a packaging material (not shown in the figure) located in the optical through hole 112, and the refractive index of the packaging material is less than the refractive index of the photoelectric effect layer.
[0064] In this embodiment, the dielectric layer structure includes a dielectric layer 107 and a passivation layer 108 on the surface of the dielectric layer 107; the conductive structure includes a first contact layer 109a, a plurality of first metal interconnect layers 110a located on the first contact layer 109a and electrically connected to the first contact layer 109a, a first lead-out layer 111a on the surface of the plurality of first metal interconnect layers 110a, a second contact layer 109b, a plurality of second metal interconnect layers 110b located on the second contact layer 109b and electrically connected to the second contact layer 109b, and a second lead-out layer 111b on the surface of the plurality of second metal interconnect layers 110b. The first lead-out layer 111a and the second lead-out layer 111b are located within the passivation layer 108, the first contact layer 109a, the second contact layer 109b, the plurality of first metal interconnect layers 110a, and the plurality of second metal interconnect layers 110b are located within the dielectric layer 107, and the first contact layer 109a is located on the surface of the source region 101, and the second contact layer 109b is located on the surface of the drain region 102.
[0065] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate; A source region and a drain region that are discrete from each other within the substrate; A photoelectric effect layer on the surface of the substrate between the source region and the drain region, the photoelectric effect layer also being on the surfaces of part of the source region and part of the drain region, and the material of the photoelectric effect layer generating electrons when irradiated by light; A cut-off protection layer on the surfaces of the source region, the drain region, and the photoelectric effect layer; A dielectric layer structure on the surface of the cut-off protection layer, the dielectric layer structure having a light through-hole that exposes part of the surface of the photoelectric effect layer of the cut-off protection layer, and the dielectric layer structure comprising a light-impermeable material; A conductive structure within the dielectric layer structure, the conductive structure being respectively on the surfaces of the source region and the drain region, and the conductive structure being isolated from the photoelectric effect layer.
2. The semiconductor structure according to claim 1, characterized in that, The material of the photoelectric effect layer comprises a photoelectric material, and the photoelectric material comprises one or a combination of more of GeSi, GgCdTe, InAs, and GaSb.
3. The semiconductor structure according to claim 1, characterized in that, The material of the cut-off protection layer comprises silicon oxide.
4. The semiconductor structure according to claim 1, wherein The thickness range of the cut-off protection layer is from 500 angstroms to 2000 angstroms.
5. The method for forming a semiconductor structure according to claim 1, wherein, Further comprising: A packaging material within the light through-hole, and the refractive index of the packaging material is less than the refractive index of the photoelectric effect layer.
6. The semiconductor structure according to claim 1, wherein The dielectric layer structure comprises a dielectric layer and a passivation layer on the surface of the dielectric layer; the conductive structure comprises a first contact layer, a plurality of first metal interconnect layers on the first contact layer and electrically connected to the first contact layer, a first lead-out layer on the plurality of first metal interconnect layers, a second contact layer, a plurality of second metal interconnect layers on the second contact layer and electrically connected to the second contact layer, and a second lead-out layer on the plurality of second metal interconnect layers, the first lead-out layer and the second lead-out layer being within the passivation layer, the first contact layer, the second contact layer, the plurality of first metal interconnect layers, and the plurality of second metal interconnect layers being within the dielectric layer, and the first contact layer being on the surface of the source region, and the second contact layer being on the surface of the drain region.
7. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a source region and a drain region that are discrete from each other within the substrate; Forming a photoelectric effect layer on the surface of the substrate between the source region and the drain region, the photoelectric effect layer also being on the surfaces of part of the source region and part of the drain region, and the material of the photoelectric effect layer generating electrons when irradiated by light; Forming a cut-off protection layer on the surfaces of the source region, the drain region, and the photoelectric effect layer; Forming a dielectric layer structure on the surface of the cut-off protection layer, the dielectric layer structure having a conductive structure therein, the dielectric layer structure having a light through-hole that exposes part of the surface of the photoelectric effect layer of the cut-off protection layer, the dielectric layer structure comprising a light-impermeable material, the conductive structure being respectively on the surfaces of the source region and the drain region, and the conductive structure being isolated from the photoelectric effect layer.
8. The method for forming a semiconductor structure according to claim 7, wherein, The forming method of the dielectric layer structure and the optical through-hole includes: forming the dielectric layer structure and the conductive structure on the surface of the cutoff protection layer; etching the dielectric layer structure until the surface of the cutoff protection layer is exposed, and forming the optical through-hole in the dielectric layer structure.
9. The method for forming a semiconductor structure according to claim 8, wherein, The dielectric layer structure includes a dielectric layer and a passivation layer located on the surface of the dielectric layer; the conductive structure includes a first contact layer, a plurality of first metal interconnect layers located on the first contact layer and electrically connected to the first contact layer, a first lead-out layer located on the surface of the plurality of first metal interconnect layers, a second contact layer, a plurality of second metal interconnect layers located on the second contact layer and electrically connected to the second contact layer, and a second lead-out layer located on the surface of the plurality of second metal interconnect layers. The first lead-out layer and the second lead-out layer are located in the passivation layer, the first contact layer, the second contact layer, the plurality of first metal interconnect layers and the plurality of second metal interconnect layers are located in the dielectric layer, and the first contact layer is located on the surface of the source region, and the second contact layer is located on the surface of the drain region.
10. The method for forming a semiconductor structure according to claim 9, wherein, The forming method of the dielectric layer structure and the conductive structure further includes: forming the dielectric layer on the surface of the cutoff protection layer, and the first contact layer, the second contact layer, the plurality of first metal interconnect layers and the plurality of second metal interconnect layers are provided in the dielectric layer; forming the passivation layer on the surface of the dielectric layer, on the surface of the plurality of first metal interconnect layers and on the surface of the plurality of second metal interconnect layers; forming the first lead-out layer and the second lead-out layer in the passivation layer.
11. The method for forming a semiconductor structure as claimed in claim 7, wherein, Further included is: providing a laser generator, which is used to inject laser into the optical through-hole to provide the light illumination.
12. The method for forming a semiconductor structure according to claim 7, wherein, The material of the photoelectric effect layer includes a photoelectric material, and the photoelectric material includes one or a combination of more of GeSi, GgCdTe, InAs, and GaSb.
13. The method for forming a semiconductor structure according to claim 7, wherein, The material of the cutoff protection layer includes silicon oxide.
14. The method for forming a semiconductor structure according to claim 7, wherein, The thickness range of the cutoff protection layer is from 500 angstroms to 2000 angstroms.
15. The method for forming a semiconductor structure according to claim 7, wherein, Further included is: filling a packaging material in the optical through-hole, and the refractive index of the packaging material is less than the refractive index of the photoelectric effect layer.